CN116643945B - Data detection method and system for secondary cache and computer equipment - Google Patents
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Abstract
The invention relates to the technical field of computers, in particular to a data detection method, a system and computer equipment for secondary cache, which comprise the following steps: packaging the request generated by the excitation generator into a request data packet, and storing the request data packet in a request queue corresponding to the type of the request; the requests include a fetch request, an access request, a store request, and an address translation request; monitoring and acquiring key information corresponding to a request in a second-level cache so as to search a request data packet with the same request identifier as the key information from a request queue; accessing the memory model according to the searched request data packet, comparing the data acquired from the memory model with the key information, and reporting errors if the data are inconsistent; and deleting the compared request data packet from the request queue. The invention can rapidly and effectively locate the errors of the read-write data of the secondary cache by monitoring a small amount of request key information, and can meet the address correlation requirement by detecting the execution sequence of the read-write request.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, a system, and a computer device for detecting data in a secondary cache.
Background
With the continuous development of electronic technology, a high-performance processor is generally configured with a first-level cache and a second-level cache, wherein the second-level cache is a memory between the first-level cache and a memory, and has a capacity larger than that of the first-level cache and far smaller than that of the memory, and is mainly used for coordinating the speed difference between the first-level cache and the memory, and the key of the second-level cache is that the query efficiency can be improved, the acquired data can be locally cached, and when the query occurs again, the data can be faster than loading data, and in addition, the second-level cache can directly store objects in the cache instead of a database, so that the time for normally extracting the objects from the database is saved, the access pressure of a CPU (central processing unit) to the main memory is lightened, and the system performance is improved, so that the second-level cache is one of the keys of the performance of the CPU.
Although the secondary cache has many advantages, the secondary cache must be completely unobstructed in deployment to ensure the accuracy of data, otherwise, the query result will not be inaccurate, even possibly have errors, but the research on the detection of the secondary cache data is lacking at present, so it is needed to provide a data detection method of the secondary cache to ensure the accuracy of the secondary cache data and improve the user experience.
Disclosure of Invention
The invention aims to provide a data detection method, a system and computer equipment for a secondary cache, so that the accuracy of the read-write data logic of the secondary cache can be effectively detected by monitoring a small number of key signals, and the accuracy of a query result of the secondary cache is ensured.
In order to solve the technical problems, the invention provides a data detection method, a system and computer equipment for secondary cache.
In a first aspect, the present invention provides a method for detecting data in a secondary cache, where the method includes the following steps:
packaging the request generated by the excitation generator into a request data packet, and storing the request data packet into a request queue corresponding to the type of the request; wherein the request comprises a fetch request, an access request, a storage request and an address translation request;
monitoring the secondary cache, acquiring key information corresponding to the request, and searching a request data packet with the same request identifier as the key information from the request queue according to the key information;
accessing a memory model according to the searched request data packet, comparing the data acquired from the memory model with the key information, and reporting errors if the data are inconsistent;
And deleting the compared request data packet from the request queue.
In a further embodiment, when the request is a finger request or an access request, the step of monitoring the second level cache, obtaining key information corresponding to the request, and searching, according to the key information, a request data packet having the same request identifier as the key information from the request queue includes:
monitoring key information of the request in the secondary cache, if the key information of the request is not acquired from the excitation generator by the secondary cache, detecting whether the request is canceled, and if the key information is canceled, deleting the request from the request queue; otherwise, continuing to monitor the key information of the request in the second-level cache;
if the secondary cache is monitored to acquire the key information of the request from the excitation generator, searching a request data packet with the same request identifier as the key information from the request queue corresponding to the request according to a preset request identifier;
detecting whether the searched request data packet is wrong, if so, deleting the wrong request data packet from the request queue directly, otherwise, accessing the memory model through the access address of the request.
In a further embodiment, when the request is a finger request or an access request, the preset request identifier is a memory high address tag of the request.
In a further embodiment, when the request is an access request, the step of comparing the data obtained from the memory model with the critical information further comprises:
if the data are consistent, traversing a storage request queue, and reporting errors when the storage request with the same access address as the access request is detected in the storage request queue to have the current time which is not completed yet and the request time of the storage request is earlier than the request time of the current completed access request.
In a further embodiment, when the request is a storage request, the step of monitoring the second level cache, obtaining key information corresponding to the request, and searching, according to the key information, a request data packet having the same request identifier as the key information from the request queue includes:
monitoring whether the newly stored storage request has merging operation or not, if so, searching a target storage request merged with the newly stored storage request from a storage request queue according to a preset merging target searching principle, merging the target storage request with the newly stored storage request, and reserving the merged storage request in the storage request queue;
Monitoring whether the secondary cache has an ongoing data writing operation, and if not, continuing monitoring;
if the ongoing data writing operation exists, searching a request data packet of a storage request with the same monitored current access address, the same current writing operation thread ID and the same request type from a storage request queue according to the monitored access address;
if the request data packet of the storage request which is the same as the monitored access address, the current write operation thread ID and the request type request and has the same request type are not found in the storage request queue, the error is reported and the corresponding debugging is carried out.
In a further embodiment, the merging target searching principle is specifically:
and searching for the existing storage requests which have the same cache line, the same thread ID and the same strong access ordering attribute as the newly stored storage request, and if a plurality of existing storage requests exist, selecting the existing storage request with the latest request time as a target storage request combined with the newly stored storage request.
In a further embodiment, when the request is a storage request, the step of accessing a memory model according to the found request packet and comparing data obtained from the memory model with the key information includes:
If a request data packet of a storage request with the same monitored access address, the same current writing operation thread ID and the same request type request is searched from the storage request queue, writing operation is carried out on the memory model according to the searched request data packet so as to write the storage request data into the memory model;
and comparing the write data acquired from the memory model with the key information.
In a further embodiment, when the request is an address translation request, the step of monitoring the second level cache to obtain key information corresponding to the request, and searching, according to the key information, a request packet having the same request identifier as the key information from the request queue includes:
monitoring key information of the address conversion request in the secondary cache, and if the key information of the address conversion request is not acquired from the excitation generator by the secondary cache, continuing to monitor the key information of the address conversion request in the secondary cache;
if the secondary cache is monitored to acquire the key information of the address conversion request from the excitation generator, searching a request data packet with the same request identifier as the key information of the address conversion request from the request queue corresponding to the request according to a preset request identifier;
Detecting whether the searched request data packet is wrong, if so, deleting the wrong request data packet from the request queue directly, otherwise, accessing the memory model through the access address of the address conversion request.
In a further embodiment, when the request is an address translation request, the preset request identifier is a memory high address tag of the address translation request.
In a further embodiment, the step of deleting the compared request packet from the request queue further comprises: and detecting whether the request queue is empty, if not, reporting errors and performing corresponding debugging.
In a second aspect, the present invention provides a data detection system for a secondary cache, the system comprising:
the excitation generator is used for generating a request, packaging the request into a request data packet and storing the request into a request queue corresponding to the type of the request; wherein the request comprises a fetch request, an access request, a storage request and an address translation request;
the DUT monitor is used for monitoring the secondary cache, acquiring key information corresponding to the request and sending the key information to the core controller;
The core controller is used for searching a request data packet with the same request identification as the key information from the request queue according to the received key information;
the method comprises the steps of,
accessing a memory model according to the searched request data packet, comparing the data acquired from the memory model with the key information, and reporting errors if the data are inconsistent; and deleting the compared request data packet from the request queue.
In a further embodiment, the system further comprises:
the memory model is used for initializing at the simulation zero moment and performing read-write operation on the memory model according to different request types;
and the comparison module is used for comparing the data returned from the secondary cache with the data acquired from the memory model.
In a further embodiment, the comparison module includes a request sequence comparator;
the request sequence comparator is used for traversing the storage request queue when the access request is completed for the access request and the storage request accessing the same cache line, and reporting errors when the storage request queue detects that the storage request with the same access address as the access request is not completed at the current moment and the request time is earlier than the request time of the current completion access request.
In a third aspect, the present invention also provides a computer device, including a processor and a memory, where the processor is connected to the memory, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the computer device performs steps for implementing the method.
The invention provides a data detection method, a system and computer equipment of a secondary cache, wherein the method is characterized in that generated requests of different types are packed into corresponding request data packets and then stored into a request queue corresponding to the type of the request; monitoring the secondary cache, acquiring key information corresponding to the request, and searching a request data packet with the same request identifier as the key information from a request queue according to the key information; accessing the memory model according to the searched request data packet, comparing the data acquired from the memory model with the key information, and reporting errors if the data are inconsistent. Compared with the prior art, the method detects the secondary cache data, and can more effectively and rapidly locate the correctness of the secondary cache read-write data by executing different controls on different types of requests, and when the data is in error, error information is reported in real time, so that the debugging efficiency is improved.
Drawings
FIG. 1 is a schematic flow chart of a data detection method for a secondary cache according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a finger request execution flow according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an access request execution flow provided by an embodiment of the present invention;
FIG. 4 is a schematic diagram of a storage request execution flow provided by an embodiment of the present invention;
FIG. 5 is a schematic diagram of an address translation request execution flow according to an embodiment of the present invention;
FIG. 6 is a block diagram of a data detection system for a secondary cache according to an embodiment of the present invention;
FIG. 7 is a block diagram of a second level cache data detection system according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
Detailed Description
The following examples are given for the purpose of illustration only and are not to be construed as limiting the invention, including the drawings for reference and description only, and are not to be construed as limiting the scope of the invention as many variations thereof are possible without departing from the spirit and scope of the invention.
Referring to fig. 1, an embodiment of the present invention provides a method for detecting data in a secondary cache, as shown in fig. 1, including the following steps:
S1, packaging a request generated by an excitation generator into a request data packet, and storing the request data packet into a request queue corresponding to the type of the request.
In this embodiment, the stimulus generator in the verification environment generates a stimulus required for verification and sends the stimulus to the secondary cache, and in the verification environment of the secondary cache, various different types of requests including a fetch request, an access (Load) request, a Store (Store) request, and an address conversion request are mainly generated, and correspondingly, a fetch request queue is used for storing a request packet of the fetch request, an access request queue is used for storing a request packet of the access request, a Store request queue is used for storing a request packet of the Store request, and an address conversion request queue is used for storing a request packet of the address conversion request.
S2, monitoring the secondary cache, acquiring key information corresponding to the request, and searching a request data packet with the same request identifier as the key information from the request queue according to the key information.
S3, accessing a memory model according to the searched request data packet, comparing the data acquired from the memory model with the key information, and reporting errors if the data are inconsistent.
In this embodiment, a DUT (Design under test, design to be verified) monitor monitors a small amount of key information of the request in the secondary cache, including the time when the secondary cache performs the instruction fetch request, the Load request or the address conversion request and returns the data to the core controller, the time when the secondary cache writes the data into the RAM of itself, the information about whether the request is canceled, the information about whether the Store request is merged, and the information about whether the synchronization request is completed, where these key information determine the execution flow of the core controller for the corresponding request, and because the amount of key information read each time is small, the power consumption of the core processor for the secondary cache operation is reduced, and meanwhile, the data accuracy detection efficiency is improved, and the fast, efficient, stable and reliable secondary cache data detection is realized.
In one embodiment, when the request is a finger request, as shown in fig. 2, the step of monitoring the second level cache, obtaining key information corresponding to the request, and searching, according to the key information, a request data packet having the same request identifier as the key information from the request queue includes:
After the excitation generator generates the fetch request, monitoring key information of the request in a secondary cache, if the secondary cache is not monitored to acquire the key information of the fetch request from the excitation generator, detecting whether the fetch request is canceled, and if the fetch request is canceled and the secondary cache returns a tag (memory high-order address tag) of the fetch request, deleting the fetch request from the fetch request queue; otherwise, continuing to monitor key information of the instruction fetching request in the second-level cache; in this embodiment, if the fetch request is cancelled after being stored in a cycle (cycle) of the fetch request queue, the cancellation flag of the fetch request is set to be 1;
if the secondary cache is monitored to acquire key information of the instruction fetch request from the excitation generator, searching a request data packet with the same request identifier as the key information from the instruction fetch request queue corresponding to the instruction fetch request according to a preset request identifier of the instruction fetch request;
detecting whether the searched request data packet is wrong, if so, deleting the wrong request data packet from the request queue directly, otherwise, accessing the memory model through the access address of the request.
In this embodiment, when the request is a fetch request, the preset request identifier is a memory high address tag of the fetch request, where in this embodiment, the information of the fetch request includes key information such as an access address, a memory high address tag (tag represents a high address that is not used for caching an index in a block address), a request type, and the like, and those skilled in the art may set the key information corresponding to the fetch request according to specific implementation cases, which is not limited to the embodiment of the present invention; according to the embodiment, the consistency detection is carried out on the instruction fetching request data acquired from the excitation generator and the data acquired from the access memory model by the secondary cache through a small amount of key information of the instruction fetching request, so that the corresponding request data can be acquired quickly, the timeliness of data detection in the cache is improved, errors can be reported quickly and effectively, and the accuracy of the instruction fetching request data is guaranteed.
In one embodiment, when the request is an access request, as shown in fig. 3, the step of monitoring the secondary cache, obtaining key information corresponding to the request, and searching, according to the key information, a request data packet having the same request identifier as the key information from the request queue includes:
Monitoring key information of the access request in the secondary cache, if the key information of the access request is not acquired from the excitation generator by the secondary cache, detecting whether the access request is canceled, and if the access request is canceled after one cycle (period) of accessing the access request queue is stored, deleting the access request from the request queue; otherwise, continuing to monitor key information of the access request in the secondary cache;
if the secondary cache is monitored to acquire the key information of the access request from the excitation generator, searching a request data packet with the same request identifier as the key information from the access request queue corresponding to the access request according to the preset request identifier of the access request;
detecting whether the searched request data packet is wrong, if so, deleting the wrong request data packet from the request queue directly, otherwise, accessing the memory model through the access address of the access request.
In this embodiment, when the request is an access request, the request identifier of the access request is a memory high address tag of the access request, where in this embodiment, the access request includes key information such as an access address, tag (memory high address tag), a request type, a request time, and a thread ID, where the request time refers to a current emulation time, and the current emulation time may be obtained by using a $time function, and may be used for comparing an access sequence of a subsequent Load request with an access sequence of a Store request, and those skilled in the art may set the corresponding key information of the access request according to a specific implementation situation, which is not limited to the embodiment of the present invention.
In this embodiment, when the request is an access request, the step of comparing the data obtained from the memory model with the key information further includes:
if the data are consistent, traversing the storage request queue, and reporting errors when the storage request with the same access address as the access request is detected in the storage request queue to have the current time of not completing and the request time of the storage request is earlier than the request time of currently completing the access request.
Specifically, because there is an address correlation between Load requests or Store requests, that is, when the accessed address is in the same cache line, the execution of the Load requests or Store requests must satisfy a certain condition, because when the processor issues the Load requests or Store requests, the instruction corresponding to the Store requests has been submitted (Commit), and the instruction corresponding to the Load requests has not been submitted (Commit), so, when the Load requests are completed, the Store requests that have an earlier time than the request time of the Load requests must be completed, therefore, when the Load requests are completed, the Store request queue needs to be searched, so that when the Store requests that do not satisfy the above condition are searched, the embodiment not only satisfies the address correlation requirement, but also avoids the situation that the execution sequence of the read data requests and the write data requests is wrong, and further, the accuracy of the data cannot be improved, and the accuracy of the second-order data cannot be obtained due to the execution sequence error of the Load requests and the Store requests.
The embodiment detects the access request, including consistency detection of the access request data acquired from the excitation generator and the data acquired from the access memory model by the secondary cache, and detection of the execution sequence of the read-write request based on address correlation existing between the read-data request and the write-data request, so that hidden danger of request data errors and the like caused by abnormal execution sequence can be eliminated, accuracy of the access request data is ensured, and the requirement of address correlation is met.
In one embodiment, when the request is an address translation request, as shown in fig. 4, the step of monitoring the second level cache, obtaining key information corresponding to the request, and searching, according to the key information, a request data packet having the same request identifier as the key information from the request queue includes:
monitoring key information of the address conversion request in the secondary cache, and if the key information of the address conversion request is not acquired from the excitation generator by the secondary cache, continuing to monitor the key information of the request in the secondary cache;
if the secondary cache is monitored to acquire key information of the address conversion request from the excitation generator, searching a request data packet with the same request identifier as the key information from the address conversion request queue corresponding to the address conversion request according to the preset request identifier of the address conversion request;
Detecting whether the searched request data packet is wrong, if so, deleting the wrong request data packet from the request queue directly, otherwise, accessing the memory model through the access address of the address conversion request.
In this embodiment, when the request is an address translation request, the request is identified as a high-order address tag of a memory of the address translation request, where the address translation request may include key information such as an access address, a tag (high-order address tag of the memory), a request type, and a thread ID, and those skilled in the art may set the corresponding key information of the address translation request according to a specific implementation situation, which is not limited to the embodiment of the present invention.
According to the embodiment, consistency analysis and detection are carried out on the data of the address conversion request, when the data of the address conversion request in the secondary cache is in error, error information of the address conversion request can be reported in real time, so that the error data can be efficiently positioned, and the correctness and the integrity of the data of the address conversion request are ensured.
In one embodiment, when the request is a storage request, as shown in fig. 5, the storage request may include key information such as an access address, write data, byte valid bit, request type, request time, and thread ID, where the request time refers to a current emulation time and may be used for comparing a Load request with a sequence of Store requests, and a person skilled in the art may set the key information corresponding to the storage request according to a specific implementation, and in this embodiment, after the stimulus generator generates the storage request, the process of monitoring the key information of the request in the secondary cache and comparing the key information with the data obtained from the memory model includes:
Monitoring whether the newly stored storage requests have merging operation, wherein the merging operation is to merge the storage requests for writing the same cache line so as to improve the writing efficiency;
if the merging operation exists, searching a target storage request merged with the newly stored storage request from a storage request queue according to a preset merging target searching principle, merging the target storage request with the newly stored storage request, reserving the merged storage request in the storage request queue, and deleting the newly stored storage request from the storage request queue;
monitoring whether the secondary cache has an ongoing data writing operation, and if not, continuing monitoring;
if the ongoing data writing operation exists, searching a request data packet of a storage request which is the same as the monitored current access address, the current writing operation thread ID (thread ID) and the request type from a storage request queue according to the monitored access address;
if the request data packet of the storage request which is the same as the monitored access address, the ID of the current writing operation thread and the request type request are not found in the storage request queue, reporting errors and carrying out corresponding debugging;
If a request data packet of the storage request which is the same as the monitored access address, the current writing operation thread ID and the request type request is searched from the storage request queue, writing operation is carried out on the memory model according to the searched information such as the access address, the writing data and the byte valid bit of the request data packet so as to write the storage request data into the memory model;
and comparing the write data acquired from the memory model with the key information.
In this embodiment, the merging target searching principle specifically includes:
and searching for the existing storage requests which have the same cache line, the same thread ID and the same strong access ordering attribute as the newly stored storage request, and if a plurality of existing storage requests exist, selecting the existing storage request with the latest request time as a target storage request combined with the newly stored storage request.
The embodiment performs data detection on the storage request, including performing coincidence comparison on the storage request data acquired from the stimulus generator by the merging operation and the ongoing data writing operation, and performing coincidence comparison on the second-level cache and the write data acquired from the access memory model, wherein the embodiment can improve the efficiency of cache coincidence detection by performing the merging operation and the ongoing data writing operation in advance before performing the data coincidence comparison, and ensure that a user extracts reliable data.
S4, deleting the compared request data packet from the request queue.
In this embodiment, the step of deleting the compared request packet from the request queue further includes: for executing different types of requests, when the simulation is finished, detecting whether a corresponding request queue is empty, and if not, indicating that the requests are not executed, and needing to report errors and carry out corresponding debugging.
The data detection method of the secondary cache provided by the embodiment can rapidly and effectively locate whether the read-write data of the secondary cache is correct or not, is irrelevant to a secondary cache micro-architecture, can effectively judge whether the logic of the read-write data is accurate or not by monitoring a small amount of key signals, can be transplanted into a secondary cache verification environment of other micro-architectures, and can check the execution sequence of the read-write request so as to meet the requirement of address correlation.
In an embodiment, the technical solution provided in this embodiment may be extended to a multi-core scenario, that is, a Verification environment in which a plurality of secondary caches and buses are interconnected, an independent request queue and a core controller are built for each secondary cache, and a memory model is shared, where the memory model corresponds to a memory in a data RAM (random access memory) of all the secondary caches and a VIP (Verification IP) connected to the buses, and in the multi-core scenario, read/write data of all the secondary caches are checked, and memory consistency is checked.
The embodiment of the application provides a data detection method of a secondary cache, which not only provides a control method for executing read data requests such as a fetch request, an access request and an address conversion request, but also realizes the detection of the execution sequence of the read data requests and the write data requests based on address correlation existing between the read data requests and the write data requests. Compared with the prior art, the technical scheme provided by the embodiment realizes control over different types of requests, compares the correctness of access data, can effectively and quickly locate errors of the read-write data of the secondary cache, and improves the debugging efficiency.
It should be noted that, the sequence number of each process does not mean that the execution sequence of each process is determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
In one embodiment, as shown in fig. 6, an embodiment of the present application provides a data detection system for a secondary cache, the system including:
an excitation generator 101, configured to generate a request, package the request into a request packet, and store the request in a request queue corresponding to a type of the request; wherein the request comprises a fetch request, an access request, a storage request and an address translation request;
The DUT monitor 102 is configured to monitor the second level cache, obtain key information corresponding to the request, and send the key information to the core controller;
the core controller 103 is configured to search, according to the received key information, a request packet having the same request identifier as the key information from the request queue;
the method comprises the steps of,
accessing a memory model according to the searched request data packet, comparing the data acquired from the memory model with the key information, and reporting errors if the data are inconsistent; deleting the compared request data packet from the request queue;
as shown in fig. 7, the data detection system for a secondary cache provided in the embodiment of the present invention further includes:
the memory model 104 is used for initializing at the simulation zero time, wherein the initialization value is determined according to the actual initial value in the DUT and is consistent with the actual initial value in the secondary cache; the memory model is also used for performing read-write operation on the memory model according to different request types in the simulation process;
and the comparison module 105 is used for comparing the data returned in the secondary cache with the data acquired from the memory model.
In this embodiment, the comparison module 105 includes an access data comparator, a storage data comparator, a synchronization request comparator, and a request sequence comparator; the access data comparator is used for comparing key information read by the DUT monitor from the secondary cache with data obtained from the memory model when the request is a fetch request, a Load request or an address conversion request; the storage data comparator is used for comparing the key information read by the DUT monitor from the secondary cache with the data obtained from the memory model when the request is a Store request; the synchronous request comparator is used for checking whether a Store request with earlier request time than the synchronous request exists in the storage request queue or not when the secondary cache sends out a synchronous request completion signal based on the principle that the synchronous request can be executed only when the request is the synchronous request (one of the storage request types) and based on the fact that the Store request before the synchronous request is executed; the request sequence comparator is used for traversing the storage request queue when the Load request is completed for the Load request and the Store request which access the same cache line, and reporting errors when the Store request which has the same access address as the Load request is detected in the storage request queue and the current moment is not completed yet and the request time is earlier than the request time of currently completing the Load request.
According to the embodiment, based on the existence of address correlation between the read data request and the write data request, the read data request and the write data request accessing the same cache line are detected through the request sequence comparator, so that the request sequence comparator not only meets the address correlation requirement, but also avoids the situation that a correct result of data cannot be obtained due to the fact that the execution sequence of the Load request and the Store request is wrong, eliminates hidden dangers such as request data errors caused by the fact that the execution sequence is wrong, and effectively improves the time sequence and accuracy of the second-level cache data.
For specific limitation of a secondary cache data detection system, reference may be made to the above limitation of a secondary cache data detection method, which is not described herein. Those of ordinary skill in the art will appreciate that the various modules and steps described in connection with the disclosed embodiments of the application may be implemented in hardware, software, or a combination of both. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The embodiment of the application provides a data detection system of a secondary cache, which realizes the data monitoring in the secondary cache through a DUT monitor; the accuracy detection of the read-write data logic and the detection of the execution sequence of the read-write request are realized through the core processor and the comparison module, so that the read-write data logic meets the address correlation requirement. Compared with the prior art, the method and the device can effectively detect the accuracy of the second-level cache read-write data logic by monitoring a small amount of key signals, thereby improving the accuracy of the second-level cache data query.
FIG. 8 is a diagram of a computer device including a memory, a processor, and a transceiver connected by a bus, according to an embodiment of the present application; the memory is used to store a set of computer program instructions and data and the stored data may be transferred to the processor, which may execute the program instructions stored by the memory to perform the steps of the above-described method.
Wherein the memory may comprise volatile memory or nonvolatile memory, or may comprise both volatile and nonvolatile memory; the processor may be a central processing unit, a microprocessor, an application specific integrated circuit, a programmable logic device, or a combination thereof. By way of example and not limitation, the programmable logic device described above may be a complex programmable logic device, a field programmable gate array, general purpose array logic, or any combination thereof.
In addition, the memory may be a physically separate unit or may be integrated with the processor.
It will be appreciated by those of ordinary skill in the art that the structure shown in FIG. 8 is merely a block diagram of some of the structures associated with the present inventive arrangements and is not limiting of the computer device to which the present inventive arrangements may be implemented, and that a particular computer device may include more or fewer components than those shown, or may combine some of the components, or have the same arrangement of components.
The foregoing examples represent only a few preferred embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the application. It should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present application, and such modifications and substitutions should also be considered to be within the scope of the present application. Therefore, the protection scope of the patent of the application is subject to the protection scope of the claims.
Claims (14)
1. The data detection method of the second-level cache is characterized by comprising the following steps of:
packaging the request generated by the excitation generator into a request data packet, and storing the request data packet into a request queue corresponding to the type of the request; wherein the request comprises a fetch request, an access request, a storage request and an address translation request;
Monitoring the secondary cache, acquiring key information corresponding to the request, and searching a request data packet with the same request identifier as the key information from the request queue according to the key information; the key information is used for determining the execution flow of the core controller to the corresponding request, and the key information comprises the moment when the secondary cache finishes executing the instruction fetch request, the access request or the address conversion request and returns the data to the core controller, the moment when the secondary cache writes the data into the self RAM, the information whether the request is cancelled, the information whether the storage request is merged and the information whether the synchronous request is completed;
accessing a memory model according to the searched request data packet, comparing the data acquired from the memory model with the key information, and reporting errors if the data are inconsistent;
and deleting the compared request data packet from the request queue.
2. The method for detecting data in a secondary cache as claimed in claim 1, wherein when said request is a finger request or an access request, said step of monitoring said secondary cache to obtain key information corresponding to said request, and searching for a request packet having the same request identifier as said key information from said request queue according to said key information comprises:
Monitoring key information of the request in the secondary cache, if the key information of the request is not acquired from the excitation generator by the secondary cache, detecting whether the request is canceled, and if the key information is canceled, deleting the request from the request queue; otherwise, continuing to monitor the key information of the request in the second-level cache;
if the secondary cache is monitored to acquire the key information of the request from the excitation generator, searching a request data packet with the same request identifier as the key information from the request queue corresponding to the request according to a preset request identifier;
detecting whether the searched request data packet is wrong, if so, deleting the wrong request data packet from the request queue directly, otherwise, accessing the memory model through the access address of the request.
3. The method for detecting data in a secondary cache as claimed in claim 2, wherein: when the request is a fetch request or an access request, the preset request identifier is a memory high-order address tag of the request.
4. The method for detecting data in a secondary cache as claimed in claim 2, wherein when said request is an access request, said step of comparing data obtained from said memory model with said critical information further comprises:
If the data are consistent, traversing a storage request queue, and reporting errors when the storage request with the same access address as the access request is detected in the storage request queue to have the current time which is not completed yet and the request time of the storage request is earlier than the request time of the current completed access request.
5. The method for detecting data in a secondary cache as claimed in claim 1, wherein when said request is a storage request, said step of monitoring said secondary cache to obtain key information corresponding to said request, and searching for a request packet having the same request identifier as said key information from said request queue according to said key information comprises:
monitoring whether the newly stored storage request has merging operation or not, if so, searching a target storage request merged with the newly stored storage request from a storage request queue according to a preset merging target searching principle, merging the target storage request with the newly stored storage request, and reserving the merged storage request in the storage request queue;
monitoring whether the secondary cache has an ongoing data writing operation, and if not, continuing monitoring;
If the ongoing data writing operation exists, searching a request data packet of a storage request with the same monitored current access address, the same current writing operation thread ID and the same request type from a storage request queue according to the monitored access address;
if the request data packet of the storage request which is the same as the monitored access address, the current write operation thread ID and the request type request and has the same request type are not found in the storage request queue, the error is reported and the corresponding debugging is carried out.
6. The method for detecting data in a secondary cache as claimed in claim 5, wherein said merging target searching principle is as follows:
and searching for the existing storage requests which have the same cache line, the same thread ID and the same strong access ordering attribute as the newly stored storage request, and if a plurality of existing storage requests exist, selecting the existing storage request with the latest request time as a target storage request combined with the newly stored storage request.
7. The method for detecting data in a secondary cache as claimed in claim 5, wherein when said request is a storage request, said step of accessing a memory model based on the searched request packet and comparing the data obtained from said memory model with said key information comprises:
If a request data packet of a storage request with the same monitored access address, the same current writing operation thread ID and the same request type request is searched from the storage request queue, writing operation is carried out on the memory model according to the searched request data packet so as to write the storage request data into the memory model;
and comparing the write data acquired from the memory model with the key information.
8. The method for detecting data in a secondary cache as claimed in claim 1, wherein when said request is an address translation request, said step of monitoring said secondary cache to obtain key information corresponding to said request, and searching for a request packet having the same request identifier as said key information from said request queue according to said key information comprises:
monitoring key information of the address conversion request in the secondary cache, and if the key information of the address conversion request is not acquired from the excitation generator by the secondary cache, continuing to monitor the key information of the address conversion request in the secondary cache;
if the secondary cache is monitored to acquire the key information of the address conversion request from the excitation generator, searching a request data packet with the same request identifier as the key information of the address conversion request from the request queue corresponding to the request according to a preset request identifier;
Detecting whether the searched request data packet is wrong, if so, deleting the wrong request data packet from the request queue directly, otherwise, accessing the memory model through the access address of the address conversion request.
9. The method for detecting data in a secondary cache as claimed in claim 8, wherein: when the request is an address conversion request, the preset request identifier is a memory high-order address tag of the address conversion request.
10. The method for detecting data in a secondary cache as claimed in claim 1, wherein said step of deleting said compared request packet from said request queue further comprises: and detecting whether the request queue is empty, if not, reporting errors and performing corresponding debugging.
11. A system for detecting data in a secondary cache, the system comprising:
the excitation generator is used for generating a request, packaging the request into a request data packet and storing the request into a request queue corresponding to the type of the request; wherein the request comprises a fetch request, an access request, a storage request and an address translation request;
The DUT monitor is used for monitoring the secondary cache, acquiring key information corresponding to the request and sending the key information to the core controller; the key information is used for determining the execution flow of the core controller to the corresponding request, and the key information comprises the moment when the secondary cache finishes executing the instruction fetch request, the access request or the address conversion request and returns the data to the core controller, the moment when the secondary cache writes the data into the self RAM, the information whether the request is cancelled, the information whether the storage request is merged and the information whether the synchronous request is completed;
the core controller is used for searching a request data packet with the same request identification as the key information from the request queue according to the received key information;
the method comprises the steps of,
accessing a memory model according to the searched request data packet, comparing the data acquired from the memory model with the key information, and reporting errors if the data are inconsistent; and deleting the compared request data packet from the request queue.
12. A two-level buffered data detection system according to claim 11, wherein said system further comprises:
The memory model is used for initializing at the simulation zero moment and performing read-write operation on the memory model according to different request types;
and the comparison module is used for comparing the data returned from the secondary cache with the data acquired from the memory model.
13. A two-level buffered data detection system according to claim 12 wherein: the comparison module comprises a request sequence comparator;
the request sequence comparator is used for traversing the storage request queue when the access request is completed for the access request and the storage request accessing the same cache line, and reporting errors when the storage request queue detects that the storage request with the same access address as the access request is not completed at the current moment and the request time is earlier than the request time of the current completion access request.
14. A computer device, characterized by: comprising a processor and a memory, the processor being connected to the memory, the memory being for storing a computer program, the processor being for executing the computer program stored in the memory to cause the computer device to perform the method of any one of claims 1 to 10.
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