CN117251216B - Server firmware starting optimization method, system, server and storage medium - Google Patents
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The invention provides a method, a system, a server and a storage medium for optimizing server firmware start, wherein the method comprises the following steps: and when the initialization of the memory is completed, carrying firmware codes corresponding to the firmware from the on-chip cache to a physical memory address, and after remapping a CPU address space to the physical memory, jumping to the physical memory address to continue operation until the starting of the operating system is completed. The invention is convenient for the high-efficiency integrated use of the IP core, can effectively reduce the switching load of the system, greatly shortens the starting time of the firmware and improves the starting efficiency of the system.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, a system, a server, and a storage medium for optimizing server firmware start.
Background
The Power architecture server is a server based on an architecture of a RISC instruction system developed by IBM, and is gradually applied to various fields due to the advantages of simple structure, high efficiency of multiple cores, tight coupling of hardware and software and the like of a processor, so that the Power architecture server is very likely to be a development direction of a high-performance computer and cloud computing.
Currently, a Power architecture server generally adopts a three-stage progressive increasing firmware architecture integrating SCP (System Control Processor) firmware, hostboot firmware and Skiboost firmware, and the initialization of several important IP cores (intellectual property core) including the initialization of a memory and the initialization of a CMN (Consistent Grid Network) interconnection bus is completed in the boot stage of the Hostboot firmware. However, the code of the Hostboot firmware adopts large-end sequence coding, and the existing third party IP cores are usually realized by small-end sequence coding, and the size end of the code needs to be manually adjusted if the IP cores are integrated, namely, the integration of the third party IP functional package is quite difficult; in addition, the Hostboot firmware is based on microkernel design, the process is frequently switched, the initialization of the important IP core in the starting stage not only increases the starting time, but also requires the transmission of all IP core data in the subsequent switching process from the Hostboot firmware starting stage to the Skiboost firmware starting stage, and additionally increases the system switching burden, thereby leading to slow switching process and longer system starting time.
Disclosure of Invention
The invention aims to provide a server firmware starting optimization method, which solves the application defects that the existing Power server cannot integrate IP cores efficiently and the system starting time is long by initializing large and important IP cores comprising an interconnection bus, a memory and the like from a Hostboot firmware starting stage to a Skiboost firmware starting stage, and is convenient for the efficient integrated use of a third party IP core, meanwhile, the system switching burden can be effectively reduced, the firmware starting time is greatly shortened, and the system starting efficiency is improved.
In order to achieve the above object, it is necessary to provide a method, a system, a server and a storage medium for optimizing the start of firmware of a server.
In a first aspect, an embodiment of the present invention provides a method for optimizing server firmware start, where the method includes the following steps:
responding to SCP firmware start, executing preset lightweight initialization on the on-chip cache; the lightweight initialization comprises power-on initialization, clock initialization and chip core register initialization;
when the light-weight initialization execution is completed, a Power big core is started, the Hostboot firmware is guided to be started, and after the basic initialization execution of the Hostboot firmware is completed, the Skiboost firmware is started;
Responding to the completion of the execution of the basic initialization of the Skiboost firmware, and executing the initialization of a plurality of IP cores according to a preset IP core initialization sequence; the IP core initialization sequence is that after the initialization of the interconnection bus and the initialization of the memory are completed in sequence, the initialization of other IP cores is executed;
and when the memory initialization is completed, carrying the firmware codes corresponding to the firmware from the on-chip caches to the corresponding physical memory addresses, and after remapping the CPU address space to the physical memory, jumping to the corresponding physical memory addresses to continue operation.
Further, the step of initializing the chip core register includes:
presetting an address remapping register;
and initializing the mapping state of the address remapping register to map the CPU address space to an on-chip cache.
Further, the step of remapping the CPU address space to the physical memory includes:
sending a cache mapping destruction signal to the address remapping register so that the address remapping register clears the mapping relation between a CPU address space and the on-chip cache according to the cache mapping destruction signal;
after the mapping relation between the CPU address space and the on-chip cache is destroyed, sending a physical memory mapping signal to the address remapping register, so that the address remapping register maps the CPU address space to the physical memory according to the physical memory mapping signal, and updating the mapping state of the address remapping register;
After the mapping state of the address remapping register is updated, a cache remapping signal is sent to the address remapping register, so that the address remapping register maps the on-chip cache to other address spaces outside the physical memory address range according to the cache remapping signal.
Further, the lightweight initialization further includes:
initializing an ECC check address range according to a preset physical memory address range;
after the step of remapping the CPU address space to the physical memory, the method further includes:
and carrying out ECC check on the data stored in the ECC check address range, and restarting SCP firmware when the check fails.
Further, the step of starting the Power big core includes:
and creating task threads with preset thread numbers by setting a starting state bit of a Power big core register.
Further, the step of performing initialization of the plurality of IP cores according to a preset IP core initialization sequence includes:
and calling a task thread, starting a multithreading task, and executing initialization of a plurality of IP cores according to a preset IP core initialization sequence.
Further, the method further comprises:
responding to a reading task of a linux kernel, dividing the linux kernel into corresponding linux kernel segments according to the preset thread number and the preset kernel loading priority, and distributing the linux kernel segments to each thread according to a preset multithreading task scheduling mechanism.
In a second aspect, an embodiment of the present invention provides a server firmware start-up optimization system, including:
the SCP starting module is used for responding to the starting of SCP firmware and executing preset lightweight initialization on the on-chip cache; the lightweight initialization comprises power-on initialization, clock initialization and chip core register initialization;
the Hostboot starting module is used for starting the Power big core and guiding the Hostboot firmware to start when the lightweight initialization execution is completed, and starting the Skiboost firmware after the basic initialization execution of the Hostboot firmware is completed;
the Skiboost starting module is used for responding to the completion of the execution of the basic initialization of the Skiboost firmware and executing the initialization of a plurality of IP cores according to a preset IP core initialization sequence; the IP core initialization sequence is that after the initialization of the interconnection bus and the initialization of the memory are completed in sequence, the initialization of other IP cores is executed;
and the address remapping module is used for moving the firmware codes corresponding to the firmware from the on-chip caches to the corresponding physical memory addresses when the memory initialization is completed, and after remapping the CPU address space to the physical memory, jumping to the corresponding physical memory addresses to continue operation.
In a third aspect, an embodiment of the present invention further provides a server, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the steps of the above method when executing the computer program.
In a fourth aspect, embodiments of the present invention also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the above method.
The method comprises the steps of executing preset Power-on initialization, clock initialization and chip core register initialization on an on-chip cache when SCP firmware is started, starting a Power big core and guiding Hostboot firmware to start corresponding basic initialization when the execution of the lightweight initialization is completed, starting Skiboost firmware, executing the execution of the basic initialization of the Skiboost firmware, executing the initialization of a plurality of IP cores according to a preset IP core initialization sequence, moving firmware codes corresponding to the firmware from the on-chip cache to corresponding physical memory addresses when the memory initialization is completed, and jumping to the corresponding physical memory addresses to continue operation after remapping a CPU address space to the physical memory. Compared with the prior art, by adopting a reasonable firmware architecture adjustment scheme for initializing large and important IP cores comprising an interconnection bus, a memory and the like and moving the initialization of the IP cores from a Hostboot firmware start stage to a Skiboost firmware start stage, the method is convenient for the efficient integrated use of the third party IP cores, can effectively reduce the switching burden of the system, greatly shortens the firmware start time and improves the system start efficiency.
Drawings
FIG. 1 is a flowchart of a method for optimizing server firmware boot up in an embodiment of the present invention;
FIG. 2 is a flow chart of a server firmware boot optimization method for enabling ECC verification in an embodiment of the invention;
FIG. 3 is a flow chart of a method for optimizing server firmware boot up for multi-threading in an embodiment of the invention;
FIG. 4 is a schematic diagram of a server firmware boot optimization system according to an embodiment of the present invention;
fig. 5 is a schematic diagram showing an internal structure of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantageous effects of the present application more apparent, the present invention will be further described in detail with reference to the accompanying drawings and examples, and it should be understood that the examples described below are only illustrative of the present invention and are not intended to limit the scope of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The method for optimizing the starting of the server firmware is based ON the defects that the existing Power server firmware architecture causes inconvenience in the integration of a third party IP core, the important IP core is initialized in a Hostboot firmware starting stage to additionally increase system switching burden, the switching process is slow, and the system starting time is overlong. The following embodiments will describe the server firmware start-up optimization method of the present invention in detail.
In one embodiment, as shown in fig. 1, a method for optimizing server firmware start is provided, including the following steps:
s11, responding to SCP firmware start, and executing preset lightweight initialization on an on-chip cache; wherein on-chip caching can be understood as OCM on chip, and the cache capacity provided by OMC is limited based on the limitation of chip area size; in order to ensure that the server system can be started normally and meet the required functional requirements while realizing architecture adjustment for initializing and moving back large and important IP cores including memories, the embodiment preferably designs lightweight initialization work according to limited cache capacity customization so that the corresponding CPU address space does not exceed the cache capacity; specifically, the lightweight initialization includes Power-on initialization, clock initialization and chip core register initialization, where the Power-on initialization is understood to be the first initialization step of Power processor chip initialization, and is used to support external Power supply, and corresponds to power_init () interface implementation; the clock initialization is understood to be the initialization of a clock module for setting the signal frequency to the functions of running rate synchronization, timing control, power consumption control and the like among various modules in the chip, for example, the initialization of a PLL (Phase Locked Loop) module corresponds to the implementation of a pll_init () interface; the core registers of the chip can be understood as being composed of special registers and general registers, and the special registers provide interfaces for setting the chip for the system, and specifically include functional registers such as a processor version information register (SPR_PVR), a processor available resource register (SPR_PURR), an exception save and restore register (SPR_SRR0), an address source register (SPR_CFAR), and a processor identification register (SPR_PIR); the general registers include functional registers (r 0-r 31) for providing general functions and transfer parameters; the specific execution process of the lightweight initialization can be understood as that the initialization interface functions corresponding to the pre-designed power-on initialization, clock initialization and chip core register initialization are sequentially called in the main initialization function of the SCP firmware, and of course, each interface only needs to meet the corresponding starting function requirement, and specific internal implementation details can be set according to the actual application scene requirements, which is not limited in detail herein.
In practical application, considering that SCP firmware start, subsequent Power big core start, hostboot firmware basic initialization and Skiboost firmware basic initialization execution all need to be perceived to execute corresponding processes on an on-chip cache, effective management and maintenance of CPU address space mapping are facilitated, reliable basis is provided for CPU address space remapping after subsequent memory initialization is completed, and normal and efficient operation of subsequent start processes is further ensured; specifically, the step of initializing the core register of the chip includes:
presetting an address remapping register; the address remapping register is understood to be a hardware register preset according to requirements and used for maintaining the remapping state of the CPU address, and the address remapping register is understood to be a 64-bit register, wherein bit 0 is used as a mapping state bit: when bit 0 is 0, the 0 address representing the CPU address space is mapped to the 0 address of the OCM; when bit 0 is 1, the 0 address representing the CPU address space is mapped to the starting 0 address of DDR;
initializing the mapping state of the address remapping register to be that the CPU address space is mapped to an on-chip cache; the mapping state is initially that the CPU address space is mapped to the on-chip cache, which is understood as that bit 0 of the address remapping register is set to 0 when the chip core register is initialized, so that the firmware boot perception related to the next step needs to execute a corresponding initialization start procedure on the OMC, and the mapping state value updates the mapping state bit when the memory initialization is completed and the CPU address space is remapped to the physical memory space in the subsequent starting stage of the Skiboot firmware.
It should be noted that, the foregoing lightweight initialization process includes initializing the Power Core0 running the Hostboot and the process of reading the Hostboot portion in Flash by HBBL (Hostboot Bootloader) and putting it into on-chip cache, which are not described in detail herein, in addition to the foregoing Power-on initialization, clock initialization and chip Core register initialization;
s12, when the lightweight initialization execution is completed, a Power big core is started, the Hostboot firmware is guided to be started, and after the basic initialization execution of the Hostboot firmware is completed, skiboost firmware is started; in the embodiment, preferably, only some basic initialization services including stacking, stack space initialization, FSI interface initialization, communication with BMC, VPD SPD and CLOCK initialization are performed in the starting stage of the Hostboot firmware, and Skiboost firmware starts to be started after the Hostboot firmware starts to run quickly; it should be noted that, the related initialization processes related to the small core to launch the Power large core and the basic initialization of the Hostboot firmware may be implemented by referring to the prior art, which will not be described in detail herein.
S13, responding to the completion of the basic initialization of the Skiboost firmware, and executing the initialization of a plurality of IP cores according to a preset IP core initialization sequence; the IP core initialization sequence is that after the initialization of the interconnection bus and the initialization of the memory are completed in sequence, the initialization of other IP cores is executed; the basic initialization of the Skiboost firmware is understood to be the initialization of some basic services for ensuring that the Skiboost firmware is normally started and operated, such as setting size end bytes (fix end), checking PVR, setting SPR, relocatable carrying function, initializing CPU stack, clearing BSS segment, initializing partial registers required by the operation of the Skiboost firmware, initializing the main flow of CPU, and the like; it should be noted that, the related initialization processes related to the basic initialization of the Skiboot firmware may be implemented by referring to the prior art, which is not described in detail herein;
the above initialization of the plurality of IP cores may be understood to include at least initialization of an interconnection bus (CMN) and initialization of a memory, and other IP cores related to integration may be selected and set according to implementation requirements, which is not limited herein, but it should be noted that, when other IP cores except for the interconnection bus and the memory are integrated, the corresponding IP core initialization sequence must strictly initialize the interconnection bus first, then initialize the memory, and perform initialization of all other IP cores in the corresponding sequence according to an integration association relationship between other IP cores;
It should be noted that, the initialization processes of the interconnection bus (CMN), the memory initialization, and possibly other IP cores may be properly adjusted with reference to the related art to be incorporated into the starting stage of the Skiboot firmware of the present embodiment, and the implementation steps of each initialization process are not described in detail herein.
S14, when the memory initialization is completed, carrying the firmware codes corresponding to the firmware from the on-chip caches to the corresponding physical memory addresses, and after remapping the CPU address space to the physical memory, jumping to the corresponding physical memory addresses to continue operation; the physical memory address corresponding to each firmware can be understood as a memory address range which is allocated to each firmware in advance and used for storing corresponding firmware codes and operation data, and can be correspondingly divided and set in the memory initialization process; after the initialization of the memory is completed, in order to improve the operation efficiency of the subsequent starting step, the data originally operated in the on-chip cache can be moved to the physical memory area, and the subsequent related codes can be directly operated on the physical memory area; in order to facilitate each firmware to timely sense the change of the running address space, in this embodiment, preferably, after the firmware code corresponding to each firmware is moved from the on-chip cache to the corresponding physical memory address, the CPU address space is remapped to the physical memory, so that the subsequent firmware can be directly switched from the on-chip cache to the physical memory to run the related program through the jump instruction;
Specifically, the step of remapping the CPU address space to the physical memory includes:
sending a cache mapping destruction signal to the address remapping register so that the address remapping register clears the mapping relation between a CPU address space and the on-chip cache according to the cache mapping destruction signal; the method comprises the steps of clearing the mapping relation between a CPU address space and an on-chip cache, and clearing a related pipeline;
after the mapping relation between the CPU address space and the on-chip cache is destroyed, sending a physical memory mapping signal to the address remapping register, so that the address remapping register maps the CPU address space to the physical memory according to the physical memory mapping signal, and updating the mapping state of the address remapping register;
after the mapping state of the address remapping register is updated, a cache remapping signal is sent to the address remapping register, so that the address remapping register maps the on-chip cache to other address spaces outside the physical memory address range according to the cache remapping signal.
The operation mode of address adjustment by calling the address remapping register in this embodiment can be understood as: firstly, a certain signal is sent to an address remapping register by a main initialization flow, then the address remapping register extracts an address value according to the signal, and the value of a CPU address space is adjusted according to the address value; specifically, in practical application, after the memory initialization in the main initialization flow is completed, a memory_ OCM signal is sent to an address remapping register, where the register directly operates the CPU address space to destroy the address mapping between the CPU and the OCM, then a remap signal is sent to the register, after the CPU address space is mapped to the DDR 0 address, a remap_ OCM command is sent to the register, and the OCM is mapped to a far address space outside a DDR address range, for example, after confirming that the CPU address space is mapped to an address space range of 0 to 0x3000000000, the OCM is remapped to 0x4000000000 outside the DDR address.
After the remapping of the CPU address space is realized through the steps, each firmware can be switched from an On-Chip cache to run On a physical memory DDR through a jump instruction, and the execution comprises the operations of initializing related equipment of a system, loading and running OCC firmware On an OCC (On-Chip Controller), initializing a memory partition, marking the partition after partition (such as os_regions and firmware_regions), constructing a device tree, loading zimage into the memory, loading a Petitboot user mode program and the like until the starting of an operating system is completed.
According to the embodiment, the firmware architecture adjustment of the large and important IP core initialization including interconnection buses, memories and the like from the Hostboot firmware start-up stage to the Skiboost firmware start-up stage is combined with the management of the CPU address space mapping switching by adding hardware registers, so that the small core and large core basic initialization flow before the memory initialization are all executed on the on-chip OCM, the CPU address space mapping is timely switched to the address space management scheme of the physical memory after the memory initialization is completed, the efficient integrated use of the third-party IP core is facilitated, the system switching load is effectively reduced, the firmware start-up time is greatly shortened, and the system start-up efficiency is improved.
In principle, the above embodiment of the present invention has solved the problems of inconvenient integration of the third party IP core of the existing Power architecture server and excessive system switching burden due to the additional increase of the important IP core initialization in the start-up stage of the hotboot firmware, which results in slow switching process and excessively long system start-up time, but in consideration of the practical application, the situation that the data formed before the memory initialization is easily changed due to level jump in the address switching process can directly affect the normal operation of the subsequent start-up flow, in order to avoid the risk of abnormal start-up caused by address space switching as much as possible, and provide the stability of system start-up, the embodiment preferably adds ECC (Error Checking and Correcting) protection function in the on-chip cache, starts the ECC check operation to perform ECC check on all the data stored in the previous initialization flow after the CPU address space is remapped from the on-chip cache to the physical memory space, and if the check fails, makes global reset and walks the start-up flow again.
The ECC check is a memory detection and error correction mechanism, and is characterized in that one more check byte is additionally stored after 8 bytes of memory data, the 8 bytes are read into an ECC buffer for calculating a check sum in the check process, the obtained check sum is compared with data of the check byte, no error is considered when the check sum is the same, and the error check and correction method for correcting a certain byte is different to carry out validity check on the switched stored data.
Before starting the ECC verification function, the related initialization setting must be performed in the early initialization stage, and in this embodiment, the ECC verification initialization is preferably set in a lightweight initialization flow, that is, after the power-on initialization, the clock initialization, the chip core register initialization, and the like are completed, related operations of the ECC verification initialization need to be added; considering that the ECC check can be executed in time after the CPU address space mapping is switched, the efficient operation of the starting flow can be ensured, and in the embodiment, the address range which needs to be checked and protected is preferably preconfigured when the ECC check is initialized; specifically, the step of ECC verification initialization includes initializing an ECC verification address range according to a preset physical memory address range; the physical memory address range may be determined according to practical design requirements, and is not specifically limited herein.
It should be noted that the effect of adding the ECC check mechanism in this embodiment is to add related initialization settings only in the lightweight initialization stage, and to add validity check on the initialization data stored in the on-chip cache after remapping the CPU address space to the physical memory, and the implementation flow may be implemented with reference to the detailed description of the above embodiments. Correspondingly, after the corresponding initialization setting is performed on the ECC check function in the initialization stage, as shown in fig. 2, after the step of remapping the CPU address space to the physical memory, the step of performing ECC check on the data stored in the ECC check address range further includes the step S14':
S14', when the memory initialization is completed, carrying the firmware codes corresponding to the firmware from the on-chip cache to the corresponding physical memory addresses, after remapping the CPU address space to the physical memory, performing ECC check on the data stored in the ECC check address range, and restarting SCP firmware when the check fails; specifically, in practical application, when the ECC check fails, the SCP firmware is restarted, and then executed again according to steps S11-S14/S14', and when the ECC check is passed, the operation can be directly skipped to the corresponding physical memory address to continue to run, and the starting of the operating system is executed.
According to the embodiment, the firmware architecture adjustment of the large and important IP core initialization including interconnection buses, memories and the like from the Hostboot firmware start-up stage to the Skiboost firmware start-up stage is combined with the management of the CPU address space mapping switching by adding hardware registers, so that the small core and large core basic initialization processes before the memory initialization are all executed on the on-chip OCM, the CPU address space mapping is timely switched to the address space management scheme of the physical memory after the memory initialization is completed, the efficient integrated use of the third party IP core is facilitated, the system switching load is effectively reduced, the firmware start-up time is greatly shortened, the technical effect of the system start-up efficiency is improved, the error correction recovery is carried out on the initialization data after the CPU address space switching by adding an ECC check mechanism, the data change caused by level jump in the address switching process can be effectively avoided, the normal running risk of the subsequent stable start process is directly influenced, and the reliable guarantee is provided for the normal start-up of the system.
In addition, considering that in practical application, the application scenario that multiple IP cores need to be integrated to involve multiple IP core initialization tasks after memory and the task amount of the linux cores is larger to be read from flash later is a bottleneck of system starting speed, in order to further improve the system starting speed on the basis of using the firmware architecture adjustment scheme, in this embodiment, preferably, multiple threads are set to execute the initialization of multiple IP cores and carry the linux cores, so as to further shorten starting duration;
in order to facilitate the initialization process using multithreading, it is necessary to start multithreading when the microkernel starts the big kernel, and specifically, the step of starting the Power big kernel includes:
creating task threads with preset thread numbers by setting a starting state bit of a Power big core register; the start state bit of the Power big Core register can be understood as the start bit of the Power big Core register, the big Core is generally composed of dozens of CPU cores, each CPU Core is provided with a corresponding direct control register, a mode of starting each CPU Core can be respectively set through the small Core, a certain number of task threads can be created according to requirements, the multi-thread environment can be ensured when the Hostboot firmware start stage is entered, the subsequent initialization flow can create the needed multi-thread tasks according to the use requirements, each task is independently distributed to one thread, the task processing speed is higher, and the corresponding initialization operation efficiency can be effectively improved; it should be noted that, the preset thread number may be set according to actual application requirements, which is not limited herein;
After the multithreading environment is started through the method steps, multithreading execution can be used during IP core initialization of the Skiboost firmware starting stage, so that the initialization efficiency of a plurality of IP core integration scenes is improved, and the operation time of the Skiboost firmware starting stage is shortened as much as possible; specifically, the step of executing initialization of the plurality of IP cores according to a preset IP core initialization sequence includes:
calling task threads, starting multithreading tasks, and executing initialization of a plurality of IP cores according to a preset IP core initialization sequence; the number of the multithreading tasks can be determined according to the number of the IP cores to be integrated in practical application, for example, if only initialization of the interconnection bus and the memory is required to be executed, one threading task can be started to be responsible for initialization of the interconnection bus CMN, and another threading task is started to be used for memory initialization; if the method further comprises performing other IP core initialization besides the interconnection bus initialization and the memory initialization, additional thread tasks can be designed to be started according to requirements for execution.
Similarly, the existing multithreading environment can be used for processing tasks with larger workload such as flash reading, kernel loading and the like, so that the processing efficiency of corresponding tasks is improved; in order to further break through the bottleneck of the operation time of reading and recording the linux kernel, the embodiment preferably improves the large task of reading the linux kernel from flash, and uses a plurality of threads to simultaneously execute carrying work; specifically, as shown in fig. 3, the method further includes:
Responding to a reading task of a linux kernel, dividing the linux kernel into corresponding linux kernel segments according to the preset thread number and the preset kernel loading priority, and distributing the linux kernel segments to each thread according to a preset multithreading task scheduling mechanism; the preset thread number is the thread number configured when the Power big core is started as described above; the preset kernel loading priority can be determined according to the sequence of loading and executing the linux kernel in actual operation; correspondingly, the linux kernel segment can be understood as a kernel code segment obtained by disassembling the linux kernel code, and the specific disassembling mode can be determined according to actual requirements, and is not particularly limited herein;
in practical application, for example, the number of preset threads in the established multithreading environment is 8, namely 8 task threads can be used for simultaneously executing carrying work, then the main thread is used for calculating in the starting stage, the linux kernel is split into 8 sections according to the corresponding loading priority, and then corresponding task allocation is carried out according to the corresponding set multithreading task scheduling mechanism, so that the time of low-speed carrying work is greatly reduced; it should be noted that, the multithreaded task scheduling mechanism only needs to satisfy the task allocation that preferentially searches for the thread without tasks in principle, and if tasks exist, the task allocation rule is only needed to be allocated by searching for the thread with the minimum task number, and the task allocation rule can be selected according to the requirements in practical application, and is not particularly limited herein.
The firmware architecture adjustment scheme for initializing large and important IP cores including interconnection buses, memories and the like and moving to the Skiboost firmware starting stage after the Hostboot firmware starting stage is combined with the address space management scheme for timely switching the CPU address space mapping to the physical memory after the memory initialization is completed by managing the CPU address space mapping switching through additionally arranging hardware registers, so that the system switching load is effectively reduced, the firmware starting time is greatly shortened, the system starting efficiency is improved, the abnormal starting risk caused by the change of the data due to level jump in the address switching process is effectively avoided, the reliable guarantee is provided for the normal starting of the system, the error correction recovery is carried out on the initialized data after the CPU address space switching through adding an ECC check mechanism, the multi-thread execution multi-IP core initialization process and the server firmware starting optimization scheme for loading by the Linux kernel segmentation, the multi-thread execution multi-IP core efficient integrated use is facilitated, the system switching load is effectively shortened, the system starting time is greatly shortened, the system starting efficiency is improved, the abnormal starting risk caused by the change of the data in the address jump process is effectively avoided, the system starting time is further ensured, the multi-thread integrated IP core integrated system is further started, and the system starting efficiency is further improved, and the system starting time is further shortened, and the system starting efficiency is further ensured.
Although the steps in the flowcharts described above are shown in order as indicated by arrows, these steps are not necessarily executed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders.
In one embodiment, as shown in FIG. 4, a server firmware start-up optimization system is provided, the system comprising:
the SCP starting module 1 is used for responding to the starting of SCP firmware and executing preset lightweight initialization on the on-chip cache; the lightweight initialization comprises power-on initialization, clock initialization and chip core register initialization;
the Hostboot starting module 2 is used for starting the Power big core and guiding the Hostboot firmware to start when the lightweight initialization execution is completed, and starting the Skiboost firmware after the basic initialization execution of the Hostboot firmware is completed;
the Skiboost starting module 3 is used for responding to the completion of the execution of the basic initialization of the Skiboost firmware and executing the initialization of a plurality of IP cores according to a preset IP core initialization sequence; the IP core initialization sequence is that after the initialization of the interconnection bus and the initialization of the memory are completed in sequence, the initialization of other IP cores is executed;
And the address remapping module 4 is used for moving the firmware codes corresponding to the firmware from the on-chip caches to the corresponding physical memory addresses when the memory initialization is completed, and after remapping the CPU address space to the physical memory, jumping to the corresponding physical memory addresses to continue operation.
For specific limitation of a server firmware start-up optimization system, reference may be made to the limitation of a server firmware start-up optimization method, and corresponding technical effects may be equally obtained, which is not described herein. The above-described modules in a server firmware start-up optimization system may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
Fig. 5 shows an internal structural diagram of a computer device, which may be a terminal or a server in particular, in one embodiment. As shown in fig. 5, the computer device includes a processor, a memory, a network interface, a display, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by a processor, implements a server firmware boot optimization method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It will be appreciated by those of ordinary skill in the art that the architecture shown in fig. 5 is merely a block diagram of some of the architecture relevant to the present application and is not intended to limit the computer device on which the present application may be implemented, and that a particular computing device may include more or fewer components than shown, or may combine certain components, or have the same arrangement of components.
In one embodiment, a server is provided that includes a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method when executing the computer program.
In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, implements the steps of the above method.
In summary, the method, the device and the storage system for optimizing the starting of the server firmware provided by the embodiment of the invention realize that when the starting of the SCP firmware is completed, the preset on-chip cache is executed, the technical scheme including Power-on initialization, clock initialization and chip core register initialization light-weight initialization is executed, when the execution of the light-weight initialization is completed, the large Power core is started and the Hostboot firmware is guided to start to complete the corresponding basic initialization, the Skiboost firmware is started, and the execution of the basic initialization of the Skiboost firmware is completed, the initialization of a plurality of IP cores is executed according to the preset IP core initialization sequence, when the memory initialization is completed, firmware codes corresponding to the firmware are carried to corresponding physical memory addresses from the on-chip cache, and after the CPU address space is remapped to the physical memory, the technical scheme is changed to the corresponding physical memory addresses, the technical scheme is continuously operated, the method is realized by moving the large and important IP initialization including interconnection buses and memory to the start-up core through the IP initialization after the start-up phase of the Hostboot firmware to the corresponding basic initialization, the execution of the Skiboost firmware is completed, the time is shortened by combining the memory address mapping scheme with the memory address space of the CPU to the memory address of the memory core, the memory address of the memory is not mapped to the memory address of the CPU, the memory is greatly reduced, the time is shortened by the time-saving and the time is reduced by the time-saving mechanism, the memory space of the system is increased, and the memory space is conveniently and the memory-saving and the memory space is conveniently and the time-saving and the memory-saving system is greatly increased by the time. The system starting efficiency is improved, abnormal starting risks caused by data change due to level jump in the address switching process can be effectively avoided, reliable guarantee is provided for normal and stable starting of the system, the system starting speed improvement bottleneck of integrating initialization of a plurality of IP cores, carrying linux cores at low speed and the like can be further broken through by utilizing multithreading, firmware starting duration is comprehensively reduced, and system starting efficiency is guaranteed.
In this specification, each embodiment is described in a progressive manner, and all the embodiments are directly the same or similar parts referring to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments. It should be noted that, any combination of the technical features of the foregoing embodiments may be used, and for brevity, all of the possible combinations of the technical features of the foregoing embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples represent only a few preferred embodiments of the present application, which are described in more detail and are not thereby to be construed as limiting the scope of the invention. It should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and substitutions should also be considered to be within the scope of the present application. Therefore, the protection scope of the patent application is subject to the protection scope of the claims.
Claims (10)
1. A method for server firmware start-up optimization, the method comprising the steps of:
responding to SCP firmware start, executing preset lightweight initialization on the on-chip cache; the lightweight initialization comprises power-on initialization, clock initialization and chip core register initialization; the chip core register initialization includes mapping a CPU address space to an on-chip cache;
when the light-weight initialization execution is completed, a Power big core is started, the Hostboot firmware is guided to be started, and after the basic initialization execution of the Hostboot firmware is completed, the Skiboost firmware is started;
responding to the completion of the execution of the basic initialization of the Skiboost firmware, and executing the initialization of a plurality of IP cores according to a preset IP core initialization sequence; the IP core initialization sequence is that after the initialization of the interconnection bus and the initialization of the memory are completed in sequence, the initialization of other IP cores is executed;
when the memory initialization is completed, carrying the firmware codes corresponding to the firmware from the on-chip cache to the corresponding physical memory addresses, and after remapping the CPU address space to the physical memory, jumping to the corresponding physical memory addresses to continue operation; the remapping the CPU address space to the physical memory includes mapping the CPU address space to the physical memory after clearing the mapping relationship between the CPU address space and the on-chip cache, and mapping the on-chip cache to other address spaces outside the physical memory address range.
2. The server firmware start-up optimization method of claim 1, wherein the step of initializing the chip core register comprises:
presetting an address remapping register;
and initializing the mapping state of the address remapping register to map the CPU address space to an on-chip cache.
3. The server firmware start-up optimization method of claim 2, wherein the step of remapping the CPU address space to physical memory comprises:
sending a cache mapping destruction signal to the address remapping register so that the address remapping register clears the mapping relation between a CPU address space and the on-chip cache according to the cache mapping destruction signal;
after the mapping relation between the CPU address space and the on-chip cache is destroyed, sending a physical memory mapping signal to the address remapping register, so that the address remapping register maps the CPU address space to the physical memory according to the physical memory mapping signal, and updating the mapping state of the address remapping register;
after the mapping state of the address remapping register is updated, a cache remapping signal is sent to the address remapping register, so that the address remapping register maps the on-chip cache to other address spaces outside the physical memory address range according to the cache remapping signal.
4. The server firmware start-up optimization method of claim 3, wherein the lightweight initialization further comprises: initializing an ECC check address range according to a preset physical memory address range;
after the step of remapping the CPU address space to the physical memory, the method further includes:
and carrying out ECC check on the data stored in the ECC check address range, and restarting SCP firmware when the check fails.
5. The server firmware start-up optimization method of claim 3 or 4, wherein the step of starting up a Power corelet comprises:
and creating task threads with preset thread numbers by setting a starting state bit of a Power big core register.
6. The server firmware start-up optimization method as set forth in claim 5, wherein the step of performing initialization of a plurality of IP cores in a preset IP core initialization order comprises:
and calling a task thread, starting a multithreading task, and executing initialization of a plurality of IP cores according to a preset IP core initialization sequence.
7. The server firmware start-up optimization method of claim 6, wherein the method further comprises:
responding to a reading task of a linux kernel, dividing the linux kernel into corresponding linux kernel segments according to the preset thread number and the preset kernel loading priority, and distributing the linux kernel segments to each thread according to a preset multithreading task scheduling mechanism.
8. A server firmware initiated optimization system, the system comprising:
the SCP starting module is used for responding to the starting of SCP firmware and executing preset lightweight initialization on the on-chip cache; the lightweight initialization comprises power-on initialization, clock initialization and chip core register initialization; the chip core register initialization includes mapping a CPU address space to an on-chip cache;
the Hostboot starting module is used for starting the Power big core and guiding the Hostboot firmware to start when the lightweight initialization execution is completed, and starting the Skiboost firmware after the basic initialization execution of the Hostboot firmware is completed;
the Skiboost starting module is used for responding to the completion of the execution of the basic initialization of the Skiboost firmware and executing the initialization of a plurality of IP cores according to a preset IP core initialization sequence; the IP core initialization sequence is that after the initialization of the interconnection bus and the initialization of the memory are completed in sequence, the initialization of other IP cores is executed;
the address remapping module is used for moving the firmware codes corresponding to each firmware from the on-chip cache to the corresponding physical memory addresses when the memory initialization is completed, and after remapping the CPU address space to the physical memory, jumping to the corresponding physical memory addresses to continue operation; the remapping the CPU address space to the physical memory includes mapping the CPU address space to the physical memory after clearing the mapping relationship between the CPU address space and the on-chip cache, and mapping the on-chip cache to other address spaces outside the physical memory address range.
9. A server comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method of any of claims 1 to 7 when the computer program is executed.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.
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