WO2022046105A1

WO2022046105A1 - Bios update

Info

Publication number: WO2022046105A1
Application number: PCT/US2020/048739
Authority: WO
Inventors: Rosilet Retnamoni BRADUKE; Wei Ze Liu; Rajesh A SHAH; Mark A. Piwonka; Stanley Hyojun PARK
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2020-08-31
Filing date: 2020-08-31
Publication date: 2022-03-03

Abstract

An example computing device may include a random-access memory, a basic input/output system (BIOS) memory storing a first ordered group of initialization instructions in a first firmware volume of the BIOS memory, and a central processing unit (CPU). The CPU is to store an update for the first ordered group of initialization instructions in a second firmware volume of the BIOS memory, and store a second ordered group of initialization instructions in the second firmware volume, wherein the second ordered group of initialization instructions are different from an update of initialization instructions. The CPU is to copy the update and the second group of initialization instructions to the random-access memory.

Description

BIOS UPDATE

BACKGROUND

[0001] A basic input/output system (BIOS) comprises hardware or hardware instructions to initialize, control, or operate a computing device prior to execution of an operating system of the computing device. The BIOS of a computing device is sometimes updated following its release to add more features, to address reported field issues, or mitigate security vulnerabilities.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 is a block diagram schematically illustrating portions of an example computing device.

[0003] Figure 2 is a block diagram schematically illustrating portions of an example computing device.

[0004] Figure 3 is a block diagram schematically illustrating portions of an example computer-readable medium.

[0005] Figure 4 is a block diagram schematically illustrating portions of an example computing device.

[0006] Figure 5 is a block diagram schematically illustrating portions of an example computing device.

[0007] Figure 6 the block diagram schematically illustrating an example a pre-extensible firmware interface update.

[0008] Figure 7 is a block diagram schematically illustrating an example driver execution environment update. [0009] Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements. The figures are not necessarily to scale, and the size of some parts may be exaggerated to more clearly illustrate the example shown. Moreover, the drawings provide examples and/or implementations consistent with the description; however, the description is not limited to the examples and/or implementations provided in the drawings.

DETAILED DESCRIPTION OF EXAMPLES

[00010] Disclosed are example computing devices and central processing unit (CPU) instructions that may reduce the time and expense associated with updating a BIOS. As used herein, a basic input/output system (BIOS) refers to hardware or hardware and instructions to initialize, control, or operate a computing device prior to execution of an operating system (OS) of the computing device. Instructions included within a BIOS may be software, firmware, microcode, or other programming that defines or controls functionality or operation of a BIOS. In one example, a BIOS may be implemented using instructions, such as platform firmware of a computing device, executable by a processor. A BIOS may operate or execute prior to the execution of the OS of a computing device. A BIOS may initialize, control, or operate components such as hardware components of a computing device and may load or boot the OS of computing device.

[00011] In some examples, a BIOS may provide or establish an interface between hardware devices or platform firmware of the computing device and an OS of the computing device, via which the OS of the computing device may control or operate hardware devices or platform firmware of the computing device. In some examples, a BIOS may implement the Unified Extensible Firmware Interface (UEFI) specification or another specification or standard for initializing, controlling, or operating a computing device. [00012] The example computing devices disclosed herein may employ a BIOS in accordance with the Unified Extensible Firmware Interface (UEFI) standard. The UEFI standard specifies several boot variables which may be updated while the system is operating to adjust how the BIOS operates. The UEFI boot process may be divided into two stages: the initialization of firmware (drivers) and the loading of the operating system. Prior to the initialization of the drivers, referred to as the driver execution environment (DXE) phase, the boot of the computing device may undergo a pre-EFI (extensible firmware interface) initialization phase. The PEI phase may follow a security phase. During the PEI phase, various specific initial configuration routines for the CPU, chipset and system board are loaded and invoked. During the PEI phase, enough of the system is initialized to allow instantiation of the DXE phase. During the PEI phase, the CPU identifies a system boot path and portions of the system RAM and firmware volumes which may contain the DXE foundation and DXE architecture protocols.

[00013] Firmware volumes comprise the logical structure of the UEFI firmware file system. Each firmware volume may have its own file system. One example of a firmware file system is the PI UEFI architecture. The basic component of a firmware volume may be a firmware file. Each firmware file may have a name, such as a globally unique identifier (GUID), a type (sometimes represented by an 8-bit integer value), an alignment (sometimes aligned to eight bytes) and a size (the size of the data in the firmware file).

[00014] Firmware volumes are provided in a physical storage device that permanently stores firmware code and data. The physical storage device may be a flash component. In some implementations, the physical storage device storing the firmware volumes may comprise other types of nonvolatile memory such as EEPROM and the like.

[00015] Firmware volumes are part of the BIOS memory and are used to store initialization instructions for the CPU. PEI initialization instructions are those instructions used by the CPU to carry out the PEI phase. DXE initialization instructions of those instructions used by the CPU to carry out the DXE phase. Such initialization instructions may be in the form of a firmware file, an ordered group of initialization instructions (OGII). Each ordered group of initialization instructions is a full set of instructions that form a complete executable process. For example, an example PEI OGII may comprise a full set of instructions for initializing access to a memory. An example DXE OGII may comprise a full set of instructions for initializing a particular driver.

[00016] The example computing devices and CPU instructions facilitate incremental updating of the BIOS. Because most components/modules within a BIOS remain unchanged during an update and because only a small portion of the components/modules are changed during the update, the incremental update reduces the time and cost of the update. The example computing devices and CPU instructions may employ a BIOS patch update process which utilizes base firmware volumes and patch or update firmware volumes. During a BIOS update, base firmware volumes are not changed, but the patch or update firmware volumes are updated. During a boot, both of the base and update firmware volumes are verified before execution.

[00017] During an update to the BIOS, the CPU may store an update for an initially released OGII (contained in a base firmware volume) in a second update firmware volume. The CPU may also store subsequently received OGIIs (OGIIs received following the release of the BIOS) in the update firmware volume. During booting, the CPU may copy both the update for the OGII and the subsequently received OGIIs, or their locations, from the update firmware volume to a random-access memory for execution.

[00018] The above example updating process may be utilized for updating PEI initialization instructions and DXE initialization instructions. Initially released PEI initialization instructions may be contained in a base or first PEI firmware volume while PEI initialization instructions updates and post release initialization instructions may be stored in an update or second PEI firmware volume. Likewise, initially released DXE initialization structures may be contained in a base or first DXE firmware volume while updates and postrelease DXE initialization instructions may be stored in an update or second DXE firmware volume.

[00019] In some implementations, an OGII and the update for the OGII may have a same identifier, such as a same GIIID, in first and second respective firmware volumes. In such implementations, the CPU is to copy the update to the random-access memory in response to the CPU determining presence of the same identifier in both of the first firmware volume and the second firmware volume. In some implementations, the CPU is to overwrite any data pertaining to the OGII in the random-access memory with the update. For example, a PEI OGII location or address in the randomaccess memory may be overwritten with a location or address for the update for the PEI OGII. A DXE OGII in the random-access memory may be overwritten with an update for the DXE OGII.

[00020] Disclosed is an example computing device. The Example computing device may include a random-access memory, a basic input/output system (BIOS) memory storing a first ordered group of initialization instructions in a first firmware volume of the BIOS memory, and a central processing unit (CPU). The CPU is to store an update for the first ordered group of initialization instructions in a second firmware volume of the BIOS memory, and is to store a second ordered group of initialization instructions in the second firmware volume, wherein the second ordered group of initialization instructions are different from an update of initialization instructions. The CPU is to copy the update and the second group of initialization instructions to the random-access memory. For purposes of this disclosure, the copying of an update or an ordered group of initialization instructions encompasses the copying of the update or ordered group of initialization instructions, themselves in full, and/or the copying of an address identifying where the update or the ordered group of initialization instructions may be accessed.

[00021] Disclosed is an example computing device that may include a first firmware volume, a second firmware volume, a third firmware volume and a fourth firmware volume. The first firmware volume stores a first ordered group of initialization instructions and a second ordered group of initialization instructions, the first ordered group of initialization instructions and the second ordered group of initialization instructions comprising pre-extensible interface (PEI) initialization instructions. In some implementations, the first and second ordered group of initialization instructions are those provided at the initial release of the BIOS.

[00022] The second firmware volume stores a third ordered group of initialization instructions and a fourth ordered group of initialization instructions. The third ordered group of initialization instructions and the fourth ordered group of initialization instructions comprise driver execution environment (DXE) initialization instructions. In some implementations, the third and fourth ordered group of initialization instructions are those provided at the initial release of the BIOS.

[00023] The third firmware volume stores first and second updates for the first ordered group of initialization instructions and the second ordered group of initialization instructions, respectively. The fourth firmware volume stores third and fourth updates for the third ordered group of initialization instructions and the fourth ordered group of initialization instructions, respectively. The first and second updates and the third and fourth update are received following the initial release of the BIOS. For purposes of this disclosure, the “release” of the BIOS refers to the time that the the production BIOS on a computing device or system which contains base PEI and base DXE ordered groups of initialization instructions, firmware files or executables without any update firmware volume is released. [00024] Disclosed is an example non-transitory computer-readable medium that comprises CPU instructions to direct a CPU of a computing device. The instructions may comprise PEI update storage instructions and PEI update loading instructions. The PEI update storage instructions may direct the CPU to store and update a first ordered group of PEI initialization instructions in a second firmware volume of a BIOS memory, wherein the first ordered group of PEI initialization instructions is stored in a first firmware volume. The CPU instructions may further direct the CPU of the computing device to copy the update (or its location or address) to a random-access memory.

[00025] Figure 1 is a block diagram schematically illustrating portions of an example computing device 20. Computing device 20 facilitates the incremental updating of its BIOS to reduce the time and costs associated with the update. Computing device 20 comprises a random-access memory 24, a BIOS memory 30 and a CPU 40.

[00026] Random-access memory 24 comprises a computer memory that may be read and changed. Examples of random-access memory include, but are not limited to, static random-access memory (SRAM) and dynamic random-access memory (DRAM).

[00027] BIOS memory 30 comprises a persistent memory that is used by a BIOS during the startup of computing device 20. BIOS memory 30 may comprise a flash memory. In some implementation, BIOS memory 30 may comprise other forms of nonvolatile memory, such as EEPROM. BIOS memory 30 comprises a first firmware volume 44 and a second firmware volume 46. First firmware volume 44 serves as a base firmware volume, storing a first ordered group of initialization instructions (OGII 1 ) 50. In some implementations, OGII 50 was contained in firmware volume 44 at the time of initial release of BIOS memory 30 and/or computing device 20. Second firmware volume 46 serves as an update firmware volume, ready to receive patches or updates for those OGIIs in firmware volume 44 and ready to receive subsequently received OGIIs, such as OGIIs received following the initial release of BIOS memory 30 and/or computing device 20.

[00028] Central processing unit 40 comprises a processor through which the operations of computing device 20 are controlled and executed. Central processing 40 may comprise a control unit, and arithmetic logic unit, registers, a cache, buses, and a clock. In some implementations, central processing unit 40 is contained on an integrated circuit chip called a microprocessor.

Central processing 40 stores data, intermediate results, and program instructions.

[00029] As schematically represented by arrow 41 , central processing unit 40 is to store an update 60 for the first OGII 50 stored in firmware volume 44. The storage of update 60 may occur following the provision of OGII 50 in firmware volume 44. In some implementations, the storage of update 60 may occur following the release of BIOS memory 30 and/or computing device 20.

[00030] As schematically represented by arrow 42, CPU 40 is to further store a second OGII 62 in the second firmware volume 46. The second OGII 62 is not an update to any OGII stored in firmware volume 44 or stored in BIOS memory 30. In some implementations, OGII 62 is received following the provision of OGII 50 in firmware volume 44. In some implementations, OGII 62 is received following the storage of update 60. In some implementations, OGII 62 is received and stored following the release of BIOS memory 30 and computing device 20.

[00031] As indicated by arrows 43 and 44, central processing 40 is to copy both the update 60 and the OGII 62 from the firmware volume 46 to the random-access memory 24. In some implementations, such copying involves copying of the file itself. In other implementations, such copying involves the copying or writing of the address identifying the location at which the update and the OGII may be accessed. For example, in implementations where the OGII being copied is a PEI OGII, the address or location of the PEI OGII is copied to the random-access memory 24. In implementations where the OGII being copied is a DXE OGII, such as a driver, the driver itself is copied to the random-access memory 24. Thereafter, the update 60 and the OGII 62 may be executed by CPU 40 using the contents of the random-access memory 24. Because both updates and newly uploaded OGIIs may be stored in the same update firmware volume 46 and thereafter copied to the random-access memory 24 for execution, updating of the BIOS may be faster and less costly.

[00032] Figure 2 is a block diagram schematically illustrating portions of an example computing device 120. Figure 2 illustrates an example of how updates to a PEI OGII may be incrementally carried out to reduce the time and cost of a PEI update. Computing device 120 comprises random-access memory 24 (described above), BIOS memory 130 and CPU 40.

[00033] BIOS memory 130 comprises a persistent memory that is used by a BIOS during the startup of computing device 120. BIOS memory 130 may comprise a flash memory. In some implementation, BIOS memory 130 may comprise other forms of nonvolatile memory, such as EEPROM. BIOS memory 130 comprises a first firmware volume 144 and a second firmware volume 146. First firmware volume 144 serves as a base firmware volume, storing a first PEI ordered group of initialization instructions (OGII 1 ) 150. In some implementations, OGII1 50 was contained in firmware volume 144 at the time of initial release of BIOS memory 130 and/or computing device 120. Second firmware volume 146 serves as an update firmware volume, ready to receive patches or updates for those OGIIs in firmware volume 144.

[00034] Central processing unit 140 comprises a processor through which the operations of computing device 120 are controlled and executed CPU 140 may comprise a control unit, and arithmetic logic unit, registers, a cache, buses, and a clock. In some implementations, CPU 140 is s contained on an integrated circuit chip called a microprocessor. CPU 140 stores data, intermediate results, and program instructions.

[00035] CPU 140 comprises a BIOS update tool 147. BIOS update tool 147 comprises a set of instructions stored in a non-transitory computer- readable medium, such as a persistent memory, for carrying out updates of the PEI OGII in firmware volume 144. As schematically represented by arrow 141 , CPU 140 is to store a PEI update 160 for the first PEI OGII 150 stored in firmware volume 144. The storage of PEI update 160 may occur following the provision of PEI OGII 150 in firmware volume 144. In some implementations, the storage of PEI update 160 may occur following the release of BIOS memory 130 and/or computing device 120.

[00036] As indicated by arrow 143, CPU 140 is to copy the PEI update 160 from the firmware volume 146 to the random-access memory 24. In one implementation, CPU 140 is to copy a location or address for the PEI update 160 to the random-access memory 24. Thereafter, the PEI update 160 may be executed by CPU 140 using the address location from the random-access memory 24. Because the PEI update is stored in a separate firmware volume as compared to the PEI OGII for which it updates, updating of the PEI initialization instructions may be carried out in an incremental fashion, reducing the cost and time associated with a PEI update.

[00037] Figure 3 is a block diagram schematically illustrating portions of an example non-transitory computer-readable medium 241 . Figure 3 illustrates an example BIOS update tool, such as a BIOS update tool 147, which directs CPU 140 to carry out updates to the PEI initialization instructions stored in a BIOS memory. As schematically shown by Figure 3, computer-readable medium 241 comprises PEI update storage instructions 270 and PEI update loading instructions 274.

[00038] PEI update storage instructions 270 are to direct a CPU, such as CPU 140, to store an update for a first PEI OGII, in a second firmware volume of a BIOS memory, wherein the first PEI OGII is stored in a first firmware volume. PEI update loading instructions 274 are to direct the CPU to copy the address or location of the update, from the second firmware volume of the BIOS, to a random-access memory to facilitate execution of the PEI update.

[00039] Figure 4 is a block diagram schematically illustrating portions of an example computing device 320. Figure 4 illustrates an example BIOS memory 330 containing various firmware volumes storing OGIIs and updates to facilitate both the incremental updating of PEI OGIIs and the incremental updating of the DXE OGIIs, such as drivers. As should be appreciated, computing device 320 may comprise additional components such as a CPU and a random-access memory, amongst others.

[00040] BIOS memory 330 comprises first firmware volume 342, second firmware volume 344, third firmware volume 346, and fourth firmware volume 348. First firmware volume 342 comprises a base firmware volume which stores PEI OGIIs which were part of the original BIOS memory 330 upon release of computing device 320. First firmware volume 342 stores a first PEI OGII 350-1 and a second PEI OGII 350-2.

[00041] Second firmware volume 344 comprises a patch or update firmware volume (sometimes referred to as a “recovery” firmware volume) which stores updates to the PEI OGIIs stored in firmware volume 342.

Second firmware volume 344 stores PEI update 360-1 and PEI update 360-2 which are updates to the existing PEI OGIIs 350-1 and 350-2, respectively. In some implementations, second firmware volume 344 may additionally store PEI OGIIs which are different from or different than any update to an original PEI OGII. For example, firmware volume 344 may store a PEI OGII that is received following the provision of OGIIs 350-1 and 350-2 in firmware volume 342. In some implementations, firmware volume 344 may store a PEI OGII that is received following the storage of update 360-1 and/or update 360-2. In some implementations, firmware volume 344 may store a PEI OGII that is received and stored following the release of BIOS memory 330 and computing device 320.

[00042] Third firmware volume 346 comprises a base firmware volume which stores DXE OGIIs which were part of the original BIOS memory 330 upon release of computing device 320. First firmware volume 346 stores DXE OGII 352-1 and second DXE OGII 352-2.

[00043] Fourth firmware volume 348 comprises a patch or update firmware volume which stores updates to the DXE OGIIs stored in firmware volume 342. Second firmware volume 344 stores DXE update 362-1 and DXE update 362-2 which are updates to the existing DXE OGIIs 352-1 and 352-2, respectively. In some implementations, fourth firmware volume 348 may additionally store DXE OGIIs which are different from or different than any update to an original DXE OGII. For example, firmware volume 348 may store a DXE OGII that is received following the provision of OGIIs 352-1 and 352-2 in firmware volume 346. In some implementations, firmware volume 348 may store a DXE OGII that is received following the storage of update 362-1 and/or update 362-2. In some implementations, firmware volume 348 may store a DXE OGII that is received and stored following the release of BIOS memory 330 and computing device 320.

[00044] Figure 5 is a block diagram schematically illustrating portions of an example computing device 420. Figure 5 illustrates additional components and specific components that a computing device, similar to computing devices 20 and 120, may incorporate. Computing device 420 comprises random-access memory in the form of dynamic random-access memory (DRAM) 424, persistent memory 426, embedded controller 428, BIOS memory 430 and CPU 440.

[00045] DRAM 424 comprises a volatile memory for storing executable files to be run by CPU 440 during the startup of computing device 420. Persistent memory 426 comprises a non-volatile memory for storing applications/programs, data, and the output of CPU 440, such as the output resulting from the execution of applications or programs by CPU 440. In some implementations, persistent memory 426 comprises a flash memory. In some implementations come persistent memory 426 comprises a hard disk drive or other non-volatile memory.

[00046] Embedded controller 428 comprises a core system component that is on in response to power being supplied to a mainboard. Embedded controller 428 may have its own random-access memory independent of DRAM 424. Embedded controller 428 may additionally have a dedicated flash read-only memory on which the controller software is stored. Embedded controller 428, sometimes known as a “keyboard controller BIOS” may be used as a keyboard controller. Embedded controller 428 make carry out tasks such as turning computing device 420 on-and-off, receiving and processing signals from keyboards and touchpads, managing battery charging and the like. In the example illustrated, embedded controller 428 cooperates with CPU 440 to carry out the initial security phase in which the various firmware volumes in the BIOS memory are verified.

[00047] BIOS memory 430 is similar to BIOS memory 30, 130 and 330 described above. BIOS memory 430 may be in the form of a serial peripheral interface (SPI) Flash. BIOS memory 430 comprises boot/update instructions 441 and firmware volumes 442. Boot/update instructions 441 comprises instructions that direct the addition of new, post-release PEI and DXE OGIIs and the updating of PEI and DXE OGIIs in the firmware volume 442 in an incremental fashion to reduce costs and time associate with such updates. Firmware volumes 442 may comprise firmware volume similar to firmware volume 342, 344, 346 and 348 described above. Such firmware volumes 442 may comprise original or base firmware volumes containing PEI and DXE OGIIs at the time of release of BIOS memory 430 and computing device 420. Such firmware volumes 442 may comprise patch or update firmware volumes that store updates to the PEI and DXE OGIIs contained in the base firmware volumes. Patch or update firmware volumes may additionally store postrelease OGIIs, such post-release OGIIs being different than the original base OGIIs, not updating such original base OGIIs. Such post-release OGIIs may be received following the release of computing device 320 and/or BIOS memory 430. Such post-release OGIIs may be received and stored following the storing of the updates.

[00048] CPU 440 is similar to CPUs 40 and 140 described above. CPU 440 may follow the update instructions 441 to store updates and post-release OGIIs in the patch or update firmware volumes in BIOS memory 430. CPU 440 may further follow the upgrade instructions 441 to copy the updates and post-release OGIIs files (or their location addresses) from the patch or update firmware volumes to a random-access memory for execution. In some implementations, CPU 440 copies the addresses for the PEI updates and post-release PEI OGIIs from a PEI patch or update firmware volume to CPU cache 443 of CPU 440. In some implementations, CPU 440 further copies the DXE updates and post-release DXE OGIIs files, such as drivers, from a DXE patch or update firmware volume to DRAM 424. The incremental storing and copying of PEI updates and post-release OGIIs as well as incremental storing and copping of DXE updates and post-release the axion OGIIs reduces the cost and time associated with such updates.

[00049] Figure 6 is a diagram schematically illustrating portions of an example of computing device 420. Figure 6 illustrates an example of how a set of PEI initialization instructions stored in BIOS memory 430 may be incrementally updated and readied for execution. The left side of Figure 6 illustrates an original or initially released BIOS memory 430-A and the copying of such initial PEI initialization files to the CPU cache 443 to ready them for execution prior to the receipt of any updates or post-release OGIIs. As shown by Figure 6, the initially released BIOS memory 430-A is provided in an SPI flash 530 which comprises a recovery or PEI base firmware volume 542 and a main DXE firmware volume 546.

[00050] Firmware volume 542 comprises an associated signature 543 and PEI OGIIs 550-1 , 550-2 and 550-3. Firmware volume 546 comprises an associated signature 547 and DXE OGIIs 552-1 for driver 1 , DXE OGII 550-2 for driver 2, and DXE OGII 552-3 for driver 3. In the example illustrated, firmware volume 546 additionally comprises applications 554 and optional read-only memories (OpROMs) 555.

[00051] During an initial startup of computing device 420, CPU 440 and embedded controller 428 verify the signature 543 of the firmware volume 542. Following such verification, CPU 440 carries out a PEI phase in which a list 570 of the PEI OGIIs discovered in firmware volume 542 is written to CPU cache 443. In addition, CPU 440 further copies the locations 572 of the different PEI OGIIs (the addresses of the PEI OGIIs within firmware volume 542) to the CPU cache 443. Thereafter, the PEI phase may be carried out by the CPU executing the PEI OGIIs using the locations 572 in the CPU cache 443. Following the PEI phase, the DXE phase and loading of the operating system may be carried out.

[00052] The right side of Figure 6 illustrates an updated BIOS memory 430-B and the copying of post-release PEI initialization locations to the CPU cache 443. As shown by Figure 6, following the initial boot of computing device 420 as depicted on the left side of Figure 6, a user or customer may execute a PEI patch update using a signed patch package. Prior to the contents of the patch package 590 being stored, CPU 440 and embedded controller 428 verify its signature. In the example illustrated, the patch package 590 comprises a patch update 560-2 for PEI OGII 550-2 and a postrelease PEI OGII 560-4. Following verification, CPU 440 stores the update 560-2 and the post-release PEI OGII 560-4 in a recovery firmware update volume 544. The recovery firmware update volume 544 comprises a signature 545.

[00053] As shown by Figure 6, following the storage of the update 560-2 and the post-release PEI OGII 560-4, the system reboots. Following such reboot, CPU 440 and embedded controller 428 validate the signature 545 of firmware volume 546. CPU 440 carries out a PEI phase in which CPU 440 writes a list 570’ of the PEI OGIIs and PEI updates discovered in firmware volumes 542 and 546 to CPU cache 443. In addition, CPU 440 further copies the locations 572’ of the different PEI OGIIs and PEI updates (the addresses of the PEI OGIIs and PEI updates within firmware volume 542 and 546) to the CPU cache 443.

[00054] In circumstances where an update is found in firmware volume 546, the location for the earlier version of the same PEI OGII being updated is overwritten or replaced with the location for the PEI update. In the example illustrated, CPU 440 compares the GUIDS of the firmware files in firmware volumes 542 and 546 to identify duplicates. In circumstances where a duplicate GUID is found, CPU 440 overwrites the older existing PEI OGII location in the CPU cache 443 with the address of the update found in firmware volume 546. Thereafter, the PEI phase may be carried out by the CPU executing the PEI OGIIs using the locations 572’ in the CPU cache 443. Following the PEI phase, the DXE phase and loading of the operating system may be carried out.

[00055] Figure 7 illustrates an example of how a set of DXE initialization instructions stored in BIOS memory 430 may be incrementally updated and readied for execution. The left side of Figure 7 illustrates an original or initially released BIOS memory 430-A and the copying of such initial DXE initialization files to the CPU cache 443 to ready them for execution prior to the receipt of any updates or post-release OGIIs.

[00056] Firmware volume 546 comprises an associated signature 547 and DXE OGIIs 552-1 for driver 1 , DXE OGII 550-2 for driver 2, and DXE OGII 552-3 for driver 3. In the example illustrated, firmware volume 546 additionally comprises applications 554 and optional read-only memories (OpROMs) 555.

[00057] Following completion of the PEI phase, CPU 440 and embedded controller 428 verify the signature 547 of the firmware volume 546. Following such verification, CPU 440 carries out a DXE phase in which a list 580 of the DXE OGIIs (drivers) discovered in firmware volume 546 is written to the DRAM 424. Thereafter, the DXE phase may be carried out by the CPU executing the DXE OGIIs found in DRAM 424. Following the DXE phase, the CPU 440 may load the operating system.

[00058] The right side of Figure 7 illustrates an updated BIOS memory 430-B and the copying of post-release PEI initialization locations to the CPU cache 443. In the example illustrated, following the earlier boot, a user or customer may execute an update package with a signed update firmware volume 544. Firmware volume 544 comprises a patch update 562-2 for DXE OGII 552-2 and a post-release DXE OGII 562-4. The update package may further include a signature 549. In some implementations, each of the signatures 543, 545, 547, and 549 are different from one another. Upon receipt of the patch package 591 , CPU 440 and embedded controller 428 verify the signature of the package. Following such verification, CPU 440 stores the firmware volume 548, containing update 562-2 and the postrelease DXE OGII 562-4 in the BIOS SPI flash memory 530.

[00059] As further shown by Figure 7, following the storage of the update 562-2 and the post-release DXE OGII 562-4, the system reboots. Following the reboot, CPU 440 and embedded controller 428 validate the signature 549 of firmware volume 548. CPU 440 carries out a DXE phase in which a list 580’ of the DXE drivers and DXE updates discovered in firmware volumes 544 and 548 is written to DRAM 424. In addition, CPU 440 further copies the drivers 582’ of the list 580’ to the DRAM 424.

[00060] In circumstances where an update is found in firmware volume 548, the earlier version of the same driver being updated, CPU 440 overwrites the existing DXE OGII (driver) in DRAM 424 with the DXE OGII update, the driver update. In the example illustrated, CPU 440 compares the GUIDS of the firmware files in firmware volumes 544 and 548 to identify duplicates. In circumstances where a duplicate GUI is found, CPU 440 overwrites the older existing driver with the new upgraded driver in the list 580’. Thereafter, the boot may continue with the loading of the operating system.

[00061] Although the present disclosure has been described with reference to example implementations, workers skilled in the art will recognize that changes may be made in form and detail without departing from the disclosure. For example, although different example implementations may have been described as including features providing various benefits, it is contemplated that the described features may be interchanged with one another or alternatively be combined with one another in the described example implementations or in other alternative implementations. Because the technology of the present disclosure is relatively complex, not all changes in the technology are foreseeable. The present disclosure described with reference to the example implementations and set forth in the following claims is manifestly intended to be as broad as possible. For example, unless specifically otherwise noted, the claims reciting a single particular element also encompass a plurality of such particular elements. The terms “first”, “second”, “third” and so on in the claims merely distinguish different elements and, unless otherwise stated, are not to be specifically associated with a particular order or particular numbering of elements in the disclosure.

Claims

WHAT IS CLAIMED IS:

1 . A computing device comprising: a random-access memory; a basic input/output system (BIOS) memory storing a first ordered group of initialization instructions in a first firmware volume of the BIOS memory; a central processing unit (CPU) to: store an update for the first ordered group of initialization instructions in a second firmware volume of the BIOS memory; store a second ordered group of initialization instructions in the second firmware volume, wherein the second ordered group of initialization instructions are different from an update of initialization instructions; and copy the update and the second group of initialization instructions to the random-access memory.

2. The computing device of claim 1 , wherein the first ordered group of initialization instructions and the second ordered group of initialization instructions comprise pre-extensible interface (PEI) initialization instructions.

3. The computing device of claim 2, wherein the BIOS memory is to store a third ordered group of initialization instructions in a third firmware volume of the BIOS memory, and wherein the CPU is further to: store a second update for the third ordered group of initialization instructions in a fourth firmware volume of the BIOS memory; store a fourth ordered group of initialization instructions in the second firmware volume of the BIOS memory, the fourth ordered group of initialization are different from an update of initialization instructions, wherein the third ordered group of initialization instructions and the fourth ordered group of initialization instructions comprise driver execution environment (DXE) initialization instructions; and copy the second update and the fourth group of initialization instructions stored in the fourth firmware volume to a second random-access memory.

4. The computing device of claim 1 , wherein the first ordered group of initialization instructions and the second ordered group of initialization instructions comprise driver execution environment (DXE) initialization instructions.

5. The computing device of claim 1 , wherein the first ordered group of initialization instructions and the update for the first ordered group of initialization instructions have a same identifier in the first firmware volume and the second firmware volume, respectively, and wherein the CPU is to copy the update to the random-access memory in response to the CPU determining presence of the same identifier in both of the first firmware volume and the second firmware volume.

6. The computing device of claim 1 , wherein the BIOS memory is to store a third ordered group of initialization instructions in a third firmware volume of the BIOS memory and wherein the CPU is further to: store an update for the third ordered group of initialization instructions in the second firmware volume of the BIOS memory; and copy the update for the third ordered group of initialization instructions stored in the second firmware volume to the randomaccess memory.

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7. The computing device of claim 1 , wherein the first firmware volume has a first security signature and wherein the second firmware volume has a second security signature different than the first security signature.

8. The computing device of claim 1 , wherein the copying of the update stored in the second firmware volume to the random-access memory comprises replacing the first ordered group of initialization instructions stored in the randomaccess memory with the update.

9. A non-transitory computer-readable medium comprising central processing unit (CPU) instructions to direct a CPU of a computing device to: store an update for a first PEI ordered group of initialization instructions, in a second firmware volume of a basic input/output system (BIOS) memory, wherein the first PEI ordered group of initialization instructions is stored in a first firmware volume; and copy the update, from the second firmware volume, to a randomaccess memory.

10. The medium of claim 9, wherein the CPU instructions are to further direct the CPU to store a second ordered group of PEI initialization instructions in the second firmware volume, the second ordered group of PEI initialization instructions not being an update of initialization instructions stored in the BIOS memory.

11 . The medium of claim 9, wherein the BIOS memory is to store a second ordered group of driver execution environment (DXE) initialization instructions in a third firmware volume of the BIOS memory, and wherein the CPU instructions are to further direct the CPU to: 23 store a second update for the second ordered group of DXE initialization instructions in a fourth firmware volume of the BIOS memory; and copy the second update to a second random-access memory.

12. The medium of claim 11 , wherein the CPU instructions are to further direct the CPU to store a fourth ordered group of DXE initialization instructions in the fourth firmware volume of the BIOS memory, wherein the fourth ordered group of DXE initialization instructions are different from an update of initialization instructions.

13. The medium of claim 9, wherein the BIOS memory stores a third ordered group of initialization instructions in a third firmware volume of the BIOS memory and wherein the CPU instructions are to direct the CPU to: store an update for the third ordered group of initialization instructions in the second firmware volume of the BIOS memory; and copy the update for the third ordered group of initialization instructions stored in the third firmware volume to the random-access memory.

14. A computing device comprising: a first firmware volume storing a first ordered group of initialization instructions and a second ordered group of initialization instructions, the first ordered group of initialization instructions and the second ordered group of initialization instructions comprising pre-extensible interface (PEI) initialization instructions; 24 a second firmware volume storing a third ordered group of initialization instructions and a fourth ordered group of initialization instructions, the third ordered group of initialization instructions and the fourth ordered group of initialization instructions comprising driver execution environment (DXE) initialization instructions; a third firmware volume storing first and second updates for the first ordered group of initialization instructions and the second ordered group of initialization instructions, respectively; and a fourth firmware volume storing third and fourth updates for the third ordered group of initialization instructions and the fourth ordered group of initialization instructions, respectively.

15. The computing device of claim 14, wherein the first firmware volume, the second firmware volume, the third firmware volume and the fourth firmware volume have a first security signature, a second security signature, a third security signature, and a fourth security signature respectively.