CN117850899A - Multi-core starting program conversion method and device for domestic DSP - Google Patents
Multi-core starting program conversion method and device for domestic DSP Download PDFInfo
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Abstract
The invention discloses a multi-core starting program conversion method and device of a domestic DSP, belonging to the field of domestic chip application, comprising the following steps: obtaining out files by using a private address compiler of the DSP chip, and merging and converting the out files into dat files by using a conversion tool after copying the out files; referring to the map data mapping file when the out file is generated, positioning all data segments of each kernel stored in the dat file on a cache according to the memory head address and the length of each data segment in the map data mapping file; s300, the located data segment memory address information is changed from a private address to a global address form in sequence; according to the code segment address and the length in the map data mapping file, the code segment data of each of a plurality of cores in the dat file is found, and only the 1 st segment is reserved. The method overcomes the limitation of the existing M6678 multi-core program conversion method and has the advantages of strong applicability and high efficiency.
Description
Technical Field
The invention relates to the field of domestic chip application, in particular to a conversion method and device for a multi-core start program of a domestic DSP.
Background
The integrated electronic system is characterized in that most of functions in the system are realized by filling different software into a general hardware module. The embedded processor commonly used by the general hardware module comprises a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP) and a General Purpose Processor (GPP). The FPGA has rich input and output pins and task parallel executability, the DSP has high-efficiency data processing capability and convenient and flexible debugging development environment, the GPP can effectively support control intensive applications of the non-digital signal processing types, the three embedded processors have advantages, and the three embedded processors are used for running different programs in the integrated system to process different types of tasks, and the powerful performance of the embedded processors is exerted by running the programs in the embedded processors.
The current integrated electronic information system mainly comprises a general Data Processing Module (DPM), a general Signal Processing Module (SPM), a network switching module (RCM), a System Control Module (SCM) and a high-speed mass storage module (MMM). The module is carried out according to the general function framework requirements of the module in the aspects of function unit division and design. The general function framework of the module requires: each module consists of a Module Supporting Unit (MSU), a Processing Unit (PU), a Routing Unit (RU), a Network Interface Unit (NIU), a power source supporting unit (PSE), a Module Physical Interface (MPI) and other units, and standardized and generalized design of module hardware circuits is realized. The MSU is a unit of each hardware module, is generally connected with the system control through a control bus, and is used for receiving a system control instruction to complete board-level management such as power-on control, reset control, program loading, program updating, current acquisition, voltage acquisition, temperature acquisition, health status reporting and the like.
The Feiteng M6678 is a domestic DSP which is fully and independently developed by the national defense science, the single-core floating point theory operation speed reaches 16GFLOPS, and the single-core floating point theory operation speed has a powerful FFT coprocessor, is a dominant DSP chip of the current integrated electronic system, and is generally used for a general signal processing hardware module of the integrated electronic system. The Feiteng M6678 adopts 28nm technology, 8C 66x processors are integrated inside, single-core main frequency is 1Hz, and the single-core Feiteng M6678 is provided with DDR3 controllers, DMA controllers, SRIO interfaces, EMIF interfaces, GPIO interfaces, UART interfaces, SPI interface peripheral equipment, and various power supplies such as cores, SERDES cores, digital IO, DDR, SERDES IO and the like required by work.
In the flash starting mode of M6678, the program to be loaded is cured in flash, and the RBL program in the ROM of the chip after the DSP is reset (the loading starting program cured in ROM after leaving factory, ROM is read only and cannot be modified) will move the program to the designated memory address and complete the loading operation. Before the flash is solidified, the program to be loaded is converted into a file format which can be identified by RBL, and then the file can be used for solidification, and a chip manual provided by national defense science and university contains conversion methods under two use scenes that 8 cores are loaded with 8 different programs respectively and 8 cores are loaded with the same program simultaneously.
The conversion method of 8 cores to load the same program requires that the program is recompiled by using the global addresses of caches L1 and L2 of cores 0-7 to obtain 8 out files, then the 8 out files are converted into a loadable program file by using a conversion tool in a manual and then are solidified into flash, after the DSP is started, the RBL program can respectively move the 8-core program to a target address space according to the global address through the core 0, and then the corresponding cores are informed to start running through inter-core interrupt. The inventor of the invention finds in experiments that the method is only suitable for use in a use scenario that the storage addresses of 8-core program code segments are different, because loadable files are obtained by recompilation of the same program by using L1 and L2 global addresses (different) of cores 0-7, private data of each core are placed on private L1 and L2 spaces for keeping independence, and the code segments further comprise operations for accessing the private data according to the addresses, the 8 executable program code segments obtained by the method are not identical. If the code segments are still placed on the same address, the code segments of cores 0-7 are sequentially moved to the same address and cover the code segment moved last time when the RBL of the chip is moved, and finally, only the code segment of the last moved core 7 is reserved, so that error exception is caused during operation.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a multi-core starting program conversion method and device for a domestic DSP, which have the advantages of strong applicability and high efficiency.
The invention aims at realizing the following scheme:
a multi-core starting program conversion method of domestic DSP comprises the following steps:
s100, obtaining an out file by using a private address compiler of a DSP chip, copying a plurality of out files, and then merging and converting the plurality of out files into a dat file by using a conversion tool;
s200, referring to a map data mapping file when an out file is generated, and positioning all data segments of each kernel stored in the dat file on a cache according to the memory head address and the length of each data segment in the map data mapping file;
s300, the located data segment memory address information is changed from a private address to a global address form in sequence;
s400, finding the code segment data of each of a plurality of cores in the dat file according to the code segment address and the length in the map data mapping file, and only reserving the 1 st segment.
Further, the DSP chip includes a model M6678 chip.
Further, in step S100, the copying of the multiple copies specifically includes copying 8 copies, and the 8 copies are merged and converted into the dat file by using the conversion tool after copying 8 copies.
Further, in step S100, the private address specifically includes: private address in model M6678 DSP chip.
Further, in step S100, the chip conversion tool specifically includes a conversion tool in a chip use manual.
Further, in step S200, the caches specifically include a cache L1 and a cache L2 in the M6678 model DSP chip.
Further, in step S200, the locating all the data segments of each kernel located on the cache in the dat file specifically includes the sub-steps of: and positioning and modifying the related operation of the address information of the data segment in the dat file, and completing the rapid modification of the dat file by writing a simple script tool.
Further, in step S300, the changing the located address information of the data segment from the private address to the global address in sequence specifically includes the sub-steps of: and changing the located memory address information of the data segment from a private address to a global address form of cores 0-7 in sequence.
Further, in step S400, the code segment data of each of the plurality of cores specifically includes code segment data of each of 8 cores, and only the 1 st segment is reserved, and 7 segments after deletion.
The multi-core start-up program conversion device of the domestic DSP comprises a processor and a memory, wherein a program is stored in the memory, and the multi-core start-up program conversion method of the domestic DSP is executed when the program is loaded by the processor.
The beneficial effects of the invention include:
aiming at the limitation of the existing M6678 multi-core program conversion method, the invention provides a multi-core quick start program conversion scheme of domestic DSP Feiteng M6678 for the field on the basis of the start flow of M6678, and the scheme has the following advantages:
1) The applicability is strong: aiming at the conversion method of loading the same program by the multiple cores in the M6678 manual, the method of the invention firstly uses the private address mode to ensure that the code segments of the converted multiple cores still keep the same by the mode of placing the code segments of the multiple cores at the same address, and then ensures the correct movement of the data segments on the premise of not changing the data by respectively modifying the address information of the data segments in the dat file, thereby achieving the full applicability of the multiple cores under the application scene of loading the same program.
2) The efficiency is high: aiming at the conversion method of loading the same program by multiple cores in the M6678 manual, under the condition that the programs are the same, the mode of recompiling the programs by using the global addresses of the cores for conversion can lead to that code segments are not the same, and at the moment, 8-core code segments are required to be placed at different addresses to ensure the correctness of data; the method provided by the invention ensures that all data segments of each core program are completely identical after being converted into the dat file by using the private address, and can finish the work of replacing the private address information of the data segments by using the global address of each core in the dat file in batch by only manufacturing a simple script tool at the moment, thereby ensuring the correct movement of the RBL program to the data. Meanwhile, compared with the method in a chip manual, the code segments of the 8-core program are placed in the same address space as the code segment data (generally more than 60% of the total size) which occupy larger code segments in the program file, so that the use of a memory is saved, and the 8-core code segments are completely identical and only need to be moved once, so that the other 7 times of movement is avoided, and the movement and loading efficiency of the program can be improved by more than one time.
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In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a flow chart of steps of a method according to an embodiment of the present invention.
Detailed Description
All of the features disclosed in all of the embodiments of this specification, or all of the steps in any method or process disclosed implicitly, except for the mutually exclusive features and/or steps, may be combined and/or expanded and substituted in any way.
As shown in fig. 1, the present invention provides a multi-core rapid start program conversion method of a domestic DSP Feiteng M6678 on the basis of knowing the start flow of M6678, aiming at the limitations of the existing M6678 multi-core program conversion method, and aims to overcome the limitations of the existing M6678 multi-core program conversion method, specifically including the following steps:
s100, compiling an application project once by using a private address to obtain an executable out file, copying 8 out files, and then merging and converting the 8 out files into dat files by using a conversion tool provided in a chip manual;
s200, referring to a map data mapping file when an out file is generated, and positioning all data segments of each kernel on L1 and L2 stored in a dat file according to the memory head address and the length of each data segment in the map file;
s300, the located data segment memory address information is changed from a private address to a global address form of cores 0-7 in sequence;
s400, finding out the code segment data of each of 8 cores in the dat file according to the code segment address and the length in the map file, only reserving the 1 st segment, and deleting 7 segments.
In an alternative embodiment, the private address refers to that in M6678, each core has an independent two-level cache memory, namely, a cache L1 and a cache L2, and the access modes of the cache L1 and the cache L2 are also divided into two modes, namely, private address access and global address access. Under the private address mode, each core can access local L1 and L2 (only can access local space) by using the same private address, for example, cores 0 to 7 can access local L2 space by using 512KB address space starting from 0x 00800000; the L1 and L2 address spaces of cores 0-7 are not identical in the global address mode, for example, the L2 global address space head address of core 0 is 0x10800000, the L2 global address space head address of core 1 is 0x11800000, but any core in cores 0-7 can access the L1 and L2 data spaces of the local core and other cores through the global address.
In an alternative embodiment, all data segments required by the normal operation of the executable programs of the cores 0 to 7 are sequentially arranged in the dat file generated by converting the out file by using a chip conversion tool, and the data segments comprise memory addresses and length information of the data segments.
In an alternative embodiment, the related operation of locating and modifying the address information of the data segment in the dat file can be achieved by writing a simple script tool.
In an alternative embodiment, the code segment data of the 8-core program is identical because the private address is used, and the code segment data of the 8-core program can be placed at the same address and only one part is reserved because of the read-only property of the code segment, so that the memory space is saved and the moving efficiency is increased.
In an alternative embodiment, the DSP chip is model M6678.
It should be noted that, within the scope of protection defined in the claims of the present invention, the following embodiments may be combined and/or expanded, and replaced in any manner that is logical from the above specific embodiments, such as the disclosed technical principles, the disclosed technical features or the implicitly disclosed technical features, etc.
Example 1
A multi-core starting program conversion method of domestic DSP comprises the following steps:
s100, obtaining an out file by using a private address compiler of a DSP chip, copying a plurality of out files, and then merging and converting the plurality of out files into a dat file by using a conversion tool;
s200, referring to a map data mapping file when an out file is generated, and positioning all data segments of each kernel stored in the dat file on a cache according to the memory head address and the length of each data segment in the map data mapping file;
s300, the located data segment memory address information is changed from a private address to a global address form in sequence;
s400, finding the code segment data of each of a plurality of cores in the dat file according to the code segment address and the length in the map data mapping file, and only reserving the 1 st segment.
Example 2
Based on the embodiment 1, the DSP chip includes a model M6678 chip.
Example 3
On the basis of embodiment 2, in step S100, the copying includes copying 8 copies, and the 8 copies are merged and converted into the dat file by using the conversion tool after copying 8 copies.
Example 4
On the basis of embodiment 2, in step S100, the private address specifically includes: private address in model M6678 DSP chip.
Example 5
On the basis of embodiment 2, in step S100, the chip converting tool specifically includes a converting tool in a chip instruction manual.
Example 6
On the basis of embodiment 2, in step S200, the cache specifically includes a cache L1 and a cache L2 in the M6678 model DSP chip.
Example 7
On the basis of embodiment 2, in step S200, locating all the data segments of each core located on the cache in the dat file specifically includes the sub-steps of: and positioning and modifying the related operation of the address information of the data segment in the dat file, and completing the rapid modification of the dat file by writing a simple script tool.
Example 8
Based on embodiment 2, in step S300, the changing the located address information of the data segment from the private address to the global address form in sequence specifically includes the following sub-steps: and changing the located memory address information of the data segment from a private address to a global address form of cores 0-7 in sequence.
Example 9
On the basis of embodiment 2, in step S400, the code segment data of each of the plurality of cores specifically includes code segment data of each of 8 cores, and only the 1 st segment is reserved, 7 segments after deletion.
Example 10
The multi-core start-up program conversion device of a domestic DSP, comprising a processor and a memory, wherein a program is stored in the memory, and the multi-core start-up program conversion method of the domestic DSP according to any one of embodiments 1 to 9 is executed when the program is loaded by the processor.
The units involved in the embodiments of the present invention may be implemented by software, or may be implemented by hardware, and the described units may also be provided in a processor. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.
According to an aspect of embodiments of the present invention, there is provided a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The computer instructions are read from the computer-readable storage medium by a processor of a computer device, and executed by the processor, cause the computer device to perform the methods provided in the various alternative implementations described above.
As another aspect, the embodiment of the present invention also provides a computer-readable medium that may be contained in the electronic device described in the above embodiment; or may exist alone without being incorporated into the electronic device. The computer-readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to implement the methods described in the above embodiments.
Claims (10)
1. The multi-core starting program conversion method of the domestic DSP is characterized by comprising the following steps of:
s100, obtaining an out file by using a private address compiler of a DSP chip, copying a plurality of out files, and then merging and converting the plurality of out files into a dat file by using a conversion tool;
s200, referring to a map data mapping file when an out file is generated, and positioning all data segments of each kernel stored in the dat file on a cache according to the memory head address and the length of each data segment in the map data mapping file;
s300, the located data segment memory address information is changed from a private address to a global address form in sequence;
s400, finding the code segment data of each of a plurality of cores in the dat file according to the code segment address and the length in the map data mapping file, and only reserving the 1 st segment.
2. The method for converting a multi-core start-up program of a domestic DSP according to claim 1, wherein the DSP chip comprises a model M6678 chip.
3. The method for converting a multi-core startup procedure of a domestic DSP according to claim 2, wherein in step S100, the copying of the plurality of copies specifically includes copying 8 copies, and the converting tool is used to merge and convert the 8 copies of out files into dat files after copying 8 copies.
4. The method for converting a multi-core start-up program of a domestic DSP according to claim 2, wherein in step S100, the private address specifically includes: private address in model M6678 DSP chip.
5. The method according to claim 2, wherein in step S100, the chip conversion tool specifically includes a conversion tool in a chip instruction manual.
6. The method according to claim 2, wherein in step S200, the cache specifically includes a cache L1 and a cache L2 in a DSP chip of model M6678.
7. The method for converting a multi-core startup procedure of a domestic DSP according to claim 2, wherein in step S200, locating all the data segments of each core located on the cache in the dat file specifically comprises the sub-steps of: and positioning and modifying the related operation of the address information of the data segment in the dat file, and completing the rapid modification of the dat file by writing a simple script tool.
8. The method for converting a multi-core start program of a domestic DSP according to claim 2, wherein in step S300, the step of sequentially changing the located address information of the data segment memory from a private address to a global address comprises the following specific steps: and changing the located memory address information of the data segment from a private address to a global address form of cores 0-7 in sequence.
9. The method according to claim 2, wherein in step S400, the code segment data of each of the plurality of cores specifically includes code segment data of each of 8 cores, and only segment 1 is reserved, and 7 segments after deletion.
10. A multi-core start-up program conversion device of a domestic DSP, comprising a processor and a memory, wherein a program is stored in the memory, and when the program is loaded by the processor, the multi-core start-up program conversion method of the domestic DSP according to any one of claims 1 to 9 is executed.
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