CN117251108A - SLC cache allocation method and device based on solid state disk and computer equipment - Google Patents
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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Abstract
The application relates to a solid state disk-based SLC cache allocation method, a solid state disk-based SLC cache allocation device, computer equipment and a storage medium, wherein the method comprises the following steps: presetting a user buffer idle critical threshold; when the host writes, judging whether the idle space of the SLC user cache is larger than the idle critical threshold of the user cache; if the idle space of the SLC user cache is larger than the idle critical threshold of the user cache, a cache writing state is entered, and the SLC Wordline cache area and the original SLC user cache area participate in the allocation when the writing data space is allocated; if the idle space of the SLC user cache is greater than 0 and less than or equal to the idle critical threshold of the user cache, entering a cache writing critical state, and only allocating the SLC user data cache area when allocating the writing data space. The invention can multiplex the SLC Wordline buffer into the SLC user data buffer for use, and increases the size of the SLC user data buffer, thereby improving the read-write performance of the solid state disk.
Description
Technical Field
The present invention relates to the field of solid state disks, and in particular, to a solid state disk-based SLC cache allocation method, apparatus, computer device, and storage medium.
Background
SSDs (solid state drives) and their widespread use in various applications, have now gradually replaced traditional HDDs (mechanical hard drives) in the PC market, providing users with a better experience in terms of reliability and performance. With the evolution of NAND technology, the NAND technology has evolved from early 1bit/cell (SLC) to 2bit/cell (MLC), 3bit/cell (TLC), 4bit/cell (QLC), and the data capacity stored therein is larger and larger, but the programming model is more and more complicated due to the increase of the bit number of each cell. Typical NAND such as SLC/MLC/TLC can complete data storage by only one-time programming, and then can read normally, while QLC can complete data storage by multiple times of programming due to the complex NAND Cell voltage distribution. In addition, because the influence between adjacent wordlines needs to be eliminated, the multiple times of programming needs to be staggered among a plurality of wordlines, so that the number of wordlines in an unstable state is large, and corresponding data needs to be cached in other places which can be read correctly because the wordlines cannot be read out. For consumer SSDs with limited memory and retention capabilities, SLC is typically used to cache such data, referred to as Wordline cache.
In order to improve the read-write performance, a part of NAND is set to SLC (Single Level Cell) mode and used as SLC user data cache. After being set to the SLC mode, the NAND capacity is only one fourth of that of the QLC mode, but has higher read-write performance. The write performance of SLC mode is typically 20 times or more than that of QLC mode, and the read performance is typically 3 times or more.
In the traditional scheme, the SLC Wordline cache for temporarily storing unstable data during QLC writing and the SLC user data cache for accelerating user writing are independent. Otherwise, when the SLC user data cache is exhausted, no idle SLC is used for the Wordline cache temporary storage of QLC writing, so that the host cannot continue writing.
Disclosure of Invention
Based on the foregoing, it is necessary to provide a solid state disk-based SLC cache allocation method, apparatus, computer device and storage medium for the above technical problems.
An SLC cache allocation method based on a solid state disk, the method comprising:
presetting a user buffer idle critical threshold;
when the host writes, judging whether the idle space of the SLC user cache is larger than the idle critical threshold of the user cache;
if the idle space of the SLC user cache is larger than the idle critical threshold of the user cache, a cache writing state is entered, and the SLC Wordline cache area and the original SLC user cache area participate in the allocation when the writing data space is allocated;
if the idle space of the SLC user cache is greater than 0 and less than or equal to the idle critical threshold of the user cache, entering a cache writing critical state, and only allocating the SLC user data cache area when allocating the writing data space.
In one embodiment, the method further comprises:
if the free space of the SLC user cache is equal to 0, entering a direct writing state, distributing the QLC user area when distributing the writing data space, and simultaneously writing the data into the QLC user area and the SLC Wordline cache area.
In one embodiment, the method further comprises:
and if the buffer memory is in the buffer memory writing critical state, triggering the Wordline buffer memory content to move to the QLC area.
In one embodiment, if the buffer write threshold state is met, the step of triggering the moving of the Wordline buffer content to the QLC area further includes:
and performing flow control on host data writing, wherein the flow control is used for ensuring that when user data caching is used up, the Wordline caching has enough idle blocks for caching unstable data when QLC (quality control logic) writes.
An SLC cache allocation apparatus based on a solid state disk, the apparatus comprising:
the preset module is used for presetting a user buffer idle critical threshold;
the judging module is used for judging whether the idle space of the SLC user cache is larger than the idle critical threshold of the user cache when the host writes;
the first state module is used for entering a cache writing state if the idle space of the SLC user cache is larger than the idle critical threshold of the user cache, and the SLC Wordline cache area and the original SLC user cache area participate in distribution when the data writing space is distributed;
and the second state module is used for entering a buffer write-in critical state if the idle space of the SLC user buffer is larger than 0 and smaller than or equal to the idle critical threshold value of the user buffer, and only the SLC user data buffer area is allocated when the write-in data space is allocated.
In one embodiment, the apparatus further comprises a third status module for:
if the free space of the SLC user cache is equal to 0, entering a direct writing state, distributing the QLC user area when distributing the writing data space, and simultaneously writing the data into the QLC user area and the SLC Wordline cache area.
In one embodiment, the second status module is further configured to:
and if the buffer memory is in the buffer memory writing critical state, triggering the Wordline buffer memory content to move to the QLC area.
In one embodiment, the second status module is further configured to:
and performing flow control on host data writing, wherein the flow control is used for ensuring that when user data caching is used up, the Wordline caching has enough idle blocks for caching unstable data when QLC (quality control logic) writes.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any one of the methods described above when the computer program is executed.
A computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of any of the methods described above.
According to the solid state disk-based SLC cache allocation method, the solid state disk-based SLC cache allocation device, the computer equipment and the storage medium, the user cache idle critical threshold value is preset; when the host writes, judging whether the idle space of the SLC user cache is larger than the idle critical threshold of the user cache; if the idle space of the SLC user cache is larger than the idle critical threshold of the user cache, a cache writing state is entered, and the SLC Wordline cache area and the original SLC user cache area participate in the allocation when the writing data space is allocated; if the idle space of the SLC user cache is greater than 0 and less than or equal to the idle critical threshold of the user cache, entering a cache writing critical state, and only allocating the SLC user data cache area when allocating the writing data space. The invention can multiplex the SLC Wordline buffer into the SLC user data buffer for use, and increases the size of the SLC user data buffer, thereby improving the read-write performance of the solid state disk.
Drawings
Fig. 1 is a schematic diagram of a conventional NAND allocation scheme of an SSD of a QLC NAND;
FIG. 2 is a flow chart of a SLC cache allocation method based on a solid state disk in one embodiment;
FIG. 3 is an inventive concept of a solid state disk-based SLC cache allocation method in one embodiment;
FIG. 4 is a flow chart of a SLC cache allocation method based on a solid state disk in another embodiment;
FIG. 5 is a block diagram of a solid state drive based SLC cache allocation device in one embodiment;
FIG. 6 is a block diagram of an SLC cache allocation device based on a solid state disk in another embodiment;
fig. 7 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
As shown in fig. 1, a conventional NAND allocation scheme of the SSD using the QLC NAND. Specifically, when the host writes, it is determined whether the SLC user cache has free space. If the solid state disk is in the cache writing state, writing the host data into the SLC user data cache area. If the SLC user cache has no free space, the solid state disk is in a direct writing state, and the host data is written into the QLC user area and the SLC Wordline cache area simultaneously. It can be seen that the SLC user data buffer area and the SLC word buffer area of the conventional scheme are independent of each other and are used in a buffer write-in state and a direct write-in state respectively. And the size of the high performance read-write area depends on the size of the SLC user data cache area.
Based on the above, the invention provides a SLC cache allocation method based on a solid state disk, which aims to increase the size of SLC user data cache and improve the read-write performance of the solid state disk.
In one embodiment, as shown in fig. 2, there is provided a solid state disk-based SLC cache allocation method, which includes:
step 202, presetting a user buffer idle critical threshold;
204, when the host writes, judging whether the idle space of the SLC user buffer is larger than the idle critical threshold of the user buffer;
step 206, if the free space of the SLC user cache is greater than the free threshold of the user cache, entering a cache writing state, and when the writing data space is allocated, the SLC Wordline cache area and the original SLC user cache area participate in allocation together;
step 208, if the free space of the SLC user buffer is greater than 0 and less than or equal to the user buffer free threshold, entering a buffer write critical state, and allocating only the SLC user data buffer area when allocating the write data space.
In this embodiment, a solid state disk-based SLC cache allocation method is provided, and when a user writes, if a condition of using SLC user data cache is satisfied, a cache writing state is entered, and when a write data space is allocated, an SLC word cache area participates in allocation together with an original SLC user cache area. If the threshold value for disabling the SLC user data cache is close when the user writes, the buffer writing critical state is entered, and only the SLC user data cache area is allocated when the writing data space is allocated.
Specifically, refer to an inventive concept diagram of a solid state disk-based SLC cache allocation method shown in fig. 3.
First, a user buffer idle threshold is preset, where the value can be customized, for example, 1 SLC data block size.
And then, when the host writes, judging the idle space of the SLC user cache, if the idle space is larger than the idle critical threshold of the user cache, considering that the user cache is sufficient, entering a cache writing state, and when the writing data space is allocated, the SLC Wordline cache area and the original SLC user cache area participate in allocation together.
When the host writes, judging the idle space of the SLC user cache, if the idle space is larger than 0 and smaller than or equal to the idle critical threshold of the user cache, considering that the SLC user cache is nearly exhausted, entering a cache writing critical state, and only allocating the SLC user data cache area when allocating the writing data space.
In one embodiment, the method further comprises: if the free space of the SLC user cache is equal to 0, entering a direct writing state, distributing the QLC user area when distributing the writing data space, and simultaneously writing the data into the QLC user area and the SLC Wordline cache area.
Specifically, when the host writes, judging the idle space of the SLC user cache, if the idle space is equal to 0, considering that the SLC user cache is exhausted, entering a direct writing state, when the writing data space is distributed, distributing the QLC user area, and writing data into the QLC user area and the SLC Wordline cache area simultaneously.
In the above embodiment, the user cache idle critical threshold is preset; when the host writes, judging whether the idle space of the SLC user cache is larger than the idle critical threshold of the user cache; if the idle space of the SLC user cache is larger than the idle critical threshold of the user cache, a cache writing state is entered, and the SLC Wordline cache area and the original SLC user cache area participate in the allocation when the writing data space is allocated; if the idle space of the SLC user cache is greater than 0 and less than or equal to the idle critical threshold of the user cache, entering a cache writing critical state, and only allocating the SLC user data cache area when allocating the writing data space. The invention can multiplex the SLC Wordline buffer into the SLC user data buffer for use, and increases the size of the SLC user data buffer, thereby improving the read-write performance of the solid state disk.
In one embodiment, as shown in fig. 4, there is provided a solid state disk-based SLC cache allocation method, where the method further includes:
step 402, if the buffer write-in critical state is reached, triggering the Wordline buffer content to move to the QLC area;
and step 404, performing flow control on host data writing, wherein the flow control is used for ensuring that when the user data cache is used up, the Wordline cache has enough free blocks for caching unstable data when the QLC writes.
In this embodiment, a solid state disk-based SLC cache allocation method is provided, and the complete implementation steps include:
4.1, preset user buffer idle threshold (the value can be customized, for example, the size of 1 SLC data block).
And 4.2, when the host writes, judging the idle space of the SLC user cache, if the idle space is larger than the idle critical threshold of the user cache, considering that the user cache is sufficient, entering a cache writing state, and when the writing data space is allocated, the SLC Wordline cache area and the original SLC user cache area participate in allocation together.
4.3, when the host writes, judging the idle space of the SLC user cache, if the idle space is larger than 0 and smaller than or equal to the idle critical threshold of the user cache, considering that the SLC user cache is nearly exhausted, entering a cache writing critical state, and when the writing data space is allocated, only allocating the SLC user data cache area;
and 4.4, if the buffer write critical state exists, triggering the moving of the Wordline buffer content to the QLC area, and performing flow control on the host data write. The flow control ensures that when the user data buffer is used up, the Wordline buffer has enough free blocks for buffering unstable data when the QLC writes.
And 4.5, when the host writes, judging the idle space of the SLC user cache, if the idle space is equal to 0, considering that the SLC user cache is exhausted, entering a direct writing state, and when the writing data space is distributed, distributing the QLC user area, and writing data into the QLC user area and the SLC Wordline cache area simultaneously.
In this embodiment, if the buffer writing critical state is reached, the moving of the Wordline buffer content to the QLC area is triggered, and the flow control is performed to the host data writing, so as to ensure that when the user data buffer is used up, the Wordline buffer has enough free space for buffering unstable data when the QLC writing.
It should be understood that, although the steps in the flowcharts of fig. 1-4 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1-4 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily occur in sequence, but may be performed alternately or alternately with at least a portion of the other steps or sub-steps or stages of other steps.
In one embodiment, as shown in fig. 5, there is provided a SLC cache allocation apparatus 500 based on a solid state disk, the apparatus including:
the preset module 501 is configured to preset a user buffer idle critical threshold;
the judging module 502 is configured to judge, when the host writes, whether an idle space of the SLC user cache is greater than the user cache idle critical threshold;
a first state module 503, configured to enter a cache write state if an idle space of the SLC user cache is greater than a user cache idle threshold, and participate in allocation together with an original SLC user cache area when allocating a write data space;
and a second state module 504, configured to enter a buffer write critical state if the free space of the SLC user buffer is greater than 0 and less than or equal to the user buffer free critical threshold, and allocate only the SLC user data buffer area when allocating the write data space.
In one embodiment, as shown in fig. 6, there is provided a SLC cache allocation apparatus 500 based on a solid state disk, and the apparatus further includes a third state module 505, where the third state module is configured to:
if the free space of the SLC user cache is equal to 0, entering a direct writing state, distributing the QLC user area when distributing the writing data space, and simultaneously writing the data into the QLC user area and the SLC Wordline cache area.
In one embodiment, the second status module 504 is further configured to:
and if the buffer memory is in the buffer memory writing critical state, triggering the Wordline buffer memory content to move to the QLC area.
In one embodiment, the second status module 504 is further configured to:
and performing flow control on host data writing, wherein the flow control is used for ensuring that when user data caching is used up, the Wordline caching has enough idle blocks for caching unstable data when QLC (quality control logic) writes.
For specific limitation of the SLC cache allocation apparatus based on the solid state disk, reference may be made to the limitation of the SLC cache allocation method based on the solid state disk, which is not described herein.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 7. The computer device includes a processor, a memory, and a network interface connected by a device bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The nonvolatile storage medium stores an operating device, a computer program, and a database. The internal memory provides an environment for the operation of the operating device and the computer program in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to realize a solid state disk-based SLC cache allocation method.
It will be appreciated by those skilled in the art that the structure shown in fig. 7 is merely a block diagram of some of the structures associated with the present application and is not limiting of the computer device to which the present application may be applied, and that a particular computer device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided that includes a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps in the method embodiments above when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, carries out the steps of the above method embodiments.
Those skilled in the art will appreciate that implementing all or part of the above described embodiment methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. An SLC cache allocation method based on a solid state disk, the method comprising:
presetting a user buffer idle critical threshold;
when the host writes, judging whether the idle space of the SLC user cache is larger than the idle critical threshold of the user cache;
if the idle space of the SLC user cache is larger than the idle critical threshold of the user cache, a cache writing state is entered, and the SLC Wordline cache area and the original SLC user cache area participate in the allocation when the writing data space is allocated;
if the idle space of the SLC user cache is greater than 0 and less than or equal to the idle critical threshold of the user cache, entering a cache writing critical state, and only allocating the SLC user data cache area when allocating the writing data space.
2. The SLC cache allocation method based on a solid state disk of claim 1 wherein said method further includes:
if the free space of the SLC user cache is equal to 0, entering a direct writing state, distributing the QLC user area when distributing the writing data space, and simultaneously writing the data into the QLC user area and the SLC Wordline cache area.
3. The SLC cache allocation method based on solid state disk of claim 2 wherein said method further includes:
and if the buffer memory is in the buffer memory writing critical state, triggering the Wordline buffer memory content to move to the QLC area.
4. The SLC buffer allocation method based on a solid state hard disk of claim 3 wherein the step of triggering the moving of the Wordline buffer contents to the QLC area if the SLC buffer allocation method is in the buffer write critical state further includes:
and performing flow control on host data writing, wherein the flow control is used for ensuring that when user data caching is used up, the Wordline caching has enough idle blocks for caching unstable data when QLC (quality control logic) writes.
5. SLC buffer memory distribution device based on solid state disk, characterized by that, said device includes:
the preset module is used for presetting a user buffer idle critical threshold;
the judging module is used for judging whether the idle space of the SLC user cache is larger than the idle critical threshold of the user cache when the host writes;
the first state module is used for entering a cache writing state if the idle space of the SLC user cache is larger than the idle critical threshold of the user cache, and the SLC Wordline cache area and the original SLC user cache area participate in distribution when the data writing space is distributed;
and the second state module is used for entering a buffer write-in critical state if the idle space of the SLC user buffer is larger than 0 and smaller than or equal to the idle critical threshold value of the user buffer, and only the SLC user data buffer area is allocated when the write-in data space is allocated.
6. The SLC cache allocation apparatus based on a solid state disk of claim 5 further comprising a third state module configured to:
if the free space of the SLC user cache is equal to 0, entering a direct writing state, distributing the QLC user area when distributing the writing data space, and simultaneously writing the data into the QLC user area and the SLC Wordline cache area.
7. The SLC cache allocation apparatus based on a solid state disk of claim 6 wherein said second state module is further configured to:
and if the buffer memory is in the buffer memory writing critical state, triggering the Wordline buffer memory content to move to the QLC area.
8. The SLC cache allocation apparatus based on a solid state disk of claim 7 wherein said second state module is further configured to:
and performing flow control on host data writing, wherein the flow control is used for ensuring that when user data caching is used up, the Wordline caching has enough idle blocks for caching unstable data when QLC (quality control logic) writes.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any one of claims 1 to 4 when the computer program is executed.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 4.
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