CN113986773A - Write amplification optimization method and device based on solid state disk and computer equipment - Google Patents
Write amplification optimization method and device based on solid state disk and computer equipment Download PDFInfo
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- CN113986773A CN113986773A CN202111356137.7A CN202111356137A CN113986773A CN 113986773 A CN113986773 A CN 113986773A CN 202111356137 A CN202111356137 A CN 202111356137A CN 113986773 A CN113986773 A CN 113986773A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
Abstract
The application relates to a write amplification optimization method and device based on a solid state disk, a computer device and a storage medium, wherein the method comprises the following steps: acquiring a write amplification optimization request based on a solid state disk; applying a certain memory space to a host computer for use as an HMB buffer area according to the write amplification optimization request, wherein the HMB buffer area is used for dynamically changing write-in behaviors; judging whether the solid state disk successfully applies to a host HMB buffer area; if the solid state disk successfully applies to a host end HMB buffer area, storing the write data with small granularity of the host in the HMB buffer area, and writing the write data into NAND after the requirement of concurrent read-write granularity is met; and if the solid state disk cannot apply for the host end HMB buffer area, writing the write data with small granularity of the host into the physical blocks of the smaller programming units, and then transferring the write data to the physical blocks of the larger programming units in batches. The scheme provided by the invention effectively reduces the write amplification and improves the reliability of the SSD.
Description
Technical Field
The invention relates to the technical field of storage systems, in particular to a write amplification optimization method and device based on a solid state disk, computer equipment and a storage medium.
Background
With the development of Solid State Disk technology, SSD (Solid State Disk) has been widely used in various occasions, and has gradually replaced traditional HDD (Hard Disk Drive) in PC market, providing better experience for users from the aspects of reliability and performance.
Currently, with the increase in host interface and NAND interface speed, SSD performance requirements are higher. Generally, a conventional SSD has a large DRAM space (e.g., 128MB of DRAM on a 128GB SSD) for storing mapping tables and read/write buffers. For data written by the host, the data can be temporarily stored in a write buffer and written to the NAND after enough data is accumulated. Due to cost/power consumption considerations, reducing DRAM capacity and even completely removing it has become a necessary feature of the product. In such a scenario, the SSD has only a limited Memory (e.g., about 10 MB) and cannot hold a large write buffer, so that data written by the host needs to be written to the NAND in real time. The programming of NAND is granular, typically 48KB for TLC, and typically 16KB for SLC. If the host writes small granularity data intermittently and needs to write TLC, larger waste is caused if NAND programming units are not neat, and write amplification (dividing the data amount actually written by NAND by the data amount needed to be written by the host) is also larger, thereby reducing the service life of the disk.
Disclosure of Invention
In view of the foregoing, it is necessary to provide a write amplification optimization method and apparatus based on a solid state disk, a computer device, and a storage medium.
A write amplification optimization method based on a solid state disk comprises the following steps:
acquiring a write amplification optimization request based on a solid state disk;
applying a certain memory space to a host computer for use as an HMB buffer area according to the write amplification optimization request, wherein the HMB buffer area is used for dynamically changing write-in behaviors;
judging whether the solid state disk successfully applies to a host HMB buffer area;
if the solid state disk successfully applies to a host end HMB buffer area, storing the write data with small granularity of the host in the HMB buffer area, and writing the write data into NAND after the requirement of concurrent read-write granularity is met;
and if the solid state disk cannot apply for the host end HMB buffer area, writing the write data with small granularity of the host into the physical blocks of the smaller programming units, and then transferring the write data to the physical blocks of the larger programming units in batches.
In one embodiment, if the solid state disk successfully applies for the host HMB buffer, the step of storing the host small-granularity write data in the HMB buffer first, and writing the write data in the NAND after the requirement of the concurrent read-write granularity is met further includes:
and the solid state disk maps the HMB buffer area to a local read-write buffer area, and data writing is carried out on the data to be buffered sufficiently.
In one embodiment, if the solid state disk cannot apply for the host HMB buffer, the step of writing the write data of the host with the small granularity into the physical block of the smaller programming unit first and then transferring the write data of the host with the small granularity to the physical block of the larger programming unit in batch further includes:
reserving a small part of area inside the solid state disk as a small programming unit of a user data area, and reserving a relatively large area inside the solid state disk as a large programming unit of the user data area;
when the host writes a small amount of data, the data is preferentially written into the smaller program cells corresponding to the user data area.
In one embodiment, the method further comprises:
when the host is idle, the data in the smaller programming units of the user data area are migrated to the larger programming units of the user data area through the background so as to meet the subsequent writing of the small-particle data of the host.
A write amplification optimization device based on a solid state disk, the device comprising:
the acquisition module is used for acquiring a write amplification optimization request based on the solid state disk;
an application module, configured to apply a certain memory space to a host as an HMB buffer according to the write amplification optimization request, where the HMB buffer is used to dynamically change a write behavior;
the judging module is used for judging whether the solid state disk successfully applies to a host end HMB buffer area;
the first processing module is used for storing the write data with small granularity of the host in the HMB buffer firstly and then writing the write data into the NAND after the requirement of concurrent read-write granularity is met if the solid state disk successfully applies for the host HMB buffer;
and the second processing module is used for writing the write data with small granularity of the host into the physical blocks of the smaller programming units firstly and then transferring the write data to the physical blocks of the larger programming units in batches if the solid state disk cannot apply for the HMB buffer at the host.
In one embodiment, the first processing module is further configured to:
and the solid state disk maps the HMB buffer area to a local read-write buffer area, and data writing is carried out on the data to be buffered sufficiently.
In one embodiment, the second processing module is further configured to:
reserving a small part of area inside the solid state disk as a small programming unit of a user data area, and reserving a relatively large area inside the solid state disk as a large programming unit of the user data area;
when the host writes a small amount of data, the data is preferentially written into the smaller program cells corresponding to the user data area.
In one embodiment, the apparatus further comprises a data migration module configured to:
when the host is idle, the data in the smaller programming units of the user data area are migrated to the larger programming units of the user data area through the background so as to meet the subsequent writing of the small-particle data of the host.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any of the above methods when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of any of the methods described above.
The write amplification optimization method, the write amplification optimization device, the computer equipment and the storage medium based on the solid state disk acquire a write amplification optimization request based on the solid state disk; applying a certain memory space to a host computer for use as an HMB buffer area according to the write amplification optimization request, wherein the HMB buffer area is used for dynamically changing write-in behaviors; judging whether the solid state disk successfully applies to a host HMB buffer area; if the solid state disk successfully applies to a host end HMB buffer area, storing the write data with small granularity of the host in the HMB buffer area, and writing the write data into NAND after the requirement of concurrent read-write granularity is met; and if the solid state disk cannot apply for the host end HMB buffer area, writing the write data with small granularity of the host into the physical blocks of the smaller programming units, and then transferring the write data to the physical blocks of the larger programming units in batches. According to the scheme provided by the invention, the programming strategy is dynamically selected according to the characteristic of HMB (host end memory borrowing) supported by the solid state disk, so that the write amplification is effectively reduced, and the reliability of the SSD is improved.
Drawings
FIG. 1 is a schematic diagram of a typical NAND composition;
FIG. 2 is a schematic diagram of a typical SSD internal write flow;
FIG. 3 is a schematic flow chart illustrating a write amplification optimization method based on a solid state disk in one embodiment;
FIG. 4 is a schematic flow chart illustrating a write amplification optimization method based on a solid state disk in another embodiment;
FIG. 5 is a schematic diagram of a writing method introduced in the present invention;
FIG. 6 is a flow chart illustrating host data writing according to the present invention;
FIG. 7 is a block diagram illustrating an embodiment of an apparatus for optimizing write amplification based on a solid state disk;
FIG. 8 is a block diagram of an apparatus for optimizing write amplification based on a solid state disk according to another embodiment;
FIG. 9 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
As shown in fig. 1, a typical NAND consists of: DIE, independently concurrently operable units; a Block, which is an independently erasable unit, wherein after data at each physical position is written, the whole Block must be erased before the next writing; page, read-write-unit, pages within the same physical block must be programmed in order 0- >1- >2- >3 ….
Existing SSD internal physical blocks typically have two modes, one being smaller program unit physical blocks (e.g., SLC) and one being larger program unit physical blocks (e.g., TLC). The former pages are smaller in size, while the latter pages are larger in size. For ease of illustration, the example of a smaller physical block of program cells (e.g., SLC) having a Page of 16KB and a larger physical block of program cells (e.g., TLC) having a Page of 48KB is used herein for illustration.
As shown in fig. 2, a typical SSD internal write flow includes: the host submits a write command to a front-end module of the SSD; the SSD front-end module splits the command into mapped units (LPAs, typically 4 KB); submitting an operation request to a buffer management module and distributing a write buffer; establishing data transmission with the host according to the allocated buffer area, and informing the host that the command is completed after the data transmission is completed; the mapping table management module is responsible for distributing corresponding physical addresses according to the logical addresses; a mapping table management module for updating a mapping table (L2P) in the memory according to the accessed logical address (LPA) and the allocated physical address (PPA); submitting an operation request to a back-end module, and initiating a NAND write request by the back-end module according to the physical address; waiting for the NAND write operation request to complete.
In this process, the SSD typically accumulates enough data in the write buffer, and the data is written only when the corresponding Page size is satisfied (e.g., 16KB or 48 KB). In the SSD of DRAMLess, since the internal memory of the disc is small, when the data is insufficient (for example, the host writes 4KB of data, and the current SSD needs to be written into the 48K Page of the larger physical block of the programming unit (such as TLC), 44KB of invalid data needs to be filled, which wastes the NAND usage space and causes the write amplification to be large, thereby affecting the service life of the SSD.
Based on the method, the invention provides a DRAMLess write amplification optimization method, and a programming strategy is dynamically selected according to the characteristic that DRAMLess SSD supports HMB (host-side memory borrowing), so that write amplification is effectively reduced, and the reliability of the SSD is improved.
In one embodiment, as shown in fig. 3, a method for optimizing write amplification based on a solid state disk is provided, and the method includes:
step 302, obtaining a write amplification optimization request based on a solid state disk;
step 304, applying a certain memory space to the host according to the write amplification optimization request to serve as an HMB buffer, wherein the HMB buffer is used for dynamically changing write-in behaviors;
step 308, if the solid state disk successfully applies for the host HMB buffer, storing the write data of the host with small granularity in the HMB buffer, and writing the write data into the NAND after the requirement of concurrent read-write granularity is met;
in step 310, if the solid state disk cannot apply for the host HMB buffer, the write data of the host with small granularity is written into the physical block of the smaller programming unit, and then is transferred to the physical block of the larger programming unit in batch.
In this embodiment, a write amplification optimization method based on a solid state disk is provided, and the specific implementation process of the method is as follows:
firstly, a write amplification optimization request based on the solid state disk is obtained. And then, applying a certain memory space to the host according to the write amplification optimization request to serve as an HMB buffer, wherein the HMB buffer is used for dynamically changing write behaviors. Specifically, because the existing dramlless generally supports the HMB (host buffer) characteristic, a certain memory space can be applied for a host.
And then, judging whether the solid state disk successfully applies for the host HMB buffer area. And if the SSD applies to the host end HMB Buffer, storing the write data with small granularity of the host in the HMB Buffer, and writing the write data into the NAND after meeting the requirement of concurrent read/write granularity. If the SSD cannot apply for the host HMB Buffer, the host small-granularity write data is written into the smaller program unit physical block (e.g., SLC) first, and then transferred to the larger program unit physical block (e.g., TLC) in batch. By allocating the data writing in the SSD according to different scenes, the writing performance is met, the writing amplification is greatly reduced, and the reliability of the disc is improved.
In the embodiment, a write amplification optimization request based on a solid state disk is obtained; applying a certain memory space to a host computer for use as an HMB buffer area according to the write amplification optimization request, wherein the HMB buffer area is used for dynamically changing write-in behaviors; judging whether the solid state disk successfully applies to a host HMB buffer area; if the solid state disk successfully applies to a host end HMB buffer area, storing the write data with small granularity of the host in the HMB buffer area, and writing the write data into NAND after the requirement of concurrent read-write granularity is met; and if the solid state disk cannot apply for the host end HMB buffer area, writing the write data with small granularity of the host into the physical blocks of the smaller programming units, and then transferring the write data to the physical blocks of the larger programming units in batches. According to the scheme provided by the embodiment, the programming strategy is dynamically selected according to the characteristics of the HMB supported by the solid state disk, so that the write amplification is effectively reduced, and the reliability of the SSD is improved.
In one embodiment, as shown in fig. 4, a method for optimizing write amplification based on a solid state disk is provided, where the method further includes:
step 402, if the solid state disk successfully applies for a host end HMB buffer, mapping the HMB buffer to a local read-write buffer, and then writing data into the data to be buffered sufficiently;
step 404, if the solid state disk cannot apply for the host HMB buffer, reserving a small area inside the solid state disk as a small programming unit of the user data area, and reserving a relatively large area inside the solid state disk as a large programming unit of the user data area;
step 406, when the host writes a small amount of data, preferentially writing the data into the smaller programming unit corresponding to the user data area;
and step 408, when the host is idle, migrating the data in the smaller programming units of the user data area to the larger programming units of the user data area through the background so as to meet the subsequent writing of the small-particle data of the host.
In this embodiment, referring to fig. 5, a method for completely implementing write amplification optimization based on a solid state disk is provided, where the method specifically includes the following steps:
the conventional DRAMLESS SSD disk basically has no write buffer, so that enough data cannot be accumulated at this time, and the size of the corresponding NAND Page is met. Dramlless generally supports HMB (host buffer) characteristics, and can apply for a certain memory space from a host.
In the scenario of successful application to HMB, the SSD may map it to a local read/write buffer, and as with the SSD with DRAM, buffer enough data for data writing.
In a scene that the HMB cannot be successfully applied, the data cannot be accumulated by means of host buffering; at this time, we reserve a small part of area (user data area-smaller programming unit, such as 16KB) inside the SSD, when the host writes a small amount of data, we preferentially write to the corresponding "user data area-smaller programming unit", and since its Page is smaller than 48KB of "user data area-larger programming unit", the write amplification is smaller when the host data is insufficient.
Further, when the host is idle, the data in the user data area-smaller programming unit can be migrated to the user data area-larger programming unit in the background so as to satisfy the subsequent small-granule data writing of the host.
By the strategy, the write strategy of the data in the SSD is dynamically switched according to whether the HMB successfully allocates the buffer area on the DRAMLess SSD, so that the problem of write amplification caused by insufficient data required by Page in a small data write scene of a host is greatly reduced, and the service life of the SSD is prolonged.
Referring to fig. 6, a flowchart of host data writing according to the present invention is shown, and the specific implementation manner is as follows:
6.1) host write data.
6.2) whether a "larger program cell physical block" is currently being written.
6.2.1) if not, writing the NAND without special processing.
6.2.2) if so, then 6.3.
6.3) whether the host data size meets the Page size required for a "larger program cell physical block".
6.3.1) if yes, writing the NAND without special processing.
6.3.2) if not, then 6.4.
6.4) check if HMB is enabled, the host allocates the corresponding buffer.
6.4.1) if yes, using an HMB buffer area distributed by a host end to fully store the data with the required Page size; the NAND is then written.
6.4.2) if not, then 6.5.
6.5) switch the NAND write point to a "smaller program unit physical block" (corresponding to a Page size of 16KB instead of 48 KB).
6.6) write host data.
6.7) host is idle, moving data from "smaller program cell physical block" that is already full to "larger program cell physical block".
It should be understood that although the various steps in the flow charts of fig. 1-6 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-6 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, as shown in fig. 7, there is provided a solid state disk based write amplification optimization apparatus 700, the apparatus comprising:
an obtaining module 701, configured to obtain a write amplification optimization request based on a solid state disk;
an application module 702, configured to apply a certain memory space to a host as an HMB buffer according to the write amplification optimization request, where the HMB buffer is used to dynamically change a write behavior;
a judging module 703, configured to judge whether the solid state disk successfully applies for the host HMB buffer;
a first processing module 704, configured to store host small-granularity write data in a HMB buffer first if the solid state disk successfully applies for the host HMB buffer, and write the write data into the NAND after a requirement on concurrent read-write granularity is met;
a second processing module 705, configured to, if the solid state disk cannot apply for a host HMB buffer, write data of a small granularity of the host into a physical block of a smaller programming unit, and then transfer the write data to a physical block of a larger programming unit in batch.
In one embodiment, the first processing module 704 is further configured to:
and the solid state disk maps the HMB buffer area to a local read-write buffer area, and data writing is carried out on the data to be buffered sufficiently.
In one embodiment, the second processing module 705 is further configured to:
reserving a small part of area inside the solid state disk as a small programming unit of a user data area, and reserving a relatively large area inside the solid state disk as a large programming unit of the user data area;
when the host writes a small amount of data, the data is preferentially written into the smaller program cells corresponding to the user data area.
In one embodiment, as shown in fig. 8, there is provided a solid state disk-based write amplification optimization apparatus 700, further comprising a data migration module 706 configured to:
when the host is idle, the data in the smaller programming units of the user data area are migrated to the larger programming units of the user data area through the background so as to meet the subsequent writing of the small-particle data of the host.
For specific limitations of the write amplification optimization device based on the solid state disk, reference may be made to the above limitations of the write amplification optimization method based on the solid state disk, and details are not repeated here.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 9. The computer apparatus includes a processor, a memory, and a network interface connected by a device bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The nonvolatile storage medium stores an operating device, a computer program, and a database. The internal memory provides an environment for the operation device in the nonvolatile storage medium and the execution of the computer program. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a solid state disk-based write amplification optimization method.
Those skilled in the art will appreciate that the architecture shown in fig. 9 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method embodiments when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above respective method embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A write amplification optimization method based on a solid state disk is characterized by comprising the following steps:
acquiring a write amplification optimization request based on a solid state disk;
applying a certain memory space to a host computer for use as an HMB buffer area according to the write amplification optimization request, wherein the HMB buffer area is used for dynamically changing write-in behaviors;
judging whether the solid state disk successfully applies to a host HMB buffer area;
if the solid state disk successfully applies to a host end HMB buffer area, storing the write data with small granularity of the host in the HMB buffer area, and writing the write data into NAND after the requirement of concurrent read-write granularity is met;
and if the solid state disk cannot apply for the host end HMB buffer area, writing the write data with small granularity of the host into the physical blocks of the smaller programming units, and then transferring the write data to the physical blocks of the larger programming units in batches.
2. The write amplification optimization method based on the solid state disk of claim 1, wherein if the solid state disk successfully applies for the host HMB buffer, the write data with the small granularity of the host is stored in the HMB buffer, and the step of writing the write data into the NAND after the requirement of the concurrent read-write granularity is met further comprises:
and the solid state disk maps the HMB buffer area to a local read-write buffer area, and data writing is carried out on the data to be buffered sufficiently.
3. The write amplification optimization method based on the solid state disk of claim 2, wherein if the solid state disk cannot apply for the host HMB buffer, the step of writing the write data of the host with the small granularity into the physical block of the smaller programming unit and then transferring the write data of the host with the small granularity to the physical block of the larger programming unit in batch further comprises:
reserving a small part of area inside the solid state disk as a small programming unit of a user data area, and reserving a relatively large area inside the solid state disk as a large programming unit of the user data area;
when the host writes a small amount of data, the data is preferentially written into the smaller program cells corresponding to the user data area.
4. The write amplification optimization method based on the solid state disk, according to claim 3, further comprising:
when the host is idle, the data in the smaller programming units of the user data area are migrated to the larger programming units of the user data area through the background so as to meet the subsequent writing of the small-particle data of the host.
5. A write amplification optimization device based on a solid state disk is characterized by comprising:
the acquisition module is used for acquiring a write amplification optimization request based on the solid state disk;
an application module, configured to apply a certain memory space to a host as an HMB buffer according to the write amplification optimization request, where the HMB buffer is used to dynamically change a write behavior;
the judging module is used for judging whether the solid state disk successfully applies to a host end HMB buffer area;
the first processing module is used for storing the write data with small granularity of the host in the HMB buffer firstly and then writing the write data into the NAND after the requirement of concurrent read-write granularity is met if the solid state disk successfully applies for the host HMB buffer;
and the second processing module is used for writing the write data with small granularity of the host into the physical blocks of the smaller programming units firstly and then transferring the write data to the physical blocks of the larger programming units in batches if the solid state disk cannot apply for the HMB buffer at the host.
6. The solid state disk-based write amplification optimization device of claim 5, wherein the first processing module is further configured to:
and the solid state disk maps the HMB buffer area to a local read-write buffer area, and data writing is carried out on the data to be buffered sufficiently.
7. The solid state disk-based write amplification optimization device of claim 6, wherein the second processing module is further configured to:
reserving a small part of area inside the solid state disk as a small programming unit of a user data area, and reserving a relatively large area inside the solid state disk as a large programming unit of the user data area;
when the host writes a small amount of data, the data is preferentially written into the smaller program cells corresponding to the user data area.
8. The solid state disk-based write amplification optimization device of claim 7, further comprising a data migration module, wherein the data migration module is configured to:
when the host is idle, the data in the smaller programming units of the user data area are migrated to the larger programming units of the user data area through the background so as to meet the subsequent writing of the small-particle data of the host.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method of any of claims 1 to 4 are implemented when the computer program is executed by the processor.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 4.
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| CN202111356137.7A CN113986773A (en) | 2021-11-16 | 2021-11-16 | Write amplification optimization method and device based on solid state disk and computer equipment |
| PCT/CN2022/117584 WO2023087861A1 (en) | 2021-11-16 | 2022-09-07 | Write amplification optimization method and apparatus based on solid state disk, and computer device |
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| CN202111356137.7A CN113986773A (en) | 2021-11-16 | 2021-11-16 | Write amplification optimization method and device based on solid state disk and computer equipment |
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| CN202111356137.7A Pending CN113986773A (en) | 2021-11-16 | 2021-11-16 | Write amplification optimization method and device based on solid state disk and computer equipment |
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| CN (1) | CN113986773A (en) |
| WO (1) | WO2023087861A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023087861A1 (en) * | 2021-11-16 | 2023-05-25 | 深圳忆联信息系统有限公司 | Write amplification optimization method and apparatus based on solid state disk, and computer device |
| CN117472294A (en) * | 2023-12-28 | 2024-01-30 | 合肥康芯威存储技术有限公司 | Memory and data processing method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10642496B2 (en) * | 2016-04-01 | 2020-05-05 | Sandisk Technologies Inc. | Out of order read transfer with host memory buffer |
| KR20180043451A (en) * | 2016-10-19 | 2018-04-30 | 삼성전자주식회사 | Computing system and operating method thereof |
| CN110955384B (en) * | 2018-09-26 | 2023-04-18 | 慧荣科技股份有限公司 | Data storage device and non-volatile memory control method |
| US11507309B2 (en) * | 2020-05-04 | 2022-11-22 | Western Digital Technologies, Inc. | Storage system and method for using memory allocated in a host for read data as a host memory buffer |
| CN113986773A (en) * | 2021-11-16 | 2022-01-28 | 深圳忆联信息系统有限公司 | Write amplification optimization method and device based on solid state disk and computer equipment |
-
2021
- 2021-11-16 CN CN202111356137.7A patent/CN113986773A/en active Pending
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- 2022-09-07 WO PCT/CN2022/117584 patent/WO2023087861A1/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023087861A1 (en) * | 2021-11-16 | 2023-05-25 | 深圳忆联信息系统有限公司 | Write amplification optimization method and apparatus based on solid state disk, and computer device |
| CN117472294A (en) * | 2023-12-28 | 2024-01-30 | 合肥康芯威存储技术有限公司 | Memory and data processing method thereof |
| CN117472294B (en) * | 2023-12-28 | 2024-04-09 | 合肥康芯威存储技术有限公司 | Memory and data processing method thereof |
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| Publication number | Publication date |
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| WO2023087861A1 (en) | 2023-05-25 |
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