CN117241644A - Display panel and display device - Google Patents

Abstract

The embodiment of the disclosure provides a display panel and a display device, wherein the display panel comprises: the substrate base plate, the substrate base plate includes display area and is located the test area of display area one side, and the test area includes: a test control line extending along a first direction configured to provide a first test signal; a voltage bus extending along the first direction and positioned at one side of the test control line close to the display area, wherein the voltage bus is configured to provide a second test signal; and a plurality of groups of test signal lines arranged along the first direction and extending along the second direction, each group of test signal lines including a first sub-signal line and a second sub-signal line, wherein the first sub-signal line is connected with the test control line through at least one first via hole, the first sub-signal line is configured to supply a first test signal to the display area in a test stage, the second sub-signal line is connected with the voltage bus through at least one second via hole, and the second sub-signal line is configured to supply a second test signal to the display area in the test stage.

Description

Display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display panel and a display device.

Background

An Organic Light-Emitting Diode (OLED) device is an electroluminescent device based on an Organic semiconductor material. It should be understood that the thin film transistor (Thin Film Transistor, TFT) is the main driving element in the OLED device at present, i.e. the driving element in the array substrate, directly related to the display performance of the OLED display product.

In general, after the Array process is completed, an Array Test (Array Test) is required to detect the driving performance of the TFT; and after the Cell manufacturing process is finished and before the driving chip is bound, a dot screen Test (Cell Test) is needed to detect whether foreign matters, uneven brightness (mura), bright spots and other defects exist in the screen so as to ensure that the layout wiring and the display function of the display panel are good.

Because the end positions of the Array Test line and the dot screen Test line in the Test area of the display panel are different, the electric potentials on the two wires are inconsistent, static electricity is easy to generate at the Test area, and then static breakdown occurs, so that problems occur in Array Test and Cell Test, and the yield of display products is reduced.

Disclosure of Invention

The embodiment of the disclosure provides a display panel and a display device.

In a first aspect, embodiments of the present disclosure provide a display panel, including: the substrate comprises a display area and a test area positioned at one side of the display area, wherein the test area comprises:

a test control line extending along a first direction configured to provide a first test signal;

a voltage bus extending along the first direction and positioned at one side of the test control line close to the display area, wherein the voltage bus is configured to provide a second test signal;

a plurality of sets of test signal lines arranged in a first direction and extending in a second direction, each set of test signal lines including a first sub-signal line and a second sub-signal line, wherein,

the first sub-signal line is connected with the test control line through at least one first via hole, and the first sub-signal line is configured to provide the first test signal to the display area in a test stage; the second sub-signal line is connected to the voltage bus via at least one second via, the second sub-signal line being configured to provide the second test signal to the display area during a test phase.

In some embodiments, the voltage bus is co-located with the test control line; the first sub-signal line and the second sub-signal line are arranged in the same layer.

In some embodiments, the test region further includes at least one test voltage division pattern, the test voltage division pattern being co-located with the voltage bus,

the test voltage division pattern is located between the test control line and the voltage bus, and the second sub-signal line is connected with the test voltage division pattern through at least one third via hole.

In some embodiments, the substrate base further includes a bonding region between the display region and the test region, the bonding region including a plurality of bonding pads,

each binding pad is provided with a plurality of connecting terminals which are distributed at intervals, and the connecting terminals are used for binding corresponding driving chips or flexible printed circuit boards;

the binding pad and the test control line are arranged on the same layer.

In some embodiments, the second sub signal line and the first sub signal line are connected to the same connection terminal, respectively, in the same group of the test signal lines.

In some embodiments, the test zone includes a plurality of the test partial pressure patterns,

the test voltage division patterns are distributed along the first direction and are arranged at intervals, and each test voltage division pattern is correspondingly connected with one binding pad.

In some embodiments, the test area includes a plurality of repeating units, each of the repeating units including a plurality of sets of test signal lines arranged along the first direction,

and the test voltage division pattern and the binding pad corresponding to the test voltage division pattern are connected through a plurality of second sub-signal lines in the same repeating unit.

In some embodiments, the second sub-signal line is located within the orthographic projection range of the test voltage division pattern correspondingly connected with the second sub-signal line on the substrate, wherein the orthographic projection range of one end of the second sub-signal line, which is far away from the display area, on the substrate;

and a plurality of groups of test signal lines are positioned on one side of the test voltage division pattern away from the substrate base plate.

In some embodiments, in the second direction, an end of the second sub-signal line remote from the display area and an end of the first sub-signal line remote from the display area are flush in the first direction;

and a plurality of groups of test signal lines are positioned on one side of the test voltage division pattern, which is close to the substrate.

In some embodiments, the display area includes a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction, the plurality of gate lines and the plurality of data lines defining a plurality of pixel cells,

one of the first sub-signal lines is correspondingly connected with one of the data lines to provide the first test signal to the data line in the test stage.

In some embodiments, the display area includes a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction, the plurality of gate lines and the plurality of data lines defining a plurality of pixel cells, the pixel cells including pixel driving circuitry, the display area further including a plurality of operating voltage lines extending in the second direction, the operating voltage lines configured to provide an operating voltage to the pixel driving circuitry,

one of the second sub signal lines is correspondingly connected with one of the working voltage lines to supply the second test signal to the working voltage line in the test stage.

In some embodiments, in the same group of the test signal lines, the working voltage line connected to the second sub signal line and the data line connected to the first sub signal line correspond to the same column of the pixel units.

In some embodiments, the voltage bus is further configured to provide an operating voltage for the pixel cells of the display area during the display phase;

the second sub signal line is further configured to supply the operating voltage to the operating voltage line in a display period.

In a second aspect, embodiments of the present disclosure provide a display device including the display panel of the first aspect.

In an embodiment of the disclosure, a first sub-signal line is connected to a test control line through at least one first via hole, and the first sub-signal line is configured to provide a first test signal to a display area; the second sub-signal line is connected with the test voltage division pattern through at least one second via hole, and the second sub-signal line is configured to provide a second test signal to the display area. When the test signal line is located below the test control line, one end of the second sub signal line, which is far away from the display area, is flush with one end of the first sub signal line, which is far away from the display area. By means of the arrangement, the end portions of the two test signal lines are flush, so that potential differences on the first sub signal line and the second sub signal line are equal, and the probability of static electricity generation is effectively reduced. When the test signal line is located above the test control line, since the via hole in the interlayer dielectric layer is already formed, when the conductive material film is coated above the interlayer dielectric layer and patterned to form the test signal line, the test signal line is connected with the test control line or the test voltage division pattern below through the via hole. Further, even if static electricity is formed on the Test signal line, the static electricity can be released by the Test control line or the Test voltage division pattern below, so that the phenomenon of static breakdown can be avoided, the Test effect of the Array Test and the Cell Test is ensured, and the product reliability and the product yield of the display panel are improved.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:

fig. 1 is a schematic structural diagram of a display panel test area according to an embodiment of the disclosure.

Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the disclosure.

Fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the disclosure.

Fig. 4 is a schematic cross-sectional structure of a display area of a display panel according to an embodiment of the disclosure.

Fig. 5 is a schematic view taken along line AA in fig. 3.

Fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the disclosure.

Reference numerals illustrate:

substrate base plate 10: display area AA, binding area BA and test area TA; a pixel unit P;

test area TA: a test control line D-B, a voltage bus VDD, a test voltage division pattern M, a test signal line T, a first sub-signal line T1, a second sub-signal line T2, and a repeating unit Re; a first test pad M1 and a second test pad M2;

the first via hole V1, the second via hole V2 and the third via hole V3;

binding area BA: binding pad ba0, first connection terminal L1, second connection terminal L2;

display area AA: a Data line Data, a gate line GL, a working voltage line vdd;

a first direction X and a second direction Y.

Detailed Description

Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the disclosure, are not intended to limit the disclosure.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present between the layer or element and the other layer or substrate.

In the embodiments of the present disclosure, the a structure is located on the "side far from the substrate" or "above" the B structure, which merely means that the layer of the a structure is formed after the layer of the B structure in the lamination relationship, and does not indicate that there is projection overlap between the a structure and the B structure or that the distance between the a structure and the B structure and the substrate satisfies a specific relationship. In the embodiments of the present disclosure, the a structure is located "on the side of the B structure near the substrate" or "under" only means that the layer of the a structure is formed prior to the layer of the B structure in the lamination relationship, and does not indicate that there is projection overlap between the a structure and the B structure or that the distance between the a structure and the B structure and the substrate satisfies a specific relationship.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

An Organic Light-Emitting Diode (OLED) device is an electroluminescent device based on an Organic semiconductor material. It should be understood that the thin film transistor (Thin Film Transistor, TFT) is the main driving element in the OLED device at present, i.e. the driving element in the array substrate, directly related to the display performance of the OLED display product.

In general, after the Array process is completed, an Array Test (Array Test) is required to detect the driving performance of the TFT; and after the Cell manufacturing process is finished and before the driving chip is bound, a dot screen Test (Cell Test) is needed to detect whether foreign matters, uneven brightness (mura), bright spots and other defects exist in the screen so as to ensure that the layout wiring and the display function of the display panel are good.

However, in the process of manufacturing the display panel, the glass substrate may rub against a machine or air during movement and handling to generate static electricity; and, during patterning of the film, static electricity is also generated during operation of the etching apparatus. When static electricity is accumulated on the glass to a certain degree, a large potential difference is generated, so that the accumulated charges have enough energy to leave the original position and are neutralized by charges with opposite polarity, and the charge movement is completed in a short time, and a large current is generated in the process. Such discharge processes are very damaging and the location of the occurrence is difficult to handle.

Fig. 1 is a schematic structural diagram of a display panel test area according to an embodiment of the disclosure. As shown in fig. 1, the test area of the display panel includes an array test line c1 and a dot screen test line c2, and an array test control line d-b connected to the array test line c1 and a dot screen test control line v-d connected to the dot screen test line c 2. The array test control line d-b and the dot screen test control line v-d extend along a first direction and are arranged on the same layer as a first metal layer, such as a Gate layer, in the display area, and the array test line and the dot screen test line extend along a second direction and are arranged on the same layer as a second metal layer, such as an SD layer, in the display area.

In one example, a dot screen test control line v-d provides a VDD voltage.

And a plurality of voltage division patterns m are also arranged between the array test control line d-b and the dot screen test control line v-d. As is known from the above analysis, the dot screen test is performed in a process before the driving chip is bonded after the completion of the Cell process, and thus, a plurality of voltage division patterns are set to simulate the voltage division result after the driving chip is bonded to provide the same dot screen test voltage as the driving voltage in the display stage to the display area.

It should be understood that the electrostatic protection during the preparation of the display product can control the production environment, such as controlling the humidity of the environment, blowing with an electronic wind in the preparation apparatus, setting a low substrate transfer speed, etc., on the one hand; on the other hand, an electrostatic protection design can be added on the panel, such as series impedance, lightning rod type pattern design, bidirectional protection transistor design and the like. The test area of the display panel has more wires and small space, so the electrostatic protection design can not be additionally arranged to protect the wires.

The Array Test line c1 is connected with the Array Test control line d-b, the dot screen Test line c2 is connected with the voltage division pattern and the dot screen Test control line respectively, so that as in the area A in fig. 1, the positions of the ends of the Array Test line and the dot screen Test line are different, and the potentials on the two wires are inconsistent, so static electricity is easy to generate at the positions, and then the interlayer dielectric layer ILD between the SD layer and the Gate layer is broken down by static electricity, so that short circuit is caused between the adjacent Array Test line and the dot screen Test line, and then the Array Test and the Cell Test are caused to have problems, and the yield of display products is reduced.

In order to solve at least one of the above technical problems, an embodiment of the present disclosure provides a display panel, which effectively avoids static electricity generated in a test area by adjusting positions of array test lines and/or dot screen test lines in the test area of the display panel, and improves product yield of the display panel.

Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure, and fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure, where, as shown in fig. 2 and fig. 3, the display panel includes: the substrate 10, the substrate 10 includes a display area AA and a test area TA located at one side of the display area AA, wherein the test area TA includes: test control lines D-B, voltage bus VDD, and a plurality of sets of test signal lines T.

Wherein the test control line D-B and the voltage bus VDD extend along the first direction X, the voltage bus VDD is positioned at one side of the test control line D-B close to the display area AA and is arranged at the same layer, the test control line D-B is configured to provide a first test signal, and the voltage bus VDD is configured to provide a second test signal; the plurality of groups of test signal lines T are arranged along the first direction X, and each group of test signal lines T comprises a first sub-signal line T1 and a second sub-signal line T2 which are arranged on the same layer and extend along the second direction Y. The test signal line T is used for array test AT and/or dot screen test CT.

Specifically, the first sub-signal line t1 is connected to the test control line D-B through at least one first via hole V1, the first sub-signal line t1 being configured to supply a first test signal to the display area AA during a test phase, the first sub-signal line t1 being connected to a data line (data line) of the display area AA; the second sub signal line t2 is connected to the voltage bus VDD through at least one second via hole V2, and the second sub signal line t2 is configured to supply a second test signal to the display area AA during a test period, and the second sub signal line t2 is connected to a voltage line (VDD line) of the display area AA.

In the display panel provided by the embodiment of the disclosure, a plurality of groups of test signal lines T are arranged in the test area TA, wherein the first sub-signal line T1 is configured to provide a first test signal to the display area AA, and the second sub-signal line T2 is configured to provide a second test signal to the display area AA, so that the test effects of array test and dot screen test are ensured in the preparation process of the display panel, and the product yield of the display panel is improved.

In addition, the two ends of the test control line D-B in the first direction X are provided with first test pads M1 extending out, and in the test stage, the external equipment is connected with the first test pads M1 through the test probes, so that a first test signal is provided for the test control line D-B. Similarly, two ends of the voltage bus VDD in the first direction X are configured with extended second test pads M2, and in the test stage, the external device is connected to the second test pads M2 through the test probes, so as to provide the voltage bus VDD with a second test signal.

In some embodiments, as shown in fig. 2 and 3, the test area TA further includes at least one test voltage division pattern M, where the test voltage division pattern M is disposed on the same layer as the voltage bus VDD, the test voltage division pattern M is located between the test control line D-B and the voltage bus VDD, and the second sub-signal line t2 is connected to the test voltage division pattern M through at least one third via V3. Thus, the voltage division result of the voltage supplied from the voltage bus VDD after the driving chip is bound is simulated by the voltage division pattern to supply the same test voltage (second test signal) as the driving voltage in the display stage to the display area AA.

In some embodiments, the substrate base plate 10 further includes a binding area BA, as shown in fig. 6, between the display area AA and the test area TA. It should be understood that the display panel provided in the embodiments of the present disclosure may be a large-sized display panel, and then a plurality of driving chips or flexible printed circuit boards (Printed Circuit Board, PCB) may be bonded on the bonding area BA of the display panel to provide driving signals to the pixel units P in the display area AA.

In addition, in order to realize the narrow frame design of the display panel, the display panel provided by the embodiment of the disclosure can be packaged by adopting a COF (Chip on flexible printed circuit) process, specifically, the driving chip is integrated on the flexible printed circuit board (Printed Circuit Board, PCB), and the flexible printed circuit board can be bent below the screen by adopting the connection mode, so that the frame is saved, and a higher screen occupation ratio is realized.

In some embodiments, the bonding area BA includes a plurality of bonding pads BA0, each bonding pad BA0 is provided with a plurality of connection terminals distributed at intervals, and the plurality of connection terminals are used for bonding a corresponding driving chip or flexible printed circuit board, that is, each bonding pad BA0 corresponds to one COF area, and the bonding pads BA0 may be disposed in the same layer as the test control line D-B. The plurality of connection terminals include a first connection terminal L1 and a second connection terminal L2, wherein the first connection terminal L1 is connected to the first sub-signal line t1, and the second connection terminal L2 is connected to the second sub-signal line t2.

At this time, a number of test voltage division patterns M corresponding to the bonding pads ba0 may be set such that each test voltage division pattern M provides the same resistance value as the driving chip in the test stage, thereby providing the same test voltage as the driving voltage in the display stage to the voltage bus VDD.

Based on this, in some embodiments, the test area TA includes a plurality of test voltage division patterns M, and the plurality of test voltage division patterns M are arranged along the first direction X and are spaced apart, and each test voltage division pattern M is correspondingly connected to one bonding pad ba0. Specifically, the test area TA includes a plurality of repeating units Re, each of which includes a plurality of sets of test signal lines T arranged in the first direction X, and the test voltage division pattern M and the bonding pad ba0 corresponding thereto are connected through a plurality of second sub-signal lines T2 in the same repeating unit Re.

Fig. 4 is a schematic cross-sectional structure diagram of a display area of a display panel according to an embodiment of the disclosure, as shown in fig. 4, in a display area AA of the display panel, the display panel includes: an active layer Act, a Gate insulating layer GI1, a first conductive layer Gate1, a second insulating layer GI2, a second conductive layer Gate2, a first insulating layer IN, a third conductive layer SD1, a passivation layer PVX, a fourth conductive layer SD2, and a planarization layer PLN are sequentially stacked on the substrate 10.

Wherein, the active layer Act includes: an active pattern act0, a source connection pattern a1, and a drain connection pattern a2 of each thin film transistor in the pixel driving circuit; the first conductive layer Gate1 includes: a grid electrode G, a reset control signal line, a grid line GL, a first electrode C1 of a storage capacitor and a light-emitting control signal line of each thin film transistor in the pixel driving circuit; the second conductive layer Gate2 includes: a reset voltage transmission line and a second pole C2 of the storage capacitor; the third conductive layer SD1 includes: a first pole t1 and a second pole t2 of each thin film transistor in the pixel driving circuit; the fourth conductive layer SD2 includes: data line Data and switching electrode e. And a first electrode (anode) E of the light emitting device is located at a side of the fourth conductive layer SD2 remote from the substrate base plate 10.

As shown in fig. 2, the plurality of sets of test signal lines T are located on one side of the test voltage division pattern M near the substrate 10. Specifically, the display panel test area TA includes a Gate layer and an SD layer, in fig. 2, multiple sets of test signal lines T, that is, the first sub-signal line T1 and the second sub-signal line T2 are both located on the Gate layer, the test control line D-B is located on the SD layer, and the test voltage division pattern M and the test control line D-B are arranged on the same layer, that is, the SD layer further includes the test voltage division pattern M.

It should be understood that the Gate layer in the test area TA in fig. 2 may be disposed in the same layer as any one of the first conductive layer Gate1 and the second conductive layer Gate2 of the display area AA; the SD layer in the test area TA may be disposed in the same layer as any one of the third conductive layer SD1 and the fourth conductive layer SD2 of the display area AA, which is not limited in the embodiment of the present disclosure.

The above-mentioned "same layer arrangement" means that the plurality of structures are formed by the same material layer through the patterning process, so that the plurality of structures formed through the same patterning process are in the same layer in the lamination relation; but this does not mean that the distances between the plurality of structures and the substrate base plate 10 are necessarily the same.

In the process of manufacturing the display panel, the conductive patterns in each film layer are formed through patterning process treatment, and the patterning process comprises the following steps: conductive film coating, exposure, development and etching. The exposure step needs an exposure machine, the etching step needs dry etching equipment, and the two equipment are extremely easy to generate static electricity through multiple experimental observation. In the process of forming the first sub-signal line t1 and the second sub-signal line t2, referring to fig. 1, since the end positions of the two signal lines are different, the electric potentials on the two signal lines are inconsistent, and thus breakdown is easily caused by static electricity generated on etching equipment in the etching process.

Based on this, as shown in fig. 2, in the second direction Y, an end of the second sub signal line t2 away from the display area AA and an end of the first sub signal line t1 away from the display area AA are flush in the first direction X. So set up, because the tip parallel and level of two Test signal lines T, then the potential difference on first sub-signal line T1 and the second sub-signal line T2 equals, has effectively reduced the probability that static produced, and then can not influence the Test effect of Array Test and Cell Test, is favorable to improving display panel's product yield.

Fig. 5 is a schematic cross-sectional view taken along line AA in fig. 3, as shown in fig. 3, an end of the second sub-signal line T2, which is far from the display area AA, is projected onto the substrate 10, and is located within a range of the front projection of the test voltage division pattern M, which is correspondingly connected to the second sub-signal line T, on the substrate 10, and at this time, as shown in fig. 5, a plurality of sets of test signal lines T are located on a side of the test voltage division pattern M, which is far from the substrate 10. That is, the test area TA of the display panel includes a Gate layer and an SD layer, in fig. 3/5, the plurality of sets of test signal lines T, i.e., the first sub-signal line T1 and the second sub-signal line T2 are both located on the SD layer, the test control line D-B is located on the Gate layer, and the test voltage division pattern M and the test control line D-B are arranged on the same layer, i.e., the Gate layer further includes the test voltage division pattern M.

Similarly, the Gate layer in the test area TA in fig. 3 and 5 may be disposed on the same layer as any one of the first conductive layer Gate1 and the second conductive layer Gate2 in the display area AA; the SD layer in the test area TA may be disposed in the same layer as any one of the third conductive layer SD1 and the fourth conductive layer SD2 of the display area AA, which is not limited in the embodiment of the present disclosure.

It should be understood that the SD layer and the Gate layer in the test area TA of the display panel are arranged in an insulating manner, that is, an interlayer dielectric layer is arranged therebetween, and the first sub-signal line t1 is connected to the test control line D-B through at least one first via hole V1 on the interlayer dielectric layer; the second sub-signal line t2 is connected to the test voltage division pattern M through at least one third via hole V3 on the interlayer dielectric layer.

When the structure of the display panel test area TA is as shown in FIG. 3 and FIG. 5, the test control line D-B and the test voltage division pattern M are positioned below the test signal line T, and then in the preparation process, the test control line D-B and the test voltage division pattern M positioned in the Gate layer are etched through patterning treatment; then forming a first via hole V1 and a second via hole V2 in the interlayer dielectric layer; finally, a test signal line T is formed on the SD layer. Specifically, since the via hole in the interlayer dielectric layer has been formed, when the conductive material thin film is coated over the interlayer dielectric layer and patterned to form the test signal line T, the test signal line T is connected to the test control line D-B or the test voltage division pattern M thereunder through the via hole. Further, even if static electricity is formed on the Test signal line T, the static electricity is released by the Test control line D-B or the Test voltage division pattern M below, so that the phenomenon of static breakdown can be avoided, the Test effect of the Array Test and the Cell Test is ensured, and the product reliability and the product yield of the display panel are improved.

Fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the disclosure, and fig. 6 shows other area structures corresponding to the display panel shown in fig. 3. In some embodiments, as shown in fig. 6, the display area AA includes a plurality of gate lines GL extending along the first direction X and a plurality of Data lines Data extending along the second direction Y, the plurality of gate lines GL and the plurality of Data lines Data define a plurality of pixel units P, and each of the first sub-signal lines t1 has a Data line Data correspondingly connected thereto to provide a first test signal to the Data line Data during a test period.

Specifically, the first test signal in the embodiments of the present disclosure is configured to test the performance of the array substrate. The first electrode of the thin film transistor is connected with the Data line Data corresponding to the pixel unit P where the first electrode of the thin film transistor is located, so that each first sub-signal line t1 is connected with the corresponding Data line Data to send a first test signal to the array substrate.

In addition, it should be noted that each pixel unit P in the display area AA may include three sub-pixels, that is, a sub-pixel R with a red emission color, a sub-pixel G with a green emission color, and a sub-pixel B with a blue emission color. Correspondingly, when the test control line D-B provides a first test signal corresponding to the sub-pixel B, the first sub-signal line t1 is connected with the Data line Data connected with the sub-pixel B of the corresponding column; similarly, when the test control line D-B provides the first test signal corresponding to the sub-pixel G, the first sub-signal line t1 is connected to the Data line Data connected to the sub-pixel G in the corresponding column; when the test control line D-B provides the first test signal corresponding to the sub-pixel R, the first sub-signal line t1 is connected to the Data line Data connected to the sub-pixel R of the corresponding column, and the sub-pixel object of the specific array test can be flexibly set by those skilled in the art.

In some embodiments, the pixel unit P includes a pixel driving circuit, and as shown in fig. 6, the display area AA further includes a plurality of operating voltage lines vdd extending in the second direction Y, the operating voltage lines vdd configured to supply operating voltages to the pixel driving circuit, and each of the second sub signal lines t2 has the operating voltage line vdd correspondingly connected thereto to supply the second test signal to the operating voltage line vdd during the test period. In one example, the operating voltage line vdd provides a high level signal.

In the embodiment of the disclosure, the second sub-signal line t2 is connected to the operating voltage line vdd in the display area AA, so as to send the second test signal to the sub-pixels of the corresponding column, so as to implement the array test or the dot screen test.

In some embodiments, as shown in fig. 2, 3 and 6, in the same group of test signal lines T, the working voltage line vdd connected to the second sub-signal line T2 and the Data line Data connected to the first sub-signal line T1 correspond to the same column of pixel units P. I.e. each column of pixel cells P is provided with test signal lines T for dot screen testing and array testing. However, when three sub-pixels are corresponding to one pixel unit P, the first sub-signal line T1 and the second sub-signal line T2 in the same group of test signal lines T correspond to the same column of sub-pixels.

In some embodiments, the voltage bus VDD is configured to provide a second test signal during the test phase; the operating voltage is supplied to the operating voltage line vdd in the display stage.

It should be appreciated that during the test phase, the voltage bus VDD provides a second test signal, which is divided by the test division pattern M to provide an array test or dot screen test voltage to the pixel cells P in the display area AA. In the preparation process of the display product, finally, the test control line D-B, the test voltage division pattern M, part of the first sub-signal line t1 and part of the second sub-signal line in the test area TA are cut off along the line K in FIG. 6 by a laser cutting process, so that the frame area of the display panel is reduced. At this time, in the display stage, the voltage bus VDD provides the operating voltage, and after passing through the driving chip, the operating voltage is provided to the pixel units P in the display area AA. The array test or dot screen test voltage and the working voltage have the same value.

The embodiment of the disclosure also provides a display device comprising the display panel.

The display device may be: any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc., which is not limited in this disclosure.

It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.

Claims (13)

1. A display panel, comprising:

the substrate comprises a display area and a test area positioned at one side of the display area, wherein the test area comprises:

a test control line extending along a first direction configured to provide a first test signal;

a voltage bus extending along the first direction and positioned at one side of the test control line close to the display area, wherein the voltage bus is configured to provide a second test signal;

a plurality of sets of test signal lines arranged in a first direction and extending in a second direction, each set of test signal lines including a first sub-signal line and a second sub-signal line, wherein,

the first sub-signal line is connected with the test control line through at least one first via hole, the first sub-signal line is configured to provide the first test signal to the display area in a test stage, the second sub-signal line is connected with the voltage bus through at least one second via hole, and the second sub-signal line is configured to provide the second test signal to the display area in a test stage.

2. The display panel of claim 1, wherein the voltage bus is co-located with the test control line;

the first sub-signal line and the second sub-signal line are arranged in the same layer.

3. The display panel of claim 1, wherein the test area further comprises at least one test voltage division pattern, the test voltage division pattern being disposed on the same layer as the voltage bus,

the test voltage division pattern is located between the test control line and the voltage bus, and the second sub-signal line is connected with the test voltage division pattern through at least one third via hole.

4. The display panel of claim 3, wherein the substrate base further comprises a bonding region between the display region and the test region, the bonding region comprising a plurality of bonding pads,

each binding pad is provided with a plurality of connecting terminals which are distributed at intervals, and the connecting terminals are used for binding corresponding driving chips or flexible printed circuit boards;

the binding pad and the test control line are arranged on the same layer.

5. The display panel of claim 4, wherein the test area comprises a plurality of the test partial pressure patterns,

the test voltage division patterns are distributed along the first direction and are arranged at intervals, and each test voltage division pattern is correspondingly connected with one binding pad.

6. The display panel of claim 5, wherein the test area comprises a plurality of repeating units, each of the repeating units comprising a plurality of sets of test signal lines arranged along the first direction,

and the test voltage division pattern and the binding pad corresponding to the test voltage division pattern are connected through a plurality of second sub-signal lines in the same repeating unit.

7. The display panel according to claim 6, wherein an end of the second sub-signal line away from the display area is projected on the substrate, and the test partial pressure pattern connected to the second sub-signal line is located within a projected range of the test partial pressure pattern on the substrate;

and a plurality of groups of test signal lines are positioned on one side of the test voltage division pattern away from the substrate base plate.

8. The display panel according to claim 6, wherein in the second direction, an end of the second sub signal line away from the display area and an end of the first sub signal line away from the display area are flush in the first direction;

and a plurality of groups of test signal lines are positioned on one side of the test voltage division pattern, which is close to the substrate.

9. The display panel of claim 7 or 8, wherein the display area includes a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction, the plurality of gate lines and the plurality of data lines defining a plurality of pixel cells,

one of the first sub-signal lines is correspondingly connected with one of the data lines to provide the first test signal to the data line in the test stage.

10. The display panel of claim 9, wherein the display area includes a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction, the plurality of gate lines and the plurality of data lines defining a plurality of pixel cells, the pixel cells including pixel driving circuits, the display area further including a plurality of operating voltage lines extending in the second direction, the operating voltage lines configured to supply an operating voltage to the pixel driving circuits,

one of the second sub signal lines is correspondingly connected with one of the working voltage lines to supply the second test signal to the working voltage line in the test stage.

11. The display panel according to claim 10, wherein the operating voltage line to which the second sub signal line is connected and the data line to which the first sub signal line is connected correspond to the same column of the pixel units in the same group of the test signal lines.

12. The display panel of claim 10, wherein the voltage bus is further configured to provide an operating voltage for the pixel cells of the display area during a display phase;

the second sub signal line is further configured to supply the operating voltage to the operating voltage line in a display period.

13. A display device comprising the display panel of any one of claims 1-12.