CN117241362A - Clock abnormality detection device, method and base station - Google Patents
Clock abnormality detection device, method and base station Download PDFInfo
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- CN117241362A CN117241362A CN202210628491.9A CN202210628491A CN117241362A CN 117241362 A CN117241362 A CN 117241362A CN 202210628491 A CN202210628491 A CN 202210628491A CN 117241362 A CN117241362 A CN 117241362A
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- 238000001514 detection method Methods 0.000 title claims abstract description 125
- 230000005856 abnormality Effects 0.000 title claims abstract description 73
- 238000000034 method Methods 0.000 title claims description 8
- 239000013078 crystal Substances 0.000 claims abstract description 128
- 230000002159 abnormal effect Effects 0.000 claims abstract description 69
- 230000002547 anomalous effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 15
- 230000001360 synchronised effect Effects 0.000 description 8
- 230000010485 coping Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
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- G—PHYSICS
- G04—HOROLOGY
- G04D—APPARATUS OR TOOLS SPECIALLY DESIGNED FOR MAKING OR MAINTAINING CLOCKS OR WATCHES
- G04D7/00—Measuring, counting, calibrating, testing or regulating apparatus
- G04D7/12—Timing devices for clocks or watches for comparing the rate of the oscillating member with a standard
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
Abstract
The embodiment of the application provides a clock abnormality detection device, a clock abnormality detection method and a base station, wherein the device comprises a main clock source unit, at least one standby clock source unit, a crystal oscillator unit, a phase discrimination unit and an abnormality detection unit, wherein the main clock source unit, the standby clock source unit and the crystal oscillator unit are all connected with the phase discrimination unit, and the abnormality detection unit is connected with the phase discrimination unit; the phase discrimination module compares the clock signal of the main clock source unit, the clock signal of the standby clock source unit and the clock signal of the crystal oscillator unit in pairs; the abnormality detection unit determines units with abnormal states in the main clock source unit, the standby clock source unit and the crystal oscillator unit according to the comparison result; whether the states of the clock source unit and the crystal oscillator unit are abnormal or not can be accurately detected, and the clock signal of the local clock of the base station is ensured to be accurate and error-free.
Description
Technical Field
The embodiment of the application relates to the technical field of communication, in particular to a clock abnormality detection device, a clock abnormality detection method and a base station.
Background
The wireless base station requires clock synchronization to make the time signal accurate. The clock device of the base station selects a current main clock source according to the priorities of a plurality of clock sources and the clock source states reported by the clock sources, and synchronizes a local clock to the main clock source; when the main clock source reports an abnormality, the local clock is switched to be synchronous to the standby clock source or maintained by the crystal oscillator. However, the clock source unit deviates from the standard clock and reports the normal state due to the condition of being interfered by fraudulent interference signals, or the problem that the frequency hopping or vibration stopping occurs to the crystal oscillator unit exists, and at the moment, the clock unit cannot judge that the state of the clock source unit or the crystal oscillator unit is abnormal, so that the local clock of the base station is misaligned.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the application provides a clock abnormality detection device, a clock abnormality detection method and a base station, which can accurately detect whether a clock source unit and a crystal oscillator unit are abnormal in state.
In a first aspect, an embodiment of the present application provides a clock anomaly detection apparatus, including:
a primary clock source unit and at least one backup clock source unit;
a crystal oscillator unit;
the phase discrimination module is used for performing two-by-two traversal comparison on the clock signal of the main clock source unit, the clock signal of the standby clock source unit and the clock signal of the crystal oscillator unit to obtain a comparison result;
the abnormality detection unit is connected with the phase discrimination unit and is used for determining units with abnormal states in the main clock source unit, the standby clock source unit and the crystal oscillator unit according to the comparison result.
In a second aspect, an embodiment of the present application further provides a clock anomaly detection method, which is applied to a clock anomaly detection device, where the clock anomaly detection device includes a main clock source unit, at least one standby clock source unit, a crystal oscillator unit, a phase detection unit and an anomaly detection unit, where the main clock source unit, the standby clock source unit and the crystal oscillator unit are all connected with the phase detection unit, and the anomaly detection unit is connected with the phase detection unit;
the method comprises the following steps:
the phase discrimination module performs two-by-two traversal comparison on the clock signal of the main clock source unit, the clock signal of the standby clock source unit and the clock signal of the crystal oscillator unit to obtain a comparison result;
and the abnormality detection unit determines units with abnormal states in the main clock source unit, the standby clock source unit and the crystal oscillator unit according to the comparison result.
In a third aspect, an embodiment of the present application further provides a base station, including the clock anomaly detection apparatus as described above.
The embodiment of the application comprises the following steps: the clock abnormality detection device comprises a main clock source unit, at least one standby clock source unit, a crystal oscillator unit, a phase discrimination unit and an abnormality detection unit, wherein the main clock source unit, the standby clock source unit and the crystal oscillator unit are all connected with the phase discrimination unit, and the abnormality detection unit is connected with the phase discrimination unit; the phase discrimination module performs two-time traversal comparison on the clock signal of the main clock source unit, the clock signal of the standby clock source unit and the clock signal of the crystal oscillator unit to obtain a comparison result; the abnormality detection unit determines units with abnormal states in the main clock source unit, the standby clock source unit and the crystal oscillator unit according to the comparison result; the clock source unit and the crystal oscillator unit can be mutually calibrated, so that whether the states of the clock source unit and the crystal oscillator unit are abnormal or not can be accurately detected, the situation that the clock source unit deviates from a standard clock and is misreported to be normal or the clock oscillator unit is wrong and is misreported to be normal and causes clock errors is avoided, and the clock signal of the local clock of the base station is ensured to be accurate and free.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and do not limit the application.
FIG. 1 is a block diagram of a clock anomaly detection device;
FIG. 2 is another construction diagram of the clock abnormality detection apparatus;
FIG. 3 is a further block diagram of the clock anomaly detection apparatus;
FIG. 4 is a step diagram of a method of clock anomaly detection;
FIG. 5 is another step diagram of a clock anomaly detection method;
FIG. 6 is a step diagram of a coping strategy for a state-abnormal unit as a primary clock source unit or a state-abnormal unit as a primary clock source unit and a portion of a standby clock source unit;
FIG. 7 is a step diagram of a coping strategy for a state-anomalous unit as part or all of the standby clock source units;
FIG. 8 is a step diagram of a coping strategy for a unit with abnormal state as a primary clock source unit and all standby clock source units;
FIG. 9 is a step diagram of a strategy for handling a unit for a state anomaly including a crystal oscillator unit;
fig. 10 is a block diagram of a base station.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It should be noted that although functional block division is performed in a device diagram and a logic sequence is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart. The terms first, second and the like in the description, in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The application provides a clock abnormality detection device, a clock abnormality detection method and a base station, wherein the clock abnormality detection device comprises a main clock source unit, at least one standby clock source unit, a crystal oscillator unit, a phase discrimination unit and an abnormality detection unit, wherein the main clock source unit, the standby clock source unit and the crystal oscillator unit are all connected with the phase discrimination unit, and the abnormality detection unit is connected with the phase discrimination unit; the phase discrimination module performs two-time traversal comparison on the clock signal of the main clock source unit, the clock signal of the standby clock source unit and the clock signal of the crystal oscillator unit to obtain a comparison result; the abnormality detection unit determines units with abnormal states in the main clock source unit, the standby clock source unit and the crystal oscillator unit according to the comparison result; the clock source unit and the crystal oscillator unit can be mutually calibrated, the situation that the clock source unit deviates from a standard clock to report the clock is normal in error or the crystal oscillator unit has a problem to report the clock in error is avoided, whether the states of the clock source unit and the crystal oscillator unit are abnormal can be accurately detected, and the clock signal of the local clock of the base station is accurate.
Embodiments of the present application will be further described below with reference to the accompanying drawings.
The embodiment of the application provides a clock abnormality detection device 10, which is applied to a base station.
Referring to fig. 1, the clock abnormality detection apparatus 10 includes: at least two clock source units, a crystal oscillator unit 200, a phase discrimination module 300 and an abnormality detection unit 400.
Wherein the clock source units include a primary clock source unit 110 and at least one standby clock source unit 120; the main clock source unit 110, the standby clock source unit 120 and the crystal oscillator unit 200 are all connected with the phase discrimination module 300; the anomaly detection unit 400 is connected to the phase discrimination unit 310. The phase discrimination module 300 is configured to perform a two-by-two traversal comparison on the clock signal of the primary clock source unit 110, the clock signal of the standby clock source unit 120, and the clock signal of the crystal oscillator unit 200, so as to obtain a comparison result. The abnormality detection unit 400 is configured to determine, based on the comparison result, a unit in which the states of the main clock source unit 110, the standby clock source unit 120, and the crystal oscillator unit 200 are abnormal.
The crystal oscillator unit 200 has a built-in crystal oscillator, specifically, a thermostatic crystal oscillator (Oven Controlled Crystal Oscillator, OCXO), which has the characteristics of high accuracy and high stability.
Referring to fig. 2, the clock anomaly detection apparatus 10 further includes a clock source selection unit 500, and the master clock source unit 110, the standby clock source unit 120, and the anomaly detection unit 400 are connected to the clock source selection unit 500, where the clock source selection unit 500 is configured to determine a target master clock from the master clock source unit 110 and the standby clock source unit 120 according to a unit of state anomaly.
The clock anomaly detection apparatus 10 further includes a control loop unit 600, an input terminal of the control loop unit 600 is connected to the clock source selection unit 500, and an output terminal of the control loop unit 600 is connected to the crystal oscillator unit 200. After determining the target master clock, the clock source selecting unit 500 outputs a clock signal of the target master clock. The control loop unit 600 receives the clock signal of the target master clock output from the clock source selection unit 500 from the input terminal, and outputs the clock signal of the target master clock to the crystal oscillator unit 200 from the output terminal. The crystal oscillator unit 200 uses the clock signal of the target master clock to tame the built-in crystal oscillator, so that the output frequency and phase of the crystal oscillator are synchronized with the clock signal of the target master clock, and the clock signal output by the crystal oscillator unit 200 is used as the clock signal of the local clock. The control loop unit 600 controls the crystal oscillator unit 200 by using the clock signal of the target master clock, so as to ensure that the clock signal output by the crystal oscillator unit 200 is synchronous with the clock signal of the external clock source, and realize the function of synchronizing the local clock of the base station with the external clock source.
The base station configures priorities of at least two clock source units, typically configures a global positioning system (Global Positioning System, GPS) clock source unit with high accuracy to a first priority, uses the GPS clock source unit as an initial primary clock source unit 110, configures other clock source units to a second priority or other priorities, and uses other clock sources as standby clock source units 120.
For the GPS clock source unit, the GPS clock source unit is based on a GPS high-precision positioning time service module, namely a GPS receiver. The GPS system corrects its own clock system regularly due to the requirement of its working characteristic, so its own clock system is stable for a long period of time, and has the characteristic of insensitivity to external physical factor change. The principle of the GPS clock source unit is to synchronize clock signals of a GPS system or other satellite navigation systems; the GPS clock source unit takes the GPS as an external clock and receives clock signals of a GPS system, thereby completing synchronous time service and having the same frequency accuracy as the GPS main clock.
The control loop unit 600 controls the crystal oscillator unit 200 by using the clock signal of the GPS clock source, so that the phase and frequency of the clock signal output by the crystal oscillator unit 200 are synchronized with the GPS system, and a high-precision time-frequency reference signal is provided, so that the 1-level reference clock source meeting the ITU-t g.811 requirement can be output.
Other clock source units may be 1588 clocks, etc. The 1588 clock is a high-precision clock adopting the IEEE 1588V2 protocol.
The phase detection module 300 performs a two-by-two traversal comparison on the clock signal of the primary clock source unit 110, the clock signal of the standby clock source unit 120, and the clock signal of the crystal oscillator unit 200, and generally compares the phase and frequency of the clock signals to obtain a comparison result. The phase discrimination module 300 includes a plurality of phase discrimination units 310; for each phase discrimination unit 310, two of the active clock source unit 110, the standby clock source unit 120, and the crystal oscillator unit 200 are connected to the phase discrimination unit 310; i.e. the phase discrimination unit 310 compares the clock signals output by the two clock source units or compares the clock signal output by one clock source unit with the clock signal output by the crystal oscillator unit 200.
Since the plurality of clock source units, including the master clock source unit 110 and the standby clock source unit 120, are aligned to the standard time, the crystal oscillator unit 200 is synchronized with the master clock source unit 110. Therefore, when the main clock source unit 110, the standby clock source unit 120, and the crystal oscillator unit 200 are all in normal states, the phases and frequencies of the clock signal of the main clock source unit 110, the clock signal of the standby clock source unit 120, and the clock signal of the crystal oscillator unit 200 are substantially identical, and the output of the phase discrimination unit 310 is 0.
For example, for the clock anomaly detection apparatus 10 having two clock source units, one of which is a GPS clock, as the main clock source unit 110, and the other of which is the standby clock source unit 120, the clock signal of the main clock source unit 110, the clock signal of the standby clock source unit 120, and the clock signal of the crystal oscillator unit 200 may be compared two by the three phase discrimination units 310. The first phase discrimination unit 310 is connected with the main clock source unit 110 and the crystal oscillator unit 200; the second phase discrimination unit 310 is connected with the standby clock source unit 120 and the crystal oscillator unit 200; the third phase discrimination unit 310 is connected to the main clock source unit 110 and the standby clock source unit 120. If the strength of the pseudo GPS signal is greater than that of the true GPS signal, the GPS receiver is decoy and receives the pseudo GPS signal, and the clock signal output by the GPS receiver is deviated from the standard clock, but the receiver module does not know, and the reported information is still in a normal working state. At this time, the output value of the first phase detecting unit 310 increases suddenly and is greater than 0, the output value of the second phase detecting unit 310 remains 0, and the output value of the third phase detecting unit 310 also increases suddenly and is greater than 0.
Referring to fig. 3, for the clock anomaly detection apparatus 10 having N clock source units, n×n+1/2 phase discrimination units 310 are required to implement phase discrimination between the N clock source units and the crystal oscillator unit 200.
For the abnormality detection unit 400, an input terminal of the abnormality detection unit 400 is connected to output terminals of the plurality of phase discrimination units 310, and the abnormality detection unit 400 receives output signals of corresponding comparison results of the plurality of phase discrimination units 310. The abnormality detection unit 400 determines a unit in which the states of the main clock source unit 110, the standby clock source unit 120, and the crystal oscillator unit 200 are abnormal, based on the comparison result.
For example, for the clock anomaly detection apparatus 10 having two clock source units, one of which is a GPS clock, as the main clock source unit 110, and the other of which is the standby clock source unit 120, the clock signal of the main clock source unit 110, the clock signal of the standby clock source unit 120, and the clock signal of the crystal oscillator unit 200 may be compared two by the three phase discrimination units 310. The first phase discrimination unit 310 is connected with the main clock source unit 110 and the crystal oscillator unit 200; the second phase discrimination unit 310 is connected with the standby clock source unit 120 and the crystal oscillator unit 200; the third phase discrimination unit 310 is connected to the main clock source unit 110 and the standby clock source unit 120. If the state of the master clock source unit 110 is abnormal, the output value of the first phase detection unit 310 will suddenly increase and be greater than 0, the output value of the second phase detection unit 310 will still be 0, and the output value of the third phase detection unit 310 will also suddenly increase and be greater than 0. The abnormality detection unit 400 receives the output values of the three phase discrimination units 310, and according to the change of the output values of the three phase discrimination units 310, that is, the output value of the first phase discrimination unit 310 suddenly increases, the output value of the third phase discrimination unit 310 suddenly increases, it may be determined that an abnormality occurs in the inputs of the first phase discrimination unit 310 and the third phase discrimination unit 310, the input of the first phase discrimination unit 310 is the clock signal of the main clock source unit 110 and the clock signal of the crystal oscillator unit 200, the input of the third phase discrimination unit 310 is the clock signal of the main clock source unit 110 and the clock signal of the standby clock source unit 120, the first phase discrimination unit 310 and the third phase discrimination unit 310 have the same input, that is, the clock signal of the main clock source unit 110, and the abnormality detection unit 400 determines that the main clock source unit 110 is abnormal. The abnormality detection unit 400 outputs a signal corresponding to the detection result, which characterizes the unit of state abnormality as the master clock source unit 110.
In some embodiments, the signal output by the anomaly detection unit 400 may only identify the unit of the state anomaly, e.g., the signal describes that the unit of the state anomaly is the primary clock source unit 110. In other embodiments, the signal output by the anomaly detection unit 400 may indicate a unit with an abnormal state, and may also indicate a unit with a normal state, for example, the signal describes that the unit with an abnormal state is the primary clock source unit 110, and the unit with a normal state is the standby clock source unit 120 and the crystal oscillator unit 200.
For the clock source selection unit 500, the clock source selection unit 500 is connected to the main clock source unit 110, the standby clock source unit 120, and the abnormality detection unit 400. The clock source selecting unit 500 determines a target master clock from the master clock source unit 110 and the standby clock source unit 120 based on the signals of the units representing the state abnormality outputted from the abnormality detecting unit 400, and the clock source selecting unit 500 receives the clock signal of the target master clock and outputs the clock signal of the target master clock to the control loop unit 600.
In some embodiments, when the anomaly detection unit 400 determines that the unit with the anomaly state is the primary clock source unit 110 or the unit with the anomaly state is the primary clock source unit 110 and part of the standby clock source units 120 according to the comparison results output by the phase discrimination units 310, the clock source selection unit 500 determines the target primary clock from the standby clock source units 120 with the normal state. And the clock abnormality detection apparatus 10 may report an alarm through an alarm module connected to the abnormality detection module.
Wherein, the unit with abnormal state is represented by the main clock source unit 110: the state of the main clock source unit 110 is abnormal, all the standby clock source units 120 are normal, and the crystal oscillator unit 200 is normal.
For example, with the clock abnormality detection apparatus 10 having two clock source units, one of which is a GPS clock as the master clock source unit 110; the other clock source unit is 1588 clock, which is used as a standby clock source unit 120; when the GPS clock state is abnormal, the clock source selection unit 500 determines the 1588 clock as the target master clock. The control loop unit 600 synchronizes the clock signal of the crystal oscillator unit 200 with the clock signal of the 1588 clock according to the clock signal of the target master clock output by the clock source selection unit 500.
The elements of the state exception are represented by the primary clock source element 110 and a portion of the standby clock source element 120: the states of the main clock source unit 110 and part of the standby clock source units 120 are abnormal, the states of the other part of the standby clock source units 120 are normal, and the states of the crystal oscillator units 200 are normal.
For example, with the clock abnormality detection apparatus 10 having three clock source units, one of which is a GPS clock as the master clock source unit 110; the other two clock source units are 1588 clocks and B-code clocks, and serve as standby clock source units 120; when the GPS clock and 1588 clock are abnormal in state, the clock source selection unit 500 determines the B-code clock as the target master clock. The control loop unit 600 synchronizes the clock signal of the crystal oscillator unit 200 with the clock signal of the B-code clock according to the clock signal of the target master clock output from the clock source selection unit 500.
In some embodiments, when the anomaly detection unit 400 determines that the unit with the anomaly status is a part or all of the standby clock source units 120 according to the comparison results output by the phase discrimination units 310, the clock source selection unit 500 determines that the target master clock is the master clock source unit 110.
Wherein the unit of state exception represents for the part of the standby clock source unit 120: part of the standby clock source units 120 are abnormal in state, the other part of the standby clock source units 120 are normal in state, the main clock source units 110 are normal in state, and the crystal oscillator units 200 are normal in state.
The elements of the state exception are represented for all standby clock source elements 120: all the standby clock source units 120 are abnormal in state, the main clock source unit 110 is normal in state, and the crystal oscillator unit 200 is normal in state.
When the state of the master clock source unit 110 is normal, the clock source selecting unit 500 continues to use the master clock source unit 110 as the target master clock, and the clock anomaly detecting device 10 may report an alarm through the alarm module.
For example, with the clock abnormality detection apparatus 10 having two clock source units, one of which is a GPS clock as the master clock source unit 110; the other clock source unit is 1588 clock, which is used as a standby clock source unit 120; when the 1588 clock state is abnormal and the GPS clock is normal, the clock source selection unit 500 determines the GPS clock as the target master clock. The control loop unit 600 continuously synchronizes the clock signal of the crystal oscillator unit 200 with the clock signal of the GPS clock according to the clock signal of the target master clock output from the clock source selecting unit 500.
In some embodiments, when the anomaly detection unit 400 determines that the units with abnormal states are the main clock source unit 110 and all the standby clock source units 120 according to the comparison results output by the phase detection units 310, the clock source selection unit 500 stops outputting the clock signal of the target main clock to the control loop unit 600, and the control loop unit 600 maintains the local clock for the crystal oscillator unit 200. And the clock abnormality detection apparatus 10 can report an alarm through an alarm module.
The elements of the state exception are represented by the master clock source unit 110 and the overall standby clock source unit 120: all clock source units are abnormal in state, and the crystal oscillator unit 200 is normal in state.
When all the clock source units are abnormal, the clock source selecting unit 500 stops outputting the clock signal of the target master clock to the control loop unit 600, and the control loop unit 600 switches to the hold mode, so that the crystal oscillator unit 200 is not synchronized with the target master clock, the crystal oscillator unit 200 maintains the local clock for a period of time by using the high stability line of the built-in constant temperature crystal oscillator, and the clock signal and the frequency signal with high reliability are continuously provided to output, so that the local clock still maintains high precision in a short time.
In some embodiments, when the abnormality detection unit 400 determines that the unit with abnormal state includes the crystal oscillator unit 200 according to the comparison results output by the phase discrimination units 310, the abnormality detection unit 400 outputs a first signal indicating that the unit with abnormal state includes the crystal oscillator unit 200 to an external switch module, so that the switch module turns off the base station service. And the clock abnormality detection apparatus 10 can report an alarm through an alarm module.
Wherein, the abnormal state unit includes a crystal oscillator unit 200 representation: the unit with abnormal state is a crystal oscillator unit 200, and the unit with normal state is all clock source units; or the abnormal state units are the crystal oscillator unit 200 and the main clock source unit 110, and the normal state units are all the standby clock source units 120; or the abnormal state units are a crystal oscillator unit 200, a main clock source unit 110 and a part of standby clock source units 120, and the normal state units are the other part of standby clock source units 120; or the abnormal state units are the crystal oscillator unit 200, the main clock source unit 110 and all the standby clock source units 120.
When the state of the crystal oscillator unit 200 is abnormal, the abnormality detection unit 400 outputs a first signal to an external switch module; the switch module receives the first signal, and knows that the state of the crystal oscillator unit 200 is abnormal, and closes the base station service, so as to avoid interference with other base stations. And the base station service is restarted until the switching module detects that the crystal oscillator unit 200 is recovered to be normal.
In this embodiment, the clock anomaly detection apparatus 10 can calibrate the clock source unit and the crystal oscillator unit 200 to each other, so as to accurately detect whether the states of the clock source unit and the crystal oscillator unit 200 are abnormal, thereby avoiding the situation that the clock source unit deviates from the standard clock and is misreported to be normal or the crystal oscillator unit 200 has a problem and is misreported to be normal and causes clock errors, and ensuring that the clock signal of the local clock of the base station is accurate and error-free.
The embodiment of the application also provides a clock abnormality detection method which is applied to the clock abnormality detection device 10. The clock anomaly detection apparatus 10 includes a main clock source unit 110, at least one standby clock source unit 120, a crystal oscillator unit 200, a phase discriminator unit 310, an anomaly detection unit 400, a clock source selection unit 500, and a control loop unit 600, where the main clock source unit 110, the standby clock source unit 120, and the crystal oscillator unit 200 are all connected to the phase discriminator unit 310, and the anomaly detection unit 400 is connected to the phase discriminator unit 310. The master clock source unit 110, the standby clock source unit 120, and the abnormality detection unit 400 are all connected to the clock source selection unit 500. An input end of the control loop unit 600 is connected to the clock source selecting unit 500, and an output end of the control loop unit 600 is connected to the crystal oscillator unit 200.
Referring to fig. 4, the clock anomaly detection method includes:
step S100, the phase detection module 300 performs a two-by-two traversal comparison on the clock signal of the main clock source unit 110, the clock signal of the standby clock source unit 120, and the clock signal of the crystal oscillator unit 200, to obtain a comparison result;
in step S200, the abnormality detection unit 400 determines the units in which the states of the main clock source unit 110, the standby clock source unit 120, and the crystal oscillator unit 200 are abnormal, based on the comparison result.
In this embodiment, the clock anomaly detection method can make the clock source unit and the crystal oscillator unit 200 calibrate each other, so as to accurately detect whether the states of the clock source unit and the crystal oscillator unit 200 are abnormal, avoid the situation that the clock source unit deviates from the standard clock and is misreported normally or the crystal oscillator unit 200 has a problem and is misreported normally to cause clock errors, and ensure that the clock signal of the local clock of the base station is accurate and error-free.
After the abnormality detection unit 400 detects the unit of the state abnormality, the base station needs to execute a corresponding coping strategy for different detection results.
Referring to fig. 5, after step S200, the clock anomaly detection method further includes:
in step S300, the clock source selecting unit 500 selects a unit with a normal state from the master clock source unit 110 and the standby clock source unit 120 according to the unit with an abnormal state, and determines the selected unit as the target master clock.
And the control loop unit 600 synchronizes the clock signal of the crystal oscillator unit 200 with the clock signal of the target master clock according to the clock signal of the target master clock outputted from the clock source selecting unit 500.
Referring to fig. 6, fig. 6 is a step diagram of a policy for coping with a state-abnormal unit as a master clock source unit or a state-abnormal unit as a master clock source unit and a part of standby clock source units. In certain embodiments, step S300 further comprises the steps of:
in step S310, when the abnormal state unit is the master clock source unit 110, or the abnormal state unit is the master clock source unit 110 and part of the standby clock source units 120, the target master clock is determined from the standby clock source units 120 with normal states.
For example, with the clock abnormality detection apparatus 10 having three clock source units, one of which is a GPS clock as the master clock source unit 110; the other two clock source units are 1588 clocks and B-code clocks, and serve as standby clock source units 120; when the GPS clock and 1588 clock are abnormal in state, the clock source selection unit 500 determines the B-code clock as the target master clock. The control loop unit 600 synchronizes the clock signal of the crystal oscillator unit 200 with the clock signal of the B-code clock according to the clock signal of the target master clock output from the clock source selection unit 500.
Referring to fig. 7, fig. 7 is a step diagram of a coping strategy in which a unit for a state abnormality is a part or all of standby clock source units. In certain embodiments, step S300 further comprises the steps of:
in step S320, when the abnormal state unit is part or all of the standby clock source units 120, it is determined that the target master clock is the master clock source unit 110.
For example, with the clock abnormality detection apparatus 10 having two clock source units, one of which is a GPS clock as the master clock source unit 110; the other clock source unit is 1588 clock, which is used as a standby clock source unit 120; when the 1588 clock state is abnormal and the GPS clock is normal, the clock source selection unit 500 determines the GPS clock as the target master clock. The control loop unit 600 continuously synchronizes the clock signal of the crystal oscillator unit 200 with the clock signal of the GPS clock according to the clock signal of the target master clock output from the clock source selecting unit 500.
Referring to fig. 8, fig. 8 is a step diagram of a policy for handling a unit with abnormal status as a primary clock source unit and all standby clock source units. In some embodiments, the clock anomaly detection method further comprises:
in step S410, when the abnormal state units are the main clock source unit 110 and all the standby clock source units 120, the clock source selecting unit 500 stops outputting the clock signal of the target main clock to the control loop unit 600, and the control loop unit 600 maintains the local clock of the crystal oscillator unit 200.
That is, when all the clock source units are abnormal, the clock source selecting unit 500 stops outputting the clock signal of the target master clock to the control loop unit 600, and the control loop unit 600 switches to the hold mode, so that the crystal oscillator unit 200 is not synchronized with the target master clock, the crystal oscillator unit 200 maintains the local clock for a period of time by using the high stability line of the built-in constant temperature crystal oscillator, and the clock signal and the frequency signal output with high reliability are continuously provided, so that the local clock still maintains high precision in a short time.
Referring to fig. 9, the unit for the abnormal state includes a step diagram of a coping strategy of the crystal oscillator unit. In some embodiments, the clock anomaly detection method further comprises:
in step S420, when the unit with abnormal state includes the crystal oscillator unit 200, the abnormality detection unit 400 outputs a first signal indicating that the unit with abnormal state includes the crystal oscillator unit 200 to the switch module, so that the switch module turns off the base station service.
That is, when the state of the crystal oscillator unit 200 is abnormal, the abnormality detection unit 400 outputs a first signal to the external switching module; the switch module receives the first signal, and knows that the state of the crystal oscillator unit 200 is abnormal, and closes the base station service, so as to avoid interference with other base stations. And the base station service is restarted until the switching module detects that the crystal oscillator unit 200 is recovered to be normal.
Referring to fig. 10, the embodiment of the application further provides a base station. The base station includes the clock abnormality detection apparatus 10 described above.
The base station further comprises an alarm module and a switch module located in the clock anomaly detection device 10.
When the clock abnormality detection apparatus 10 detects that any one of the main clock source unit 110, the standby clock source unit 120, and the crystal oscillator unit 200 is abnormal, the alarm module is notified to report the abnormal situation. When the clock abnormality detection device 10 detects that the state of the crystal oscillator unit 200 is abnormal, a signal is output to the switch module, and after the switch module receives the first signal, the base station service is closed.
In this embodiment, the base station can calibrate the clock source unit and the crystal oscillator unit 200 through the clock anomaly detection device 10, so as to accurately detect whether the states of the clock source unit and the crystal oscillator unit 200 are abnormal, thereby avoiding the situation that the clock source unit deviates from the standard clock and is misreported normally or the crystal oscillator unit 200 has a problem and is misreported normally to cause clock errors, and ensuring that the clock signal of the local clock of the base station is accurate.
While the preferred embodiment of the present application has been described in detail, the present application is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit and scope of the present application, and these equivalent modifications or substitutions are included in the scope of the present application as defined in the appended claims.
Claims (11)
1. A clock anomaly detection apparatus comprising:
a primary clock source unit and at least one backup clock source unit;
a crystal oscillator unit;
the phase discrimination module is used for performing two-by-two traversal comparison on the clock signal of the main clock source unit, the clock signal of the standby clock source unit and the clock signal of the crystal oscillator unit to obtain a comparison result;
the abnormality detection unit is connected with the phase discrimination unit and is used for determining units with abnormal states in the main clock source unit, the standby clock source unit and the crystal oscillator unit according to the comparison result.
2. The clock anomaly detection apparatus of claim 1, wherein the phase discrimination module comprises a plurality of phase discrimination units; for each phase discrimination unit, two of the main clock source unit, the standby clock source unit and the crystal oscillator unit are connected with the phase discrimination unit.
3. The clock anomaly detection apparatus according to claim 1, further comprising a clock source selection unit, wherein the master clock source unit, the standby clock source unit, and the anomaly detection unit are each connected to the clock source selection unit, and wherein the clock source selection unit is configured to determine a target master clock from the master clock source unit and the standby clock source unit according to the unit whose state is anomalous.
4. A clock apparatus as claimed in claim 3, wherein the clock anomaly detection apparatus further comprises a control loop unit, an input terminal of the control loop unit being connected to the clock source selection unit, and an output terminal of the control loop unit being connected to the crystal oscillator unit.
5. The clock abnormality detection method is applied to a clock abnormality detection device, and the clock abnormality detection device comprises a main clock source unit, at least one standby clock source unit, a crystal oscillator unit, a phase discrimination unit and an abnormality detection unit, wherein the main clock source unit, the standby clock source unit and the crystal oscillator unit are all connected with the phase discrimination unit, and the abnormality detection unit is connected with the phase discrimination unit;
the method comprises the following steps:
the phase discrimination module performs two-by-two traversal comparison on the clock signal of the main clock source unit, the clock signal of the standby clock source unit and the clock signal of the crystal oscillator unit to obtain a comparison result;
and the abnormality detection unit determines units with abnormal states in the main clock source unit, the standby clock source unit and the crystal oscillator unit according to the comparison result.
6. The clock anomaly detection method according to claim 5, wherein the clock anomaly detection apparatus further comprises a clock source selection unit, the primary clock source unit, the standby clock source unit, and the anomaly detection unit are all connected to the clock source selection unit;
the method further comprises the steps of:
and the clock source selecting unit selects a unit with normal state from the main clock source unit and the standby clock source unit according to the unit with abnormal state to determine the unit as a target main clock.
7. The clock anomaly detection method according to claim 6, wherein the clock source selection unit selects a unit having a normal state from the main clock source unit and the standby clock source unit as a target main clock according to the unit having the abnormal state, comprising:
and when the unit with abnormal state is the main clock source unit or the unit with abnormal state is the main clock source unit and part of the standby clock source units, determining the target main clock from the standby clock source units with normal state.
8. The clock anomaly detection method according to claim 6, wherein the clock source selection unit selects a unit having a normal state from the main clock source unit and the standby clock source unit as a target main clock according to the unit having the abnormal state, comprising:
and when the unit with abnormal state is part or all of the standby clock source units, determining the target main clock as the main clock source unit.
9. The clock anomaly detection method according to claim 6, wherein the clock anomaly detection apparatus further comprises a control loop unit, an input end of the control loop unit is connected to the clock source selection unit, and an output end of the control loop unit is connected to the crystal oscillator unit;
the method further comprises the steps of:
and when the units with abnormal states are the main clock source unit and all the standby clock source units, the clock source selection unit stops outputting the clock signal of the target main clock to the control loop unit, and the control loop unit enables the crystal oscillator unit to maintain a local clock.
10. The clock anomaly detection method of claim 6, wherein the method further comprises:
when the unit with abnormal state comprises a crystal oscillator unit, the abnormality detection unit outputs a first signal indicating that the unit with abnormal state comprises the crystal oscillator unit to the switch module so as to enable the switch module to close the base station service.
11. A base station comprising the clock anomaly detection apparatus according to any one of claims 1 to 4.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210628491.9A CN117241362A (en) | 2022-06-06 | 2022-06-06 | Clock abnormality detection device, method and base station |
| PCT/CN2023/095311 WO2023236761A1 (en) | 2022-06-06 | 2023-05-19 | Clock anomaly detection apparatus and method, and base station |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210628491.9A CN117241362A (en) | 2022-06-06 | 2022-06-06 | Clock abnormality detection device, method and base station |
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| Publication Number | Publication Date |
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| CN117241362A true CN117241362A (en) | 2023-12-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210628491.9A Pending CN117241362A (en) | 2022-06-06 | 2022-06-06 | Clock abnormality detection device, method and base station |
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| Country | Link |
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| CN (1) | CN117241362A (en) |
| WO (1) | WO2023236761A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0588050B1 (en) * | 1992-08-18 | 1997-12-29 | Siemens Aktiengesellschaft | Arrangement for generating a clock signal having missing pulses with a bit precision |
| US6194969B1 (en) * | 1999-05-19 | 2001-02-27 | Sun Microsystems, Inc. | System and method for providing master and slave phase-aligned clocks |
| CN101079629B (en) * | 2006-05-23 | 2010-05-12 | 中兴通讯股份有限公司 | A digital phase lock device for seamless switching of SDH product clock board |
| CN102013920A (en) * | 2010-12-03 | 2011-04-13 | 中兴通讯股份有限公司 | Clock backup method and system for time division duplex base station |
-
2022
- 2022-06-06 CN CN202210628491.9A patent/CN117241362A/en active Pending
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2023
- 2023-05-19 WO PCT/CN2023/095311 patent/WO2023236761A1/en unknown
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| WO2023236761A1 (en) | 2023-12-14 |
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