CN112969229B - Clock correction method and device and network equipment - Google Patents
Clock correction method and device and network equipment Download PDFInfo
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- CN112969229B CN112969229B CN202110119585.9A CN202110119585A CN112969229B CN 112969229 B CN112969229 B CN 112969229B CN 202110119585 A CN202110119585 A CN 202110119585A CN 112969229 B CN112969229 B CN 112969229B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/004—Synchronisation arrangements compensating for timing error of reception due to propagation delay
- H04W56/005—Synchronisation arrangements compensating for timing error of reception due to propagation delay compensating for timing error by adjustment in the receiver
Abstract
The specification provides a clock correction method, a clock correction device and network equipment, and relates to the technical field of communication. A clock correction method, comprising: acquiring a compensation parameter, wherein the compensation parameter is determined based on a compensation signal sent by an external clock source; determining an iteration value according to the obtained at least two compensation parameters; converging the iteration value through a Kalman model to determine a convergence value; and when the fault of the external clock source is determined, compensating the clock signal generated by the crystal oscillator according to the convergence value. By the method, the clock signal generated by the crystal oscillator can be reliably compensated when the external clock source fails, and the reliability of the network equipment is improved.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a clock correction method, an apparatus, and a network device.
Background
With the development of 5G (fifth Generation mobile communication technology, 5th-Generation) technology, the data transmission speed is faster and the clock accuracy is higher. For network devices, two clock sources are typically provided, one generated by itself and the other received from the outside.
In the network device, the clock signal is generated by the crystal oscillator, and due to the characteristics of the crystal oscillator, the generated clock signal is also deviated along with the aging of the crystal oscillator in the accumulation of time. At this time, the clock signal generated by the crystal oscillator needs to be corrected by the compensation signal received from the outside, so as to ensure that the clocks among the plurality of network devices are kept uniform. For example, the internal clock is corrected by receiving the frequency or phase shift through the 1588 protocol.
However, in the process of operating the network device, the network device may not receive an external compensation signal due to a fault of a boundary clock (a time service device in the 1588 protocol), and the network device may not correct a clock signal generated by an internal crystal oscillator, so that when a certain deviation is accumulated in the crystal oscillator, a large deviation is generated in data processing and data interaction of the network device, and thus reliability of the network device, that is, the entire networking is affected.
Disclosure of Invention
To overcome the problems in the related art, the present specification provides a clock correction method, apparatus, and network device.
In combination with the first aspect of the embodiments of the present specification, the present application provides a clock correction method, including:
acquiring a compensation parameter, wherein the compensation parameter is determined based on a compensation signal sent by an external clock source;
determining an iteration value according to the obtained at least two compensation parameters;
converging the iteration value through a Kalman model to determine a convergence value;
and when the fault of the external clock source is determined, compensating the clock signal generated by the crystal oscillator according to the convergence value.
Optionally, the external clock source is a clock source of 1588 protocol, and the compensation parameter includes phase deviation or frequency deviation;
determining an iteration value according to the obtained at least two compensation parameters, comprising:
recording compensation parameters corresponding to at least two compensation signals in a preset time period;
calculating the difference value between the compensation parameters corresponding to any two compensation signals in the at least two compensation signals;
determining a proportional relation of compensation parameters according to the issuing interval of any two compensation signals, wherein the proportional relation is the fraction proportion of iteration values corresponding to the compensation parameters;
and calculating an iteration value according to the difference and the proportional relation.
Further, compensating the clock signal generated by the crystal oscillator according to the convergence value includes:
determining the number of parts of a convergence value corresponding to the compensation time according to the compensation time set in the time period;
calculating an actual compensation value, wherein the actual compensation value is the number of parts multiplied by the convergence value;
and compensating the clock signal generated by the crystal oscillator through the actual compensation value at the compensation time.
Optionally, the external clock source is a clock source of a synchronous ethernet, and the compensation parameter is a compensation coefficient determined by the phase-locked loop according to the external clock source;
determining an iteration value according to the obtained at least two compensation parameters, comprising:
reading a compensation parameter from the phase-locked loop at intervals of a preset time period;
calculating a difference value corresponding to two adjacent compensation parameters as an iteration value;
compensating the clock signal generated by the crystal oscillator according to the convergence value, comprising:
acquiring a compensation coefficient recorded in a phase-locked loop as an initial value and a convergence value determined by a Kalman model;
and calculating an actual compensation value, wherein the actual compensation value is equal to an initial value + N multiplied by a convergence value, and N is the number of time periods which pass after the external clock source fails.
In combination with the second aspect of the embodiments of the present specification, the present application further provides a clock correction apparatus, including:
the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring a compensation parameter, and the compensation parameter is determined based on a compensation signal sent by an external clock source;
the calculation unit is used for determining an iteration value according to the acquired at least two compensation parameters;
the convergence unit is used for converging the iteration value through a Kalman model to determine a convergence value;
and the compensation unit is used for compensating the clock signal generated by the crystal oscillator according to the convergence value when the fault of the external clock source is determined.
Optionally, the external clock source is a clock source of 1588 protocol, and the compensation parameter includes phase deviation or frequency deviation;
a computing unit comprising:
the recording module is used for recording compensation parameters corresponding to at least two compensation signals in a preset time period;
the first difference module is used for calculating the difference between compensation parameters corresponding to any two compensation signals in the at least two compensation signals;
the proportion module is used for determining the proportion relation of the compensation parameters according to the issuing intervals of any two compensation signals, wherein the proportion relation is the fraction proportion of the iteration values corresponding to the compensation parameters;
and the determining module is used for calculating an iteration value according to the difference value and the proportional relation.
Further, the compensation unit includes:
the number-of-copies module is used for determining the number of copies of the convergence value corresponding to the compensation time according to the compensation time set in the time period;
the calculating module is used for calculating an actual compensation value, wherein the actual compensation value is the number of parts multiplied by the convergence value;
and the compensation module is used for compensating the clock signal generated by the crystal oscillator through the actual compensation value at the compensation time.
Optionally, the external clock source is a clock source of a synchronous ethernet, and the compensation parameter is a compensation coefficient determined by the phase-locked loop according to the external clock source;
a computing unit comprising:
the reading module is used for reading the compensation parameters from the phase-locked loop at intervals of a preset time period;
the second difference module is used for calculating the difference value corresponding to the two adjacent compensation parameters as an iteration value;
a compensation unit comprising:
the acquisition module is used for acquiring a compensation coefficient recorded in the phase-locked loop as an initial value and a convergence value determined by a Kalman model when the fault of an external clock source is determined;
and the compensation determining module is used for calculating an actual compensation value, wherein the actual compensation value is an initial value + Nx convergence value, and N is the number of time periods elapsed after the external clock source fails.
In combination with the third aspect of the embodiments of the present specification, the present application further provides a network device, including: the system comprises a processor, a memory, a receiver, a crystal oscillator and a phase-locked loop;
the memory has program code stored therein that is called by the processor to perform the following operations:
acquiring a compensation parameter, wherein the compensation parameter is determined based on a compensation signal sent by an external clock source received by a receiver;
determining an iteration value according to the obtained at least two compensation parameters;
converging the iteration value through a Kalman model to determine a convergence value;
and when the fault of the external clock source is determined, writing the determined convergence value into the phase-locked loop so that the phase-locked loop compensates the clock signal generated by the crystal oscillator according to the convergence value.
Optionally, the external clock source is a clock source of 1588 protocol, and the compensation parameter includes phase deviation or frequency deviation;
determining an iteration value according to the obtained at least two compensation parameters, comprising:
recording compensation parameters corresponding to at least two compensation signals in a preset time period;
calculating the difference value between the compensation parameters corresponding to any two compensation signals in the at least two compensation signals;
determining a proportional relation of compensation parameters according to the issuing interval of any two compensation signals, wherein the proportional relation is the fraction proportion of iteration values corresponding to the compensation parameters;
calculating an iteration value according to the difference value and the proportional relation;
compensating the clock signal generated by the crystal oscillator according to the convergence value, comprising:
determining the number of parts of a convergence value corresponding to the compensation time according to the compensation time set in the time period;
calculating an actual compensation value, wherein the actual compensation value is the number of parts multiplied by the convergence value;
and compensating the clock signal generated by the crystal oscillator through the actual compensation value at the compensation time.
Furthermore, the external clock source is a clock source of the synchronous Ethernet, and the compensation parameter is a compensation coefficient;
the receiver receives a compensation signal sent by an external clock source and sends a compensation coefficient carried in the compensation signal to the phase-locked loop;
determining an iteration value according to the obtained at least two compensation parameters, comprising:
reading a compensation parameter from the phase-locked loop at intervals of a preset time period;
calculating a difference value corresponding to two adjacent compensation parameters as an iteration value;
compensating the clock signal generated by the crystal oscillator according to the convergence value, comprising:
acquiring a compensation coefficient recorded in a phase-locked loop as an initial value and a convergence value determined by a Kalman model;
and calculating an actual compensation value, wherein the actual compensation value is equal to an initial value + N multiplied by a convergence value, and N is the number of time periods which pass after the external clock source fails.
In the embodiment of the present specification, when the network device can acquire the compensation signal, the compensation parameter determined according to the compensation signal is converged through the kalman model, and when the external clock source fault is detected, the clock signal generated by the crystal oscillator is compensated through the convergence value obtained after the convergence, so that when the network device cannot acquire the compensation signal of the external clock source for compensation, a reliable clock compensation mode is provided for the network device, the clock uniformity is improved, and the reliability of data processing and data interaction of the network device and even the network is improved.
The technical scheme provided by the implementation mode of the specification can have the following beneficial effects:
in the embodiment of the present specification, when the network device can acquire the compensation signal, the compensation parameter determined according to the compensation signal is converged through the kalman model, and when the external clock source fault is detected, the clock signal generated by the crystal oscillator is compensated through the convergence value obtained after the convergence, so that when the network device cannot acquire the compensation signal of the external clock source for compensation, a reliable clock compensation mode is provided for the network device, the clock uniformity is improved, and the reliability of data processing and data interaction of the network device and even the network is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the specification.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present specification and together with the description, serve to explain the principles of the specification.
Fig. 1 is a schematic diagram of a network device according to the present application;
FIG. 2 is a flow chart of a clock correction method to which the present application relates;
fig. 3 is a timing diagram according to a clock correction method according to an embodiment of the present application, where a compensation parameter is issued through a 1588 message of a 1588 protocol;
fig. 4 is a schematic structural diagram of a clock correction apparatus according to the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present specification.
A typical network device, as shown in fig. 1, includes a processor, memory, a receiver, a crystal oscillator, and a phase-locked loop. The crystal oscillator is used to generate a clock signal, which is typically a square wave. After the crystal oscillator generates the clock signal, the clock signal is sent to the phase-locked loop, and the phase-locked loop can correct the clock signal generated by the crystal oscillator by taking the input signal as a reference and output the corrected clock signal, so that the clock signal applied in the network equipment can reduce deviation and is more accurate.
The receiver is typically a PHY (physical layer) chip, an FPGA (Field Programmable logic Array) chip, or a MAC (media access control layer) chip. For example, when the network device performs clock compensation through the 1588 protocol, the clock compensation may be implemented by a PHY chip, an FPGA, or an MAC chip, and when the network device performs clock compensation through a synchronous ethernet (SyncE), the clock compensation may be implemented by the PHY chip or the FPGA. Certainly, in the practical application process, other chips or units may be further included to implement receiving and processing of the compensation signal, and output the compensation signal to the phase-locked loop for compensation, which is not limited herein.
The network device may receive the compensation signal sent by the external clock source, and for the network device, the clock signal of the network device may be compensated by one or two external clock sources.
However, the external clock source may be disconnected from the network device due to unreliable communication, so that the network device cannot acquire the compensation signal, and the deviation of the crystal oscillator cannot be corrected. To avoid this, the present application provides a clock compensation method, as shown in fig. 2, including:
and S100, acquiring a compensation parameter.
The compensation parameter is determined based on a compensation signal sent by an external clock source, where the external clock source may be 1588 protocol, GPS (Global Positioning System) protocol, SyncE (Synchronous Ethernet) signal carried in Ethernet information, and the like.
S101, determining an iteration value according to the obtained at least two compensation parameters.
And S102, converging the iteration value through a Kalman model, and determining a convergence value.
Because the external clock source can always send the compensation signal to the network equipment, the network equipment can complete the continuous compensation of the crystal oscillator. The compensation parameters carried in the compensation signals do not change according to a certain rule, and noise exists due to jitter in the transmission process of the transceiving links and temperature change of the network equipment, when the network equipment receives the compensation signals, the noise needs to be filtered, and a Kalman model expressing the aging characteristic of the crystal oscillator is established.
Under the condition that an external clock source of the network equipment normally works, the Kalman model comprises a priori process and a posterior process. And the compensation parameters obtained by the external clock source are received, the prior value is corrected through the compensation parameters to form a posterior value, and the posterior value is used as the prior value when the compensation parameters are obtained next time, so that the Kalman model can finally output the compensation parameters for accurately compensating the clock signals in a circulating manner.
The iteration value and the convergence value can be understood as input variables and calculation results of the kalman model, the iteration value is calculated based on compensation parameters acquired by the network equipment, the iteration value is input into the kalman model and then iterated, and the convergence value is formed after the iteration is completed. For example, the multiple of the iteration value may be equal to the compensation parameter, or a difference between two compensation parameters. The setting is required according to the actual situation, and will be described in detail later.
Of course, since the iterative process may continue in a situation where the network device can receive the compensation signal of the external clock source, completing the iteration may be understood in this application as determining the timing of the disconnection of the external clock source.
And subsequently, the compensation parameters output by the Kalman model are called local compensation parameters, and the local compensation parameters are obtained by calculation according to the convergence values. The kalman model may be represented as:
prediction equation 1:
prediction equation 2:
correction equation 1:
correction equation 2:
correction equation 3:
Xkis a compensation parameter predicted according to a Kalman model; pkIs the confidence variance; kkIs the Kalman gain; zkAn iteration value determined according to a compensation parameter issued by a protocol; and R is the covariance of the compensation parameters issued by the protocol. It is composed ofThe value with the negative superscript represents the prior value determined using the Kalman model, and the value with the ^ superscript represents the posterior value determined using the Kalman model.
The Kalman model has the function of providing an accurate compensation parameter for the phase-locked loop when the external clock source fails, so that the Kalman model is iterated all the time under the condition that the external clock source is normal.
In applying the kalman model, in the prediction formula,
and Pk-1An initial value may be preset, and the initial value may be 0 or within an arbitrary range, and the closer the two initial values are to the actual values, the faster the two initial values can converge, for example, the farther the setting is from the actual values, only the final convergence speed is affected.
Because the Kalman model uses the actually received values to converge in the iterative process, for example, ZkMay be an iteration value determined with a compensation parameter determined from the received compensation signal, and therefore it is possible to achieve that the convergence value approaches the actual value of the compensation parameter.
Taking an operation process as an example for description, assume that
Is 0 and Pk-1Is 1, then both are assigned to prediction equation 1 and prediction equation 2
And
then, the network device receives the compensation signal of the external clock source, and obtains the compensation parameter according to the compensation signal, and further obtains the iteration value (Zk in the correction formula 2) and the covariance R corresponding to the compensation parameter.
Thereafter, the iteration value and the covariance R are substituted according to correction formulas 1 to 3 toCalculating the posterior value
And update PkAnd KkAnd the calculation of the prior value is used for the next time, and the iteration is completed according to the loop.
And S103, when the fault of the external clock source is determined, compensating the clock signal generated by the crystal oscillator according to the convergence value.
When the network device determines that the compensation signal of the external clock source is not received within a period of time, it may be considered that the external clock source or a transmission line between the external clock source and the network device has failed, and the network device cannot compensate its own clock signal through the external clock source.
At this time, the network device may determine an actual compensation parameter that actually needs to be output to the phase-locked loop from a convergence value formed by the completion of the convergence, so as to compensate the clock signal generated by the crystal oscillator.
In the embodiment of the present specification, when the network device can acquire the compensation signal, the compensation parameter determined according to the compensation signal is converged through the kalman model, and when the external clock source fault is detected, the clock signal generated by the crystal oscillator is compensated through the convergence value obtained after the convergence, so that when the network device cannot acquire the compensation signal of the external clock source for compensation, a reliable clock compensation mode is provided for the network device, the clock uniformity is improved, and the reliability of data processing and data interaction of the network device and even the network is improved.
A clock correction method according to the present application will be described below with reference to a specific embodiment. In this embodiment, the device selected by the network device is a clock source of 1588 protocol, the boundary clock of 1588 will continuously send 1588 message (compensation signal) to the network device, and the structure of the network device is as shown in fig. 1.
S11, the network equipment receives the 1588 message sent by the boundary clock.
And S12, the network equipment analyzes the 1588 message to obtain the phase deviation (or frequency deviation) serving as the compensation parameter.
Through the 1588 protocol, the network device can acquire the phase deviation and the frequency deviation respectively. The periods of the phase deviation and the frequency deviation are different, for example, for the phase deviation, the network device may receive messages sent by 16 boundary clocks every second, and for the frequency deviation, the network device may receive messages sent by 2 boundary clocks every second. Therefore, it can be understood that, in one period, the 8 th 1588 message and the 16 th 1588 message may carry a phase offset and a frequency offset, respectively.
Since the compensation of the frequency deviation also has an influence on the phase, the iteration can be performed with the phase deviation being issued every 8 times. The boundary clock is based on a 1588 message issued in a 1588 protocol, and the issued frequency is shown in fig. 4, wherein Δ t represents issued phase deviation, Δ F represents issued frequency deviation, a short line on an abscissa represents the timing of issuing Δ t, and a long line represents the timing of issuing Δ F. As can be seen from the figure, Δ t occurs 8 times between adjacent Δ F. The adjacent Δ t is set as the acceleration variation process with respect to the time interval, but this formula is only an approximate formula derived through long-time iteration, and actually, the phase deviation carried by the 1588 message is a process of jump, and the phase deviation may also include positive values and negative values.
S＝(1/2)at2
S is phase deviation, a is an aging variable, and t is a time interval of two times of issuing.
And S13, recording compensation parameters corresponding to the at least two compensation signals by the network equipment within a preset time period.
The network device may receive the compensation signal for the phase deviation 8 times within a time period, such as 0.5 second set in the present embodiment. In order to be able to iterate more accurately, a plurality of compensation parameters need to be recorded, and the recorded compensation parameters need to exclude the previously recorded compensation parameters.
And S14, the network equipment determines the proportional relation of the compensation parameters according to the issuing intervals of any two compensation signals.
Wherein, the proportion relation is the proportion of the number of parts of the iteration value corresponding to the compensation parameter. According to the derivation formula, the square relation between adjacent compensation parameters according to the number of issuing times can be roughly determined, that is, the phase deviation of 8 issuing times can be roughly defined as the ratio of 1:4:9:16:25:36:49: 64.
And S15, the network equipment calculates the difference value between the compensation parameters corresponding to any two compensation signals in the at least two compensation signals.
And S16, the network equipment calculates an iteration value according to the difference and the proportional relation.
The network device calculates a difference between the two compensation parameters based on the recorded compensation parameters. And, based on the proportional relationship determined in S4, it can be concluded that the difference between adjacent compensation parameters contains a fraction of iteration values that may be 1:3:5:7:9:11:13: 15.
In this embodiment, the compensation parameters issued for the first time, the third time and the fourth time may be selected as a basis for calculation, that is, 13 iteration values of 1+5+7 are included. Suppose that the first compensation parameter is 0.3 ns, the second compensation parameter is-0.1 ns, the third compensation parameter is 0.7 ns, and the fourth compensation parameter is 0.9 ns. Thus, the sum of 13 iteration values can be determined to be 0.3+0.8+0.2 to 1.3 ns, and thus one iteration value can be determined to be 0.1 ns.
And when the 1588 message carries the frequency deviation, the network equipment records the carried frequency deviation. Because the frequency deviation sent by the 1588 message is more accurate relative to the phase deviation, iteration can be performed without the frequency deviation, and the phase-locked loop is compensated according to the frequency deviation sent by the 1588 message under the condition of the failure of an external clock source. Of course, iteration may also be performed according to a plurality of received frequency deviations, and a more accurate frequency deviation is obtained, assuming that the finally obtained iteration value related to the frequency deviation may be 10 HZ.
In the above process, the network device always listens to the external clock source, and if the network device can receive the compensation signal sent by the external clock source, the network device executes the processes of steps S11-S16. Once the network device does not receive the compensation signal of the external clock source within a preset time, it jumps to S17 for execution.
And S17, the network equipment determines the number of parts of the convergence value corresponding to the compensation time according to the compensation time set in the time period.
And S18, the network equipment calculates an actual compensation value.
After the external clock source fails, the network device needs to correct the clock signal generated by the crystal oscillator through the convergence value trained by the network device, that is, the clock signal generated by the crystal oscillator is written into the phase-locked loop, and the processor of the network device determines the actual compensation value which needs to be sent to the phase-locked loop currently according to the time period (the period shown in fig. 3, a 0.5 second period). The actual compensation value is a product of the fraction corresponding to the number of issuing times in the current time period and the convergence value, that is, the actual compensation value is the fraction × the convergence value.
That is, with reference to the above proportional relationship, it can be determined that the phase deviations at 8 times are respectively 0.1, 0.4, 0.9, 1.6, 2.5, 3.6, 4.9 and 6.4 nanoseconds, and on this basis, the phase deviation at the previous issue is removed from the phase deviation at the next issue, and repeated issue is avoided. Finally, the phase deviation for each issue is 0.1, 0.3, 0.5, 0.7, 0.9, 1.1, 1.3, and 1.5 nanoseconds, respectively.
And S19, compensating the clock signal generated by the crystal oscillator through the actual compensation value at the compensation time by the network equipment.
Through the determined phase deviation, 0.1 nanosecond is issued when the phase deviation is issued to the phase-locked loop for the first time; when the phase deviation is issued to the phase-locked loop for the second time, 0.3 nanosecond is issued; when the phase deviation is issued to the phase-locked loop for the third time, 0.5 nanosecond is issued; when the phase deviation is issued to the phase-locked loop for the fourth time, 0.7 nanosecond is issued; when the phase deviation is issued to the phase-locked loop for the fifth time, 0.9 nanosecond is issued; when the phase deviation is issued to the phase-locked loop for the sixth time, 1.1 nanosecond is issued; when the phase deviation is issued to the phase-locked loop for the seventh time, 1.3 nanoseconds are issued; and when the phase deviation is issued to the phase-locked loop for the eighth time, 1.5 nanoseconds are issued.
And, when the phase deviation is issued for the eighth time, the determined frequency deviation, namely 10HZ, is also issued to the phase-locked loop.
The implementation inside the specific phase-locked loop is the same as that of the current phase-locked loop, and only when an external clock source fails, the compensation signal generated by the external clock source is replaced by the output result of the Kalman model and is input into the phase-locked loop.
After that, after the network device monitors the compensation signal issued by the external clock source again, the network device will execute the processes of S11-S16 again, train the issued compensation according to the kalman model until the external clock source fault is determined next time, and cycle sequentially.
Through the process, a reliable compensation parameter can be provided for the network equipment when the external clock source fails, and the phase deviation and the frequency deviation of the clock signal provided by the crystal oscillator are compensated.
Due to the difference of the external clock source, the application also provides another embodiment to describe a clock correction method. In this embodiment, the external clock source is a synchronous ethernet SyncE signal, and the network device inputs the SyncE signal into the phase-locked loop after receiving the SyncE signal.
It should be noted that, since the SyncE signal can only correct the frequency, the SyncE signal is not used as a compensation signal independently, and generally, the SyncE signal is used as an auxiliary signal based on a compensation including 1588 protocol or GNSS (Global Navigation Satellite System). At this time, two phase-locked loops need to be deployed in the network device, one phase-locked loop is used for filtering SyncE signals, and the other phase-locked loop is used for filtering 1588 protocol or GNSS signals. In the current phase-locked chip, the functions of the two phase-locked loops can be implemented respectively, in this case, one phase-locked loop can be referred to as a phase-locked unit in the phase-locked loop chip, and a frequency control word analysis unit can be further disposed between the two phase-locked loops to determine the compensation coefficient to output to the outside of the phase-locked loop chip.
S21, the network device receives the SyncE signal through the ethernet interface.
And S22, the network equipment obtains the compensation coefficient through the phase-locked loop at intervals of a preset time period.
In this embodiment, the compensation parameter is a compensation coefficient determined by the phase-locked loop according to the external clock source.
The process of finally outputting the compensation coefficient for the corresponding processing of acquiring the SyncE signal by the phase-locked loop is the same as that of the current phase-locked loop, and is not described herein. The preset time period is the time when the phase-locked loop filters and outputs the SyncE signal.
And S23, the network equipment calculates the difference value corresponding to the two adjacent compensation coefficients as an iteration value.
The recorded compensation coefficients are frequency-dependent, so that the compensation coefficients can be understood as approximately linear relations with respect to time, and the determined iteration value can be understood as the change value of two adjacent compensation coefficients.
And S24, inputting the network equipment into the Kalman model according to the iteration value for convergence.
The formulas related to the kalman model are similar to those described above, that is, the formulas include a prediction formula 1, a prediction formula 2, a correction formula 1, a correction formula 2, and a correction formula 3. Unlike the previous embodiment, Z in the present embodimentkRepresenting the difference between adjacent compensation coefficients.
S25, the network device listens to the SyncE signal, if the SyncE signal is listened, the S21-S24 are executed circularly, if the SyncE signal is not detected in a period of time, the S26 is jumped to.
And S26, the network equipment acquires the current compensation coefficient in the phase-locked loop as an initial value.
And S27, the network equipment calculates the actual compensation value and sends the actual compensation value to the phase-locked loop so as to compensate the clock signal generated by the crystal oscillator through the phase-locked loop.
The actual compensation value is equal to the initial value + N × a convergence value, where N is the number of time periods elapsed after the external clock source fails, and the convergence value is a convergence value determined by the kalman model when the external clock source fails.
After each time period is reached, an actual compensation value is performed according to the number N of the elapsed time periods.
Thereafter, when the network device listens to the SyncE signal transmitted by the external clock source again, the process of S21-S24 starts to be executed again until the next time the external clock source fails.
Correspondingly, the present application also provides a clock calibration apparatus, as shown in fig. 1, including:
the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring a compensation parameter, and the compensation parameter is determined based on a compensation signal sent by an external clock source;
the calculation unit is used for determining an iteration value according to the acquired at least two compensation parameters;
the convergence unit is used for converging the iteration value through a Kalman model to determine a convergence value;
and the compensation unit is used for compensating the clock signal generated by the crystal oscillator according to the convergence value when the fault of the external clock source is determined.
Optionally, the external clock source is a clock source of 1588 protocol, and the compensation parameter includes phase deviation or frequency deviation;
a computing unit comprising:
the recording module is used for recording compensation parameters corresponding to at least two compensation signals in a preset time period;
the first difference module is used for calculating the difference between compensation parameters corresponding to any two compensation signals in the at least two compensation signals;
the proportion module is used for determining the proportion relation of the compensation parameters according to the issuing intervals of any two compensation signals, wherein the proportion relation is the fraction proportion of the iteration values corresponding to the compensation parameters;
and the determining module is used for calculating an iteration value according to the difference value and the proportional relation.
Further, the compensation unit includes:
the number-of-copies module is used for determining the number of copies of the convergence value corresponding to the compensation time according to the compensation time set in the time period;
the calculating module is used for calculating an actual compensation value, wherein the actual compensation value is the number of parts multiplied by the convergence value;
and the compensation module is used for compensating the clock signal generated by the crystal oscillator through the actual compensation value at the compensation time.
Optionally, the external clock source is a clock source of a synchronous ethernet, and the compensation parameter is a compensation coefficient determined by the phase-locked loop according to the external clock source;
a computing unit comprising:
the reading module is used for reading the compensation parameters from the phase-locked loop at intervals of a preset time period;
the second difference module is used for calculating the difference value corresponding to the two adjacent compensation parameters as an iteration value;
a compensation unit comprising:
the acquisition module is used for acquiring a compensation coefficient recorded in the phase-locked loop as an initial value and a convergence value determined by a Kalman model when the fault of an external clock source is determined;
and the compensation determining module is used for calculating an actual compensation value, wherein the actual compensation value is an initial value + Nx convergence value, and N is the number of time periods elapsed after the external clock source fails.
Correspondingly, the present application also provides a network device, as shown in fig. 1, including: the system comprises a processor, a memory, a receiver, a crystal oscillator and a phase-locked loop;
the memory has program code stored therein that is called by the processor to perform the following operations:
acquiring a compensation parameter, wherein the compensation parameter is determined based on a compensation signal sent by an external clock source received by a receiver;
determining an iteration value according to the obtained at least two compensation parameters;
converging the iteration value through a Kalman model to determine a convergence value;
and when the fault of the external clock source is determined, writing the determined convergence value into the phase-locked loop so that the phase-locked loop compensates the clock signal generated by the crystal oscillator according to the convergence value.
Optionally, the external clock source is a clock source of 1588 protocol, and the compensation parameter includes phase deviation or frequency deviation;
determining an iteration value according to the obtained at least two compensation parameters, comprising:
recording compensation parameters corresponding to at least two compensation signals in a preset time period;
calculating the difference value between the compensation parameters corresponding to any two compensation signals in the at least two compensation signals;
determining a proportional relation of compensation parameters according to the issuing interval of any two compensation signals, wherein the proportional relation is the fraction proportion of iteration values corresponding to the compensation parameters;
calculating an iteration value according to the difference value and the proportional relation;
compensating the clock signal generated by the crystal oscillator according to the convergence value, comprising:
determining the number of parts of a convergence value corresponding to the compensation time according to the compensation time set in the time period;
calculating an actual compensation value, wherein the actual compensation value is the number of parts multiplied by the convergence value;
and compensating the clock signal generated by the crystal oscillator through the actual compensation value at the compensation time.
Optionally, the external clock source is a clock source of a synchronous ethernet, and the compensation parameter is a compensation coefficient;
the receiver receives a compensation signal sent by an external clock source and sends a compensation coefficient carried in the compensation signal to the phase-locked loop;
determining an iteration value according to the obtained at least two compensation parameters, comprising:
reading a compensation parameter from the phase-locked loop at intervals of a preset time period;
calculating a difference value corresponding to two adjacent compensation parameters as an iteration value;
compensating the clock signal generated by the crystal oscillator according to the convergence value, comprising:
acquiring a compensation coefficient recorded in a phase-locked loop as an initial value and a convergence value determined by a Kalman model;
and calculating an actual compensation value, wherein the actual compensation value is equal to an initial value + N multiplied by a convergence value, and N is the number of time periods which pass after the external clock source fails.
In the embodiment of the present specification, when the network device can acquire the compensation signal, the compensation parameter determined according to the compensation signal is converged through the kalman model, and when the external clock source fault is detected, the clock signal generated by the crystal oscillator is compensated through the convergence value obtained after the convergence, so that when the network device cannot acquire the compensation signal of the external clock source for compensation, a reliable clock compensation mode is provided for the network device, the clock uniformity is improved, and the reliability of data processing and data interaction of the network device and even the network is improved.
It will be understood that the present description is not limited to the precise arrangements described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.
The above description is only for the purpose of illustrating the preferred embodiments of the present disclosure and is not to be construed as limiting the present disclosure, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (11)
1. A clock correction method, comprising:
acquiring a compensation parameter, wherein the compensation parameter is determined based on a compensation signal sent by an external clock source;
determining an iteration value according to the obtained at least two compensation parameters;
converging the iterative value through a Kalman model to determine a convergence value;
and when the external clock source is determined to be in fault, compensating the clock signal generated by the crystal oscillator according to the convergence value.
2. The method according to claim 1, wherein the external clock source is a 1588 protocol clock source, and the compensation parameter includes a phase deviation or a frequency deviation;
determining an iteration value according to the obtained at least two compensation parameters, including:
recording compensation parameters corresponding to at least two compensation signals in a preset time period;
calculating a difference value between compensation parameters corresponding to any two compensation signals in the at least two compensation signals;
determining a proportional relation of the compensation parameters according to the issuing intervals of any two compensation signals, wherein the proportional relation is the fraction proportion of the iteration values corresponding to the compensation parameters;
and calculating an iteration value according to the difference value and the proportional relation.
3. The method of claim 2, wherein compensating the clock signal generated by the crystal oscillator according to the convergence value comprises:
determining the number of parts of a convergence value corresponding to the compensation time according to the compensation time set in the time period;
calculating an actual compensation value, wherein the actual compensation value is the number of parts multiplied by the convergence value;
and compensating the clock signal generated by the crystal oscillator through the actual compensation value at the compensation time.
4. The method according to claim 1, wherein the external clock source is a clock source of a synchronous ethernet, and the compensation parameter is a compensation coefficient determined by a phase-locked loop according to the external clock source;
determining an iteration value according to the obtained at least two compensation parameters, including:
reading a compensation parameter from the phase-locked loop at intervals of a preset time period;
calculating a difference value corresponding to two adjacent compensation parameters as an iteration value;
the compensating the clock signal generated by the crystal oscillator according to the convergence value comprises the following steps:
acquiring a compensation coefficient recorded in a phase-locked loop as an initial value and a convergence value determined by a Kalman model;
and calculating an actual compensation value, wherein the actual compensation value is equal to an initial value + N multiplied by a convergence value, and N is the number of time periods which pass after the external clock source fails.
5. A clock correction apparatus, comprising:
the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring a compensation parameter, and the compensation parameter is determined based on a compensation signal sent by an external clock source;
the calculation unit is used for determining an iteration value according to the acquired at least two compensation parameters;
the convergence unit is used for converging the iteration value through a Kalman model to determine a convergence value;
and the compensation unit is used for compensating the clock signal generated by the crystal oscillator according to the convergence value when the external clock source is determined to be in fault.
6. The apparatus according to claim 5, wherein the external clock source is a clock source of 1588 protocol, and the compensation parameter includes a phase deviation or a frequency deviation;
the calculation unit includes:
the recording module is used for recording compensation parameters corresponding to at least two compensation signals in a preset time period;
the first difference module is used for calculating the difference between the compensation parameters corresponding to any two compensation signals in the at least two compensation signals;
the proportion module is used for determining the proportion relation of the compensation parameters according to the issuing intervals of any two compensation signals, wherein the proportion relation is the proportion of the number of parts of the iteration values corresponding to the compensation parameters;
and the determining module is used for calculating an iteration value according to the difference value and the proportional relation.
7. The apparatus of claim 6, wherein the compensation unit comprises:
the number-of-copies module is used for determining the number of copies of the convergence value corresponding to the compensation time according to the compensation time set in the time period;
the calculating module is used for calculating an actual compensation value, wherein the actual compensation value is the number of parts multiplied by the convergence value;
and the compensation module is used for compensating the clock signal generated by the crystal oscillator through the actual compensation value at the compensation time.
8. The apparatus according to claim 5, wherein the external clock source is a clock source of a synchronous ethernet, and the compensation parameter is a compensation coefficient determined by the phase-locked loop according to the external clock source;
the calculation unit includes:
the reading module is used for reading the compensation parameters from the phase-locked loop at intervals of a preset time period;
the second difference module is used for calculating the difference value corresponding to the two adjacent compensation parameters as an iteration value;
the compensation unit includes:
the acquisition module is used for acquiring a compensation coefficient recorded in a phase-locked loop as an initial value and a convergence value determined by a Kalman model when the external clock source is determined to be in fault;
and the compensation determining module is used for calculating an actual compensation value, wherein the actual compensation value is an initial value + Nx convergence value, and N is the number of time periods elapsed after the external clock source fails.
9. A network device, comprising: the system comprises a processor, a memory, a receiver, a crystal oscillator and a phase-locked loop;
the memory has program code stored therein that is called by the processor to perform the following operations:
acquiring a compensation parameter, wherein the compensation parameter is determined based on a compensation signal sent by an external clock source received by the receiver;
determining an iteration value according to the obtained at least two compensation parameters;
converging the iterative value through a Kalman model to determine a convergence value;
and when the external clock source is determined to be in fault, writing the determined convergence value into the phase-locked loop so that the phase-locked loop compensates the clock signal generated by the crystal oscillator according to the convergence value.
10. The network device according to claim 9, wherein the external clock source is a clock source of 1588 protocol, and the compensation parameter includes a phase deviation or a frequency deviation;
determining an iteration value according to the obtained at least two compensation parameters, including:
recording compensation parameters corresponding to at least two compensation signals in a preset time period;
calculating a difference value between compensation parameters corresponding to any two compensation signals in the at least two compensation signals;
determining a proportional relation of the compensation parameters according to the issuing intervals of any two compensation signals, wherein the proportional relation is the fraction proportion of the iteration values corresponding to the compensation parameters;
calculating an iteration value according to the difference value and the proportional relation;
the compensating the clock signal generated by the crystal oscillator according to the convergence value comprises the following steps:
determining the number of parts of a convergence value corresponding to the compensation time according to the compensation time set in the time period;
calculating an actual compensation value, wherein the actual compensation value is the number of parts multiplied by the convergence value;
and compensating the clock signal generated by the crystal oscillator through the actual compensation value at the compensation time.
11. The network device according to claim 9, wherein the external clock source is a clock source of a synchronous ethernet, and the compensation parameter is a compensation coefficient;
the receiver receives a compensation signal sent by the external clock source and sends a compensation coefficient carried in the compensation signal to the phase-locked loop;
determining an iteration value according to the obtained at least two compensation parameters, including:
reading a compensation parameter from the phase-locked loop at intervals of a preset time period;
calculating a difference value corresponding to two adjacent compensation parameters as an iteration value;
the compensating the clock signal generated by the crystal oscillator according to the convergence value comprises the following steps:
acquiring a compensation coefficient recorded in a phase-locked loop as an initial value and a convergence value determined by a Kalman model;
and calculating an actual compensation value, wherein the actual compensation value is equal to an initial value + N multiplied by a convergence value, and N is the number of time periods which pass after the external clock source fails.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347814A (en) * | 2011-10-11 | 2012-02-08 | 上海电力学院 | Slave clock regulation method based on master clock frequency difference |
| CN104378109A (en) * | 2013-08-13 | 2015-02-25 | 中兴通讯股份有限公司 | Synchronous clock signal compensation method and device |
| CN108156500A (en) * | 2017-12-29 | 2018-06-12 | 珠海全志科技股份有限公司 | Multi-medium data time correcting method, computer installation, computer readable storage medium |
| US10498565B1 (en) * | 2018-09-05 | 2019-12-03 | Macom Technology Solutions Holding, Inc | Sampling phase optimization for digital modulated signals |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8489053B2 (en) * | 2011-01-16 | 2013-07-16 | Siport, Inc. | Compensation of local oscillator phase jitter |
-
2021
- 2021-01-28 CN CN202110119585.9A patent/CN112969229B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347814A (en) * | 2011-10-11 | 2012-02-08 | 上海电力学院 | Slave clock regulation method based on master clock frequency difference |
| CN104378109A (en) * | 2013-08-13 | 2015-02-25 | 中兴通讯股份有限公司 | Synchronous clock signal compensation method and device |
| CN108156500A (en) * | 2017-12-29 | 2018-06-12 | 珠海全志科技股份有限公司 | Multi-medium data time correcting method, computer installation, computer readable storage medium |
| US10498565B1 (en) * | 2018-09-05 | 2019-12-03 | Macom Technology Solutions Holding, Inc | Sampling phase optimization for digital modulated signals |
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