CN117238857A - Electronic device and method for manufacturing the same - Google Patents

Abstract

The present disclosure provides an electronic device and a method for manufacturing the same. The electronic device includes a chip, an element structure layer, a rewiring structure layer, and a protective layer. The chip is provided with an active surface and a plurality of contacts arranged on the active surface. The element structure layer is arranged adjacent to the active surface and is provided with a switching element. The switch element is electrically connected to the chip through at least one of the plurality of contacts. The rewiring structure layer is arranged adjacent to the active surface and is electrically connected to the chip through at least one of the plurality of contacts. The protective layer includes a first portion and a second portion. The first portion surrounds the chip and the second portion surrounds the element structure layer and the redistribution structure layer.

Description

Electronic device and method for manufacturing the same

Technical Field

The present disclosure relates to an electronic device and a method for manufacturing the same.

Background

The market competitiveness of electronic devices is affected by the factors such as the functionality and reliability of the electronic devices, so how to integrate different elements to achieve different functions or to improve the reliability is an important issue.

Disclosure of Invention

The present disclosure provides an electronic device and a method for manufacturing the same, which are helpful for integrating different devices or improving reliability.

According to an embodiment of the disclosure, an electronic device includes a chip, an element structure layer, a rewiring structure layer, and a protective layer. The chip has an active surface (active surface) and a plurality of contacts disposed on the active surface. The element structure layer is arranged adjacent to the active surface and is provided with a switching element. The switch element is electrically connected to the chip through at least one of the plurality of contacts. The rewiring structure layer is arranged adjacent to the active surface and is electrically connected to the chip through at least one of the plurality of contacts. The protective layer includes a first portion and a second portion. The first portion surrounds the chip and the second portion surrounds the element structure layer and the redistribution structure layer.

According to an embodiment of the present disclosure, a method of manufacturing an electronic device includes: forming an element structure layer and a rewiring structure layer on a carrier plate, wherein the element structure layer is provided with a switching element; a chip is arranged on the carrier plate, wherein the chip is provided with an active surface and a plurality of contacts arranged on the active surface, and the contacts are electrically connected with the switching element and the rewiring structure layer; and forming a protective layer on the carrier, wherein the protective layer comprises a first part and a second part, the first part surrounds the chip, and the second part surrounds the element structure layer and the rewiring structure layer.

In order to make the above features and advantages of the present disclosure more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic cross-sectional view of an electronic device according to a first embodiment of the disclosure;

fig. 2 is an enlarged view of region R in fig. 1;

fig. 3A to 3F are schematic cross-sectional views illustrating a manufacturing process of the electronic device according to the first embodiment;

FIG. 4 is a schematic cross-sectional view of an electronic device according to a second embodiment of the disclosure;

fig. 5A to 5E are schematic cross-sectional views illustrating a manufacturing process of the electronic device according to the second embodiment;

FIG. 6 is a schematic top view of an electronic device according to a third embodiment of the disclosure;

Fig. 7 and 8 are a schematic top view and a schematic cross-sectional view, respectively, of an electronic device according to a fourth embodiment of the disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Certain terms are used throughout the description and following claims to refer to particular components. Those skilled in the art will appreciate that electronic device manufacturers may refer to a component by different names. It is not intended to distinguish between components that differ in function but not name. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to …".

Directional terms mentioned herein, such as: "upper", "lower", "front", "rear", "left", "right", etc., are merely directions with reference to the drawings. Thus, the directional terminology is used for purposes of illustration and is not intended to be limiting of the disclosure. In the drawings, the various figures illustrate the general features of methods, structures and/or materials used in certain embodiments. However, these drawings should not be construed as defining or limiting the scope or nature of what is covered by these embodiments. For example, the relative dimensions, thicknesses, and locations of various layers, regions, and/or structures may be reduced or exaggerated for clarity.

The description of one structure (or layer, element, substrate) being above/on another structure (or layer, element, substrate) in this disclosure may refer to two structures being adjacent and directly connected, or may refer to two structures being adjacent and not directly connected. Indirect connection refers to having at least one intervening structure (or intervening layers, intervening elements, intervening substrates, intervening spaces) between two structures, the lower surface of one structure being adjacent to or directly connected to the upper surface of the intervening structure, and the upper surface of the other structure being adjacent to or directly connected to the lower surface of the intervening structure. The intermediate structure may be a single-layer or multi-layer solid structure or a non-solid structure, and is not limited thereto. In the present disclosure, when a structure is disposed "on" another structure, it may mean that the structure is "directly" on the other structure, or that the structure is "indirectly" on the other structure, that is, at least one structure is further interposed between the structure and the other structure.

The terms "about," "equal," or "identical," "substantially," or "substantially" are generally interpreted as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of the given value or range. Furthermore, the terms "range from a first value to a second value," and "range between a first value and a second value," mean that the range includes the first value, the second value, and other values therebetween.

The use of ordinal numbers such as "first," "second," and the like in the description and in the claims is used for modifying an element, and is not by itself intended to exclude the presence of any preceding ordinal number(s) or order(s) of a certain element or another element or order(s) of manufacture, and the use of such ordinal numbers merely serves to distinguish one element having a certain name from another element having a same name. The same words may not be used in the claims and the specification, whereby a first element in the description may be a second element in the claims.

The electrical connection or coupling described in this disclosure may refer to a direct connection or an indirect connection, in which case the terminals of the elements of the two circuits are directly connected or connected with each other by a conductor segment, and in which case the terminals of the elements of the two circuits have a switch, a diode, a capacitor, an inductor, a resistor, other suitable elements, or a combination thereof, but is not limited thereto.

In the present disclosure, the thickness, length and width may be measured by an optical microscope (Optical Microscope, OM), and the thickness or width may be measured by a cross-sectional image of an electron microscope, but is not limited thereto. In addition, any two values or directions used for comparison may have some error. In addition, references in the present disclosure to the terms "equal," "identical," "substantially," or "substantially" generally represent ranges that fall within 10% of the given values or ranges. Furthermore, the terms "a given range of values from a first value to a second value," "a given range falling within a range of values from the first value to the second value," or "a given range between the first value and the second value," mean that the given range includes the first value, the second value, and other values therebetween. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

It is to be understood that the following exemplary embodiments may be substituted, rearranged, and mixed for the features of several different embodiments without departing from the spirit of the disclosure to accomplish other embodiments. Features of the embodiments can be mixed and matched at will without departing from the spirit of the invention or conflicting.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be appreciated that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the present disclosure, the electronic device may include a packaging device, a semiconductor device, a display device, a backlight device, an antenna device, a sensing device, or a stitching device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous type display device or a self-luminous type display device. The display device may include, for example, liquid crystals (QDs), light emitting diodes (leds), fluorescence (fluorescence), phosphorescence (phosphorescence), quantum Dots (QDs), other suitable display media, or combinations of the foregoing. The Antenna arrangement may for example comprise a frequency selective surface (Frequency Selective Surface, FSS), a radio frequency Filter (RF-Filter), a Polarizer, a Resonator or an Antenna or the like. The antenna may be a liquid crystal type antenna or a non-liquid crystal type antenna. The sensing device may be a sensing device for sensing capacitance, light, heat energy or ultrasonic wave, but is not limited thereto. In the present disclosure, an electronic device may include electronic components, which may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, and the like. The diode may comprise a light emitting diode or a photodiode. The light emitting diode may include, for example, an organic light emitting diode (organic light emitting diode, OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot LED (but is not limited thereto. The splicing device can be, for example, a display splicing device or an antenna splicing device, but is not limited to this. It should be noted that the electronic device may be any of the above arrangements, but is not limited thereto. Furthermore, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shape. The electronic device may have a driving system, a control system, a light source system, and other peripheral systems to support a display device, an antenna device, a wearable device (including augmented reality or virtual reality, for example), an in-vehicle device (including an automobile windshield, for example), or a mosaic device.

Fig. 1 is a schematic cross-sectional view of an electronic device according to a first embodiment of the disclosure. Fig. 2 is an enlarged view of region R in fig. 1.

Referring to fig. 1, the electronic device 1 may include a chip 10, a device structure layer 11, a redistribution layer 12, and a passivation layer 13, but is not limited thereto. The electronic device 1 may also comprise other elements or films according to different requirements. For example, the electronic device 1 may further include a buffer layer 14, an insulating layer 15, a conductive pad 16, a bonding pad 17, a conductive pad 18, a bonding pad 19, a via structure V, and an Underfill (UF).

In detail, the chip 10 may include an integrated circuit, a controller, a driver, a processor, a memory, other functional elements, or a combination thereof, and the chip 10 may be a system-on-chip (SoC), a system-on-integrated-circuit (SoIC), a diode, or a variable capacitor, but is not limited thereto.

The chip 10 may have an active surface S10A, a back surface S10R, and a plurality of side surfaces S10S. The back surface S10R is opposite to the active surface S10A, and the active surface S10A is located between the back surface S10R and the redistribution layer 12, but not limited thereto. The plurality of side surfaces S10S are located between the back surface S10R and the active surface S10A, and each of the plurality of side surfaces S10S connects the back surface S10R with the active surface S10A.

The chip 10 may include a plurality of contacts 100 for electrical connection with external components. The plurality of contacts 100 are disposed on the active surface S10A and face the redistribution layer 12, for example. The material of the contacts 100 may include, but is not limited to, metal such as copper, aluminum, titanium, nickel, or combinations thereof.

In some embodiments, the chip 10 may further include an insulating layer 101. The insulating layer 101 is disposed on the active surface S10A and exposes the plurality of contacts 100. The material of the insulating layer 101 may include an organic material, an inorganic material, or a combination of the above. The organic material includes, for example, photosensitive polyimide (photosensitive polyimide, PSPI), polyolefin (polyolefin), soluble Polytetrafluoroethylene (PFA), an ajinomoto build-up film (ABF), epoxy resin (Epoxy resin), benzocyclobutene (BCB), polybenzoxazoles (PBO), or a combination thereof, but is not limited thereto. The inorganic material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The element structure layer 11 is disposed adjacent to the active surface S10A. For example, the device structure layer 11 may include at least one first insulating layer (e.g. the insulating layer 111 and the insulating layer 113), at least one conductive layer (e.g. the conductive layer 112 and the conductive layer 114), and a semiconductor layer (e.g. the semiconductor layer 110), but is not limited thereto. In some embodiments, the semiconductor layer 110, the insulating layer 111, the conductive layer 112, the insulating layer 113, and the conductive layer 114 are sequentially stacked between the buffer layer 14 and the re-wiring structure layer 12, for example, in a thickness direction (e.g., a direction Z) of the electronic device 1. The proximity referred to in this disclosure means that there is a shortest distance between the first element and the second element.

In detail, the semiconductor layer 110 is disposed on the buffer layer 14, and the material of the semiconductor layer 110 may include amorphous silicon (amorphous silicon), polysilicon (polysilicon), or metal oxide, such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), but not limited thereto. The semiconductor layer 110 is, for example, a patterned semiconductor layer, and the semiconductor layer 110 may include a plurality of semiconductor patterns CH (only one is schematically shown). According to some embodiments, the thickness of the semiconductor layer 110 is greater than or equal to 0.5 micrometers (m) and less than or equal to 3 micrometers, but is not limited thereto.

The insulating layer 111 is disposed on the semiconductor layer 110 and the buffer layer 14, and the material of the insulating layer 111 may include an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but is not limited thereto. According to some embodiments, the thickness of the insulating layer 111 is greater than or equal to 0.5 micrometers and less than or equal to 5 micrometers, but is not limited thereto.

The conductive layer 112 is disposed on the insulating layer 111, for example, and the material of the conductive layer 112 may include a metal or a metal stack, such as aluminum, molybdenum, titanium, molybdenum/aluminum/molybdenum, or titanium/aluminum/titanium, but not limited thereto. The conductive layer 112 is, for example, a patterned conductive layer, and the conductive layer 112 may include a plurality of gates GE (only one schematically shown), a plurality of scan lines SL (only one schematically shown), and other circuits (not shown), but is not limited thereto. The plurality of gate electrodes GE are respectively overlapped with the plurality of semiconductor patterns CH in the direction Z, and each gate electrode GE is electrically connected with a corresponding one of the scan lines SL (electrically connected with each other by a dashed double arrow). According to some embodiments, the thickness of the insulating layer 111 is greater than or equal to 1 micron and less than or equal to 5 microns, but is not limited thereto.

The insulating layer 113 is disposed on the insulating layer 111 and the conductive layer 112, and the material and the thickness of the insulating layer 113 can refer to the material of the insulating layer 111, which will not be described again.

The conductive layer 114 is disposed on the insulating layer 113, and the material of the conductive layer 114 may include a metal or a metal stack, such as aluminum, molybdenum, titanium, molybdenum/aluminum/molybdenum, or titanium/aluminum/titanium, but not limited thereto. The conductive layer 114 may be a patterned conductive layer, and the conductive layer 114 may include a plurality of first electrodes E1 (only one is schematically shown), a plurality of second electrodes E2 (only one is schematically shown), a plurality of data lines (not shown), and other circuits (not shown), but is not limited thereto. One of the first electrodes E1 and the second electrodes E2 is a source, and the other one of the first electrodes E1 and the second electrodes E2 is a drain, wherein each source is electrically connected to a corresponding one of the data lines. Each of the first electrodes E1 and the adjacent one of the second electrodes E2 are disposed at opposite sides of the corresponding one of the semiconductor patterns CH, respectively, and each of the plurality of first electrodes E1 and the plurality of second electrodes E2 penetrates the insulating layer 111 and the insulating layer 113 to be in contact with the corresponding one of the semiconductor patterns CH.

The element structure layer 11 has a switching element SW. The switching element SW includes, for example, a semiconductor pattern CH, a gate electrode GE, a first electrode E1, and a second electrode E2. The boundary or range of the switching element SW is defined by, for example, the edge of the semiconductor pattern CH. Fig. 1 schematically shows one switching element SW, but it is understood that the electronic device 1 may include a plurality of switching elements SW, and the plurality of switching elements SW may be arranged in an array.

The redistribution layer (redistribution layer) 12 is disposed adjacent to the active surface S10A. For example, the redistribution layer 12 may include at least one second insulating layer (such as the insulating layer 120 and the insulating layer 123) and at least one conductive layer (such as the conductive layer 121), wherein the at least one second insulating layer and the at least one conductive layer in the redistribution layer 12 are alternately stacked in the direction Z. According to some embodiments, the device structure layer 11 may be electrically connected to the chip 10 through the redistribution structure layer 12. For example, the redistribution layer 12 may be configured to achieve the desired electrical connection relationship between the components. According to some embodiments, the rewiring structure layer 12 may further increase the fan-out area of the conductive circuit of the electronic device, but is not limited thereto.

In detail, the insulating layer 120 is disposed on the insulating layer 113 and the conductive layer 114, and the material of the insulating layer 120 may include an organic material, such as photosensitive polyimide, polyolefin, soluble polytetrafluoroethylene, a film of a material, epoxy, benzocyclobutene, polybenzoxazole, or a combination thereof, but is not limited thereto. According to some embodiments, the thickness T120 of the insulating layer 120 is greater than or equal to 5 microns and less than or equal to 25 microns, but is not limited thereto. According to some embodiments, the thickness T120 of the insulating layer 120 may be greater than the thickness T111 of the insulating layer 111, so that the protection of the device structure layer 11 may be improved by the above design, thereby improving reliability.

The conductive layer 121 is disposed on the insulating layer 120, and the material of the conductive layer 121 may include a metal, such as copper, but not limited thereto. The conductive layer 121 may be a patterned conductive layer, and the conductive layer 121 may include a plurality of wires (e.g., wire W1, wire W2, wire W3, and wire W4). The wiring W1 penetrates through the insulating layer 120 and is electrically connected to a corresponding one of the first electrodes E1. The wiring W2 penetrates through the insulating layer 120 and is electrically connected to a corresponding one of the second electrodes E2. The wiring W3 penetrates through the insulating layer 120 and the insulating layer 113, for example, and is electrically connected to a corresponding one of the scan lines SL. According to some embodiments, the thickness T121 of the conductive layer 121 is greater than or equal to 5 micrometers and less than or equal to 25 micrometers, but is not limited thereto. According to some embodiments, the thickness T121 of the conductive layer 121 may be greater than the thickness of the conductive layer 112.

The insulating layer 122 is disposed on the insulating layer 120 and the conductive layer 121, and the material of the insulating layer 122 may refer to the material of the insulating layer 120 and will not be described again herein.

In fig. 1, at least one second insulating layer (e.g., insulating layer 120 and insulating layer 123) in the redistribution layer 12 is formed using an organic material to provide a planar surface for carrying the conductive layer 121. Compared to at least one first insulating layer (e.g., insulating layer 111 and insulating layer 113) formed of an inorganic material in the device structure layer 11, the thickness of the at least one first insulating layer in the device structure layer 11 is smaller than the thickness of the at least one second insulating layer in the redistribution structure layer 12. Herein, the thickness of the film layer is the maximum thickness of the film layer in the thickness direction (e.g., direction Z) of the electronic device 1, which is located on a plane, as seen in a cross-sectional view of the electronic device 1. In other words, the above-mentioned "the thickness of the at least one first insulating layer in the device structure layer 11 is smaller than the thickness of the at least one second insulating layer in the redistribution structure layer 12" means that the maximum thickness (e.g. the thickness T111 or the thickness T113) of at least one of the insulating layer 111 and the insulating layer 113 in the direction Z is smaller than the maximum thickness (e.g. the thickness T120 or the thickness T123) of at least one of the insulating layer 120 and the insulating layer 123 in the direction Z.

The conductive pad 16 is disposed on the insulating layer 122, and the material of the conductive pad 16 may include a metal such as copper, titanium, nickel, tin, silver, gold, or a combination thereof, but is not limited thereto. Fig. 1 schematically illustrates two conductive pads 16, wherein one conductive pad 16 penetrates the insulating layer 122 to be electrically connected with the wiring W2, and the other conductive pad 16 penetrates the insulating layer 122 to be electrically connected with the wiring W4. However, it should be understood that the number of conductive pads 16 and their connection relationship to other layers may vary according to actual requirements.

The plurality of conductive pads 16 may be electrically connected to external components, such as the plurality of contacts 100 of the chip 10 or other components, such as active components, passive components, etc., through the plurality of bond pads 17. The material of the bonding pads 17 may include metals such as tin, nickel, gold, copper, or combinations thereof, but is not limited thereto. In some embodiments, as shown in fig. 1, the redistribution layer 12 may be electrically connected to the chip 10 through the conductive pad 16 and the contact 100, and the switching element SW may be electrically connected to the chip 10 through the redistribution layer 12, the conductive pad 16 and the contact 100.

In some embodiments, the plurality of conductive pads 16 do not overlap the plurality of semiconductor patterns CH in the direction Z, so as to reduce the probability of the plurality of semiconductor patterns CH being crushed when the plurality of conductive pads 16 are bonded to the plurality of contacts 100. According to some embodiments, in a direction perpendicular to the direction Z (e.g., a lateral direction in fig. 1), a space IV is provided between the side edge of the conductive pad 16 and the side edge of the semiconductor pattern CH, and the space IV is greater than 0m. According to some embodiments, the pitch IV is greater than 5m. According to some embodiments, the pitch IV is greater than 8m.

The protective layer 13 includes a first portion 130 and a second portion 131. The first portion 130 surrounds the chip 10, and the second portion 131 surrounds the element structure layer 11 and the rerouting structure layer 12. In this context, a first element surrounding a second element means that the second element is at least partially disposed within the first element, and the second element may or may not contact a side of the first element. In fig. 1, the first portion 130 contacts, for example, a side S10S of the chip 10, and the second portion 131 contacts, for example, the device structure layer 11 and the redistribution structure layer 12, but the disclosure is not limited thereto. The material of the protective layer 13 may include an organic material, such as a molding compound (epoxy molding compound, EMC) to reduce the influence of moisture. According to some embodiments, the protection layer 13 may further include filler particles, and the material of the filler particles is, but not limited to, silicon oxide, aluminum oxide, or other suitable materials. The filler particles have a particle size of greater than or equal to 0.1 microns and less than or equal to 30 microns. According to some embodiments, a thermal expansion coefficient of the insulating layer 111 is smaller than a thermal expansion coefficient of the insulating layer 120, and a thermal expansion coefficient of the insulating layer 111 is smaller than a thermal expansion coefficient of the protecting layer 13. According to some embodiments, the protection layer 13 may not contact the back surface S10R, but is not limited thereto.

In some embodiments, the first portion 130 and the second portion 131 of the protection layer 13 may be integrally formed, i.e. the first portion 130 and the second portion 131 may be formed at the same time, but not limited thereto. In other embodiments, the first portion 130 and the second portion 131 may be formed sequentially, and the first portion 130 and the second portion 131 may be formed of the same or different materials.

The buffer layer 14 is disposed between the insulating layer 15 and the element structure layer 11, for example, to protect the semiconductor layer 110 or to reduce contamination of the semiconductor layer 110 by a metal layer (e.g., a copper layer) or an organic insulating layer in a high temperature process. The material of the buffer layer 14 may include inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but is not limited thereto. Buffer layer 14 may be a single layer or multiple layers.

In some embodiments, as shown in fig. 2, the buffer layer 14 may include a first sub-layer 140, a second sub-layer 141, and a third sub-layer 142 sequentially stacked in a direction Z. The material of the third sub-layer 142 is, for example, silicon oxide, and the materials of the first sub-layer 140 and the second sub-layer 141 may be the same or different from the inorganic material of the third sub-layer 142. The total thickness T14 of the buffer layer 14 is, for example, between 0.3 microns or more and 2 microns or less, i.e., 0.3 m+.t14+.2m, based on process cost, process time, and protectiveness considerations. In addition, the thickness T142 of the third sub-layer 142 is, for example, greater than the thickness T141 of the second sub-layer 141.

The insulating layer 15 is provided, for example, on a side of the buffer layer 14 remote from the element structure layer 11 and covers the plurality of conductive pads 18. The material of the insulating layer 15 may be an organic material to provide a planar bearing surface. For example, the material of the insulating layer 15 may include photosensitive polyimide, polyolefin, soluble polytetrafluoroethylene, a film of a taste element, epoxy, benzocyclobutene, polybenzoxazole, or a combination thereof, but is not limited thereto. The insulating layer 15 may be a single insulating layer or a plurality of insulating layers stacked along the direction Z, wherein the thickness of the insulating layer of a single layer is greater than or equal to 5 microns and less than or equal to 25 microns, but is not limited thereto.

The conductive pad 18 is disposed between the bonding pad 19 and the insulating layer 15, and the material of the conductive pad 18 can refer to the material of the conductive pad 16, which will not be repeated here.

In some embodiments, the plurality of conductive pads 18 do not overlap the plurality of semiconductor patterns CH in the direction Z to reduce the probability of the plurality of semiconductor patterns CH being crushed when the plurality of conductive pads 18 are bonded with an external element (not shown). According to some embodiments, the conductive pad 18 may have a ground (ground) or floating (floating) potential. According to some embodiments, the conductive pad 18 may further have a heat dissipation function when it is at a dummy (dummy) potential.

The bonding pad 19 is connected to the conductive pad 18 so that the conductive pad 18 is electrically connected to an external element (not shown). The material of the bonding pad 19 may be referred to as the material of the bonding pad 17 and will not be repeated here. According to some embodiments, a maximum width of the bonding pad 19 is greater than a maximum width of the bonding pad 17, and further, a ratio of the width of the bonding pad 19 to the width of the bonding pad 17 may be greater than or equal to 1.2 and less than or equal to 2, wherein the width is measured along a direction perpendicular to the direction Z, for example. By the design, the bonding strength between the electronic device 1 and the external element can be improved. The external component referred to in this disclosure may be, for example, but not limited to, a printed circuit board (Printed circuit board, PCB) or other suitable component.

The via structure V penetrates through the insulating layer 120, the insulating layer 113, the insulating layer 111, the buffer layer 14, and the insulating layer 15 to electrically connect one of the wires (e.g., the wire W1, the wire W3, or the wire W4) with the corresponding one of the conductive pads 18. Fig. 1 schematically shows three via structures V, wherein the via structure V on the left side of fig. 1 electrically connects the wiring W1 with a corresponding one of the conductive pads 18, the wiring W1 is electrically connected with the first electrode E1 of the switching element SW, and the second electrode E2 of the switching element SW is electrically connected to one of the contacts 100 of the chip 10 through the wiring W2, the conductive pad 16 and the bonding pad 17. In addition, the via structure V in the middle of fig. 1 electrically connects the wiring W3 with the corresponding other conductive pad 18, and the wiring W3 is electrically connected with the scan line SL, and the scan line SL is electrically connected with the gate electrode GE of the switching element SW. In addition, the via structure V on the right side of fig. 1 electrically connects the wire W4 with the corresponding further conductive pad 18, and the wire W4 is electrically connected to the other contact 100 of the chip 10 through the conductive pad 16 and the bonding pad 17. However, it should be understood that the number of via structures V and their connection relationship with other elements or layers may be changed according to actual requirements.

The underfill UF is disposed between the chip 10 and the insulating layer 122 to protect the plurality of bonding pads 17 or to promote adhesion between the chip 10 and the plurality of conductive pads 16.

By integrating the element structure layer 11 and the re-wiring structure layer 12 together, it is facilitated to integrate different elements (e.g. chips 10 of different functions) into the electronic device 1, enabling the electronic device 1 to provide more functions. In addition, by the first portion 130 of the protection layer 13 surrounding the chip 10 and the second portion 131 of the protection layer 13 surrounding the element structure layer 11 and the redistribution layer 12, the protection (such as the oxygen blocking capability or scratch resistance) can be improved, so that the reliability of the electronic device 1 as a whole can be improved.

Fig. 3A to 3F are schematic cross-sectional views illustrating a manufacturing process of the electronic device according to the first embodiment. The method of manufacturing the electronic device 1 may include: forming an element structure layer 11 and a rewiring structure layer 12 on the carrier board C, wherein the element structure layer 11 has a switching element SW; the chip 10 is disposed on the carrier, wherein the chip 10 has an active surface S10A and a plurality of contacts 100 disposed on the active surface S10A, and the plurality of contacts 100 are electrically connected to the switching element SW and the redistribution layer 12; and forming a protective layer 13 on the carrier board C, wherein the protective layer 13 includes a first portion 130 and a second portion 131, the first portion 130 surrounds the chip 10, and the second portion 131 surrounds the element structure layer 11 and the redistribution structure layer 12.

In some embodiments, as shown in fig. 3A to 3F, the device structure layer 11 and the redistribution layer 12 may be formed on the carrier C, and then the chip 10 is bonded, and then the protection layer 13 (including the first portion 130 and the second portion 131) is formed.

In detail, referring to fig. 3A, the method for manufacturing the electronic device 1 may include: a release layer RL, a plurality of conductive pads 18, an insulating layer 15, a buffer layer 14, and an element structure layer 11 are sequentially formed on a carrier board C. The release layer RL may be a thermal release layer or a photo release layer, i.e., the tackiness of the release layer RL may be reduced by heat or light, so that the carrier plate C is separated from the film layer or element disposed thereon. The insulating layer 15 may include one or more patterns 150 (two patterns 150 are schematically shown). The plurality of patterns 150 may be separated from one another and, for example, arranged in an array. The contents (such as materials, relative arrangement, etc.) of the plurality of conductive pads 18, the insulating layer 15, the buffer layer 14, and the device structure layer 11 are referred to in the foregoing, and will not be repeated here.

Referring to fig. 3B, the method for manufacturing the electronic device 1 may further include: forming an insulating layer 120 over the insulating layer 113 and the conductive layer 114; and forming a plurality of openings A1, a plurality of openings A2, and a plurality of openings A3, wherein each opening A1 penetrates the insulating layer 120 and exposes a portion of the first electrode E1 or a portion of the second electrode E2, each opening A2 penetrates the insulating layer 120 and the insulating layer 113 and exposes a portion of the scan line SL, and each opening A3 penetrates the insulating layer 120, the insulating layer 113, the insulating layer 111, the buffer layer 14, and the insulating layer 15 and exposes a portion of the conductive pad 18.

In some embodiments, the openings (e.g., the openings A1, A2, and A3) may be formed by one or more patterning processes. Fig. 3B schematically illustrates an aspect formed in a two patterning process. For example, the insulating layer 120 may be removed by a photolithography process, and then the insulating layer 113, the insulating layer 111, the buffer layer 14, and the insulating layer 15 may be removed by a photolithography process or a laser process. Thus, the quality or the process stability of the patterning process can be improved. The size of the opening formed by the first patterning process is, for example, larger than the size of the opening formed by the second patterning process based on process considerations, so that the openings (e.g., the plurality of openings A2 and the plurality of openings A3) formed by the two patterning processes have a stepped profile (see the dashed line box of fig. 3B). According to some embodiments, the corner of at least one insulating layer at the opening may have an arc-shaped profile (see the enlarged view of fig. 3B, which schematically illustrates that the corners of the insulating layer 120 and the insulating layer 113 have arc-shaped profiles), but not limited thereto. Through the design that the opening part corner of insulating layer has arc profile, can slow down the risk that the rete breaks.

Referring to fig. 3C, the method for manufacturing the electronic device 1 may further include: conductive material is formed on the insulating layer 120 and in the openings (e.g., the openings A1, A2, and A3 of fig. 3B) to form the conductive layer 121 including the wirings (e.g., the wirings W1, W2, W3, and W4) and the via structures V. The conductive layer 121 and the plurality of via structures V may have the same material and may be formed simultaneously. In addition, the via structure V formed in the opening A3 of fig. 3B may also have a stepped profile (see the oval dashed box of fig. 3B). According to some embodiments, the corner CN of the via structure V may have an arc profile, which may further reduce the risk of cracking the insulating layer, but is not limited thereto.

Referring to fig. 3D, the method for manufacturing the electronic device 1 may further include: an insulating layer 122 and a plurality of conductive pads 16 are sequentially formed on the insulating layer 120 and the conductive layer 121, and then the plurality of contacts 100 of the plurality of chips 10 are bonded to the plurality of conductive pads 16 through the plurality of bonding pads 17.

Referring to fig. 3E, the method for manufacturing the electronic device 1 may further include: a protective layer 13 is formed on the carrier plate C. The protection layer 13 may be referred to in the foregoing description (e.g., materials, relative arrangement, etc.), and will not be repeated here. In some embodiments, as shown in fig. 3E, the first portion 130 and the second portion 131 of the protection layer 13 may be formed simultaneously and integrally, but not limited thereto. In other embodiments, although not shown in fig. 3E, the first portion 130 and the second portion 131 of the protective layer 13 may be formed sequentially, and the materials of the first portion 130 and the second portion 131 may be the same or different.

Referring to fig. 3E and fig. 3F, the method for manufacturing the electronic device 1 may further include: removal of carrier plate C, such as by a temperature-increasing or light-illuminating process, reduces the tackiness of release layer RL, separating carrier plate C from the film layers or elements disposed thereon (e.g., plurality of conductive pads 18 and insulating layer 15).

In an embodiment in which the insulating layer 15 includes a plurality of patterns 150, a dicing process, for example, dicing along dicing lines CL in fig. 3F, may be performed to form a plurality of (two are schematically shown) electronic devices 1 as shown in fig. 1.

By the design that the organic insulating layers (e.g., insulating layer 120, insulating layer 122, and insulating layer 15) under adjacent chips 10 are separated from each other, adverse effects (e.g., abrasion) of the organic insulating layers on the dicing apparatus (e.g., tool) can be improved or the service life of the dicing apparatus can be prolonged.

Fig. 4 is a schematic cross-sectional view of an electronic device according to a second embodiment of the disclosure. Referring to fig. 4, the main differences between the electronic device 1A and the electronic device 1 of fig. 1 are described as follows.

In the electronic device 1 of fig. 1, an insulating layer 15, a buffer layer 14, an element structure layer 11, a rewiring structure layer 12, a plurality of conductive pads 16, and a plurality of bonding pads 17 are sequentially provided from a plurality of conductive pads 18 to the chip 10. The wire W1 penetrates through the insulating layer 120 and is electrically connected to the first electrode E1, and the wire W1 is electrically connected to a corresponding one of the conductive pads 18 through a via structure V. The wire W2 penetrates the insulating layer 120 to be electrically connected to the second electrode E2, and one conductive pad 16 penetrates the insulating layer 122 to be electrically connected to the wire W2. The wiring W3 penetrates the insulating layer 120 and the insulating layer 113 to be electrically connected to the scan line SL, and the wiring W3 is electrically connected to the other conductive pad 18 through the other via structure V. The wire W4 is electrically connected to the further conductive pad 18 through the further via structure V. The via structure V penetrates the insulating layer 120, the insulating layer 113, the insulating layer 111, the buffer layer 14, and the insulating layer 15. The first portion 130 and the second portion 131 of the protective layer 13 are, for example, integrally formed.

On the other hand, in the electronic device 1A, the electronic device 1A may not include the plurality of conductive pads 16 and the plurality of bonding pads 17 of fig. 1. The insulating layer 15, the buffer layer 14, the element structure layer 11, and the rewiring structure layer 12A are sequentially provided from the chip 10 to the plurality of conductive pads 18. The redistribution structure layer 12A may not include the insulating layer 122 of fig. 1. The wiring W1 is provided on the surface of the insulating layer 113 remote from the chip 10 and connects the first electrode E1 with a corresponding one of the conductive pads 18. The wiring W2 is disposed on the surface of the insulating layer 113 away from the chip 10 and connected to the second electrode E2, and the wiring W2 is electrically connected to a contact 100 through a via structure VA. The wiring W3 is disposed on a surface of the insulating layer 113 away from the chip 10 and penetrates the insulating layer 113 to be electrically connected to the scan line SL. Wire W4 passes through another via structure VA and another contact 100. The via structure VA penetrates the insulating layer 113, the insulating layer 111, the buffer layer 14, and the insulating layer 15. According to some embodiments, a portion of buffer layer 14 is located between first portion 130A and second portion 131A. In detail, the first portion 130A and the second portion 131A of the protective layer 13A are not integrally formed, and a part of the buffer layer 14 is located between the first portion 130A and the second portion 131A.

Fig. 5A to 5E are schematic cross-sectional views illustrating a manufacturing process of the electronic device according to the second embodiment. The main differences between the manufacturing process of fig. 5A to 5E and the manufacturing process of fig. 3A to 3F are described below.

In the manufacturing process of fig. 3A to 3F, the plurality of conductive pads 18, the insulating layer 15, the buffer layer 14, the device structure layer 11 and the redistribution layer 12 are sequentially formed on the carrier C, and then the plurality of chips 10 are bonded, and then the protection layer 13 and the plurality of bonding pads 19 are formed, wherein the first portion 130 and the second portion 131 of the protection layer 13 may be formed simultaneously.

On the other hand, in the manufacturing flow of fig. 5A to 5E, the first portion 130A of the protection layer 13A and the plurality of chips 10 are formed on the carrier C, and then the insulating layer 15, the buffer layer 14, the element structure layer 11, the redistribution structure layer 12A, the second portion 131A of the protection layer 13A and the plurality of bonding pads 19 are sequentially formed. In other words, the first portion 130A and the second portion 131A of the protection layer 13A are sequentially formed, wherein the first portion 130A is formed before the element structure layer 11 and the redistribution layer 12A are formed, and the second portion 131A is formed after the element structure layer 11 and the redistribution layer 12A are formed.

In detail, referring to fig. 5A, the method for manufacturing the electronic device 1A may include: the release layer RL, the first portion 130A of the protective layer 13A, and the plurality of chips 10 are formed on the carrier C, wherein the back surface S10R of the chip 10 is located between the active surface S10A of the chip 10 and the carrier C, and the first portion 130A of the protective layer 13A surrounds the sidewalls S10S of the plurality of chips 10 and exposes the plurality of contacts 100.

In some embodiments, a method of forming the architecture of fig. 5A may include: placing a plurality of chips 10, on which a plurality of contacts 100 are not formed, on another carrier plate (not shown) on which a peeling layer (not shown) is formed, with an active surface S10A between a back surface S10R and the other carrier plate; forming a first portion 130A of the protective layer 13A on the other carrier plate to cover the plurality of chips 10; inverting the entire structure on the carrier plate C formed with the peeling layer RL and removing the other carrier plate; and forming a plurality of contacts 100. Alternatively, a method of forming the architecture of fig. 5A may include: placing a plurality of chips 10, on which the plurality of contacts 100 are not formed, on a carrier plate C on which a peeling layer RL is formed, with a back surface S10R located between an active surface S10A and the carrier plate C; forming a first portion 130A of the protective layer 13A on the carrier board C to cover the plurality of chips 10; performing a polishing process to expose the insulating layer 101; and forming a plurality of contacts 100.

Referring to fig. 5B, the method for manufacturing the electronic device 1A may further include: an insulating layer 15 and a buffer layer 14 are sequentially formed on the first portion 130A and the plurality of chips 10.

Referring to fig. 5C, the method for manufacturing the electronic device 1A may further include: a semiconductor layer 110, an insulating layer 111, a conductive layer 112, and an insulating layer 113 are sequentially formed on the buffer layer 14.

The method of manufacturing the electronic device 1A may further include: a plurality of openings A4, a plurality of openings A5, and a plurality of openings A6 are formed, wherein each opening A4 penetrates the insulating layer 113 and exposes a portion of the scan line SL, each opening A5 penetrates the insulating layer 113 and the insulating layer 111 and exposes a portion of the semiconductor pattern CH, and each opening A6 penetrates the insulating layer 113, the insulating layer 111, the buffer layer 14, and the insulating layer 15 and exposes a portion of the contact 100. The methods for forming the plurality of openings A4, A5 and A6 can refer to the methods for forming the plurality of openings A1, A2 and A3, and will not be repeated here.

According to some embodiments, although not shown in fig. 5C, buffer layer 14 may be patterned via a photolithographic etching process, a laser process, or a combination thereof, such that the edge of buffer layer 14 is recessed a distance from the edge of carrier plate C. According to some embodiments, the step of patterning the buffer layer 14 may be performed together with the step of forming the openings (e.g., the openings A4, A5, and A6) or before or after the step of forming the openings (e.g., simultaneously with the step of forming the openings A7 of fig. 5D); alternatively, the step of patterning the buffer layer 14 may be omitted.

The method of manufacturing the electronic device 1A may further include: the openings A5 are filled with conductive material to form a first electrode E1 and a second electrode E2.

Referring to fig. 5D, the method for manufacturing the electronic device 1A may further include: conductive material is formed on the insulating layer 113 and in the plurality of openings A1, the plurality of openings A2, and the plurality of openings A3 to form a conductive layer 121 including a plurality of wirings (e.g., wiring W1, wiring W2, wiring W3, and wiring W4) and a plurality of via structures VA. The conductive layer 121 and the plurality of via structures VA may have the same material and may be formed simultaneously. In addition, the via structure VA formed at the opening A6 of fig. 5C may also have a stepped profile (see the dashed box of fig. 5C).

The method of manufacturing the electronic device 1A may further include: an insulating layer 120 and a plurality of conductive pads 18 are sequentially formed on the insulating layer 113 and the conductive layer 121, wherein each conductive pad 18 penetrates through the insulating layer 120 and is electrically connected to a corresponding one of the wires W1, W3, and W4.

The method of manufacturing the electronic device 1A may further include: an opening A7 penetrating the insulating layer 120, the insulating layer 113, the insulating layer 111, the buffer layer 14, and the insulating layer 15 is formed between two adjacent chips 10. The opening A7 may be formed via one or more patterning processes. For example, the opening A7 may be formed by a photolithography etching process, a laser process, or a combination thereof, but is not limited thereto. According to some embodiments, the buffer layer 14 may be patterned via a photolithographic etching process, a laser process, or a combination thereof, as described above, such that the edge of the buffer layer 14 is recessed a distance from the edge of the carrier plate C.

Referring to fig. 5E, the method for manufacturing the electronic device 1A may further include: forming a second portion 131A of the protective layer 13A, wherein the second portion 131A fills the opening A7 in fig. 5D and surrounds the element structure layer 11, the re-wiring structure layer 12A, and the buffer layer 14; and forming a plurality of bonding pads 19 on the plurality of conductive pads 18. In detail, in the normal direction (direction Z) of the electronic device 1, a part of the buffer layer 14 is located between the first portion 130A and the second portion 131A. The above design can prevent the influence of water and oxygen on the electronic device, but is not limited thereto.

The method of manufacturing the electronic device 1 may further comprise: a dicing process is performed, for example, along dicing lines CL in fig. 5E, to form a plurality of (two are schematically shown) electronic devices 1A as shown in fig. 4.

By the design that the organic insulating layers (e.g., insulating layer 120 and insulating layer 15) under adjacent chips 10 are separated from each other, adverse effects (e.g., abrasion) of the organic insulating layers on cutting equipment (e.g., tools) can be improved or the service life of the cutting equipment can be prolonged.

Although the above embodiment breaks the organic insulating layers (such as the insulating layer 120 and the insulating layer 15) over the adjacent chips 10 after forming the plurality of conductive pads 18, the present disclosure is not limited thereto. For example, after the insulating layer 15 is formed, the insulating layer 15 may also be subjected to a patterning process to form a plurality of patterns 150 as shown in fig. 3A.

Fig. 6 is a schematic top view of an electronic device according to a third embodiment of the disclosure. Referring to fig. 6, the electronic device 1B may include a chip 10, a device structure layer 11B, a redistribution layer 12B, and a passivation layer 13, but is not limited thereto. The element structure layer 11B may include a plurality of Demultiplexers (DEMUX) U to reduce the number of pins (I/O pins) P or free space. Each demultiplexer U may include a plurality of switching elements SW (three are schematically shown in fig. 6, but is not limited thereto).

Fig. 7 and 8 are a schematic top view and a schematic cross-sectional view, respectively, of an electronic device according to a fourth embodiment of the disclosure. Referring to fig. 7, the main differences between the electronic device 1C and the electronic device 1 of fig. 1 are described as follows.

In the element structure layer 11C of the electronic device 1C, the positions of the semiconductor layer 110 and the conductive layer 112 are reversed. In addition, the element structure layer 11C includes a switching element SW1 and a switching element SW2, and the switching element SW1 and the switching element SW2 constitute an electrostatic discharge (electrostatic discharge, ESD) protection unit. The first electrode E1 of the switching element SW1 penetrates the insulating layer 113 and is electrically connected to the semiconductor pattern CH of the switching element SW1, and the first electrode E1 also penetrates the insulating layer 113 and the insulating layer 111 and is electrically connected to the gate electrode GE of the switching element SW 1. Similarly, the first electrode E1 of the switching element SW2 penetrates the insulating layer 113 to be electrically connected to the semiconductor pattern CH of the switching element SW1, and the first electrode E1 also penetrates the insulating layer 113 and the insulating layer 111 to be electrically connected to the gate electrode GE of the switching element SW 2.

In the electronic device 1C, the conductive layer 121C includes a wiring W1, a wiring W2, a wiring W3, a wiring W4, and a wiring W5. The wiring W1 penetrates the insulating layer 120 and is electrically connected to the first electrode E1 of the switching element SW1, and the wiring W1 is electrically connected to a conductive pad 18 through a via structure V. In addition, the wiring W1 is electrically connected to the wiring W5. The wire W2 penetrates the insulating layer 120 and is electrically connected to the second electrode E2 of the switching element SW1, and the wire W2 is also electrically connected to the wire W3. The wiring W5 penetrates the insulating layer 120 and is electrically connected to the second electrode E2 of the switching element SW 2. The wiring W3 penetrates the insulating layer 120 and is electrically connected to the first electrode E1 of the switching element SW2, and the wiring W3 is electrically connected to the other conductive pad 18 through the other via structure V. The wire W4 is electrically connected to the further conductive pad 18 through the further via structure V.

In the electronic device 1C, the element structure layer 11, the redistribution structure layer 12, the buffer layer 14, and the insulating layer 15 may be patterned by a photolithography etching process, a laser process, other suitable processes, or a combination thereof, so that the protection layer 13 may surround the element structure layer 11, the redistribution structure layer 12, the buffer layer 14, and the insulating layer 15.

In summary, in the embodiments of the disclosure, the integration of the device structure layer and the redistribution structure layer is helpful for integrating different devices (e.g. chips with different functions) into the electronic device, so that the electronic device can provide more functions. In addition, the first part of the protection layer surrounds the chip, the second part of the protection layer surrounds the element structure layer and the rewiring structure layer, so that the protection (such as the oxygen blocking capability or scratch resistance) can be improved, and the reliability of the whole electronic device can be improved.

The above embodiments are only for illustrating the technical solution of the present disclosure, but not limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Although embodiments and advantages thereof have been disclosed, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, and those of skill in the art will appreciate from the present disclosure that any process, machine, manufacture, composition of matter, means, methods and steps which are presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present application. Accordingly, the scope of the present application includes such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes combinations of the individual claims and embodiments. The scope of the present disclosure is defined by the appended claims.

Claims (10)

1. An electronic device, comprising:

the chip is provided with an active surface and a plurality of contacts arranged on the active surface;

the element structure layer is arranged adjacent to the active surface and is provided with a switching element, and the switching element is electrically connected to the chip through at least one of the plurality of contacts;

a rewiring structure layer disposed adjacent to the active surface and electrically connected to the chip through at least one of the plurality of contacts; and

and the protective layer comprises a first part and a second part, wherein the first part surrounds the chip, and the second part surrounds the element structure layer and the rerouting structure layer.

2. The electronic device of claim 1, wherein the first portion contacts a side of the chip and the second portion contacts the element structure layer and the rerouting structure layer.

3. The electronic device of claim 1, wherein the device structure layer comprises at least one first insulating layer, the redistribution structure layer comprises at least one second insulating layer, and a thickness of the at least one first insulating layer is less than a thickness of the at least one second insulating layer.

4. The electronic device of claim 3, wherein the at least one first insulating layer comprises an inorganic material and the at least one second insulating layer comprises an organic material.

5. The electronic device of claim 3, further comprising:

and the through hole structure penetrates through the at least one first insulating layer and the at least one second insulating layer.

6. The electronic device of claim 5, wherein the via structure has a stepped profile.

7. The electronic device of claim 1, further comprising:

a buffer layer, wherein the element structure layer is disposed between the buffer layer and the rewiring structure layer; and

an insulating layer, wherein the buffer layer is disposed between the insulating layer and the element structure layer.

8. A method of manufacturing an electronic device, comprising:

forming an element structure layer and a rewiring structure layer on a carrier plate, wherein the element structure layer is provided with a switching element;

a chip is arranged on the carrier, wherein the chip is provided with an active surface and a plurality of contacts arranged on the active surface, and the contacts are electrically connected with the switch element and the rewiring structure layer; and

And forming a protective layer on the carrier plate, wherein the protective layer comprises a first part and a second part, the first part surrounds the chip, and the second part surrounds the element structure layer and the rerouting structure layer.

9. The method of manufacturing an electronic device according to claim 8, wherein the first portion is formed before the element structure layer and the rerouting structure layer are formed, and wherein the second portion is formed after the element structure layer and the rerouting structure layer are formed.

10. The method of manufacturing an electronic device of claim 9, further comprising:

an insulating layer and a buffer layer are sequentially formed on the carrier before the element structure layer and the rerouting structure layer are formed, wherein a portion of the buffer layer is located between the first portion and the second portion.