CN117954439A

CN117954439A - Electronic device and method for manufacturing electronic device

Info

Publication number: CN117954439A
Application number: CN202310924110.6A
Authority: CN
Inventors: 高克毅; 黄进明; 郑惟元; 乐瑞仁; 李冠锋
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2022-10-27
Filing date: 2023-07-26
Publication date: 2024-04-30
Also published as: TW202418525A

Abstract

The invention provides an electronic device, which comprises at least one electronic element, a packaging layer surrounding the at least one electronic element, a first circuit structure, a second circuit structure and a connecting structure. The packaging layer is provided with an upper surface, a lower surface and at least one opening, wherein a side wall of the at least one opening is connected with the upper surface and the lower surface. The first circuit structure is arranged on the upper surface of the packaging layer. The second circuit structure is arranged on the lower surface of the packaging layer. The connecting structure is arranged in the at least one opening, wherein the at least one electronic element is electrically connected to the second circuit structure through the first circuit structure and the connecting structure. The connecting structure comprises a first sub-layer and a second sub-layer, wherein the first sub-layer is positioned between the packaging layer and the second sub-layer, and the first sub-layer covers the side wall of at least one opening.

Description

Electronic device and method for manufacturing electronic device

Technical Field

The present invention relates to an electronic device and a method for manufacturing the same, and more particularly, to an electronic device including a package structure and a method for manufacturing the same.

Background

A conventional quad flat no-lead (quad flat no leads, QFN) package structure is formed by placing a chip on a leadframe (LEAD FRAME) and electrically connecting the chip to conductive pads on the leadframe by wire bonding (wirebonding). However, the quad flat non-leaded package structure has a high production cost and a large overall thickness. Therefore, how to reduce the production cost of the quad flat non-leaded package structure or reduce the overall thickness of the package structure is one of the important issues in the art.

Disclosure of Invention

The invention aims to provide an electronic device and a manufacturing method of the electronic device.

In some embodiments, the present invention provides an electronic device including at least one electronic component, a package layer surrounding the at least one electronic component, a first circuit structure, a second circuit structure, and a connection structure. The packaging layer is provided with an upper surface, a lower surface and at least one opening, wherein a side wall of the at least one opening is connected with the upper surface and the lower surface. The first circuit structure is arranged on the upper surface of the packaging layer. The second circuit structure is arranged on the lower surface of the packaging layer. The connecting structure is arranged in the opening, wherein at least one electronic element is electrically connected to the second circuit structure through the first circuit structure and the connecting structure. The connecting structure comprises a first sub-layer and a second sub-layer, wherein the first sub-layer is positioned between the packaging layer and the second sub-layer, and the first sub-layer covers the side wall of at least one opening.

In some embodiments, the present invention provides an electronic device including at least one electronic component, a package layer surrounding the at least one electronic component, a first circuit structure, a second circuit structure, and a connection structure. The packaging layer is provided with an upper surface, a lower surface and at least one opening, wherein the side wall of the at least one opening is connected with the upper surface and the lower surface. The first circuit structure is arranged on the upper surface of the packaging layer. The second circuit structure is arranged on the lower surface of the packaging layer. The connecting structure is arranged in the at least one opening, wherein the at least one electronic element is electrically connected to the second circuit structure through the first circuit structure and the connecting structure.

In some embodiments, the present invention provides a method of manufacturing an electronic device, comprising: providing an electronic element; forming an encapsulation layer surrounding the electronic element, wherein the encapsulation layer has an upper surface and a lower surface; forming at least one opening in the packaging layer, wherein the side wall of the at least one opening connects the upper surface and the lower surface; a first circuit structure is arranged on the upper surface of the packaging layer; a second circuit structure is arranged on the lower surface of the packaging layer; and forming a connection structure in the opening, wherein the electronic component is electrically connected to the second circuit structure through the first circuit structure and the connection structure. The connecting structure comprises a first sub-layer and a second sub-layer, wherein the first sub-layer is positioned between the packaging layer and the second sub-layer, and the first sub-layer covers the side wall of at least one opening.

Drawings

Fig. 1 is a schematic cross-sectional view of an electronic device according to a first embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view of an electronic device according to a variation of the first embodiment of the present invention.

Fig. 3A to 3F are schematic views illustrating a manufacturing process of an electronic device according to a first embodiment of the invention.

Fig. 4 is a schematic top view of an electronic device according to a second embodiment of the invention.

Fig. 5 is a schematic cross-sectional view of an electronic device according to a second embodiment of the invention.

Fig. 6A to 6G are schematic diagrams illustrating a manufacturing process of an electronic device according to a second embodiment of the invention.

Fig. 7A to 7B are schematic diagrams illustrating a manufacturing process of an electronic device according to a variation of the second embodiment of the invention.

Fig. 8 is a schematic cross-sectional view of an electronic device according to a third embodiment of the invention.

Fig. 9A to 9C are schematic diagrams illustrating a manufacturing process of an electronic device according to a third embodiment of the invention.

Fig. 10 is a schematic cross-sectional view of an electronic device according to a fourth embodiment of the invention.

Fig. 11A to 11C are schematic views illustrating a manufacturing process of an electronic device according to a fourth embodiment of the invention.

Fig. 12 is a schematic cross-sectional view of an electronic device according to a fifth embodiment of the invention.

Fig. 13A to 13C are schematic views illustrating a manufacturing process of an electronic device according to a sixth embodiment of the invention.

Fig. 14A to 14C are schematic views of a manufacturing process of an electronic device according to a seventh embodiment of the invention.

Fig. 15A to 15D are schematic diagrams illustrating a manufacturing process of an electronic device according to an eighth embodiment of the invention.

Reference numerals illustrate: BE. BE1, BE2, BE3, BE4, BE 5-binding elements; a BL-bonding layer; CL 1-a first circuit structure; CL 2-a second circuit configuration; CP, CP1, CP2, CP 3-conductive pad; CR, CR1, CR 2-carrier plate; CS-connection structure; CT-cut; d1-depth; d3, D4-height; DF. DF1, DF 2-patterned photoresist; ED. ED1, ED3, ED2, ED4, ED5, ED6, ED 7-electronic devices; EL, EL1, EL 2-electronic elements; an EN-packaging layer; GM-abrasive tools; g1-spacing; IL 1-a first insulating layer; IL 2-a second insulating layer; IL3, IL4, IL5, IL6, IL7, IL 8-insulating layers; IML, IML1, IML 2-interlayer; m1-a first conductive layer; m2-a second conductive layer; m3, M4, M5, M6, M7, M8-conductive layers; OP, OP1, OP2, OP ', OP1' -opening; p1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12-moieties; s1, S3 and S5-upper surfaces; s2, S4 and S14-lower surfaces; s6, S7, S8, S11, S13-surfaces; s9, S10, S12-side surfaces; SL 1-first sub-layer; SL 2-second sub-layer; SP-space; SW-side walls; t1, T2, D2-thickness; UBM-bottom metal layer; a Z-direction; A-A' -tangent; θ1, θ2, θ3-included angle.

Detailed Description

The present invention may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, it being noted that, in order to facilitate the understanding of the reader and for the sake of brevity of the drawings, various drawings in the present invention depict only a portion of the apparatus and the specific elements of the drawings are not necessarily drawn to actual scale. In addition, the number and size of the elements in the drawings are illustrative only and are not intended to limit the scope of the invention.

Certain terms are used throughout the description and following claims to refer to particular components. Those skilled in the art will appreciate that electronic device manufacturers may refer to a same component by different names. The present invention is not intended to distinguish between components that differ in function but not name.

In the description and claims, the terms "comprising" and "including" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to …".

It will be understood that when an element or film is referred to as being "disposed on" or "connected to" another element or film, it can be directly on or connected to the other element or film or intervening elements or films may be present therebetween (not directly). In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or film, there are no intervening elements or films present therebetween. When an element or film is referred to as being "electrically connected" to another element or film, it can be construed as being directly electrically connected or indirectly electrically connected. The electrical connection or coupling described in the present invention may refer to a direct connection or an indirect connection, in which case the terminals of the two components on the circuit are directly connected or connected with each other by a conductor segment, and in which case the terminals of the two components on the circuit have a switch, a diode, a capacitor, an inductor, a resistor, other suitable components, or a combination of the above components, but are not limited thereto.

Although the terms "first," "second," "third," … may be used to describe various elements, the elements are not limited by this term. This term is used only to distinguish a single component element from other component elements within the specification. The same terms may not be used in the claims but instead the first, second, third … are substituted in the order in which the elements were recited in the claims. Thus, in the present description, a first constituent element may be a second constituent element in the claims.

In the present invention, the thickness, length and width may be measured by an optical microscope, and the thickness or width may be measured by a cross-sectional image in an electron microscope, but not limited thereto.

In addition, any two values or directions used for comparison may have some error. The terms "about," "equal," or "identical," "substantially," or "substantially" are generally construed to be within a range of about plus or minus 20% of a given value, or to be within a range of about plus or minus 10%, about plus or minus 5%, about plus or minus 3%, about plus or minus 2%, about plus or minus 1%, or about plus or minus 0.5% of a given value.

Furthermore, the terms "a given range of values from a first value to a second value," "a given range falling within a range of values from the first value to the second value," and the like, mean that the given range includes the first value, the second value, and other values therebetween.

If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be appreciated that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be understood that the following embodiments may be used to replace, reorganize, and mix features of several different embodiments to accomplish other embodiments without departing from the spirit of the present invention.

The electronic device of the present invention may include, but is not limited to, a packaging device, a display device, a sensing device, a backlight device, an antenna device, a splicing device, a power management device, or other suitable electronic devices. The electronic device of the present invention may comprise any suitable device applied to the above-described device. The electronic device may be a bendable, flexible or stretchable electronic device. The display device may be applied to, but not limited to, a notebook computer, a public display, a tiled display, a vehicular display, a touch display, a television, a monitor, a smart phone, a tablet computer, a light source module, a lighting device, or an electronic device applied to the above products, for example. The sensing means may comprise a biosensor, a touch sensor, a fingerprint sensor, other suitable sensors or a combination of the above types of sensors. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, for example, but not limited thereto. The splicing device may include, for example, a display splicing device or an antenna splicing device, but is not limited thereto. The shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shape. The electronic device may include an electronic unit, wherein the electronic unit may include passive elements and active elements, such as capacitors, resistors, inductors, diodes, transistors, sensors, and the like. The diode may comprise a light emitting diode or a photodiode. The light emitting diode may include, for example, an Organic LIGHT EMITTING Diode (OLED) or an inorganic light emitting diode (in-organic LIGHT EMITTING diode), which may include, for example, a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot LED, but is not limited thereto. The electronic device may include a semiconductor package device. It should be noted that the electronic device of the present invention can be various combinations of the above devices, but is not limited thereto. It should be noted that the electronic device may be any of the above arrangements, but the present invention is not limited thereto. The electronic device may have a driving system, a control system, a light source system, and other peripheral systems to support a display device, an antenna device, a wearable device (including, for example, an augmented reality or a virtual reality), an in-vehicle device (including, for example, an automobile windshield), or a mosaic device.

Referring to fig. 1, fig. 1 is a schematic cross-sectional view of an electronic device according to a first embodiment of the invention. According to the present embodiment, as shown in fig. 1, the electronic device ED includes an electronic element EL, an encapsulation layer EN surrounding the electronic element EL, a first circuit structure CL1, a second circuit structure CL2 and a connection structure CS, but is not limited thereto. The encapsulation layer EN has an upper surface S1 and a lower surface S2 opposite to the upper surface S1, wherein the first circuit structure CL1 is disposed on the upper surface of the encapsulation layer EN, and the second circuit structure CL2 is disposed on the lower surface of the encapsulation layer EN. In other words, the first circuit structure CL1 and the second circuit structure CL2 are disposed on both sides of the encapsulation layer EN, respectively. The packaging layer EN has an opening OP, and a sidewall SW of the opening OP connects the upper surface S1 and the lower surface S2, wherein the connection structure CS is disposed in the opening OP. The structure of each element of the electronic device ED of the present embodiment will be described in detail below.

The electronic element EL may comprise any suitable active or passive element. For example, the electronic component EL may include a printed circuit board (printed circuit board, PCB), an integrated circuit (INTEGRATED CIRCUIT, IC), a diode, a resistor, a capacitor, other suitable electronic components, or a combination of the foregoing electronic components. The type of the electronic element EL may be determined according to the type of the electronic device ED. In some embodiments, the electronic device ED may comprise a display device, and the electronic element EL may comprise a light emitting diode chip, but is not limited thereto, e.g., the electronic element EL may be a chip comprising one or more elements. In this embodiment, the electronic device ED may include at least one electronic element EL. For example, fig. 1 shows a structure in which the electronic device ED includes two electronic elements EL, but is not limited thereto. It should be noted that the types of the plurality of electronic elements EL in the electronic device ED may be the same or different, depending on the design or use of the electronic device ED. The electronic element EL may include at least one conductive pad CP, wherein the conductive pad CP may be located at one side of the electronic element EL. The conductive pad CP of the electronic element EL may be electrically connected to other conductive elements. In the present embodiment, the number of conductive pads CP of different electronic elements EL may be the same or different. According to some embodiments, the conductive pads CP of different electronic elements EL may be the same or different in size. For example, in a cross-sectional view of the electronic device ED, the widths of the conductive pads CP may be the same or different. The conductive pad CP may comprise any suitable conductive material, such as copper (Cu), aluminum (Al), nickel (Ni), molybdenum (Mo), titanium (Ti), an alloy or combination of the above materials, or other suitable materials, but is not limited thereto. In the present invention, the above-described "width" may be measured, for example, in a direction perpendicular to the direction Z.

The electronic device ED may further include a first insulating layer IL1, wherein the first insulating layer IL1 may be disposed at one side of the electronic element EL. Specifically, the first insulating layer IL1 may be provided on a surface corresponding to one side of the conductive pad CP of the electronic element EL. For example, as shown in fig. 1, the conductive pad CP of the electronic element EL may be located on the upper surface S3 of the electronic element EL, and the first insulating layer IL1 may be disposed on the upper surface S3 of the electronic element EL, but is not limited thereto. The first insulating layer IL1 may serve as a protective layer (passivation layer) of the electronic component EL. The first insulating layer IL1 may include an inorganic insulating material, such as silicon oxide or silicon nitride, but is not limited thereto.

The electronic device ED may further include a second insulating layer IL2, wherein the second insulating layer IL2 may be disposed on a side of the first insulating layer IL1 opposite to the electronic element EL. For example, the second insulating layer IL2 may be disposed on the first insulating layer IL1, but is not limited thereto. In other words, the first insulating layer IL1 is disposed between the second insulating layer IL2 and the electronic element EL. The second insulating layer IL2 may cover the first insulating layer IL1. The second insulating layer IL2 may comprise any suitable organic material, such as ABF (Ajinomoto build-up film) material or Polyimide (PI), but is not limited thereto. In the present embodiment, the elastic coefficient of the second insulating layer IL2 may be greater than that of the first insulating layer IL1.

In the present embodiment, the first insulating layer IL1 has a thickness T1, and the second insulating layer IL2 has a thickness T2, wherein the thickness T2 may be greater than the thickness T1. The thickness T1 of the first insulating layer IL1 may range from 0.5 micrometers (micrometer μm) to 3 μm, and the thickness T2 of the second insulating layer IL2 may range from 5 μm to 25 μm, but is not limited thereto. Since the elastic coefficient of the material of the second insulating layer IL2 may be greater than the elastic coefficient of the material of the first insulating layer IL1, or the thickness T2 of the second insulating layer IL2 may be greater than the thickness T1 of the first insulating layer IL1, the second insulating layer IL2 may provide a protection effect, so as to reduce the possibility of the first insulating layer IL1 being damaged during the process (e.g. dicing process) of the electronic device ED. In detail, when the elastic modulus of the second insulating layer IL2 is greater than that of the first insulating layer IL1, the second insulating layer IL2 can absorb or alleviate stress of the electronic device ED during the dicing process, so as to reduce the risk of cracking the electronic device EL, such as alleviating electrical doubt caused by cracking (dicing) or affecting the subsequent process due to cracking, but not limited thereto. According to some embodiments, the thermal expansion coefficient of the second insulating layer IL2 may be greater than that of the first insulating layer IL1, or the thermal expansion trend of the first insulating layer IL1 is opposite to that of the second insulating layer IL2, so as to reduce the warpage of the electronic device ED.

The encapsulation layer EN may surround the electronic element EL and encapsulate the electronic element EL. Specifically, the encapsulation layer EN may surround the electronic element EL and the first and second insulating layers IL1 and IL2 disposed on the electronic element EL. In this embodiment, "an element surrounds another element" may mean that the element may at least partially contact a side surface of the other element in a cross-sectional view of the electronic device ED. For example, as shown in fig. 1, the encapsulation layer EN may contact side surfaces of the electronic element EL, the first insulating layer IL1, and the second insulating layer IL2. The encapsulation layer EN can provide the waterproof effect of the electronic component EL, thereby improving the reliability of the electronic device ED. The encapsulation layer EN may comprise any suitable encapsulation material, such as, but not limited to, a solid molding material (epoxy molding compound, EMC).

In the present embodiment, the upper surface S1 of the encapsulation layer EN may be adjacent to a side of the electronic element EL where the conductive pad CP is located, and the lower surface S2 may be another surface of the encapsulation layer EN opposite to the upper surface S1. The surface of the electronic element EL on which the conductive pad CP is disposed (i.e., the upper surface S3) may be regarded as an active surface (or active surface) of the electronic element EL, and the surface of the electronic element EL opposite to the active surface (i.e., the lower surface S4) may be regarded as an inactive surface (or back surface) of the electronic element EL. In other words, the upper surface S1 of the encapsulation layer EN may be adjacent to the active surface of the electronic element EL, and the lower surface S2 may be adjacent to the inactive surface of the electronic element EL. The first insulating layer IL1 and the second insulating layer IL2 may be disposed on the active surface of the electronic element EL. In the present embodiment, the upper surface S1 of the encapsulation layer EN may be aligned with the upper surface S5 of the second insulating layer IL2, and the lower surface S2 may be aligned with the back surface (i.e. the lower surface S4) of the electronic element EL, but not limited thereto. In other words, the encapsulation layer EN may expose the upper surface S5 of the second insulating layer IL2 and the back surface of the electronic element EL.

The encapsulation layer EN may have at least one opening OP, which may penetrate the encapsulation layer EN, wherein the opening OP may be formed by removing a portion of the encapsulation layer EN. Thus, the sidewall SW of the opening OP can connect the upper surface S1 and the lower surface S2 of the encapsulation layer EN. In the present embodiment, the opening OP may not overlap the electronic element EL, the first insulating layer IL1, and the second insulating layer IL2 in the normal direction (i.e., the direction Z) of the electronic device ED. In other words, the electronic element EL, the first insulating layer IL1 and the second insulating layer IL2 may not be removed during the formation of the opening OP. The opening OP may have a trapezoid shape in a cross-sectional view of the electronic device ED, but is not limited thereto. In other words, the upper bottom width and the lower bottom width of the opening OP may be different. According to some embodiments, the sidewall SW of the opening OP may have an angle θ2 with the upper surface S1 of the encapsulation layer EN, and the sidewall SW of the opening OP may have an angle θ3 with the lower surface S2 of the encapsulation layer EN, wherein the angle θ2 and the angle θ3 may be the same or different. The included angle θ2 and the included angle θ3 may range from 65 degrees to 135 degrees, but are not limited thereto.

The first circuit structure CL1 may be disposed on the upper surface S1 of the encapsulation layer EN. Specifically, the first circuit structure CL1 may be disposed on the upper surface S1 of the encapsulation layer EN. The first circuit structure CL1 may include any suitable structure formed by a stack of an insulating layer and a conductive layer, wherein the stacking direction of the insulating layer and the conductive layer may be parallel to the normal direction of the electronic device ED. For example, as shown in fig. 1, the first circuit structure CL1 may include a first conductive layer M1 and an insulating layer IL3 disposed on the first conductive layer M1 and covering the first conductive layer M1, but is not limited thereto. In some embodiments, first circuit structure CL1 may include a structure formed from a stack of more conductive layers and insulating layers. In the present embodiment, a conductive layer in the first circuit structure CL1 may be directly disposed on the upper surface S1 of the encapsulation layer EN, or contact the upper surface S1, for example, but not limited to, the first conductive layer M1 of the first circuit structure CL 1. The conductive layer (e.g., the first conductive layer M1) in the first circuit structure CL1 may include any suitable conductive material, such as copper, titanium, nickel, combinations or alloys thereof, but is not limited thereto. The insulating layer (e.g., insulating layer IL 3) in the first circuit structure CL1 may include any suitable insulating material, such as build-up material (bulid up film), polyimide, resin (epoxy), silicon dioxide, silicon nitride, solder mask (solder mask), or a combination thereof, but is not limited thereto. In the present embodiment, a corner (corner) of the insulating layer IL3 opposite to the electronic element EL may be curved or other suitable non-sharp corner shape, but is not limited thereto.

According to the present embodiment, the first circuit structure CL1 may be electrically connected to the electronic element EL. Specifically, the first conductive layer M1 extending on the upper surface S1 of the encapsulation layer EN may be electrically connected to the conductive pad CP of the electronic element EL through the openings OP1 of the first insulating layer IL1 and the second insulating layer IL2, thereby electrically connecting the electronic element EL to the first circuit structure CL1. In detail, the opening OP1 may be formed by removing a portion of the first insulating layer IL1 and a portion of the second insulating layer IL2, wherein the opening OP1 may correspond to the conductive pad CP of the electronic element EL, or the opening OP1 may at least partially overlap the conductive pad CP in a normal direction of the electronic device ED. In this case, the opening OP1 may expose the conductive pad CP. Accordingly, the first conductive layer M1 may fill the opening OP1 and directly contact the conductive pad CP, so that the electronic element EL may be electrically connected to the first circuit structure CL1. The opening OP1 may have a trapezoid shape in a cross-sectional view of the electronic device ED, but is not limited thereto. Specifically, an included angle θ1 may be formed between a sidewall of the opening OP1 (or a portion of the first conductive layer M1 filled into the opening OP 1) and a surface of the first insulating layer IL1, where the included angle θ1 may range from 65 degrees to 85 degrees, but is not limited thereto. Further, in the present embodiment, a portion of the first conductive layer M1 that is not overlapped with the electronic element EL may contact a side surface of the electronic element EL, or that is, a lower surface S14 of the portion of the first conductive layer M1 may be lower than an upper surface S5 of the second insulating layer IL 2. In this case, a space G1 may be provided between the lower surface S14 of the first conductive layer M1 and the upper surface S5 of the second insulating layer IL 2. According to the present embodiment, the pitch G1 may range from 2 μm to 10 μm, for example, but is not limited thereto. By the above design, the degree of fitting of the element (for example, the first conductive layer M1 and the electronic element EL) can be improved, thereby improving the bonding strength. It should be noted that the electrical connection between the first circuit structure CL1 and the electronic element EL is merely exemplary, and the present invention is not limited thereto. According to some embodiments, the size of the openings OP1 corresponding to different electronic elements EL may be the same or different. For example, in a cross-sectional view of the electronic device ED, the widths of the openings OP1 corresponding to different electronic elements EL may be the same or different. In other words, when the electronic device ED includes a plurality of electronic components EL, the width or height of the opening OP1 corresponding to one electronic component EL may be larger than the width or height of the other opening OP1 corresponding to the other electronic component EL, or the width or height of the opening OP1 corresponding to one electronic component EL may be equal to the width or height of the other opening OP1 corresponding to the other electronic component EL.

In the present embodiment, the first conductive layer M1 of the first circuit structure CL1 may overlap the opening OP of the encapsulation layer EN in the normal direction of the electronic device ED, or the first conductive layer M1 may cover the opening OP. In this way, the first circuit structure CL1 may be electrically connected to the second circuit structure CL2 through a connection structure CS (to be described later) in the opening OP.

The second circuit structure CL2 may be disposed on the lower surface S2 of the encapsulation layer EN. Specifically, the second circuit structure CL2 may be disposed under the lower surface S2 of the encapsulation layer EN. In other words, the encapsulation layer EN and the electronic element EL may be disposed between the first circuit structure CL1 and the second circuit structure CL2. Similar to the first circuit structure CL1, the second circuit structure CL2 may include any suitable structure formed by a stack of insulating layers and conductive layers, wherein the stacking direction of the insulating layers and conductive layers may be parallel to the normal direction of the electronic device ED. For example, as shown in fig. 1, the second circuit structure CL2 may include a second conductive layer M2, a conductive layer M3, a conductive layer M4, and an insulating layer IL4, but is not limited thereto. The conductive layer M3 may be located under the second conductive layer M2. Conductive layer M4 may be located under conductive layer M3. The insulating layer IL4 may surround the second conductive layer M2, the conductive layer M3, and the conductive layer M4. In some embodiments, second circuit structure CL2 may include other suitable structures formed from a stack of conductive and insulating layers. It should be noted that the spatial relationship between the film layers (e.g., below … or above …) referred to herein is a spatial relationship describing the film layers in the structure shown in the drawings. The second conductive layer M2, the conductive layer M3 and the conductive layer M4 may comprise any suitable conductive material, such as a metal material, but not limited thereto. The insulating layer IL4 may comprise any suitable insulating material, and the material of the insulating layer IL4 may be the same as or different from the material of the insulating layer IL 3. In this embodiment, a conductive layer (e.g., the second conductive layer M2) in the second circuit structure CL2 may contact the lower surface S2 of the encapsulation layer EN and extend into the opening OP of the encapsulation layer EN. As shown in fig. 2, the second conductive layer M2 of the second circuit structure CL2 may extend into the opening OP and extend on the sidewall SW of the opening OP. Since the opening OP may penetrate the encapsulation layer EN, and the first conductive layer M1 of the first circuit structure CL1 may overlap the opening OP in the normal direction of the electronic device ED, the second conductive layer M2 may contact the first conductive layer M1. In other words, the second circuit structure CL2 and the first circuit structure CL1 may be electrically connected to each other through the opening OP. As described above, since the first circuit structure CL1 can be electrically connected to the electronic element EL, the electronic element EL can be electrically connected to the second circuit structure CL2 through the first circuit structure CL 1.

The connection structure CS may be disposed in the opening OP of the encapsulation layer EN, wherein the connection structure CS may include a first sub-layer SL1 and a second sub-layer SL2. The first sub-layer SL1 may be disposed between the encapsulation layer EN and the second sub-layer SL2, and the first sub-layer SL1 may cover the sidewalls SW of the opening OP. Specifically, the first sub-layer SL1 of the connection structure CS may be a portion of the second conductive layer M2 of the second circuit structure CL2 extending into the opening OP and covering the sidewall SW of the opening OP. In other words, a portion of the second conductive layer M2 may extend into the opening OP to form the first sub-layer SL1. Therefore, the first sub-layer SL1 of the connection structure CS may be connected to the second conductive layer M2 of the second circuit structure CL2 or be the same layer as the second conductive layer M2. Furthermore, at least a portion of the first sub-layer SL1 and the second conductive layer M2 may include the same material. The second sub-layer SL2 may be located on a side of the first sub-layer SL1 opposite to the sidewall SW, i.e., the first sub-layer SL1 may be located between the encapsulation layer EN and the second sub-layer SL2. Specifically, the second sub-layer SL2 may be formed on the surface of the first sub-layer SL1. In this case, the first sub-layer SL1 may be used, for example, as a seed layer (SEED LAYER) to provide the second sub-layer SL2 on the surface thereof. Similarly, the second conductive layer M2 may be used as a seed layer, thereby providing the conductive layer M3 on the surface thereof. The second sub-layer SL2 may include any suitable conductive material, such as copper, titanium, combinations or alloys thereof, but is not limited thereto. It should be noted that, in some embodiments, the first conductive layer M1 of the first circuit structure CL1 may be used as a seed layer, so that other conductive layers are disposed on the surface thereof. Accordingly, as shown in fig. 1, the electronic element EL can be electrically connected to the second circuit structure CL2 through the first circuit structure CL1 and the connection structure CS.

According to the present embodiment, the electronic device ED further includes a bonding element BE, wherein the bonding element BE may BE disposed on a surface of the second circuit structure CL2 opposite to the electronic element EL (for example, but not limited to, a lower surface of the insulating layer IL4 shown in fig. 1). The engagement element BE may BE electrically connected to the second circuit structure CL2. For example, the bonding element BE may BE electrically connected to the conductive layer M4 in the second circuit structure CL2, and in turn, to the conductive layer M3 and the second conductive layer M2 in the second circuit structure CL2. The electronic element EL may BE electrically connected to the bonding element BE through the first circuit structure CL1, the connection structure CS, and the second circuit structure CL2. The engagement element BE may BE electrically connected to any suitable external electronic unit (not shown). In this case, the electronic element EL may BE electrically connected to an external electronic unit through the bonding element BE. The external electronic unit includes, for example, but not limited to, a printed circuit board. In other words, the bonding position of the electronic device ED and the external electronic unit of the present embodiment may be on the back side (the side corresponding to the back side) of the electronic element EL. In this embodiment, the bonding element BE may include nickel, gold, tin, silver, alloys of the above metals, anisotropic conductive paste (anisotropic conductive film, ACF), solder, or other suitable materials. In this case, the bonding element BE can provide a protective effect (e.g., prevent oxidation of the conductive layer) of the conductive layer in the second circuit structure CL2 in addition to electrically connecting the electronic element EL to an external electronic unit, thereby improving the reliability of the electronic device ED. As shown in fig. 1, in the present embodiment, the bonding element BE may not overlap the opening OP of the encapsulation layer EN in the normal direction of the electronic device ED. Alternatively, the engagement element BE and the opening OP may BE disposed in a staggered manner, but not limited thereto.

In the present embodiment, the conductive layers in the first circuit structure CL1 and the second circuit structure CL2 can be patterned, so that the conductive pads CP of the electronic element EL can have different conductive paths or can be electrically connected to different external electronic units. Specifically, the first conductive layer M1 may be patterned to include a plurality of portions electrically insulated from each other, and the conductive pad CP may be electrically connected to different portions of the first conductive layer M1. In some embodiments, the conductive pads CP of different electronic elements EL may be electrically connected to different portions of the first conductive layer M1. In some embodiments, the conductive pads CP of one electronic element EL may be electrically connected to different portions of the first conductive layer M1. In addition, the second conductive layer M2 and the conductive layer M3 in the second circuit structure CL2 may be patterned to include a plurality of portions electrically insulated from each other, wherein the portions may be electrically connected to different portions of the first conductive layer M1, respectively, such that different conductive pads CP may be electrically connected to the second conductive layer M2 (and the conductive layer M3) of the different portions. Furthermore, the conductive layer M4 may BE patterned to correspond to the location of the placement of the bonding element BE, wherein the bonding element BE may BE electrically connected to the second conductive layer M2 (and the conductive layer M3) of the different portions through the conductive layer M4. In this manner, different conductive pads CP can BE electrically connected to different bonding elements BE. For example, as shown in fig. 1, the conductive pad CP1 of the electronic element EL located on the left side may BE electrically connected to the portion P1 of the first conductive layer M1, and the portion P1 of the first conductive layer M1 may BE electrically connected to the portion P2 of the conductive layer M3 through the connection structure CS, so as to electrically connect the conductive pad CP1 to the bonding element BE1 and the bonding element BE2, but not limited thereto. Similarly, conductive pads CP2 and CP3 of the electronic element EL located on the left side may BE electrically connected to portion P3 of the first conductive layer M1, and portion P3 of the first conductive layer M1 may BE electrically connected to portion P4 of the conductive layer M3 through the connection structure CS, thereby electrically connecting conductive pads CP2 and CP3 to the bonding elements BE3, BE 4and BE5, but not limited thereto. It is to BE noted that, although not shown in fig. 1, the conductive pad CP of the electronic element EL located on the right side may BE electrically connected to other bonding elements BE. In some embodiments, first circuit structure CL1 and second circuit structure CL2 can include a rewiring layer (redistribution layer, RDL) such that conductive pad CP of electronic element EL can BE electrically connected to bonding element BE at any suitable location through a routing design in the rewiring layer. In some embodiments, the first circuit structure CL1 and the second circuit structure CL2 may further include driving elements, such as, but not limited to, thin film transistor elements. In this case, the electronic component EL can also be controlled by the first circuit structure CL1 and/or the second circuit structure CL 2. It should BE noted that the above description is only exemplary of the embodiment in which the different conductive pads CP are electrically connected to the different bonding elements BE through the pattern design of the first circuit structure CL1 and the second circuit structure CL2, and the embodiment is not limited thereto. In other embodiments, the manner in which the conductive pads CP are electrically connected to the bonding elements BE and the film designs and pattern designs of the first circuit structure CL1 and the second circuit structure CL2 can BE adjusted according to the design requirements of the electronic device ED.

As described above, the electronic device ED of the present invention may include the electronic element EL surrounded (or packaged) by the packaging layer EN, the first and second circuit structures CL1 and CL2 respectively disposed at both sides of the electronic element EL, and the connection structure CS disposed in the opening OP of the packaging layer EN, wherein the first and second circuit structures CL1 and CL2 respectively include a structure formed by stacking conductive layers and insulating layers, such that the electronic element EL may BE connected to the bonding element BE through the first and second circuit structures CL1 and CS and CL2, and thus electrically connected to the external electronic unit. The electronic device ED of the present invention may include a quad flat no-lead (quad flat no leads, QFN) package structure, but the leadframe (LEAD FRAME) and metal traces for electrically connecting the electronic component to the leadframe are omitted as compared to the conventional quad flat no-lead package structure, i.e., the process of the electronic device ED may not include wire bonding. Since the electronic device ED does not include the lead frame, the production cost of the electronic device ED can be reduced. In addition, since the electronic element EL of the electronic device ED is not electrically connected to an external electronic unit through wire bonding, the overall thickness of the electronic device ED can be reduced.

In addition, as shown in fig. 1, the second circuit structure CL2 may include a conductive layer (e.g., the second conductive layer M2) contacting the back surface (i.e., the lower surface S4) of the electronic element EL. In this case, the conductive layer in the second circuit structure CL2 provides a heat dissipation effect of the electronic element EL, so as to reduce the possibility of overheat of the electronic element EL to affect its performance. For example, the second conductive layer M2 may completely overlap the back surface of the electronic element EL in the normal direction of the electronic device ED, but is not limited thereto. In some embodiments, the second conductive layer M2 may partially overlap the back surface of the electronic element EL in the normal direction of the electronic device ED. Specifically, the heat generated by the electronic element EL can be conducted through the second conductive layer M2 and the conductive layers M3 and M4 contacting the back surface of the electronic element EL, so as to achieve the heat dissipation effect. The second conductive layer M2, the conductive layer M3 and the conductive layer M4 may include, for example, a conductive material with better thermal conductivity, such as copper, but not limited thereto.

Further, as shown in fig. 1, in the present embodiment, the second conductive layer M2 and the conductive layer M3 in the second circuit structure CL2 may be surrounded by the insulating layer IL4, that is, the side surfaces of the second conductive layer M2 and the conductive layer M3 may be covered by the insulating layer IL 4. In other words, the second conductive layer M2 and the conductive layer M3 may not be exposed. In this case, the reliability of the second circuit structure CL2 may be improved by the insulating layer IL 4. In some embodiments, the side surfaces of the second conductive layer M2 and the conductive layer M3 may not be covered by the insulating layer IL 4. In other words, the side surfaces of the second conductive layer M2 and the conductive layer M3 may be exposed, or the side surfaces of the second conductive layer M2 and the conductive layer M3 may be aligned with the side surface of the encapsulation layer EN. In this case, the heat dissipation effect of the electronic element EL provided by the conductive layer of the second circuit structure CL2 can be increased.

Referring to fig. 2, fig. 2 is a schematic cross-sectional view of an electronic device according to a variation of the first embodiment of the invention. According to the present variation, the bonding element BE of the electronic device ED may overlap or partially overlap the opening OP of the encapsulation layer EN in the normal direction of the electronic device ED. In this case, the surfaces of the conductive layers (including, for example, the conductive layer M3 and the conductive layer M4) and the bonding element BE corresponding to the opening OP may have concave surfaces affected by the topography of the opening OP. For example, as shown in FIG. 2, the engagement elements BE (e.g., engagement element BE1 and engagement element BE 3) corresponding to the opening OP may have a surface S6, wherein the surface S6 may BE a concave surface, but is not limited thereto. Surface S6 may BE the surface of the engagement element BE that contacts the external electronic unit. In addition, in the present variant embodiment, the sidewall SW of the opening OP of the encapsulation layer EN may have a rough surface, but is not limited thereto. The feature that the sidewall SW of the opening OP may have a rough surface may be applied to various embodiments and modifications of the present invention, so that the description thereof will not be repeated. Furthermore, in the present embodiment, the insulating layer IL3 of the first circuit structure CL1 may expose a portion of the surface of the encapsulation layer EN (i.e. the surface S1), but is not limited thereto. The other elements and/or features of the film layer of the electronic device ED shown in fig. 2 may be referred to above, and thus will not be described again. It should be noted that the "the element has a rough surface" mentioned above may refer to that the surface of the element has a height fluctuation or the surface of the element exhibits a variation of a peak and a trough in a direction along the Z direction or a direction perpendicular to the Z direction when a cross-sectional view of the electronic device ED is observed by an electron microscope.

Referring to fig. 3A to 3F, fig. 3A to 3F are schematic views illustrating a manufacturing process of an electronic device according to a first embodiment of the invention. According to the present embodiment, the manufacturing method of the electronic device ED may include the steps of:

s102: providing an electronic element;

S104: forming an encapsulation layer surrounding the electronic component, wherein the encapsulation layer has an upper surface and a lower surface;

s106: forming an opening in the encapsulation layer, wherein the opening connects the upper surface and the lower surface;

S108: a first circuit structure is arranged on the upper surface of the packaging layer;

s110: a second circuit structure is arranged on the lower surface of the packaging layer; and

S112: a connection structure is formed in the opening, wherein the electronic component is electrically connected to the second circuit structure through the first circuit structure and the connection structure.

It should be noted that the steps described above are included in the method for manufacturing the electronic device ED, and do not refer to the order of the steps. In some embodiments, different steps may be performed simultaneously. In some embodiments, the processes in different steps may alternate with each other. In addition, other steps may be interposed between any of the steps in the manufacturing method of the electronic device ED as required. Furthermore, any steps in the manufacturing method of the electronic device ED may be adjusted in order or deleted according to the requirements.

The manufacturing method of the electronic device ED of the present embodiment will be described below by taking the process shown in fig. 3A to 3F as an example. It should be noted that the manufacturing method of the electronic device ED shown in fig. 3A to 3F is only exemplary, and the invention is not limited thereto.

As shown in fig. 3A, the method for manufacturing the electronic device ED may first include step S102 to provide the electronic element EL. The features of the electronic component EL are referred to above, and thus will not be described in detail. Next, a first insulating layer IL1 may be disposed on an upper surface S3 of the electronic element EL where the conductive pad CP is located (the upper surface S3 in fig. 3A is located at a lower side of the electronic element EL), and a second insulating layer IL2 may be disposed on a surface of the first insulating layer IL 1. Then, the opening OP1 may be formed by removing a portion of the first insulating layer IL1 and a portion of the second insulating layer IL2, wherein the opening OP1 may correspond to the conductive pad CP of the electronic element EL, i.e. the conductive pad CP may be exposed. The insulating layer removal step may include photolithography, development, etching, laser drilling, mechanical drilling, cleaning, or other suitable means to ensure that the insulating layer is removed, avoiding affecting the electrical characteristics. Then, the composite structure including the electronic element EL, the first insulating layer IL1 and the second insulating layer IL2 may be attached to a carrier CR by an intermediate layer IML in such a way that the second insulating layer IL2 faces down (chip face down), thereby being disposed on the carrier CR. In this case, the second insulating layer IL2 may be located between the electronic element EL and the carrier CR. Then, an encapsulation layer EN may be formed on the carrier CR, wherein the encapsulation layer EN may cover the electronic element EL. In other words, the step of forming the encapsulation layer EN surrounding the electronic element EL may further include providing an insulating layer (e.g., the first insulating layer IL1 and/or the second insulating layer IL 2) on the surface (i.e., the upper surface S3) of the electronic element EL. Thus, the structure shown in fig. 3A can be formed. In this case, the surface of the encapsulation layer EN contacting the intermediate layer IML may be the upper surface S1 shown in fig. 1, and the encapsulation layer EN may include a surface S7 opposite to the carrier CR, wherein the surface S7 may be higher than the back surface (i.e. the lower surface S4) of the electronic element EL, but is not limited thereto. The carrier CR may comprise any suitable supporting material, such as, but not limited to, a glass substrate, a silicon substrate, a BT carrier, a steel plate, or a combination thereof. The intermediate layer IML may comprise any suitable adhesive material for temporarily securing the electronic component EL to the carrier CR, and the adhesive material may be de-tacky by any physical or chemical means during the manufacturing process.

Then, the carrier CR1 may be disposed on the surface S7 of the encapsulation layer EN. Specifically, the encapsulation layer EN may be attached to the carrier plate CR1 through the intermediate layer IML 1. Thereafter, the formed structure is turned over so that the electronic element EL can be disposed on the carrier board CR1, as shown in fig. 3B. In this case, the conductive pad CP of the electronic element EL faces upward, or the active face of the electronic element EL faces upward. Next, the carrier CR and the intermediate layer IML may be removed to expose the opening OP1 and the upper surface S1 of the encapsulation layer EN, and the first conductive layer M1 is disposed on the upper surface S1 of the encapsulation layer EN. The first conductive layer M1 may be disposed on the upper surface S1 of the encapsulation layer EN by any suitable process, such as sputtering (sputtering), electroplating, and chemical plating, but not limited thereto. The first conductive layer M1 may fill the opening OP1 and contact the conductive pad CP of the electronic element EL. In addition, the first conductive layer M1 may be disposed corresponding to a predetermined disposition position of the opening OP of the subsequent encapsulation layer EN, such that the first conductive layer M1 may overlap the opening OP in a normal direction (i.e., the direction Z) of the carrier CR1. Specifically, a whole layer of the material of the first conductive layer M1 may be disposed on the upper surface S1 of the encapsulation layer EN, and the first conductive layer M1 may be formed by a patterning process. Thus, the structure shown in fig. 3B can be formed. According to some embodiments, a cleaning step is performed before providing the first conductive layer M1 to ensure the cleanliness of the opening OP1, so as to avoid affecting the electrical characteristics. According to some embodiments, the patterning process includes, but is not limited to, photolithography, dry etching, wet etching, developing, or other suitable process steps.

Next, an insulating layer IL3 may be disposed on the first conductive layer M1, so as to complete step S108, and a first circuit structure CL1 is formed on the upper surface of the encapsulation layer EN. The step of forming the insulating layer IL3 may include surface-treating the first conductive layer M1, and then the insulating layer IL3 may be disposed on the first conductive layer M1 by coating, bonding, high temperature and high pressure, etc. In this way, the adhesion between the insulating layer IL3 and the first conductive layer M1 can be improved, but not limited thereto. After forming the first circuit structure CL1, the carrier CR2 may be disposed on the first circuit structure CL1. Specifically, the first circuit structure CL1 may be attached to the carrier plate CR2 through the intermediate layer IML 2. Thereafter, the formed structure is flipped so that the electronic component EL can be disposed on the carrier board CR2, as shown in fig. 3C. Then, a polishing process (polishing) or a polishing process (polishing) may be performed on the surface S7 of the encapsulation layer EN opposite to the upper surface S1, so as to remove a portion of the encapsulation layer EN to expose the back surface (the lower surface S4) of the electronic device EL. After the polishing process, the lower surface S2 of the encapsulation layer EN is exposed, so that step S104 is completed to form the encapsulation layer EN surrounding the electronic element EL, wherein the encapsulation layer EN has an upper surface S1 and a lower surface S2. Thus, the structure shown in fig. 3C can be formed.

Next, referring to fig. 3D, step S106 may be performed to form an opening OP in the encapsulation layer EN, wherein a sidewall SW of the opening OP connects the upper surface S1 and the lower surface S2 of the encapsulation layer EN. The opening OP penetrating the encapsulation layer EN may be formed by removing a portion of the encapsulation layer EN, wherein the opening OP does not penetrate the electronic element EL, or the opening OP does not overlap the electronic element EL in the normal direction (i.e., the direction Z) of the carrier CR 2. As described above, since the first conductive layer M1 may also be disposed corresponding to a predetermined disposition position of the opening OP, the opening OP may expose the first conductive layer M1 after the opening OP is formed. In addition, although not shown in fig. 3D, the surface of the first conductive layer M1 exposed by the opening OP may be changed into a concave surface by the process of the opening OP, but not limited thereto, according to some embodiments, when the first conductive layer M1 has a concave surface, the adhesion strength between the connection structure CS and the first conductive layer M1 may be improved, but not limited thereto. The step of forming the opening OP includes laser drilling, mechanical drilling, etching, cleaning, combinations thereof or other suitable steps. According to some embodiments, the sidewall SW of the opening OP has a rough surface through the step of forming the opening OP, so as to improve the adhesion strength between the conductive layer and the encapsulation layer EN, but not limited thereto. Then, a second conductive layer M2 may be formed on the lower surface S2 of the encapsulation layer EN, wherein the second conductive layer M2 may extend on the lower surface of the encapsulation layer EN and contact the lower surface S2. In addition, the second conductive layer M2 may enter the opening OP and extend on the sidewall SW of the opening OP. Furthermore, since the opening OP exposes the first conductive layer M1, the second conductive layer M2 may extend over a portion of the first conductive layer M1 exposed by the opening OP, thereby contacting the first conductive layer M1. The second conductive layer M2 may be disposed by any suitable process, such as sputtering, electroplating, chemical plating, but not limited thereto. A portion of the second conductive layer M2 located in the opening OP may be the first sub-layer SL1 of the connection structure CS, that is, the second conductive layer M2 of the second circuit structure CL2 and the first sub-layer SL1 of the connection structure CS may be formed simultaneously or be the same layer. After forming the second conductive layer M2 and the first sub-layer SL1, the second sub-layer SL2 may be formed in the opening OP. In particular, the second sub-layer SL2 may be formed on the first sub-layer SL 1. The second sub-layer SL2 may be formed by, for example, electroplating, but not limited to, the foregoing. The first sub-layer SL1 may be located between the encapsulation layer EN and the second sub-layer SL2, and the first sub-layer SL1 may cover the sidewalls SW of the opening OP. The first sub-layer SL1 may, for example, serve as a seed layer to facilitate the formation of the second sub-layer SL2 thereon. After the second sub-layer SL2 is formed, step S112 may be completed, and the connection structure CS is formed in the opening OP, wherein the electronic element EL is electrically connected to the second circuit structure CL2 through the first circuit structure CL1 and the connection structure CS. Thereafter, a conductive layer M3 may be formed on the second conductive layer M2, wherein the conductive layer M3 may contact the second sub-layer SL2. The conductive layer M3 may be formed by, for example, electroplating, but is not limited thereto. The second conductive layer M2 may, for example, serve as a seed layer to facilitate the formation of the conductive layer M3 thereon. In some embodiments, the second sub-layer SL2 and the conductive layer M3 may be formed in the same process, for example, the second sub-layer SL2 and the conductive layer M3 may be formed simultaneously by electroplating. In this manner, the structure shown in FIG. 3D may be formed.

Next, as shown in fig. 3E, a conductive layer M4 may be disposed on the conductive layer M3, wherein the conductive layer M4 may be patterned. The formation of the conductive layer M4 may include, but is not limited to, dry etching, wet etching, electroplating, polishing, laser cleaning, or other suitable steps. Then, an insulating layer IL4 may be disposed on the conductive layer M4, so as to complete step S110, and a second circuit structure is disposed on the lower surface of the encapsulation layer. The insulating layer IL4 may surround the second conductive layer M2, the conductive layer M3, and the conductive layer M4, and may expose a surface S8 of the conductive layer M4 opposite to the conductive layer M3. Specifically, after the insulating layer IL4 is disposed, if the insulating layer IL4 covers the surface S8 of the conductive layer M4, a polishing process may be performed on the insulating layer IL4, so that the surface S8 of the conductive layer M4 may be exposed, but not limited thereto. Thus, the structure shown in fig. 3E can be formed.

After forming the second circuit structure CL2, the carrier CR2 and the intermediate layer IML2 may be removed. Thereafter, a bonding element BE may BE formed on the conductive layer M4, wherein the bonding element BE may BE disposed corresponding to the conductive layer M4. Thus, the structure shown in fig. 3F can be formed. Then, a dicing process may be performed on the structure shown in fig. 3F to form a plurality of electronic devices ED. For example, the structure shown in fig. 3F may be cut along a scribe line CT, thereby forming the electronic device ED shown in fig. 1.

Further embodiments of the invention will be described hereinafter. For simplicity, the same reference numerals are used for the same layers or elements in the following embodiments, and the features thereof will not be described again, but the differences between the embodiments will be described in detail below.

Referring to fig. 4 and 5, fig. 4 is a schematic top view of an electronic device according to a second embodiment of the invention, and fig. 5 is a schematic cross-sectional view of the electronic device according to the second embodiment of the invention. Specifically, fig. 4 shows a schematic top view of two electronic devices ED1 formed on the same carrier plate. After the dicing process (e.g., dicing along dicing lines CT, but not limited to, the structure shown in fig. 4 may be divided into two electronic devices ED1, which are shown in the dashed boxes of fig. 4, respectively. For simplifying the drawing, fig. 4 only shows the electronic element EL in the electronic device ED1 and the conductive layers in the first circuit structure CL1 and the second circuit structure CL2, and the detailed structure of the electronic device ED1 can refer to fig. 5, but not limited thereto. In addition, FIG. 5 may be a cross-sectional view of the structure shown in FIG. 4 along the line of tangents A-A'. As shown in fig. 5, the electronic device ED may include an electronic element EL, an encapsulation layer EN surrounding the electronic element EL, a first circuit structure CL1 disposed on an upper surface S1 of the encapsulation layer EN, and a second circuit structure CL2 disposed under a lower surface S2 of the encapsulation layer EN. The features of the electronic element EL and the encapsulation layer EN are referred to above, and thus will not be described in detail.

According to the present embodiment, the first circuit structure CL1 includes, but is not limited to, a first conductive layer M1, a conductive layer M5, and an insulating layer IL 5. The first conductive layer M1 may contact the upper surface S1 of the encapsulation layer EN. The conductive layer M5 may be formed on the first conductive layer M1. The insulating layer IL5 may cover the first conductive layer M1 and the conductive layer M5. In this embodiment, the first conductive layer M1 of the first circuit structure CL1 may enter the opening OP and may extend on the sidewall SW of the opening OP. In other words, the first sub-layer SL1 of the connection structure CS of the present embodiment may be connected to the first conductive layer M1 or be the same layer as the first conductive layer M1. The first conductive layer M1 may, for example, serve as a seed layer to facilitate the formation of the conductive layer M5 thereon. The first conductive layer M1 may extend into the opening OP1 and contact the conductive pad CP of the electronic element EL. The conductive layer M5 may be filled into the opening OP1, but is not limited thereto. In this embodiment, the conductive layers (e.g., the first conductive layer M1 and the conductive layer M5, but not limited thereto) in the first circuit structure CL1 can BE patterned to form a plurality of portions, and different conductive pads CP can BE electrically connected to different portions of the conductive layers in the first circuit structure CL1, thereby being electrically connected to different portions of the second circuit structure CL2, or to different bonding elements BE.

The second circuit structure CL2 may include, but is not limited to, a second conductive layer M2, a conductive layer M6, and an insulating layer IL6. The second conductive layer M2 may contact the lower surface S2 of the encapsulation layer EN. In addition, the second conductive layer M2 may at least partially overlap the opening OP in the normal direction (i.e., the direction Z) of the electronic device ED1, such that the first conductive layer M1 of the first circuit structure CL1 may contact the second conductive layer M2 after entering the opening OP, thereby electrically connecting the first circuit structure CL1 and the second circuit structure CL2. The conductive layer M6 is located under the second conductive layer M2. In the present embodiment, the conductive layers (such as the second conductive layer M2 and the conductive layer M6, but not limited thereto) of the second circuit structure CL2 may be patterned to form the space SP, and the insulating layer IL6 may be disposed in the space SP. In other words, the second conductive layer M2 and the conductive layer M6 may be patterned first, and then the insulating layer IL6 is disposed. The lower surface of the insulating layer IL6 may be aligned with the lower surface of the conductive layer M6. In the present embodiment, the patterned conductive layer M6 may correspond to the patterned second conductive layer M2, or the pattern of the conductive layer M6 may be the same as the pattern of the second conductive layer M2, but is not limited thereto. Specifically, as shown in fig. 4 and 5, the conductive layer of the second circuit structure CL2 may be patterned to form a portion P5 and a plurality of portions P6, wherein the portions P5 and P6 may include a portion of the second conductive layer M2 and a portion of the conductive layer M6, respectively. The portion P5 may correspond to the electronic element EL and may contact the back surface (i.e., the lower surface S4) of the electronic element EL, and the portion P6 may be electrically connected to the first circuit structure CL1. In other words, the electronic element EL may be electrically connected to the portion P6 of the second circuit structure CL2 through the first circuit structure CL1. Since the conductive layer of the second circuit structure CL2 can contact the electronic element EL, it can provide a heat dissipation effect of the electronic element EL. The portion P5 and the plurality of portions P6 may be electrically insulated from each other, but not limited thereto. The above-described "portion P5 corresponds to the electronic element EL" may mean that the second conductive layer M2 and the conductive layer M6 in the portion P5 correspond to the electronic element EL. The above-described "portion P6 may be electrically connected to the first circuit structure CL1" may refer to the second conductive layer M2 and the conductive layer M6 in the portion P6 being electrically connected to the first circuit structure CL1. For example, as shown in fig. 4 and 5, in the electronic element EL in the electronic device ED1, one of the conductive pads CP may be electrically connected to one portion P6 of the conductive layer in the second circuit structure CL2 through a portion (e.g., portion P7) of the conductive layer in the first circuit structure CL1 and the connection structure CS in the opening OP, and the other of the conductive pads CP may be electrically connected to the other portion P6 of the conductive layer in the second circuit structure CL2 through the other portion (e.g., portion P8) of the conductive layer in the first circuit structure CL1 and the connection structure CS in the opening OP, but not limited thereto. The electronic device ED1 may also include a bonding element BE located under the conductive layer M6. Specifically, the bonding element BE may BE disposed corresponding to the conductive layer M6. Thus, the electronic element EL can BE electrically connected to an external electronic unit through the bonding element BE provided corresponding to the conductive layer M6 in the portion P6. In some embodiments, the bonding element BE may not BE disposed under the conductive layer M6 in the portion P5.

In the present embodiment, the side surface S9 of a portion of the outermost second conductive layer M2 and the side surface S10 of a portion of the outermost conductive layer M6 may not be covered by the insulating layer IL6, but is not limited thereto. In other words, the side surfaces S9 and S10 may be exposed, or the side surfaces S9 and S10 may be aligned with the side surfaces of the encapsulation layer EN. In this case, the second conductive layer M2 and the conductive layer M6 may be exposed, thereby improving the heat dissipation effect of the electronic element EL provided by the conductive layer of the second circuit structure CL 2.

Further, in the present embodiment, the size of the portion P5 of the conductive layer of the second circuit structure CL2 may be substantially matched to the size of the electronic element EL. Specifically, the side of the portion P5 may substantially correspond to the side of the electronic element EL. For example, in the top view direction of the electronic device ED1, the portion P5 and the electronic element EL may have rectangular shapes, and four sides of the portion P5 may correspond to four sides of the electronic element EL, but not limited thereto. In some embodiments, as shown in fig. 4, the side of the portion P5 may slightly protrude from the side of the corresponding electronic element EL. In some embodiments, as shown in fig. 5, the sides of the portion P5 may be aligned with the sides of the corresponding electronic element EL. Further, in some embodiments, as shown in fig. 5, the second conductive layer M2 and the conductive layer M6 in the portion P5 may be patterned. In this way, the stress to which the portion P5 is subjected can be reduced. In some embodiments, the second conductive layer M2 and the conductive layer M6 in the portion P5 may not be patterned.

In this embodiment, a plurality of electronic devices ED1 may be formed on the same carrier, and then the electronic devices ED1 are separated by a dicing process. In some embodiments, as shown in fig. 4, the conductive layers of the second circuit structure CL2 of the electronic device ED1 on the same carrier board may be connected to each other. In other words, the conductive layers of the second circuit structure CL2 of each electronic device ED1 may be electrically connected to each other before performing the dicing process. After the dicing process, the conductive layer of the second circuit structure CL2 of each electronic device ED1 may be disconnected, and the conductive layers of the second circuit structure CL2 (e.g., the portion P6) at both sides of the disconnected position may be electrically connected to the external electronic unit, which may serve as a contact between the electronic device ED1 and the external electronic unit. It should be noted that, in some embodiments, the conductive layers in the second circuit structures CL2 may not be disposed corresponding to the dicing lanes CT, i.e., the conductive layers in the second circuit structures CL2 in the electronic devices ED1 may not be connected to each other. In this case, the insulating layer IL6 of the second circuit structure CL2 may be disposed corresponding to the scribe line CT. Thus, the difficulty of the dicing process can be reduced, and the yield of the electronic device ED1 can be improved.

It should be noted that the structures of the first circuit structure CL1 and the second circuit structure CL2 in the present embodiment are not limited to those shown in fig. 4 and 5, and any suitable structure can be included according to the design requirement of the electronic device ED 1. The other elements and/or features of the film layer of the electronic device ED1 shown in fig. 4 and 5 may be referred to above, and thus will not be described again.

An embodiment of a method for manufacturing the electronic device ED1 of the present embodiment will be described below.

Referring to fig. 6A to 6G, fig. 6A to 6G are schematic views illustrating a manufacturing process of an electronic device according to a second embodiment of the invention. As shown in fig. 6A, the method for manufacturing the electronic device ED1 of the present embodiment may include providing an electronic element EL, disposing a first insulating layer IL1 on an upper surface S3 of the electronic element EL where the conductive pad CP is located, and disposing a second insulating layer IL2 on the first insulating layer IL 1. Then, an opening OP1 may be formed by removing a portion of the first insulating layer IL1 and a portion of the second insulating layer IL2, wherein the opening OP1 may expose the conductive pad CP of the electronic element EL. Then, the composite structure including the electronic element EL, the first insulating layer IL1 and the second insulating layer IL2 may be attached to a carrier CR by an intermediate layer IML with the second insulating layer IL2 facing downward, so as to be disposed on the carrier CR. Then, an encapsulation layer EN may be disposed on the carrier CR, where the encapsulation layer EN may cover the electronic element EL. In this case, the upper surface S1 of the encapsulation layer EN shown in fig. 5 may contact the intermediate layer IML. Then, a polishing process is performed on the encapsulation layer EN by using the polishing tool GM, so as to expose the lower surface S2 of the encapsulation layer EN. Thus, the structure shown in fig. 6A can be formed.

Next, as shown in fig. 6B, a patterned second conductive layer M2 and a patterned conductive layer M6 may be formed on the lower surface S2 of the encapsulation layer EN. In the present embodiment, the patterned second conductive layer M2 and the patterned conductive layer M6 may overlap the predetermined setting position of the opening OP in the normal direction (i.e., the direction Z) of the carrier CR. In one embodiment, the patterned second conductive layer M2 and the patterned conductive layer M6 may be formed as follows. First, a whole second conductive layer M2 may be formed on the lower surface S2 of the encapsulation layer EN, wherein the second conductive layer M2 may be used as a seed layer. Then, a patterned photoresist layer may be disposed on the second conductive layer M2, and the conductive layer M6 may be disposed between the patterned photoresist layers, thereby forming a patterned conductive layer M6. The pattern of the photoresist layer may be dependent on the pattern of the conductive layer M6. Then, the photoresist layer is removed, and the second conductive layer M2 is patterned according to the pattern of the conductive layer M6. Thus, the structure shown in fig. 6B can be formed. In this case, a portion of the second conductive layer M2 and the conductive layer M6 may be removed to form a space SP, wherein the space SP may expose a portion of the lower surface S2 of the encapsulation layer EN. It should be noted that the above method for forming the patterned second conductive layer M2 and the patterned conductive layer M6 is only exemplary, and the present embodiment is not limited thereto. According to some embodiments, the step of forming the space SP may include a laser, yellow light, dry etching, wet etching, cleaning, or other suitable step. According to some embodiments, when forming the space SP, a recess structure (as shown in fig. 6B, not shown in the subsequent figures) may be formed on a surface of the encapsulation layer EN (i.e., a surface S2 of the encapsulation layer EN facing the space SP). Thus, the adhesion between the insulating layer IL6 and the encapsulation layer EN can be improved, but not limited thereto.

After forming the patterned second conductive layer M2 and the conductive layer M6, an insulating layer IL6 may be disposed on the conductive layer M6, wherein the insulating layer IL6 may cover the conductive layer M6 and may fill the space SP. Next, an interlayer IML1 and a carrier CR1 may be disposed on the insulating layer IL6 (e.g., the insulating layer IL6 may be attached to the carrier CR1 through the interlayer IML 1), and the formed structure may be flipped over (as shown in fig. 6C). In this case, the electronic element EL may be disposed on the carrier board CR 1. Next, the carrier CR and the intermediate layer IML may be removed. Thereafter, a portion of the encapsulation layer EN may be removed to form an opening OP, wherein the opening OP may expose a portion of the second conductive layer M2. Thus, the structure shown in fig. 6C can be formed.

Next, as shown in fig. 6D, a first conductive layer M1 may be formed on the upper surface S1 of the encapsulation layer EN, wherein the first conductive layer M1 may extend on the upper surface S1 of the encapsulation layer EN and may extend into the opening OP and the opening OP1. The first conductive layer M1 may extend on the sidewall SW of the opening OP and contact the second conductive layer M2, so as to be electrically connected to the second conductive layer M2. The first conductive layer M1 may extend into the opening OP1 and contact the conductive pad CP of the electronic element EL, thereby being electrically connected to the electronic element EL. A portion of the first conductive layer M1 extending on the sidewall SW of the opening OP may form the first sub-layer SL1 of the connection structure CS. Thereafter, a second sub-layer SL2 of the connection structure CS may be formed in the opening OP. Specifically, a patterned photoresist DF may be disposed on the first conductive layer M1, where the patterned photoresist DF may expose the opening OP. Next, a second sub-layer SL2 may be formed in the opening OP by patterning the photoresist DF. The second sub-layer SL2 may be formed by, for example, electroplating, but not limited to, the foregoing.

As shown in fig. 6E, after the second sub-layer SL2 is formed, the patterned photoresist DF may be removed, and the patterned photoresist DF1 may be disposed on the first conductive layer M1. The patterned photoresist DF1 may expose the opening OP and the opening OP1. In some embodiments, the patterned photoresist DF1 may be formed by removing a portion of the patterned photoresist DF (including a portion corresponding to the opening OP 1). Next, a conductive layer M5 may be formed by patterning the photoresist DF1, wherein the conductive layer M5 may be connected between the opening OP and the opening OP1. The conductive layer M5 may be filled into the opening OP1, but is not limited thereto. The conductive layer M5 may be formed by, for example, electroplating, but is not limited thereto.

In the present embodiment, the second sub-layer SL2 and the conductive layer M5 can be formed by two electroplating processes, but not limited thereto. In this case, the second sub-layer SL2 may be formed in the opening OP1 first, and then the conductive layer M5 may be formed to fill the opening OP 1. Thus, the possibility of increasing the electroplating difficulty due to the overlarge depth difference between the openings OP1 and OP can be reduced. In some embodiments, the second sub-layer SL2 and the conductive layer M5 may be formed in the same electroplating process.

After the conductive layer M5 is formed, a patterning process may be performed on the first conductive layer M1, and then the insulating layer IL5 is disposed on the conductive layer M5. The first conductive layer M1 may be patterned, for example, according to the pattern of the conductive layer M5, so that the first conductive layer M1 may correspond to the conductive layer M5, but is not limited thereto. The insulating layer IL5 may cover the conductive layer M5. Thereafter, an intermediate layer IML2 and a carrier CR2 may be disposed on the insulating layer IL5 (e.g., the insulating layer IL5 may be attached to the carrier CR2 through the intermediate layer IML 2), and the formed structure may be flipped over (as shown in fig. 6F). In this case, the electronic element EL may be disposed on the carrier board CR 2. Then, the carrier CR1 and the intermediate layer IML1 may be removed. Thereafter, a polishing process may be performed on the insulating layer IL6 (e.g., a portion of the insulating layer IL6 is removed by the polishing tool GM), so as to expose a surface (e.g., the surface S11) of the conductive layer M6. In this case, the surface of the insulating layer IL6 may be aligned with the surface of the conductive layer M6. Thus, the structure shown in fig. 6F can be formed.

Next, as shown in fig. 6G, a bonding element BE may BE disposed on the conductive layer M6, wherein the bonding element BE may correspond to the conductive layer M6. Then, a dicing process is performed to remove the intermediate layer IML2 and the carrier CR2, thereby forming the electronic device ED1 shown in fig. 5. In some embodiments, the intermediate layer IML2 and the carrier CR2 may be removed first, and then a dicing process may be performed. In some embodiments, a dicing process may be performed first, and then the interlayer IML2 and the carrier CR2 may be removed.

Another embodiment of the method for manufacturing the electronic device ED1 of the present embodiment is described below.

Referring to fig. 7A to 7B, fig. 7A to 7B are schematic views illustrating a manufacturing process of an electronic device according to a variation of the second embodiment of the invention. The method for manufacturing the electronic device ED1 according to the present embodiment may include providing the structure shown in fig. 6A, wherein after the polishing process is performed on the encapsulation layer EN to expose the lower surface S2 of the encapsulation layer EN, an entire second conductive layer M2 may be disposed on the lower surface S2 of the encapsulation layer EN. Next, as shown in fig. 7A, an intermediate layer IML1 and a carrier CR1 may be disposed on the second conductive layer M2 (for example, the second conductive layer M2 may be attached to the carrier CR1 through the intermediate layer IML 1), and the formed structure may be flipped. In this case, the electronic element EL may be disposed on the carrier board CR 1. Next, the carrier CR and the intermediate layer IML shown in fig. 6A may be removed, and an opening OP is formed in the encapsulation layer EN.

Next, as shown in fig. 7A, a first conductive layer M1 may be formed on the upper surface S1 of the encapsulation layer EN, wherein the first conductive layer M1 may extend on the upper surface S1 and may extend into the opening OP and the opening OP1, thereby being electrically connected to the second conductive layer M2 and the electronic component EL. A portion of the first conductive layer M1 extending on the sidewall SW of the opening OP may form the first sub-layer SL1 of the connection structure CS.

Next, as shown in fig. 7A, a second sub-layer SL2 of the connection structure CS may be formed in the opening OP, a conductive layer M5 may be formed on the first conductive layer M1, the first conductive layer M1 may be patterned, and an insulating layer IL5 may be disposed on the conductive layer M5. The forming method of the second sub-layer SL2, the conductive layer M5 and the insulating layer IL5 can refer to fig. 6D to 6F and the related matters above, and thus will not be repeated.

After the insulating layer IL5 is formed, as shown in fig. 7B, an intermediate layer IML2 and a carrier CR2 may be provided on the insulating layer IL5 (for example, the insulating layer IL5 may be attached to the carrier CR2 through the intermediate layer IML 2), and the formed structure may be flipped. In this case, the electronic element EL may be disposed on the carrier board CR 2. Then, the carrier CR1 and the intermediate layer IML1 may be removed. Thereafter, a step of disposing the conductive layer M6 on the second conductive layer M2 and a step of patterning the second conductive layer M2 and the conductive layer M6 may be performed, which may refer to fig. 6B and the above related contents, and thus will not be described again. After forming the patterned second conductive layer M2 and the conductive layer M6, an insulating layer IL6 may BE disposed on the conductive layer M6 (refer to fig. 6C), a polishing process may BE performed on the insulating layer IL6 to expose the conductive layer M6 (refer to fig. 6F), and a bonding element BE may BE disposed on the conductive layer M6 (refer to fig. 6G). Then, a dicing process is performed to remove the intermediate layer IML2 and the carrier CR2, thereby forming the electronic device ED1 shown in fig. 5.

It should be noted that the manufacturing method of the electronic device ED1 is only exemplary, and the invention is not limited thereto.

Referring to fig. 8, fig. 8 is a schematic cross-sectional view of an electronic device according to a third embodiment of the invention. One of the main differences between the electronic device ED2 of the present embodiment and the electronic device ED1 shown in fig. 5 is the design of the second circuit structure CL 2. According to the present embodiment, the side surface of the portion of the conductive layer of the second circuit structure CL2 at the outermost side may be at least partially covered with the insulating layer without being aligned with the side surface of the encapsulation layer EN. In other words, at least a portion of the conductive layer of the second circuit structure CL2 in the outermost portion may not be exposed. For example, as shown in fig. 8, the outermost portion of the conductive layer M6 of the second circuit structure CL2 may include a side surface S12 partially covered by the insulating layer IL6, so that the side surface S12 may not be exposed, or may not be aligned with the side surface of the encapsulation layer EN, but is not limited thereto. That is, at least a portion of the conductive layer M6 in the outermost portion may not be exposed. In other words, the insulating layer IL6 may surround a portion of the conductive layer M6. In some embodiments, the insulating layer IL6 may entirely cover the side surfaces of the portion of the conductive layer M6 at the outermost side. In some embodiments, the insulating layer IL6 may entirely cover the side surface of the portion of the conductive layer M6 at the outermost side and partially cover the side surface of the portion of the first conductive layer M1 at the outermost side.

The following describes a method for manufacturing the electronic device ED2 of the present embodiment. It should be noted that the following manufacturing method of the electronic device ED2 is only exemplary, and the invention is not limited thereto.

Referring to fig. 9A to 9C, fig. 9A to 9C are schematic views illustrating a manufacturing process of an electronic device according to a third embodiment of the invention. According to the present embodiment, the method for manufacturing the electronic device ED2 may first include forming the structure shown in fig. 7A. Specifically, the structure shown in fig. 7A can be formed by referring to the process shown in fig. 7A, but is not limited thereto. Next, as shown in fig. 9A, an interlayer IML2 and a carrier CR2 may be disposed on the insulating layer IL5, and the formed structure may be flipped over, and then the interlayer IML1 and the carrier CR1 (shown in fig. 7A) may be removed to expose the second conductive layer M2. In this case, the electronic element EL may be disposed on the carrier board CR 2. Thereafter, a patterned photoresist DF may be disposed on the second conductive layer M2, and a portion of the conductive layer M6, i.e., a portion P9, may be formed by the patterned photoresist DF. The pattern of the patterned photoresist DF may be dependent on the pattern of the portion P9.

Next, as shown in fig. 9B, after forming the portion P9 of the conductive layer M6, another patterned photoresist DF1 may be disposed on the portion P9. The patterned photoresist DF1 may include a portion corresponding to the patterned photoresist DF and another portion aligned with a side surface of the encapsulation layer EN, but is not limited thereto. After the patterned photoresist DF1 is disposed, another portion of the conductive layer M6, i.e., the portion P10, can be formed by patterning the photoresist DF1. Since the patterned photoresist DF1 includes a portion that is aligned with a side surface of the encapsulation layer EN, the portion P10 may not be aligned with the side surface of the encapsulation layer EN. The portions P9 and P10 of the conductive layer M6 may be formed by electroplating, for example, but not limited thereto. In other words, the portion P9 and the portion P10 may be formed by two electroplating processes to form the conductive layer M6.

Next, as shown in fig. 9C, after the conductive layer M6 is formed, the patterned photoresist DF and the patterned photoresist DF1 are removed, and a patterning process is performed on the second conductive layer M2. Specifically, a portion of the second conductive layer M2 exposed after the removal of the patterned photoresist DF and the patterned photoresist DF1 may be removed. Thereafter, an insulating layer IL6 may be disposed, wherein the insulating layer IL6 may be filled into a space (not shown) formed by removing the patterned photoresist DF, the patterned photoresist DF1, and a portion of the second conductive layer M2. The surface of the insulating layer IL6 may be aligned with the surface of the portion P10 of the conductive layer M6 or the portion P10 that does not protrude from the conductive layer M6.

Then, the bonding element BE is disposed corresponding to the portion P10 of the conductive layer M6, and the dicing process and the step of removing the interlayer IML2 and the carrier CR2 are performed, so as to form the electronic device ED2 shown in fig. 8.

Referring to fig. 10, fig. 10 is a schematic cross-sectional view of an electronic device according to a fourth embodiment of the invention. One of the main differences between the electronic device ED3 of the present embodiment and the electronic device ED1 shown in fig. 5 is the design of the second circuit structure CL 2. According to the present embodiment, the side surface of the portion of the conductive layer of the second circuit structure CL2 at the outermost side may be covered with the insulating layer without being aligned with the side surface of the encapsulation layer EN. In other words, the portion of the conductive layer of the second circuit structure CL2 at the outermost side may not be exposed. For example, as shown in fig. 10, the side surfaces (including the side surfaces S9 and S10) of the outermost portions of the conductive layers (including the second conductive layer M2 and the conductive layer M6) of the second circuit structure CL2 may be covered by the insulating layer IL6, so that they may not be exposed, or may not be aligned with the side surfaces of the encapsulation layer EN. In other words, the insulating layer IL6 may surround the conductive layer of the second circuit structure CL 2. By the above design, the reliability of the second circuit structure CL2 can be improved.

The following describes a method for manufacturing the electronic device ED3 of the present embodiment. It should be noted that the following manufacturing method of the electronic device ED3 is only exemplary, and the invention is not limited thereto.

Referring to fig. 11A to 11C, fig. 11A to 11C are schematic views illustrating a manufacturing process of an electronic device according to a fourth embodiment of the invention. According to the present embodiment, the method for manufacturing the electronic device ED3 may first include forming the structure shown in fig. 7A. Specifically, the structure shown in fig. 7A can be formed by referring to the process shown in fig. 7A, but is not limited thereto. Next, as shown in fig. 11A, an interlayer IML2 and a carrier CR2 may be disposed on the insulating layer IL5, and the formed structure may be flipped over, and then the interlayer IML1 and the carrier CR1 (shown in fig. 7A) may be removed to expose the second conductive layer M2. In this case, the electronic element EL may be disposed on the carrier board CR 2. Then, the second conductive layer M2 may be patterned and a patterned photoresist DF may be disposed. Specifically, a portion of the second conductive layer M2 adjacent to the outer edge of the encapsulation layer EN may be removed, and the patterned photoresist DF may be disposed corresponding to the location of the removed portion of the second conductive layer M2. The patterned photoresist DF may be aligned with a side surface of the encapsulation layer EN. After the patterned photoresist DF is disposed, a patterned photoresist DF1 may be disposed on the second conductive layer M2, and a portion of the conductive layer M6, that is, a portion P11, is formed by the patterned photoresist DF and the patterned photoresist DF 1.

Next, as shown in fig. 11B, after forming the portion P11, a patterned photoresist DF2 may be disposed on the patterned photoresist DF and the patterned photoresist DF1. The patterned photoresist DF2 may correspond to the patterned photoresist DF and the patterned photoresist DF1. Thereafter, another portion of the conductive layer M6, i.e., the portion P12, may be formed by patterning the photoresist DF1. Thus, the conductive layer M6 not aligned to the side surface of the encapsulation layer EN can be formed.

Next, as shown in fig. 11C, after the conductive layer M6 is formed, the patterned photoresist DF1 and the patterned photoresist DF2 are removed, and a patterning process is performed on the second conductive layer M2. Specifically, a portion of the second conductive layer M2 exposed after the removal of the patterned photoresist DF1 and the patterned photoresist DF2 may be removed. Thereafter, an insulating layer IL6 may be disposed, wherein the insulating layer IL6 may be filled into a space (not shown) formed by removing the patterned photoresist DF, the patterned photoresist DF1, the patterned photoresist DF2, and a portion of the second conductive layer M2. The surface of insulating layer IL6 may be level with the surface of portion P12 of conductive layer M6.

Then, the bonding element BE is disposed corresponding to the portion P12 of the conductive layer M6, and the dicing process and the step of removing the interlayer IML2 and the carrier CR2 are performed, so as to form the electronic device ED3 shown in fig. 10.

Referring to fig. 12, fig. 12 is a schematic cross-sectional view of an electronic device according to a fifth embodiment of the invention. One of the main differences between the electronic device ED4 of the present embodiment and the electronic device ED1 shown in fig. 5 is the design of the first circuit structure CL 1. According to the present embodiment, both sides of the electronic device ED4 can be used for electrical connection to an external electronic unit. Specifically, the first circuit structure CL1 and the second circuit structure CL2 of the electronic device ED4 can be electrically connected to an external electronic unit. For example, as shown in fig. 12, the first circuit structure CL1 may further include, in addition to the first conductive layer M1, the conductive layer M5, and the insulating layer IL5, an insulating layer IL7 disposed on the insulating layer IL5 and covering the conductive layer M5, a conductive layer M7 disposed on the insulating layer IL7, an insulating layer IL8 disposed on the insulating layer IL7 and covering the conductive layer M7, and a bottom metal layer UBM disposed on a surface of the insulating layer IL8, but is not limited thereto. Conductive layer M7 may be electrically connected to conductive layer M5 through vias through insulating layer IL 7. The bottom metal layer UBM may contact the conductive layer M7, thereby being electrically connected to the conductive layer M7. In this embodiment, the bottom metal layer UBM may be electrically connected to an external electronic unit. The surface of the bottom metal layer UBM contacting the external electronic unit may be a concave surface, but is not limited thereto. Accordingly, the electronic element EL may be electrically connected to an external electronic unit through the bottom metal layer UBM of the first circuit structure CL 1. It should be noted that the first circuit structure CL1 shown in fig. 12 is only exemplary, and the present embodiment is not limited thereto. In some embodiments, a conductive pad CP in the electronic element EL may be electrically connected to the external electronic unit through the first circuit structure CL 1. In some embodiments, a conductive pad CP in the electronic element EL may be electrically connected to an external electronic unit through the first circuit structure CL1, and the conductive pad CP may also be electrically connected to another external electronic unit through the second circuit structure CL 2.

Please refer to fig. 13A to 13C. Fig. 13A to 13C are schematic views illustrating a manufacturing process of an electronic device according to a sixth embodiment of the invention. The structure shown in fig. 13C is an embodiment of the electronic device ED5 of the present embodiment, but the present embodiment is not limited thereto. As shown in fig. 13A, the method for manufacturing the electronic device ED5 may first include attaching the second conductive layer M2 to the carrier CR through the intermediate layer IML. Then, the electronic element EL may be disposed on the second conductive layer M2. In the present embodiment, the electronic element EL may be attached to the second conductive layer M2 through the bonding layer BL. The bonding layer BL may comprise any suitable adhesive material. Accordingly, the bonding layer BL may be disposed between the electronic element EL and the second conductive layer M2. The electronic component EL may be attached to the second conductive layer M2 with the conductive pad CP facing upward. Next, a first insulating layer IL1 and a second insulating layer IL2 may be provided on the electronic element EL. After the second insulating layer IL2 is formed, an encapsulation layer EN surrounding the electronic element EL, the first insulating layer IL1, and the second insulating layer IL2 may be formed. The lower surface S2 of the encapsulation layer EN may contact the second conductive layer M2, and the upper surface S1 may be aligned with a surface of the second insulating layer IL2 opposite to the first insulating layer IL 1. For example, an encapsulation layer EN may be disposed on the carrier CR, where the encapsulation layer EN may cover the electronic element EL, the first insulating layer IL1, and the second insulating layer IL2. Then, a polishing process is performed on the encapsulation layer EN by using the polishing tool GM, so as to expose the surface of the second insulating layer IL2.

After the encapsulation layer EN is formed, the process shown in fig. 7A may be referred to form the opening OP in the encapsulation layer EN, the opening OP1 exposing the conductive pad CP, the connection structure CS, and the first circuit structure CL1, thereby forming the structure shown in fig. 13A. Details of the above devices and/or layers may be referred to in fig. 7A and above, and thus are not described herein.

As shown in fig. 13B, after the first circuit structure CL1 is formed, the intermediate layer IML1 and the carrier CR1 may be disposed on the insulating layer IL5, the formed structure may be flipped over, and the carrier CR and the intermediate layer IML may be removed. Next, a patterned photoresist layer DF may be disposed on the second conductive layer M2, and a conductive layer M6 may be formed through the patterned photoresist layer DF. The details of the process of the conductive layer M6 can be referred to above, and thus will not be described again.

As shown in fig. 13C, after the conductive layer M6 is formed, the patterned photoresist DF may be removed, and a portion of the second conductive layer M2 exposed after the patterned photoresist DF is removed may be removed to pattern the second conductive layer M2. Next, the insulating layer IL6 may BE disposed in a space (not shown) formed by removing the patterned photoresist DF and a portion of the second conductive layer M2, and the bonding element BE may BE disposed corresponding to the conductive layer M6. Details of the above processes are referred to above, and thus will not be described again. Then, a dicing process and a step of removing the intermediate layer IML1 and the carrier CR1 may be performed to form the electronic device ED5. One of the main differences between the electronic device ED5 of the present embodiment and the electronic device ED1 shown in fig. 5 is that the bonding layer BL is located between the electronic element EL and the second conductive layer M2. It should be noted that the manufacturing method of the electronic device ED5 is only exemplary, and the invention is not limited thereto.

Referring to fig. 14A to 14C, fig. 14A to 14C are schematic views illustrating a manufacturing process of an electronic device according to a seventh embodiment of the invention. Fig. 14C shows an embodiment of the electronic device ED6 according to the present embodiment, but the present embodiment is not limited thereto. As shown in fig. 14A, the manufacturing method of the electronic device ED6 may include, but is not limited to, attaching the second conductive layer M2 to the carrier CR through the intermediate layer IML, and attaching the electronic element EL to the second conductive layer M2 through the bonding layer BL. In some embodiments, the electronic element EL may be disposed directly on the second conductive layer M2. Thereafter, a first insulating layer IL1 and a second insulating layer IL2 may be provided on the electronic element EL.

According to the present embodiment, the manufacturing method of the electronic device ED6 may further include disposing the conductive layer M8 on the second conductive layer M2, wherein the conductive layer M8 may contact the second conductive layer M2, so as to be electrically connected to the second conductive layer M2. In the present embodiment, the conductive layer M8 can be used as an alignment mark (ALIGNMENT MARK) of the electronic component EL. Specifically, in the present embodiment, the conductive layer M8 may be disposed on the second conductive layer M2 first, and then the electronic element EL may be disposed on the second conductive layer M2. The conductive layer M8 may not overlap the electronic element EL in the normal direction of the carrier CR. In this case, the conductive layer M8 provided on the second conductive layer M2 can assist in positioning the electronic component EL, thereby reducing the possibility that the electronic component EL deviates from the predetermined set position. In addition, according to the present embodiment, the conductive layer M8 may overlap the opening OP of the encapsulation layer EN formed in the subsequent process in the normal direction of the carrier CR. After the conductive layer M8, the electronic element EL, the first insulating layer IL1, and the second insulating layer IL2 are formed, the encapsulation layer EN may be formed. The lower surface S2 of the encapsulation layer EN may contact the second conductive layer M2, and the upper surface S1 may be aligned with a surface of the second insulating layer IL2 opposite to the first insulating layer IL 1. For example, a package layer EN covering the electronic element EL, the first insulating layer IL1, and the second insulating layer IL2 may be first provided on the carrier CR. Then, a polishing process is performed on the encapsulation layer EN by using the polishing tool GM, so as to expose the surface of the second insulating layer IL 2. In this embodiment, the encapsulation layer EN may cover the conductive layer M8, that is, the upper surface S1 of the encapsulation layer EN is higher than the surface S13 of the conductive layer M8 opposite to the second conductive layer M2.

As shown in fig. 14A, after forming the encapsulation layer EN, an opening OP in the encapsulation layer EN, an opening OP1 exposing the conductive pad CP, the connection structure CS, and the first circuit structure CL1 may be formed next. The details of the above process may refer to fig. 7A and the above, and thus are not repeated. According to the present embodiment, since the conductive layer M8 may overlap the opening OP of the encapsulation layer EN formed in the subsequent process in the normal direction of the carrier CR, at least a portion of the surface S13 of the conductive layer M8 may be exposed after removing a portion of the encapsulation layer EN to form the opening OP. In this case, the first conductive layer M1 may extend into the opening OP and contact the surface S13 of the conductive layer M8, or the first sub-layer SL1 of the connection structure CS contacts the surface S13 of the conductive layer M8. Accordingly, the connection structure CS may be electrically connected to the conductive layer M8. According to the present embodiment, since the conductive layer M8 may be formed on the second conductive layer M2 before the opening OP is formed, the depth of the opening OP may be smaller than the thickness of the encapsulation layer EN. For example, the depth D1 of the opening OP may be smaller than the thickness D2 of the encapsulation layer EN. Thus, the difficulty of the process of forming the connection structure CS in the opening OP can be reduced. Specifically, by reducing the depth D1 of the opening OP by providing the conductive layer M8, the possibility that the connection structure CS (e.g., the second sub-layer SL 2) cannot be effectively filled into the opening OP due to an excessive depth of the opening OP can be reduced. Further, since the depth D1 of the opening OP can be reduced by providing the conductive layer M8, a depth gap between the depth D1 of the opening OP and the depth of the opening OP1 can be reduced. In this case, the second sub-layer SL2 and the conductive layer M5 of the connection structure CS can be formed simultaneously, for example, the second sub-layer SL2 and the conductive layer M5 can be formed by a single electroplating process, but not limited thereto. It should be noted that, in the present embodiment, the conductive layer M8 may be regarded as being disposed in an opening OP 'of the encapsulation layer EN, and the opening OP' may form an opening OP2, wherein the opening OP2 may be connected to the upper surface S1 and the lower surface S2 of the encapsulation layer EN.

Next, as shown in fig. 14B, after the first circuit structure CL1 is formed, the intermediate layer IML1 and the carrier CR1 may be disposed on the insulating layer IL5, the formed structure may be flipped over, and the carrier CR and the intermediate layer IML may be removed. Next, a patterned photoresist layer DF may be disposed on the second conductive layer M2, and a conductive layer M6 may be formed through the patterned photoresist layer DF. The details of the process of the conductive layer M6 can be referred to above, and thus will not be described again.

As shown in fig. 14C, after the conductive layer M6 is formed, the patterned photoresist DF may be removed, and a portion of the second conductive layer M2 exposed after the patterned photoresist DF is removed may be removed to pattern the second conductive layer M2. Next, the insulating layer IL6 may BE disposed in a space (not shown) formed by removing the patterned photoresist DF and a portion of the second conductive layer M2, and the bonding element BE may BE disposed corresponding to the conductive layer M6. Details of the above processes are referred to above, and thus will not be described again. Then, a dicing process and a step of removing the intermediate layer IML1 and the carrier CR1 may be performed to form the electronic device ED6.

According to the present embodiment, the electronic device ED6 may include a conductive layer M8 contacting the second conductive layer M2, wherein the conductive layer M8 may overlap the opening OP in a normal direction of the electronic device ED 6. The electronic element EL may be electrically connected to the second circuit structure CL2, and thus to an external electronic unit, through the first circuit structure CL1, the connection structure CS in the opening OP, and the conductive layer M8.

Referring to fig. 15A to 15D, fig. 15A to 15D are schematic views illustrating a manufacturing process of an electronic device according to an eighth embodiment of the invention. The structure shown in fig. 15D is an embodiment of the electronic device ED7 of the present embodiment, but the present embodiment is not limited thereto. The electronic device ED7 of the present embodiment may include a plurality of electronic elements EL. For example, as shown in fig. 15D, the electronic device ED7 may include two electronic elements EL, but is not limited thereto. As shown in fig. 15A, the manufacturing method of the electronic device ED7 may include first attaching the electronic element EL1 and the electronic element EL2 to the carrier CR through the intermediate layer IML, and disposing the first insulating layer IL1 and the second insulating layer IL2 on the electronic element EL1 and the electronic element EL2, respectively. Next, an encapsulation layer EN surrounding the electronic element EL1, the electronic element EL2, the first insulating layer IL1, and the second insulating layer IL2 may be formed. In the present embodiment, the electronic element EL1 and the electronic element EL2 may have different heights, but not limited thereto. In this case, the encapsulation layer EN may expose the surface of the second insulating layer IL2 disposed on the higher one of the electronic element EL1 and the electronic element EL 2. For example, an encapsulation layer EN covering the electronic element EL1, the electronic element EL2, the first insulating layer IL1 and the second insulating layer IL2 may be first disposed on the carrier CR, wherein the height D3 of the electronic element EL1 is greater than the height D4 of the electronic element EL 2. Then, a polishing process may be performed on the encapsulation layer EN by using the polishing tool GM, so as to expose the surface of the second insulating layer IL2 disposed on the electronic device EL 1. In this case, the upper surface S1 of the encapsulation layer EN may be aligned with the surface of the second insulating layer IL2 on the electronic element EL 1.

Next, as shown in fig. 15B, after forming the encapsulation layer EN, an opening OP in the encapsulation layer EN, an opening OP1 exposing the conductive pad CP of the electronic element EL1, an opening OP1' exposing the conductive pad CP of the electronic element EL2, the connection structure CS, and the first circuit structure CL1 may be formed next. In the present embodiment, since the second insulating layer IL2 on the electronic element EL2 can be covered by the encapsulation layer EN, the opening OP1' can be formed by removing a portion of the encapsulation layer EN, the first insulating layer IL1 and the second encapsulation layer IL 2. The details of the above process may refer to fig. 7A and the above, and thus are not repeated.

As shown in fig. 15C, after the first circuit structure CL1 is formed, the intermediate layer IML1 and the carrier CR1 may be disposed on the insulating layer IL5, the formed structure may be flipped over, and the carrier CR and the intermediate layer IML may be removed. Next, a second conductive layer M2 may be formed on the lower surface S2 of the encapsulation layer EN, a patterned photoresist layer DF is disposed on the second conductive layer M2, and a conductive layer M6 is formed through the patterned photoresist layer DF. The details of the above process are referred to above, and thus will not be described again.

As shown in fig. 15D, after the conductive layer M6 is formed, the patterned photoresist DF may be removed, and a portion of the second conductive layer M2 exposed after the patterned photoresist DF is removed may be removed to pattern the second conductive layer M2. Next, the insulating layer IL6 may BE disposed in a space (not shown) formed by removing the patterned photoresist DF and a portion of the second conductive layer M2, and the bonding element BE may BE disposed corresponding to the conductive layer M6. Details of the above processes are referred to above, and thus will not be described again. Then, a dicing process and a step of removing the intermediate layer IML1 and the carrier CR1 may be performed to form the electronic device ED7. It should be noted that the structures of the first circuit structure CL1 and the second circuit structure CL2 in the electronic device ED7 shown in fig. 15D are only exemplary, and the invention is not limited thereto.

In summary, the present invention provides an electronic device, which includes an electronic element, a package layer surrounding the electronic element, and a first circuit structure and a second circuit structure respectively disposed on two sides of the package layer. The encapsulation layer includes an opening through which the first circuit structure can be electrically connected to the second circuit structure. Thus, the electronic component may be electrically connected to the external electronic unit through the first circuit structure and the second circuit structure. Compared with the traditional square plane leadless packaging structure, the electronic device of the invention can not comprise a lead frame or be formed by a wire bonding process, thereby reducing the production cost or having smaller device thickness.

The above description is only an example of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An electronic device, comprising:

At least one electronic component;

an encapsulation layer surrounding the at least one electronic element, the encapsulation layer having an upper surface, a lower surface and at least one opening, wherein a sidewall of the at least one opening connects the upper surface and the lower surface;

The first circuit structure is arranged on the upper surface of the packaging layer;

the second circuit structure is arranged on the lower surface of the packaging layer; and

A connection structure disposed in the at least one opening, wherein the at least one electronic component is electrically connected to the second circuit structure through the first circuit structure and the connection structure;

The connecting structure comprises a first sub-layer and a second sub-layer, wherein the first sub-layer is positioned between the packaging layer and the second sub-layer, and the first sub-layer covers the side wall of the at least one opening.

2. The electronic device of claim 1, further comprising a first insulating layer disposed on an upper surface of the at least one electronic component.

3. The electronic device of claim 2, further comprising a second insulating layer disposed on the first insulating layer, wherein a thickness of the second insulating layer is greater than a thickness of the first insulating layer.

4. The electronic device of claim 1, further comprising a bonding element disposed on a surface of the second circuit structure opposite the at least one electronic component.

5. The electronic device of claim 4, wherein the engagement element is offset from the at least one opening in a top view of the electronic device.

6. The electronic device of claim 1, wherein the sidewall of the at least one opening has a roughened surface.

7. An electronic device, comprising:

At least one electronic component;

A connection structure disposed in the at least one opening;

Wherein the at least one electronic component is electrically connected to the second circuit structure through the first circuit structure and the connection structure.

8. The electronic device of claim 7, further comprising:

a first insulating layer disposed on the upper surface of the at least one electronic component; and

A second insulating layer disposed on the first insulating layer,

Wherein the thickness of the second insulating layer is greater than the thickness of the first insulating layer.

9. The electronic device of claim 7, further comprising a bonding element disposed on a surface of the second circuit structure opposite the at least one electronic component.

10. The electronic device of claim 7, wherein the sidewall of the at least one opening has a roughened surface.