TW202412196A - Electronic device - Google Patents

Abstract

An electronic device includes a chip and a circuit structure layer overlapping the chip. The circuit structure layer includes a redistribution structure layer and an element structure layer, and the redistribution structure layer and the element structure layer are electrically connected to the chip. At least one of the redistribution structure layer and the element structure layer includes at least one opening, and the at least one opening overlaps a side of the chip in a normal direction of the electronic device.

Description

Electronic devices

The present disclosure relates to an electronic device, and more particularly to an electronic device including a packaging structure.

An electronic device may include a chip and a redistribution layer for electrically connecting the chip to other electronic components. However, the film layer in the redistribution layer may be affected by stress and easily damaged. Therefore, how to reduce the stress in the package structure is still an important issue in the art.

In some embodiments, the present disclosure provides an electronic device, including a chip and a circuit structure layer superimposed on the chip. The circuit structure layer includes a redistribution structure layer and a component structure layer, wherein the redistribution structure layer and the component structure layer are electrically connected to the chip. At least one of the redistribution structure layer and the component structure layer includes at least one opening, and in a normal direction of the electronic device, the opening is superimposed on a side of the chip.

The present disclosure can be understood by referring to the following detailed description and the accompanying drawings. It should be noted that, in order to facilitate the reader's understanding and for the simplicity of the drawings, the various drawings in the present disclosure only depict a portion of the device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the figure are only for illustration and are not used to limit the scope of the present disclosure.

Certain terms are used throughout this disclosure and the attached patent applications to refer to specific components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same component by different names. This document does not intend to distinguish between components that have the same function but different names.

In the following description and patent application, the words "including" and "comprising" are open-ended words and should be interpreted as "including but not limited to..."

It should be understood that when an element or film layer is referred to as being "disposed on" or "connected to" another element or film layer, it can be directly on or directly connected to the other element or film layer, or there may be an intervening element or film layer between the two (indirect situation). Conversely, when an element is referred to as being "directly" "on" or "directly connected to" another element or film layer, there may be no intervening element or film layer between the two. When an element or film layer is referred to as being "electrically connected" to another element or film layer, it may be interpreted as being directly electrically connected or indirect electrically connected. The electrical connection or coupling described in the present disclosure may refer to direct connection or indirect connection. In the case of direct connection, the end points of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there are switches, diodes, capacitors, inductors, resistors, other suitable components, or combinations of the above components between the end points of the components on the two circuits, but not limited to these.

Although the terms "first", "second", "third" ... can be used to describe a variety of components, the components are not limited to these terms. These terms are only used to distinguish a single component from other components in the specification. The same terms may not be used in the patent application, but may be replaced by first, second, third ... according to the order of the components declared in the patent application. Therefore, in the following specification, the first component may be the second component in the patent application.

In the present disclosure, the thickness, length and width may be measured by using an optical microscope, and the thickness or width may be measured by using a cross-sectional image under an electron microscope, but the present invention is not limited thereto.

In addition, any two values or directions used for comparison may have a certain error. The terms "approximately", "equal to", "equal" or "same", "substantially" or "approximately" are generally interpreted as being within plus or minus 20% of the given value, or within plus or minus 10%, plus or minus 5%, plus or minus 3%, plus or minus 2%, plus or minus 1% or plus or minus 0.5% of the given value.

In addition, the expressions “a given range is from a first value to a second value” and “a given range falls within the range from a first value to a second value” mean that the given range includes the first value, the second value and other values therebetween.

If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

It should be noted that the following embodiments may replace, reorganize, or mix the technical features in several different embodiments to implement other embodiments without departing from the spirit of the present disclosure.

The electronic device disclosed herein may include a semiconductor device, a packaging device, a display device, a sensing device, a backlight device, an antenna device, a splicing device or other suitable electronic devices, but is not limited thereto. The electronic device disclosed herein may include any suitable device applied to the above-mentioned devices. The electronic device may be a bendable, flexible or stretchable electronic device. The display device may be applied to, for example, a notebook computer, a public display, a splicing display, a car display, a touch display, a television, a monitor, a smart phone, a tablet computer, a light source module, a lighting device or, for example, an electronic device applied to the above-mentioned products, but is not limited thereto. The sensing device may include a biosensor, a touch sensor, a fingerprint sensor, other suitable sensors or a combination of the above-mentioned types of sensors. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device, for example, including a liquid crystal antenna device, but not limited thereto. The splicing device may, for example, include a display splicing device or an antenna splicing device, but not limited thereto. The shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may include an electronic unit, wherein the electronic unit may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. The diode may include a light-emitting diode or a photodiode. The light emitting diode may, for example, include an organic light emitting diode (OLED) or an inorganic light emitting diode (in-organic light emitting diode), and the inorganic light emitting diode may, for example, include a sub-millimeter light emitting diode (mini LED), a micro LED or a quantum dot LED, but is not limited thereto. It should be noted that the electronic device disclosed herein may be various combinations of the above-mentioned devices, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the aforementioned devices, but the disclosure is not limited thereto. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, etc. to support a display device, an antenna device, a wearable device (for example, including augmented reality or virtual reality), a vehicle-mounted device (for example, including a car windshield), or a splicing device.

Please refer to FIG. 1 , which is a schematic cross-sectional view of an electronic device according to the first embodiment of the present disclosure. Specifically, FIG. 1 shows a cross-sectional structure of the structure shown in FIG. 2 along the tangent line A-A’. According to the present embodiment, as shown in FIG. 1 , the electronic device ED may include a chip CP and a circuit structure layer CS, wherein the circuit structure layer CS may overlap the chip CP in the normal direction of the electronic device ED (i.e., parallel to the direction Z, which will not be described in detail below). The circuit structure layer CS may include a redistribution structure layer RDL and an element structure layer ES, wherein the element structure layer ES may be located on the side of the redistribution structure layer RDL opposite to the chip CP, i.e., the redistribution structure layer RDL is located between the chip CP and the element structure layer ES, but is not limited thereto. The electronic device ED may further include a buffer layer INL, which is disposed on a side of the component structure layer ES opposite to the redistribution structure layer RDL, that is, the component structure layer ES is disposed between the buffer layer INL and the redistribution structure layer RDL. The electronic device ED may further include an encapsulation layer EN, wherein the encapsulation layer EN may be disposed around the chip CP. The above-mentioned "encapsulation layer EN is disposed around the chip CP" may mean that in a cross-sectional view of the electronic device ED (e.g., FIG. 1 ), at least a portion of the chip CP is disposed in the encapsulation layer EN, and the encapsulation layer EN may contact the side surface of the chip CP. The encapsulation layer EN may be used to encapsulate the chip CP, the circuit structure layer CS, or other components and/or film layers of the electronic device ED. The encapsulation layer EN may include any suitable encapsulation material. For example, the packaging layer EN may include organic materials, inorganic materials or a combination of the above materials. The packaging layer EN may include transparent packaging materials or opaque packaging materials. It should be noted that although Figure 1 shows a structure in which the packaging layer EN encapsulates a single chip CP, the present disclosure is not limited to this. In some embodiments, the packaging layer EN can be used to encapsulate multiple chips CP, that is, the electronic device ED may include a multi-chip packaging structure. The packaging layer EN can reduce the impact of external moisture on components and/or film layers in the electronic device ED. In this embodiment, the method for forming the electronic device ED may include first forming a circuit structure layer CS and then forming a chip CP, which can be regarded as a circuit redistribution layer first (RDL-first) process. Specifically, a circuit structure layer CS may be formed on the buffer layer INL first, and then a chip CP may be disposed on the circuit structure layer CS. Then, an encapsulation layer EN may be disposed to cover the chip CP and the circuit structure layer CS to form an electronic device ED. It should be noted that the method for forming the electronic device ED disclosed herein is not limited to the above.

The structure of each component of the electronic device ED of this embodiment will be described in detail below.

The chip CP disclosed herein may include an integrated circuit (IC) chip, a diode chip, other suitable chips or a combination of the above chips, depending on the type or purpose of the electronic device ED. For example, when the electronic device ED includes a display device, the chip CP may include a light-emitting diode chip, but is not limited to this. The chip CP may be electrically connected to the circuit structure layer CS. Specifically, the redistribution structure layer RDL and the element structure layer ES in the circuit structure layer CS may be electrically connected to the chip CP. For example, as shown in FIG. 1 , the chip CP may include an insulating layer INL2, which is disposed on the side of the chip CP facing the circuit structure layer CS, and a conductive layer CL1 may be disposed in the insulating layer INL2, and the chip CP may be electrically connected to the bottom metal layer (under bump metalization) UM1 through the conductive layer CL1 and the bonding pad SD1. The bottom metal layer UM1 may be disposed in one of the insulating layers of the redistribution structure layer RDL that is closest to the chip CP (e.g., the insulating layer IL3), but is not limited thereto. The bottom metal layer UM1 may be electrically connected to the redistribution structure layer RDL and the device structure layer ES in the circuit structure layer CS, thereby electrically connecting the chip CP to the redistribution structure layer RDL and the device structure layer ES. The bottom metal layer UM1 and the conductive layer CL1 may include any suitable conductive material, such as molybdenum (Mo), tantalum (Ta), niobium (Nb), hafnium (Hf), nickel (Ni), chromium (Cr), cobalt (Co), zirconium (Zr), tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), other suitable metals, or alloys or combinations thereof. In some embodiments, the bottom metal layer UM1 and the conductive layer CL1 are, for example, a single metal layer or a stacked structure formed by stacking a plurality of sub-metal layers, but are not limited thereto. The bonding pad SD1 may include tin, nickel, gold, silver, a tin-containing alloy, or other suitable conductive materials. It should be noted that the structures of the insulating layer INL2 and the conductive layer CL1 shown in FIG. 1 are exemplary only. In some embodiments, the insulating layer INL2 may include a structure formed by stacking multiple insulating layers. The insulating layer INL2 may include an organic material or an inorganic material. The thickness of the insulating layer INL2 may be greater than or equal to 0.5 micrometers (μm) and less than or equal to 20 μm. The chip CP may be formed by cutting a wafer or a semiconductor substrate, and when the wafer or the semiconductor substrate includes a hard and brittle material, cracking or chipping may occur easily after the cutting process. According to this embodiment, the cracking or chipping of the wafer or semiconductor substrate can be reduced by designing the thickness of the insulating layer INL2. For example, the thickness of the insulating layer INL2 can be designed to be greater than or equal to 7 μm and less than or equal to 20 μm, preferably greater than or equal to 10 μm and less than or equal to 20 μm, but not limited thereto.

The redistribution structure layer RDL includes any suitable film layer that can adjust the positions of the signal input terminal and the signal output terminal, or can adjust the routing layout. In the present disclosure, the redistribution structure layer RDL may include a stacked structure formed by stacking at least one insulating layer and at least one conductive layer, wherein the stacking direction of the insulating layer and the conductive layer may be, for example, parallel to the normal direction of the electronic device ED. For example, as shown in FIG1 , the redistribution wiring structure layer RDL of the present embodiment may include an insulating layer IL1, an insulating layer IL2 disposed on the insulating layer IL1, a conductive layer CL2 disposed on the insulating layer IL2, and an insulating layer IL3 disposed on the insulating layer IL2 and covering the conductive layer CL2, but not limited thereto. The insulating layer IL1, the insulating layer IL2, and the insulating layer IL3 may include any suitable organic material, such as photosensitive polyimide (PSPI), ABF (Ajinomoto build-up film) material, a combination of the above materials, or other build-up layer materials, but not limited thereto. The conductive layer CL2 may include any suitable conductive material, and the conductive layer CL2 may be the same as or different from the conductive layer CL1. It should be noted that the number and relative arrangement positions of the insulating layer and the conductive layer in the redistribution structure layer RDL shown in FIG1 are merely exemplary, and the present disclosure is not limited thereto.

The element structure layer ES may include an electronic element EL for receiving signals from the chip CP or transmitting signals to the chip CP, but is not limited thereto. The electronic element EL may, for example, include at least one switching element, at least one driving element, at least one protection element or other suitable active or passive elements, depending on the design of the electronic device ED. Specifically, the electronic element EL in the electronic device ED and the film layer used to set the electronic element EL can be regarded as part of the element structure layer ES. In this embodiment, the electronic element EL may include a driving element DU, but is not limited thereto. The driving element DU may include a thin film transistor, so the element structure layer ES may include a thin film transistor and a film layer used to set the thin film transistor. Specifically, as shown in Figure 1, the element structure layer ES may include an insulating layer IL4, a semiconductor layer SM arranged on the insulating layer IL4, an insulating layer IL5 arranged on the insulating layer IL4 and covering the semiconductor layer SM, a conductive layer CL3 arranged on the insulating layer IL5, an insulating layer IL6 arranged on the insulating layer IL5 and covering the conductive layer CL3, and a conductive layer CL4 arranged on the insulating layer IL6, but is not limited to this. The insulating layer IL4, the insulating layer IL5 and the insulating layer IL6 may include any suitable insulating material, such as an organic insulating material or an inorganic insulating material, but not limited thereto. The organic insulating material may include, for example, a photosensitive polyimide or an ABF material, and the inorganic insulating material may include, for example, silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto. The semiconductor layer SM may form the channel region CR, the source region SR and the drain region DR of the driving element DU. The material of the semiconductor layer SM may include, for example, low temperature polysilicon (LTPS), low temperature polysilicon oxide (LTPO) or amorphous silicon (a-Si), but not limited thereto. The conductive layer CL3 may form the gate electrode GE of the driving element DU. In the normal direction of the electronic device ED, the channel region CR may be defined as the portion where the semiconductor layer SM overlaps with the gate electrode GE. The conductive layer CL4 may form a source electrode SE and a drain electrode DE electrically connected to the source region SR and the drain region DR, respectively. The source electrode SE and the drain electrode DE may be filled in through-holes passing through the insulating layer IL5 and the insulating layer IL6 and electrically connected to the source region SR and the drain region DR, respectively. It should be noted that in some embodiments, the source region SR and the source electrode SE may be the drain region and the drain electrode, respectively, and the drain region DR and the drain electrode DE may be the source region and the source electrode, respectively, that is, the positions or functions of the source region SR/source electrode SE and the drain region DR/drain electrode DE may be interchanged. The conductive layer CL3 and the conductive layer CL4 may include any suitable conductive material, such as a metal material, but are not limited thereto. Although not shown in FIG. 1 , the device structure layer ES may include other suitable electronic components EL in addition to the driving component DU. It should be noted that the structure of the device structure layer ES disclosed herein is not limited to that shown in FIG. 1 . In addition, although the electronic element EL of the present embodiment includes a top gate thin film transistor, the present disclosure is not limited thereto. In some embodiments, the electronic element EL may include a bottom gate thin film transistor, a dual gate thin film transistor or other suitable types of thin film transistors.

According to some embodiments, in the normal direction of the electronic device ED, the thickness of the insulating layer in the device structure layer ES is less than the thickness of the insulating layer in the redistribution wiring structure layer RDL. In this way, the influence of the noise generated by the electronic components in the device structure layer ES on the electrical quality can be reduced, but the present invention is not limited thereto. For example, the thickness of the insulating layer (e.g., insulating layer IL4, insulating layer IL5, and insulating layer IL6) in the device structure layer ES is greater than or equal to 0.1 μm and less than or equal to 5 μm, and the thickness of the insulating layer (e.g., insulating layer IL1, insulating layer IL2, and insulating layer IL3) in the redistribution structure layer RDL is greater than or equal to 6 μm and less than or equal to 15 μm. According to some embodiments, the thermal expansion coefficient of the insulating layer in the device structure layer ES is smaller than the thermal expansion coefficient of the insulating layer in the redistribution structure layer RDL. For example, the thermal expansion coefficient of the insulating layer in the device structure layer ES is greater than or equal to 0.1ppm/°C and less than or equal to 10ppm/°C, and the thermal expansion coefficient of the insulating layer in the redistribution wiring structure layer RDL is greater than or equal to 12ppm/°C and less than or equal to 30ppm/°C. In some embodiments, the warp trend of the insulating layer in the device structure layer ES is opposite to the warp trend of the insulating layer in the redistribution wiring structure layer RDL. In this way, the stress of the electronic device ED can be alleviated, the risk of cracking of the electronic device ED can be reduced, and the reliability of the electronic device ED can be improved.

According to the present disclosure, the buffer layer INL can be used to block metal ions (for example, metal ions from the outside) from diffusing into the electronic elements EL in the element structure layer ES. In this way, the possibility of the electronic elements EL being damaged by the metal ions can be reduced. The buffer layer INL can also be used to provide a flat surface to facilitate the arrangement of the circuit structure layer CS thereon. Specifically, the buffer layer INL can be used as a flat layer to facilitate a deposition process on its surface to form electronic elements EL, such as drive elements DU. Although the buffer layer INL shown in FIG. 1 is a single-layer structure, the present disclosure is not limited thereto. In some embodiments, the buffer layer INL may include a multi-layer structure. In addition, in some embodiments, the buffer layer INL may include a structure formed by stacking an insulating layer and a conductive layer and may serve as another redistribution layer.

According to the present disclosure, the insulating layer in the device structure layer ES disposed on the buffer layer INL may protrude from the buffer layer or be aligned with the side surface S1 of the buffer layer INL, depending on the manufacturing process (e.g., cutting process) of the electronic device ED. For example, in the present embodiment, as shown in FIG. 1 , the insulating layer IL4, the insulating layer IL5, and the insulating layer IL6 in the device structure layer ES may protrude from the side surface S1 of the buffer layer INL and extend on the side surface S1 to the bottom of the side surface S1, but the present invention is not limited thereto. In some embodiments, the insulating layers IL4, IL5, and IL6 may be aligned with the side surface S1 of the buffer layer INL, or the side surfaces of the insulating layers IL4, IL5, and IL6 may be coplanar with the side surface S1 of the buffer layer INL without covering the side surface S1, as shown in FIG. 3 .

According to the present embodiment, the chip CP can be electrically connected to the redistribution structure layer RDL (e.g., electrically connected to the conductive layer CL2 in the redistribution structure layer RDL), and electrically connected to the electronic element EL of the device structure layer ES through the redistribution structure layer RDL. For example, as shown in FIG1 , a portion of the conductive layer CL2 in the redistribution structure layer RDL can be electrically connected to the chip CP, and the conductive layer CL2 of the portion can be filled in the through hole V1 passing through the insulating layer IL1 and the insulating layer IL2 and contact one of the source electrode SE and the drain electrode DE of the driving element DU of the device structure layer ES (e.g., the drain electrode DE shown in FIG1 , but not limited thereto), thereby electrically connecting the chip CP to the electronic element EL. In this way, the operation of the chip CP can be controlled by the driving element DU, or the chip CP can transmit a signal to the electronic element EL. In addition, another part of the conductive layer CL2 can be electrically connected to the other of the drain electrode DE and the source electrode SE of the driving element DU (for example, the source electrode SE shown in FIG. 1 , but not limited thereto) and the bottom metal layer UM2, and electrically connected to an external electronic element (not shown) through the bottom metal layer UM2 and the bonding pad SD2. The external electronic element includes, for example, a printed circuit board (PCB), but not limited thereto. Specifically, a portion of the conductive layer CL2 may be filled into the through hole V2 that passes through the insulating layer IL1, the insulating layer IL2, the insulating layer IL4, the insulating layer IL5, the insulating layer IL6, and the buffer layer INL and contacts the bottom metal layer UM2. The bottom metal layer UM2 may be disposed in the buffer layer INL, but is not limited thereto. In this way, the chip CP may be electrically connected to external electronic components through the circuit structure layer CS. As shown in FIG1 , by setting up the redistribution structure layer RDL, the positions of the signal input terminals (e.g., corresponding to the positions of the conductive layer CL1) and the signal output terminals (e.g., corresponding to the positions of the bottom metal layer UM2) respectively located on both sides of the redistribution structure layer RDL may not correspond to each other. In other words, the signal input/output terminals of the chip CP and the signal input/output terminals of the electronic device ED may be misaligned with each other in the top view direction of the electronic device ED, or may not overlap in the normal direction. It should be noted that the electrical connection method of the chip CP, the circuit structure layer CS and the external electronic components described above is only exemplary, and the present embodiment is not limited thereto. Furthermore, in some embodiments, the circuit structure layer CS may include a redistribution structure layer RDL but does not include the device structure layer ES, and the chip CP may be electrically connected to external electronic devices through the redistribution structure layer RDL.

The bottom metal layer in the electronic device ED disclosed herein may have a suitable structure. In some embodiments, the bottom metal layer may protrude from the surface of the insulating layer on which it is disposed, and its surface may have a recessed structure. For example, as shown in FIG. 1 , the surface of the bottom metal layer UM1 in contact with the bonding pad SD1 (i.e., surface S2) may protrude from the surface of the insulating layer IL3, and the surface S2 of the bottom metal layer UM1 may have a recessed structure, or the bottom metal layer UM1 may have a recessed surface S2. In some embodiments, the bottom metal layer may be aligned with the surface of the insulating layer on which it is disposed, and its surface may have a recessed structure. For example, as shown in FIG. 1 , the surface (i.e., surface S3) of the bottom metal layer UM2 in contact with the bonding pad SD2 may be aligned with or not protrude from the surface of the buffer layer INL, and the surface S3 of the bottom metal layer UM2 may have a recessed structure. By making the surface of the bottom metal layer in contact with the bonding pad include a recessed structure, the electrical connection between the bottom metal layer and the bonding pad may be improved, thereby improving the reliability of the electronic device ED. The bottom metal layer disclosed herein may also include other suitable structures, and is not limited to the above-mentioned structures.

Please refer to Figures 1 and 2. Figure 2 is a schematic top view of the component configuration of the electronic device of the first embodiment of the present disclosure, which shows the main components of the electronic device but does not show all the components of the electronic device. Specifically, as shown in Figure 2, the input/output point (hereinafter referred to as I/O point) IO1 of the chip CP can be electrically connected to the electronic component EL of the component structure layer ES through the wiring WL1, and the electronic component EL can be electrically connected to the I/O point IO2 through the wiring WL2. The I/O point IO1 may correspond to the position of the conductive layer CL1. The wiring WL1 may refer to any suitable conductive element used to electrically connect the chip CP to the electronic element EL. For example, the wiring WL1 may include a conductive layer (such as the conductive layer CL2) in the redistribution structure layer RDL. The wiring WL2 may refer to any suitable conductive element that electrically connects the electronic element EL to the bottom metal layer UM2. For example, the trace WL2 may include a portion of the conductive layer CL2 shown on the left side of FIG. 1. The I/O point IO2 may correspond to the position of the bottom metal layer UM2 and may be electrically connected to an external electronic component. It should be noted that FIG. 2 only shows the electrical connection of each component by way of example, and does not show the detailed structure or location of each component. In addition, the number of electronic components EL and I/O points shown in FIG. 2 is only exemplary.

According to the present embodiment, at least one of the redistribution structure layer RDL and the element structure layer ES may include at least one opening, wherein in the normal direction of the electronic device ED, the at least one opening may overlap with the side of the chip CP. Specifically, the opening may overlap with at least a portion of the side of the chip CP. The "opening" here may refer to a structure that disconnects at least one layer of the film layer structure. In other words, when a film layer structure includes an opening, in a cross-sectional view of the film layer, at least one layer of the film layer structure may be separated by the opening, or the portions of the at least one layer located on both sides of the opening will not be connected to each other through the material of the at least one layer. Therefore, the above-mentioned "opening" can also be regarded as a through hole that penetrates the at least one layer. As shown in FIG. 1 , the device structure layer ES of the present embodiment may include at least one first opening ST1, wherein the first opening ST1 overlaps the side SS of the chip CP in the normal direction of the electronic device ED. In the present embodiment, the first opening ST1 may be formed by removing part of the insulating layer IL4, the insulating layer IL5, and the insulating layer IL6, but the present disclosure is not limited thereto. In other words, the first opening ST1 may be used as a through hole penetrating the insulating layer IL4, the insulating layer IL5, and the insulating layer IL6. In this case, the first opening ST1 disconnects the insulating layer IL4, the insulating layer IL5, and the insulating layer IL6 on both sides thereof. In some embodiments, the first opening ST1 may be formed by removing part of the insulating layer IL4 and exposing the upper surface of the insulating layer IL5. In this case, the first opening ST1 disconnects the insulating layer IL4. In some embodiments, the first opening ST1 may be formed by removing part of the insulating layer IL4 and the insulating layer IL5 and exposing the upper surface of the insulating layer IL6. In this case, the first opening ST1 disconnects the insulating layer IL4 and the insulating layer IL5. In addition, the redistribution structure layer RDL of the present embodiment may include at least one second opening ST2, wherein the second opening ST2 overlaps the side SS of the chip CP in the normal direction of the electronic device ED. Therefore, in the normal direction of the electronic device ED, the first opening ST1 may overlap or at least partially overlap the second opening ST2. In the present embodiment, the second opening ST2 may be formed by removing part of the insulating layer IL2, but the present disclosure is not limited thereto. In other words, the second opening ST2 may serve as a through hole that penetrates the insulating layer IL2 and disconnects the insulating layer IL2. In some embodiments, the electronic device ED may include the first opening ST1 but not the second opening ST2. In this case, the conductive layer CL2 may extend on the flat insulating layer IL2. In some embodiments, the electronic device ED may include the second opening ST2 but not the first opening ST1.

Specifically, as shown in FIGS. 1 and 2 , the electronic device ED may have a first region R1, a second region R2, and a third region R3. The first region R1 may be a region of the electronic device ED that roughly corresponds to the side SS of the chip CP. The second region R2 may be a region of the electronic device ED that roughly corresponds to the chip CP. In a top view of the electronic device ED (e.g., FIG. 2 ), the second region R2 is surrounded by the first region R1, but is not limited thereto. The third region R3 may be other regions of the electronic device ED except the first region R1 and the second region R2. According to this embodiment, the first opening ST1 of the element structure layer ES and/or the second opening ST2 of the redistribution structure layer RDL are disposed in the first region R1 of the electronic device ED, so that the first opening ST1 and/or the second opening ST2 overlap the side SS of the chip CP. In the present embodiment, as shown in FIG. 2 , the chip CP may have a rectangular shape and four side edges SS, and the device structure layer ES (and/or the redistribution structure layer RDL) may include a first opening ST1 (and/or a second opening ST2), wherein the first opening ST1 and/or the second opening ST2 may be arranged along the four side edges SS of the chip CP (the range of the first opening ST1 and/or the second opening ST2 is indicated by diagonal lines in FIG. 2 ), that is, the first opening ST1 and/or the second opening ST2 may surround the chip CP (or surround the second region R2) in the top view of the electronic device ED, but the present disclosure is not limited thereto. In some embodiments, the first opening ST1 and/or the second opening ST2 may not completely surround the chip CP in the top view of the electronic device ED. In some embodiments, the device structure layer ES (and/or the redistribution structure layer RDL) may include a plurality of first openings ST1 (and/or a second opening ST2), which are respectively disposed along a portion of the side SS of the chip CP. The electronic device ED may also include other openings, and the present disclosure is not limited thereto.

In the chip packaging structure of the prior art, the film layer corresponding to the side of the chip is more susceptible to stress and causes fracture or damage, thereby reducing the reliability of the device. For example, when the chip is set, the film layer corresponding to the side of the chip may be subjected to greater stress. According to the first embodiment provided by the present disclosure, since the redistribution structure layer RDL and/or the component structure layer ES include the first opening ST1 and/or the second opening ST2 corresponding to the side SS of the chip CP, the stress borne by the insulating layer in the redistribution structure layer RDL and the component structure layer ES corresponding to the side SS of the chip CP can be reduced, thereby reducing the possibility of fracture in the insulating layer in the redistribution structure layer RDL and the component structure layer ES. In addition, as shown in FIG1 , the bottom of the first opening ST1 and the second opening ST2 may be in an arc shape or other suitable non-pointed shape, but is not limited thereto. In this way, the stress on the portion of the redistribution structure layer RDL and the device structure layer ES corresponding to the side SS of the chip CP can be further reduced.

According to the present embodiment, the electronic device ED may further include a supporting element disposed in the opening. Specifically, the portion of the element and/or film layer of the electronic device ED that fills the opening may be defined as a supporting element. For example, as shown in FIG1 , the element structure layer ES may include a first opening ST1, and a portion of the insulating layer IL1 in the redistribution structure layer RDL may extend into the first opening ST1, or be filled in the first opening ST1. In this case, the portion of the insulating layer IL1 that fills the first opening ST1 may be defined as a supporting element SP1. The material of the supporting element SP1 may be determined according to the material of the film layer and/or element that fills the first opening ST1. In the present embodiment, since a portion of the insulating layer IL1 is filled into the first opening ST1, the material of the supporting element SP1 may be the material of the insulating layer IL1. In other embodiments, a portion of the conductive layer (e.g., the conductive layer CL2) in the redistribution structure layer RDL may be filled into the first opening ST1, and the material of the supporting element SP1 may be the material of the conductive layer CL2. In still other embodiments, a portion of the insulating layer IL1 and the conductive layer CL2 in the redistribution structure layer RDL may be filled into the first opening ST1, and the material of the supporting element SP1 may include the materials of the insulating layer IL1 and the conductive layer CL2. In other words, the supporting element SP1 may include an insulating material, a metal material, or a combination of the above materials. As described above, the insulating layer IL1 may include an organic insulating material. Therefore, by providing a supporting element SP1 in the first opening ST1, wherein the supporting element SP1 may include an organic insulating material or a metal material, the stress borne by the portion of the electronic device ED corresponding to the side SS of the chip CP can be reduced, thereby improving the reliability of the electronic device ED. Similarly, as shown in FIG1 , the redistribution structure layer RDL may include a second opening ST2, and a portion of the conductive layer CL2 and the insulating layer IL3 in the redistribution structure layer RDL may extend into the second opening ST2. Therefore, the electronic device ED may include a supporting element SP2 provided in the second opening ST2, wherein the supporting element SP2 includes a portion of the conductive layer CL2 and the insulating layer IL3, but is not limited thereto. According to different embodiments of the present disclosure, the supporting element SP2 may include one or more of an insulating material and a conductive material.

In some embodiments, the surface of the redistribution structure layer RDL of the electronic device ED may selectively have at least one groove, wherein in the normal direction of the electronic device ED, the groove may overlap with the side SS of the chip CP. Specifically, as shown in FIG. 1 , the surface S4 of the redistribution structure layer RDL facing the chip CP may have a groove RS, wherein the groove RS may correspond to the side SS of the chip CP. The groove RS may be formed by removing at least a portion of the surface of the redistribution structure layer RDL, for example, by removing a portion of the insulating layer IL3, but is not limited thereto. In some embodiments, the groove RS may extend along the side SS of the chip CP and form a closed structure. In some embodiments, the groove RS may extend only along a portion of the side SS of the chip CP. In some embodiments, the surface S4 of the redistribution structure layer RDL may have a plurality of grooves RS, which extend along a portion of the side SS of the chip CP. In the normal direction of the electronic device ED, since the groove RS may overlap the side SS of the chip CP, the groove RS may overlap or at least partially overlap the first opening ST1 and/or the second opening ST2, but is not limited thereto. The bottom of the groove RS may be an arc shape or other suitable non-pointed shape, but is not limited thereto. By forming the groove RS on the surface S4 of the redistribution structure layer RDL, the stress borne by the portion of the electronic device ED corresponding to the side SS of the chip CP can be reduced. In some embodiments, the surface S4 of the redistribution structure layer RDL may not have a groove RS. In detail, in the normal direction of the electronic device ED, the height of the recess RS is less than the thickness of the insulating layer of the redistribution structure layer RDL. Specifically, the height of the recess RS is less than half of the thickness of the insulating layer of the redistribution structure layer RDL.

In some embodiments, in the normal direction of the electronic device ED, the electronic element EL in the element structure layer ES does not overlap the side SS of the chip CP. In other words, the electronic element EL may not be arranged corresponding to the side SS of the chip CP. Specifically, the electronic element EL of the present embodiment may include a thin film transistor element, wherein the thin film transistor element may not overlap the side SS of the chip CP in the normal direction of the electronic device ED. The above-mentioned "thin film transistor element does not overlap the side SS of the chip CP" may at least include the situation that the semiconductor layer SM of the thin film transistor element does not overlap the side SS of the chip CP, but is not limited thereto. In this case, the electronic element EL is not arranged in the first region R1 of the electronic device ED. In some embodiments, as shown in FIG. 1 , the electronic element EL may be arranged in the third region R3. In some embodiments, although not shown in the figure, the electronic element EL may be arranged in the second region R2, that is, the electronic element EL may overlap a part of the chip CP in the normal direction of the electronic device ED but still does not overlap the side SS of the chip CP. By making the setting position of the electronic element EL not overlap the side SS of the chip CP, the influence of stress on the electronic element EL can be reduced. In addition, in some embodiments, the electronic element EL may not overlap the bonding pad SD1 and/or the bonding pad SD2 in the normal direction of the electronic device ED. In other words, the setting position of the electronic element EL may not correspond to the position of the side SS of the chip CP, the bonding pad SD1 and/or the bonding pad SD2. In this case, the electronic element EL may be arranged in the second region R2 or the third region R3 at a position that does not correspond to the bonding pad.

More embodiments of the present disclosure will be described below. For simplicity of description, the same film layers or components in the following embodiments will use the same reference numerals, and their features will not be repeated, and the differences between the embodiments will be described in detail below.

Please refer to FIG3 , which is a cross-sectional view of an electronic device according to a second embodiment of the present disclosure. According to this embodiment, the device structure layer ES may have a first opening ST1, and the conductive layer CL2 in the redistribution structure layer RDL may extend into the first opening ST1. In other words, the conductive layer CL2 may be filled into the first opening ST1. In detail, as shown in Fig. 3, the insulating layers IL1 and IL2 of the redistribution structure layer RDL and the portions of the insulating layers IL4, IL5 and IL6 of the element structure layer ES corresponding to the side SS of the chip CP may be removed to form the first opening ST1 of the element structure layer ES and the second opening ST2 of the redistribution structure layer RDL, and the conductive layer CL2 disposed on the insulating layer IL2 may extend downward and fill in the first opening ST1 and the second opening ST2. In this case, the supporting element SP1 disposed in the first opening ST1 and the supporting element SP2 disposed in the second opening ST2 may include the material of the conductive layer CL2, such as a metal material. In addition, the supporting element SP1 may, for example, be in contact with the supporting element SP2. Furthermore, in the normal direction of the electronic device ED, the first opening ST1 may overlap or at least partially overlap the second opening ST2.

In addition, in the present embodiment, as shown in FIG3 , a plurality of grooves RS may be provided on the surface S4 of the redistribution structure layer RDL, wherein the grooves RS may be disposed in the first region R1 of the electronic device ED, or in other words, disposed corresponding to/adjacent to the side SS of the chip CP. In some embodiments, the grooves RS may extend along the side SS of the chip CP and form a closed structure. In some embodiments, the grooves RS may extend along a portion of the side SS of the chip CP. It should be noted that the number and shape of the grooves RD shown in FIG3 are merely exemplary, and the present disclosure is not limited thereto.

In addition, compared to the structure shown in FIG1 , the bottom metal layer of the present embodiment may have a different structure. In some embodiments, the bottom metal layer may be aligned with the surface of the insulating layer on which it is disposed. For example, as shown in FIG3 , the surface S2 of the bottom metal layer UM1 in contact with the bonding pad SD1 may be aligned with the surface of the insulating layer IL3, and the surface S2 of the bottom metal layer UM1 may be substantially a flat surface. In some embodiments, the bottom metal layer may protrude from the surface of the insulating layer on which it is disposed, and its surface may be a flat surface. For example, as shown in FIG3 , the surface S3 of the bottom metal layer UM2 in contact with the bonding pad SD2 may protrude from the surface of the buffer layer INL, and the surface S3 of the bottom metal layer UM2 may be substantially a flat surface. The structural features of the bottom metal layer of this embodiment and the bottom metal layer of the above-mentioned embodiments can be applied to various embodiments of the present disclosure.

The structural features of other components and/or film layers of the electronic device ED shown in FIG. 3 can be found in the above text, so they will not be described in detail.

Please refer to FIG. 4 and FIG. 5 , FIG. 4 is a schematic top view of the component configuration of the electronic device of the third embodiment of the present disclosure, and FIG. 5 is a schematic diagram of the equivalent circuit of the electronic component of the third embodiment of the present disclosure. According to the present embodiment, the first opening ST1 of the component structure layer ES and/or the second opening ST2 of the redistribution structure layer RDL may not completely surround the chip CP in the top view of the electronic device ED. In detail, as shown in FIG. 4 , the component structure layer ES (and/or the redistribution structure layer RDL) of the present embodiment may include a plurality of first openings ST1 (and/or second openings ST2), and the first openings ST1 (and/or second openings ST2) may be respectively arranged along a portion of the side SS of the chip CP. In the present embodiment, the first opening ST1 and/or the second opening ST2 may be arranged corresponding to the wiring WL1 electrically connecting the I/O point of the chip CP and the electronic element EL, that is, the first opening ST1 and/or the second opening ST2 may overlap the wiring WL1 in the normal direction of the electronic device ED, but the present invention is not limited thereto. In other words, the first opening ST1 and/or the second opening ST2 may be arranged in the first region R1 corresponding to a portion of the wiring WL1. As described above, the wiring WL1 may include the conductive layer CL2 of the redistribution structure layer RDL. Therefore, in the present embodiment, the first opening ST1 and/or the second opening ST2 may overlap the conductive layer CL2 of the redistribution structure layer RDL, but the present invention is not limited thereto.

In addition, in the present embodiment, the electronic element EL may include, for example, a demultiplexer (DeMUX) DMX, wherein the demultiplexer DMX may include at least one thin film transistor element, but is not limited thereto. For example, as shown in FIG5 , the demultiplexer DMX may include a thin film transistor T1, a thin film transistor T2, and a thin film transistor T3, wherein the gates of the thin film transistors are respectively electrically connected to one of the I/O points IO2, the sources of the thin film transistors may be electrically connected to a signal input terminal IN, and the drains of the thin film transistors may be respectively electrically connected to a signal output terminal, wherein the signal output terminal may be electrically connected to the I/O point IO1. It should be noted that the circuit of the demultiplexer DMX shown in FIG5 is merely exemplary, and the present disclosure is not limited thereto. By making the electronic element EL of the electronic device ED include a demultiplexer DMX, the number of I/O points IO2 can be reduced, thereby simplifying the wiring layout of the electronic device ED. In this embodiment, in the normal direction of the electronic device ED, the demultiplexer DMX may not overlap with the side SS of the chip CP, or may not be set corresponding to the side SS of the chip CP. In addition, in some embodiments, the demultiplexer DMX may not overlap with the bonding pad SD1 and/or the bonding pad SD2 in the normal direction of the electronic device ED. In this case, the demultiplexer DMX may be set at a position that does not correspond to the bonding pad in the second region R2 or the third region R3.

Please refer to Figures 6 and 7, Figure 6 is a cross-sectional schematic diagram of the electronic device of the fourth embodiment of the present disclosure, and Figure 7 is a top view schematic diagram of the component configuration of the electronic device of the fourth embodiment of the present disclosure. According to this embodiment, the electronic component EL of the component structure layer ES of the electronic device ED may include an electrostatic protection element ESD. The electrostatic protection element ESD can be electrically connected between the I/O point IO1 and the I/O point IO2, and can be used to eliminate static electricity. Specifically, as shown in Figure 7, the electrostatic protection element ESD can be electrically connected to the electrical connection path between the I/O point IO1 and the I/O point IO2, and can be electrically connected to the ground point GP. Figure 6 exemplarily shows the structure of the electrostatic protection element ESD of the present embodiment. The structure and electrical connection method of the electrostatic protection element ESD of the present embodiment are described below. It should be noted that the ESD protection device of this embodiment may include any suitable structure or be electrically connected to the I/O point IO1 and the I/O point IO2 in any suitable manner, and is not limited to the structure shown in FIG. 6 .

As shown in FIG6 , the electrostatic protection element ESD may include a thin film transistor T4 and a thin film transistor T5, wherein the thin film transistor T4 includes a gate electrode GE1, a semiconductor layer SM1, a drain electrode DE1, and a source electrode SE1, and the thin film transistor T5 includes a gate electrode GE2, a semiconductor layer SM2, a drain electrode DE2, and a source electrode SE2. The source electrode SE1 of the thin film transistor T4 may be electrically connected to the semiconductor layer SM1 and the gate electrode GE1, and the drain electrode DE2 of the thin film transistor T5 may be electrically connected to the semiconductor layer SM2 and the gate electrode GE2. The device structure layer ES may include an insulating layer IL4, a conductive layer IL5 disposed on the insulating layer IL4, an insulating layer IL5 disposed on the insulating layer IL4 and covering the conductive layer IL5, a semiconductor layer SM1 and a semiconductor layer SM2 disposed on the insulating layer IL5, and a semiconductor layer SM2 disposed on the insulating layer IL5 and covering the conductive layer IL5. The insulating layer IL6 covers the semiconductor layer SM1 and the semiconductor layer SM2, wherein the conductive layer IL5 can form the gate electrode GE1 and the gate electrode GE2, and the conductive layer IL4 can form the drain electrode DE1, the source electrode SE1, the drain electrode DE2 and the source electrode SE2, but not limited thereto. The thin film transistor T4 and the thin film transistor T5 of this embodiment can be bottom gate thin film transistors, but not limited thereto. As shown in FIG6 , the source electrode SE1 of the thin film transistor T4 can be electrically connected between the bonding pad SD1 and the bonding pad SD2 through the conductive layer CL2, and the drain electrode DE2 of the thin film transistor T5 can be electrically connected to the bottom metal layer UM3 and the bonding pad SD3 through the conductive layer CL2. Specifically, a portion of the conductive layer CL2 can be filled into the through hole V3 passing through the insulating layer IL1 and the insulating layer IL2 and contacting the source electrode SE1, thereby electrically connecting the thin film transistor T4 between the bonding pad SD1 and the bonding pad SD2. In addition, another portion of the conductive layer CL2 can be filled into the through hole V3 and contacting the drain electrode DE2, and filled into the through hole V2 and contacting the bottom metal layer UM3. The bonding pad SD3 can be grounded, that is, can be electrically connected to the grounding point GP shown in FIG7 , so that the electrostatic protection element ESD can be grounded through the conductive layer CL2, the bottom metal layer UM3 and the bonding pad SD3. Furthermore, although not shown in FIG6 , the source electrode SE1 of the thin film transistor T4 can be electrically connected to the source electrode SE2 of the thin film transistor T5, and the drain electrode DE1 of the thin film transistor T4 can be electrically connected to the drain electrode DE2 of the thin film transistor T5. The material of the bottom metal layer UM3 can refer to the materials of the above-mentioned bottom metal layer UM1 and the bottom metal layer UM2. The material of the bonding pad SD3 can refer to the materials of the above-mentioned bonding pad SD1 and the bonding pad SD2. With the above structural design, static electricity on the electrical connection path between the I/O point IO1 and the I/O point IO2 can be eliminated through the electrostatic protection element ESD, so as to reduce the influence of static electricity on the electronic device ED.

According to the present embodiment, in the normal direction of the electronic device ED, the electrostatic protection element ESD may not overlap the side SS of the chip CP, or may not be arranged corresponding to the side SS of the chip CP. In addition, in some embodiments, the electrostatic protection element ESD may not overlap the bonding pad SD1, the bonding pad SD2, and the bonding pad SD3. Therefore, in some embodiments, as shown in FIG6, the electrostatic protection element ESD may be arranged in a position in the second region R2 that does not correspond to the bonding pad SD2 and the bonding pad SD3. In some embodiments, as shown in FIG7, the electrostatic protection element ESD may be arranged in a position in the third region R3 that does not correspond to the bonding pad SD1.

Although not shown in FIG. 6 and FIG. 7 , the element structure layer ES of the electronic device ED may also include other electronic elements EL (e.g., the drive element DU shown in FIG. 1 ), which are electrically connected between the I/O point IO1 and the I/O point IO2, or between the bonding pad SD1 and the bonding pad SD2. In addition, the arrangement of the first opening ST1 and/or the second opening ST2 shown in FIG. 7 is only exemplary, and the present embodiment is not limited thereto. The structural features of other elements and/or film layers of the electronic device ED shown in FIG. 6 can be referred to above, so they will not be repeated.

Please refer to Figure 8, which is a cross-sectional schematic diagram of the electronic device of the fifth embodiment of the present disclosure. According to this embodiment, the method for forming the electronic device ED may include first forming a packaging structure including a chip CP and a packaging layer EN arranged around the chip CP, and then forming a circuit structure layer CS on the packaging structure. For example, a component structure layer ES may be first formed on the above-mentioned packaging structure, and a redistribution structure layer RDL may be formed on the component structure layer ES, but is not limited to this. In other words, the component structure layer ES may be disposed between the chip CP and the redistribution structure layer RDL. In addition, the electronic device ED may further include a buffer layer INL, which is disposed between the packaging layer EN and the circuit structure layer CS. It should be noted that in some embodiments, the buffer layer INL may include a structure formed by stacking a conductive layer and an insulating layer as another redistribution structure layer. The external electronic element may be electrically connected to the conductive layer in the redistribution structure layer RDL through the bonding pad SD2 and the bottom metal layer UM2, and electrically connected to the electronic element EL in the element structure layer ES through the conductive layer in the redistribution structure layer RDL, for example, electrically connected to the drain electrode DE or source electrode SE (for example, the drain electrode DE, but not limited thereto) of the electronic element EL (driving element DU). In order to simplify the drawings, FIG8 shows only a single conductive layer CL as the conductive layer in the redistribution structure layer RDL, and a single insulating layer IL as the insulating layer in the redistribution structure layer RDL, but the present embodiment is not limited thereto. The drain electrode DE or source electrode SE (for example, source electrode SE, but not limited thereto) of the electronic element EL (driving element DU) can be electrically connected to the bottom metal layer UM1 and the conductive layer CL1 through the conductive layer CL in the redistribution structure layer RDL, thereby electrically connecting the chip CP to the external electronic element.

In the present embodiment, the element structure layer ES may include at least one first opening ST1, wherein the first opening ST1 may overlap the side SS of the chip CP in the normal direction of the electronic device ED. That is, the first opening ST1 may be arranged corresponding to the first region R1. In the normal direction of the electronic device ED, the first opening ST1 may surround the chip CP along the side SS, but is not limited thereto. In some embodiments, the first opening ST1 may extend along at least a portion of the side SS. In addition, in the present embodiment, the conductive layer CL in the redistribution structure layer RDL may be filled in the first opening ST1, that is, the supporting element SP1 arranged in the first opening ST1 may include the material of the conductive layer CL, such as a metal material, but is not limited thereto. The structural features of each film layer or element in the element structure layer ES may refer to the contents of the above-mentioned embodiments, so they will not be described in detail. In addition, the surface of the redistribution structure layer RDL of the present embodiment may include a groove RS, wherein the groove RS may at least partially overlap the side SS of the chip CP in the normal direction of the electronic device ED, but the present invention is not limited thereto.

Please refer to FIG. 9 , which is a schematic cross-sectional view of an electronic device according to the sixth embodiment of the present disclosure. One of the main differences between the electronic device ED shown in FIG. 9 and the electronic device ED shown in FIG. 8 is the structure of the supporting element SP1. Specifically, as shown in FIG. 9 , in the electronic device ED, a portion of the insulating layer (represented by the insulating layer IL) and the conductive layer (represented by the conductive layer CL) of the redistribution structure layer RDL may be filled into the first opening ST1. In this case, the supporting element SP1 disposed in the first opening ST1 may include a combination of a conductive material and an insulating material. For example, the supporting element SP1 may include a combination of a metal material and an organic insulating material, but is not limited thereto. The structural features of other elements or film layers of the electronic device ED of this embodiment may be referred to above, so they will not be elaborated upon.

In summary, the present disclosure provides an electronic device, including a chip and a circuit structure layer superimposed on the chip, wherein the circuit structure layer includes a redistribution structure layer and a component structure layer. At least one of the redistribution structure layer and the component structure layer includes at least one opening, wherein the opening can overlap at least a portion of at least one side of the chip in the normal direction of the electronic device. In this way, the possibility of damage to the components or film layers in the electronic device due to stress can be reduced, thereby improving the reliability of the electronic device. The above is only an embodiment of the present disclosure, and all equal changes and modifications made according to the scope of the patent application of the present disclosure should be covered by the present disclosure.

CL1,CL2,CL3,CL4,CL: Conductive layer CP: Chip CR: Channel region CS: Circuit structure layer DE,DE1,DE2: Drain electrode DR: Drain region DU: Driver element ED: Electronic device EL: Electronic element EN: Packaging layer ES: Component structure layer ESD: Electrostatic protection element GE,GE1,GE2: Gate electrode GP: Ground point IN: Signal input terminal INL: Buffer layer INL2,IL3,IL1,IL2,IL4,IL5,IL6,IL: Insulation layer IO1,IO2: I/O point DMX: Demultiplexer R1: First region R2: Second region R3: Third region RDL: redistribution structure layer RS: groove S1: side surface S2, S3, S4: surface SD1, SD2, SD3: bonding pad SE, SE1, SE2: source electrode SM, SM1, SM2: semiconductor layer SP1, SP2: support element SR: source region SS: side ST1: first opening ST2: second opening T1, T2, T3, T4, T5: thin film transistor UM1, UM2, UM3: bottom metal layer V1, V2, V3: through hole WL1, WL2: routing Z: direction A-A’: tangent

FIG. 1 is a schematic cross-sectional view of an electronic device according to the first embodiment of the present disclosure. FIG. 2 is a schematic top view of a component configuration of an electronic device according to the first embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view of an electronic device according to the second embodiment of the present disclosure. FIG. 4 is a schematic top view of a component configuration of an electronic device according to the third embodiment of the present disclosure. FIG. 5 is a schematic diagram of an equal calibration circuit of an electronic component according to the third embodiment of the present disclosure. FIG. 6 is a schematic cross-sectional view of an electronic device according to the fourth embodiment of the present disclosure. FIG. 7 is a schematic top view of a component configuration of an electronic device according to the fourth embodiment of the present disclosure. FIG. 8 is a schematic cross-sectional view of an electronic device according to the fifth embodiment of the present disclosure. FIG. 9 is a schematic cross-sectional view of an electronic device according to the sixth embodiment of the present disclosure.

CL1,CL2,CL3,CL4: Conductive layer

CP: Chip

CR: Channel area

CS: Circuit structure layer

DE: Drain electrode

DR: Drain region

DU: drive unit

ED: Electronic devices

EL: Electronic components

EN:Packaging layer

ES: Component structure layer

GE: Gate electrode

INL: Buffer layer

INL2,IL3,IL1,IL2,IL4,IL5,IL6: Insulation layer

R1: First area

R2: Second area

R3: The third area

RDL: redistribution layer

RS: Groove

S1: Side surface

S2, S3, S4: Surface

SD1, SD2: Joint pad

SE: Source electrode

SM: semiconductor layer

SP1, SP2: Support components

SR: Source region

SS: Side

ST1: First opening

ST2: Second opening

UM1,UM2: bottom metal layer

V1, V2: Perforation

Z: Direction

A-A’: tangent

Claims (10)

An electronic device comprises: a chip; and a circuit structure layer, overlapping the chip, the circuit structure layer comprising a redistribution structure layer and a component structure layer, the redistribution structure layer and the component structure layer being electrically connected to the chip; wherein at least one of the redistribution structure layer and the component structure layer comprises at least one opening, and in a normal direction of the electronic device, the at least one opening overlaps a side of the chip. The electronic device according to claim 1 further comprises a packaging layer, wherein the packaging layer is arranged around the chip. An electronic device according to claim 1, wherein the at least one opening includes a first opening of the component structure layer and a second opening of the redistribution structure layer, and in the normal direction of the electronic device, the first opening overlaps with the second opening. The electronic device according to claim 1, wherein the at least one opening comprises a first opening of the component structure layer, the redistribution structure layer comprises at least one insulating layer and at least one conductive layer, and a portion of the at least one insulating layer extends into the first opening. The electronic device according to claim 1, wherein the at least one opening comprises a first opening of the component structure layer, the redistribution structure layer comprises at least one insulating layer and at least one conductive layer, and a portion of the at least one conductive layer extends into the first opening. The electronic device according to claim 1 further comprises a buffer layer, wherein the component structure layer is disposed between the buffer layer and the redistribution structure layer. According to the electronic device of claim 1, the surface of the redistribution structure layer has at least one groove, and in the normal direction of the electronic device, the at least one groove overlaps the side of the chip. The electronic device according to claim 1 further comprises a supporting element disposed in the at least one opening, wherein the supporting element comprises an insulating material, a metal material or a combination thereof. An electronic device according to claim 1, wherein the device structure layer includes a thin film transistor device. An electronic device according to claim 9, wherein in the normal direction of the electronic device, the thin film transistor element does not overlap the side of the chip.

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