CN117223107A - Integrated circuit, preparation method thereof and electronic equipment - Google Patents
Integrated circuit, preparation method thereof and electronic equipment Download PDFInfo
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- CN117223107A CN117223107A CN202180097680.1A CN202180097680A CN117223107A CN 117223107 A CN117223107 A CN 117223107A CN 202180097680 A CN202180097680 A CN 202180097680A CN 117223107 A CN117223107 A CN 117223107A
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 230000004888 barrier function Effects 0.000 claims description 75
- -1 nitrogen ions Chemical class 0.000 claims description 66
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 31
- 229910052757 nitrogen Inorganic materials 0.000 claims description 29
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 26
- 229910052786 argon Inorganic materials 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 20
- 230000006911 nucleation Effects 0.000 claims description 18
- 238000010899 nucleation Methods 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- JLVVSXFLKOJNIY-UHFFFAOYSA-N Magnesium ion Chemical compound [Mg+2] JLVVSXFLKOJNIY-UHFFFAOYSA-N 0.000 claims description 17
- 229910001425 magnesium ion Inorganic materials 0.000 claims description 17
- 239000011810 insulating material Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000009825 accumulation Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 166
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 15
- 229910002704 AlGaN Inorganic materials 0.000 description 14
- 229910002601 GaN Inorganic materials 0.000 description 14
- 230000008569 process Effects 0.000 description 14
- 238000002161 passivation Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 230000005533 two-dimensional electron gas Effects 0.000 description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The application discloses an integrated circuit, a preparation method thereof and electronic equipment, wherein the integrated circuit comprises: a substrate, a channel layer over the substrate; the surface of the channel layer may include an active region, an insulating region disposed around the active region, and a conductive channel passing through the insulating region and communicating with edges of the active region and the integrated circuit. The active region can be communicated to the edge of the integrated circuit by forming the conductive channel on the surface of the channel layer, so that electrostatic charges possibly generated in the active region can be conducted away as soon as possible through the edge of the integrated circuit, and electrostatic damage and even burning of the integrated circuit caused by charge accumulation are avoided.
Description
The present application relates to the field of semiconductor technologies, and in particular, to an integrated circuit, a method for manufacturing the integrated circuit, and an electronic device.
When an integrated circuit is manufactured, the active areas in all circuit areas are separated from each other on the surface of a channel layer formed on a substrate, charges introduced during subsequent manufacturing are accumulated in the separated active areas, the charges cannot be quickly conducted away, the charges are accumulated, the inside of the active areas are damaged, and the reliability of the integrated circuit is greatly affected.
Disclosure of Invention
The application provides an integrated circuit, a preparation method thereof and electronic equipment, and aims to improve the antistatic capability of a device.
In a first aspect, the present application provides an integrated circuit comprising: a substrate, a channel layer over the substrate. The integrated circuit may be a field effect transistor, or may be a high electron mobility transistor, and may further include a source, a drain, a gate, and the like. The integrated circuit may be a semiconductor triode, and may further include a collector, a base, an emitter, and the like. When the integrated circuit is a high electron mobility transistor, the integrated circuit may further include: a nucleation layer between the substrate and the channel layer, and a barrier layer over the channel layer, may further comprise: a buffer layer located between the nucleation layer and the channel layer. Also, a passivation layer may be further covered over the barrier layer in order to mitigate the current collapse effect. In particular, to avoid microwave damage, the substrate material may be selected from high-resistance substrates, such as high-insulation SiC substrates, having a resistivity of about 10 9 Omega cm2, high resistance Si substrate with resistivity of about 10 3 Omega cm2, or alternatively, the substrate may be a conductive substrate, such as a sapphire substrate or the like. The nucleation layer can be made of AlN and other materials, the buffer layer can be made of AlGaN and other insulating materials, the channel layer can be made of GaN and other conductive materials, and the barrier layer can be made of AlGaN and other insulating materials.
In embodiments of the application, the surface of the channel layer (which may be considered the interface between the channel layer and the barrier layer when the integrated circuit is a high electron mobility transistor) may include an active region, an insulating region disposed around the active region, and a conductive channel passing through the insulating region and communicating with the edges of the active region and the integrated circuit. The active region can be communicated to the edge of the integrated circuit by forming a conductive channel at the interface between the channel layer and the barrier layer, so that electrostatic charges possibly generated in the active region can be conducted away as soon as possible through the edge of the integrated circuit, and electrostatic damage and even burning of the integrated circuit caused by charge accumulation are avoided. In the process of preparing integrated circuits, before a wafer is not cut into a plurality of independent integrated circuits, a conductive channel can be used for connecting active areas which are originally mutually separated in each circuit area to dicing channels among the circuits (the wafer is cut along the dicing channels to form a plurality of independent integrated circuits), so that conduction among the active areas in each circuit area in the wafer is realized, when electric charges reach the surface of the wafer, the electric charges can be conducted away as soon as possible through the conductive channel, the active areas in each circuit area on the whole wafer are in an equipotential state, and the electric charges cannot be accumulated in a single circuit area to cause damage to the integrated circuits. And the charge accumulated in the scribe line can be conducted away during the testing process of the integrated circuit or after the scribe line is grounded by adopting other metal connection modes.
In one possible implementation of the present application, in order to enable the charge in the active region to be conducted away as soon as possible, and avoid static damage caused by charge accumulation, the conductive path may take a shortest path, i.e. the conductive path generally communicates between the first edge of the active region and the second edge of the integrated circuit closest to the first edge. Specifically, the first edge and the second edge may be at any positions on the integrated circuit, and the number of the conductive channels may be one or more, and the width of the conductive channels may be any value.
In one possible implementation of the present application, when the wafer is cut into a plurality of integrated circuits, since a certain alignment offset error is allowed, the width of the scribe line provided in the wafer is generally larger than the cutting width, for example, the width of the scribe line is 80um, the width of the wafer is cut by a blade or a laser, if there is no or a small amount of offset, the scribe line may remain about 10um at one edge of the integrated circuit after cutting along one scribe line, and the remaining scribe line may be used as a conductive channel because the scribe line is conductive; if a certain offset occurs during the dicing process, i.e., dicing lanes at the edge of the integrated circuit may be completely cut during dicing, no dicing lanes may remain at a certain edge of the integrated circuit. Thus, in the final integrated circuit, dicing streets may be present at least one edge of the integrated circuit and dicing streets may also be present at multiple edges of the integrated circuit. When dicing along the edges of the integrated circuit, the dicing lanes disposed around the insulating regions may be formed in the resulting integrated circuit with less dicing offset.
In one possible implementation manner of the present application, in order to form an insulating region for isolating each integrated circuit at an interface between the barrier layer and the channel layer, after the barrier layer and the channel layer are epitaxially grown on the wafer, nitrogen ions or argon ions may be implanted at a position corresponding to the insulating region on the surface of the epitaxial structure, and nitrogen ions or argon ions may not be implanted at a position corresponding to the active region and the conductive channel, so that the barrier layer and the channel layer are insulating materials implanted with nitrogen ions or argon ions at a position corresponding to the insulating region. Also, in order to ensure that electrostatic charges generated in the active region can be conducted away by the conductive vias communicating to the scribe lanes, at least a portion of the scribe lanes need to ensure conductivity, for example, all of the scribe lanes have conductivity, or only the scribe lanes in the column direction may have conductivity when the conductive vias are located on the left and/or right side of the circuit region, or only the scribe lanes in the row direction may have conductivity when the conductive vias are located on the upper and/or lower side of the circuit region, and nitrogen ions or argon ions cannot be implanted at positions corresponding to the scribe lanes having conductivity.
In one possible implementation manner of the present application, after nitrogen ions or argon ions are implanted in the position corresponding to the insulating region on the surface of the epitaxial structure on the wafer, in order to make the surface conductivity of the integrated circuit better, silicon ions may be implanted in the position corresponding to the active region and the conductive channel on the surface of the epitaxial structure, so that the portions of the barrier layer and the channel layer close to the barrier layer are N-type semiconductor materials implanted with silicon ions in the position corresponding to the active region and the conductive channel, and the conductivity of the active region and the conductive channel is better. Similarly, silicon ions can be implanted into the surface of the epitaxial structure at the position corresponding to the dicing streets, so that the conductivity of the dicing streets can be improved. Or after nitrogen ions or argon ions are injected into the positions, corresponding to the insulating regions, of the surface of the epitaxial structure on the wafer, magnesium ions can be injected into the positions, corresponding to the active regions and the conductive channels, of the surface of the epitaxial structure, and the positions, corresponding to the active regions and the conductive channels, of the barrier layer and the channel layer, which are close to the barrier layer, are made of P-type semiconductor materials injected with the magnesium ions, so that the conductivity of the active regions and the conductive channels is better. Similarly, magnesium ions can be implanted into the surface of the epitaxial structure at the position corresponding to the dicing streets, so that the conductivity of the dicing streets can be improved. It is noted that the barrier layer is an insulating material when no silicon ions or magnesium ions are implanted on the surface of the integrated circuit, and is an N-type semiconductor material or a P-type semiconductor material when silicon ions or magnesium ions are implanted on the surface of the integrated circuit.
In a second aspect, the present application provides a method for preparing an integrated circuit provided in any of the above examples of the first aspect, including: forming a channel layer on a substrate, wherein the substrate is divided into a plurality of circuit areas which are arranged in an array manner and scribing channels which are positioned between the circuit areas; nitrogen ions or argon ions are injected into a partial region in the circuit region, so that an insulating region is formed on the surface of the channel layer at the ion injection position, an active region and a conductive channel are formed at the position which is not injected with ions, the insulating region is arranged around the active region, and the conductive channel passes through the insulating region and is communicated with the active region and the scribing channel; the substrate is cut along the scribe lanes to form a plurality of integrated circuits.
In one possible implementation of the application, the integrated circuit may be a field effect transistor in particular, or may be a high electron mobility transistor as well. When the integrated circuit is a high electron mobility transistor, a nucleation layer may be formed on the substrate first, followed by formation of the channel layer and barrier layer. Further, a buffer layer may also be formed on the nucleation layer, followed by forming a channel layer and a barrier layer.
Specifically, when the integrated circuit is a high electron mobility transistor, the two-dimensional electron gas formed at the interface between the channel layer and the barrier layer is entirely conductive before the nitrogen ion or argon ion implantation is performed, and electrostatic damage does not exist. After the insulating region is formed at the interface between the channel layer and the barrier layer, the conductive channel can communicate the active regions originally separated from each other in each circuit region to the dicing channel between the circuits, so that conduction between the active regions in each circuit region in the wafer is realized, when charges reach the surface of the wafer, the charges can be conducted away as soon as possible through the conductive channel, the active regions in each circuit region on the whole wafer are in an equipotential state, and the charges cannot be accumulated in a single circuit region to cause damage to the integrated circuit. And, the charge accumulated in the scribe line can be conducted away during the testing process of the integrated circuit or after the scribe line is grounded by adopting other metal connection modes.
In one possible implementation of the present application, the substrate material may be selected from high resistance substrates, such as high insulating SiC substrates, having a resistivity of about 10 9 Ω·cm 2 High resistance Si substrate with resistivity of about 10 3 Ω·cm 2 Alternatively, the substrate may be a conductive substrate, such as a sapphire substrate, which is not limited herein. The nucleation layer can be made of AlN and other materials, the buffer layer can be made of AlGaN and other insulating materials, the channel layer can be made of GaN and other conductive materials, and the barrier layer can be made of AlGaN and other insulating materials. The nucleation layer, buffer layer, channel layer and barrier layer may all be obtained by epitaxial growth on the substrate.
In one possible implementation manner of the present application, after nitrogen ions or argon ions are implanted in the position of the wafer corresponding to the insulating region, in order to make the surface conductivity of the integrated circuit better, silicon ions may be implanted in the positions of the active region, the conductive channel and the scribe line, so that the portions of the barrier layer and the channel layer close to the barrier layer are N-type semiconductor materials implanted with silicon ions in the positions corresponding to the active region, the conductive channel and the scribe line, and the conductivity of the active region, the conductive channel and the scribe line is better. Alternatively, after nitrogen ions or argon ions are implanted in the positions of the wafer corresponding to the insulating regions, in order to make the surface conductivity of the integrated circuit better, magnesium ions may be implanted in the positions of the active region, the conductive channels and the dicing channels, so that the portions of the barrier layer and the channel layer, which are close to the barrier layer, are P-type semiconductor materials implanted with magnesium ions in the positions corresponding to the active region, the conductive channels and the dicing channels, and the conductivity of the active region, the conductive channels and the dicing channels is better.
In one possible implementation of the present application, a passivation layer may also be formed on the barrier layer to mitigate the current collapse effect. Specifically, the passivation layer is etched away at the locations corresponding to the scribe lanes.
In one possible implementation of the present application, when dicing into a plurality of integrated circuits, since a certain alignment offset error is allowed, the scribe line width disposed in the wafer is generally larger than the dicing width, for example, the scribe line width is 80um, the width of the wafer is 60um by using a blade or a laser, if there is no or a trace offset, a scribe line of about 10um may remain on one edge of the integrated circuit after dicing along one scribe line, and the remaining scribe line may be used as a conductive path because the scribe line is conductive; if a certain offset occurs during the dicing process, i.e., dicing lanes at the edge of the integrated circuit may be completely cut during dicing, no dicing lanes may remain at a certain edge of the integrated circuit. Thus, in the final integrated circuit, dicing streets may be present at least one edge of the integrated circuit, dicing streets may also be present at multiple edges of the integrated circuit, and dicing streets disposed around the insulating regions may be formed in the final integrated circuit with less dicing offset when dicing along the edges of the integrated circuit.
In a third aspect, the present application provides an electronic device comprising a circuit board and an integrated circuit as described in various embodiments of the first aspect disposed on the circuit board.
The technical effects achieved by the third aspect may be described with reference to any possible design of the first aspect, and the description is not repeated here.
Fig. 1a is a schematic diagram of a conventional epitaxial structure;
fig. 1b is another schematic structure of a conventional epitaxial structure;
FIG. 2 is a schematic top view of a conventional wafer;
FIG. 3 is a schematic cross-sectional view of a conventional wafer;
FIG. 4 is a schematic cross-sectional diagram of an integrated circuit according to an embodiment of the present application;
FIG. 5a is a schematic cross-sectional view of another integrated circuit according to an embodiment of the present application;
FIG. 5b is a schematic cross-sectional view of another integrated circuit according to an embodiment of the present application;
FIG. 6 is a schematic top view of an interface between a channel layer and a barrier layer in an integrated circuit according to an embodiment of the present application;
FIG. 7 is a schematic top view of an interface between a channel layer and a barrier layer in a wafer according to an embodiment of the present application;
FIG. 8 is a schematic top view of an interface between a channel layer and a barrier layer in an integrated circuit according to an embodiment of the present application;
FIG. 9 is a schematic top view of an interface between a channel layer and a barrier layer in an integrated circuit according to an embodiment of the present application;
FIG. 10 is a schematic top view of an interface between a channel layer and a barrier layer in a wafer according to an embodiment of the present application;
FIG. 11 is a schematic cross-sectional view of the structure along the OO direction in FIG. 10;
FIG. 12 is a schematic view of another cross-sectional structure along the OO direction in FIG. 10;
fig. 13 is a flow chart of a method for manufacturing an integrated circuit according to an embodiment of the present application.
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings.
Gallium nitride (GaN) based high electron mobility transistors (High Electron Mobility Transistor, HEMT) have evolved rapidly over the last 30 years, with GaN HEMTs having higher breakdown voltages, higher electron saturation velocities, higher frequencies than gallium arsenide (GaAs) HEMTs, and many research institutes and companies have added their research lines.
The semiconductor GaN material has the performance advantages of large forbidden bandwidth, high breakdown field intensity, high polarization coefficient, high electron mobility, high electron saturation drift speed and the like, and has a huge application prospect in the fields of power electronics and radio frequency. The GaN HEMT device mainly realizes high electron mobility by utilizing two-dimensional electron gas generated by polarization effect at AlGaN/GaN heterojunction interface, and has the advantages of high withstand voltage, high power density, high working speed and the like.
The application can be applied to the field of microelectronics: including microwave rf devices and power electronics, and the like, and may also extend to the field of optoelectronic devices or other microelectronics. The microwave radio frequency device mainly adopts a GaN device working power amplifier, and the power amplifier is used for amplifying radio frequency signals in an active antenna unit (active antenna unit, AAU) of the base station and then transmitting the radio frequency signals through an antenna. The power electronic device mainly adopts a GaN device work rate switch, and is used for quick charging of terminal products such as mobile phones and the like, and switching of a laser radar and the like.
To avoid microwave loss, gaN-based RF devices are typically grown epitaxially on a high-resistance substrate, such as a high-insulation silicon carbide (SiC) substrate (having a resistivity of about 10 9 Ω·cm 2 ) High resistance silicon (Si) substrate (its resistivity is about 10 3 Ω·cm 2 ) Etc. Referring to fig. 1a, a conventional epitaxial structure may include an AlGaN barrier layer, a GaN channel layer, an AlN nucleation layer, and a SiC substrate in order from top to bottom; alternatively, referring to fig. 1b, the conventional epitaxial structure may include an AlGaN barrier layer, a GaN channel layer, an AlGaN buffer layer, an AlN nucleation layer, and a Si substrate in order from top to bottom. The surface layer of the epitaxial structure is made of non-conductive AlGaN material, the thickness of the material is about 20nm, and a layer of two-dimensional electron gas (2-dimension electron gas,2 DEG) with better conductivity is arranged at the interface between the AlGaN barrier layer and the GaN channel layer. Although 2DEG is conductive, the fabrication process often uses implantation of nitrogen (N) ions to isolate the circuit area on the wafer (wafer), so that a separate active region (the active region may also be referred to as a conductive region) will appear on the wafer surface. Meanwhile, in order to passivate the wafer surface and alleviate the current collapse effect, the wafer surface is covered with a passivation layer formed by non-conductive dielectric materials such as SiN/SiO, so that charges introduced by processes such as cleaning, plasma bombardment and the like can accumulate in the separated active regions in the subsequent processThe damage inside the active region is caused, and the reliability of the device is greatly affected.
Specifically, in the case of the GaN-based rf device fabricated in the prior art, referring to fig. 2 and 3, after each film layer is epitaxially grown on the wafer 100 to form an epitaxial structure, two-dimensional electron gas is formed at the interface between the barrier layer and the channel layer, and as shown by the transverse dotted line in fig. 3, nitrogen (N) ions are injected into other regions except for the active region a of the circuit region S to form an insulating region B (also referred to as an isolation region), so as to isolate the active region a between the device and the circuit, and at the same time, nitrogen ions are also injected into the scribe line D between the circuit regions S, and in fig. 3, the region of the filling point is the region in which the nitrogen ions are injected, after that, passivation is performed on the surface of the epitaxial structure, that is, a passivation layer covering the entire surface of the epitaxial structure is formed by using dielectric material such as SiN or SiO, and etching is performed on the portion of the passivation layer in the scribe line D between the circuit regions S, and then cutting the wafer 100 along the scribe line D to form a plurality of individual devices. In the etching process, for example, the processes of plasma bombardment or cleaning and the like, if charges bombard the surface of the epitaxial structure, as the substrate is a high-resistance substrate and is not conductive, the charges can accumulate on the surface of the epitaxial structure, so that instant high voltage is generated, damage is caused to a formed device, or the device is burnt in the device testing process, or potential damage is caused, and the service life of the device is influenced.
Therefore, the embodiment of the application provides an integrated circuit capable of solving the problems, a preparation method thereof and electronic equipment, and the integrated circuit is described in detail below with reference to the specific drawings and the embodiment.
The terminology used in the following examples is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
Fig. 4 schematically illustrates a cross-sectional structure of an integrated circuit according to an embodiment of the present application, fig. 5a schematically illustrates a cross-sectional structure of another integrated circuit according to an embodiment of the present application, and fig. 5b schematically illustrates a cross-sectional structure of another integrated circuit according to an embodiment of the present application.
Referring to fig. 4, in an embodiment of the present application, an integrated circuit may include: a substrate 1, a channel layer 4 located over the substrate 1. The integrated circuit may be a field effect transistor, or may be a high electron mobility transistor, and may further include a source 7, a drain 8, a gate 9, and the like. The integrated circuit may be a semiconductor triode, and may further include a collector, a base, an emitter, and the like. When the integrated circuit is a high electron mobility transistor, referring to fig. 5a, in another embodiment of the present application, the integrated circuit may further include: a nucleation layer 2 between the substrate 1 and the channel layer 4, and a barrier layer 5 over the channel layer 4; referring to fig. 5b, in another embodiment of the present application, the integrated circuit may further include: a buffer layer 3 located between the nucleation layer 2 and the channel layer 4. Also, referring to fig. 5a and 5b, a passivation layer 6 may be further covered on the barrier layer 5 in order to mitigate the current collapse effect. In particular, in order to avoid microwave damage, the material of the substrate 1 may be selected from high-resistance substrates, such as high-insulation SiC substrates, having a resistivity of about 10 9 Ω·cm 2 High resistance Si substrate with resistivity of about 10 3 Ω·cm 2 Alternatively, the substrate 1 may be a conductive substrate, such as a sapphire substrate, which is not limited herein. The nucleation layer 2 may be made of AlN or the like, the buffer layer 3 may be made of AlGaN or the like, the channel layer 4 may be made of GaN or the like, and the barrier layer 5 may be made of AlGaN or the like.
Fig. 6 schematically illustrates a schematic top-down structure of an interface between a channel layer and a barrier layer in an integrated circuit according to an embodiment of the present application, and fig. 7 schematically illustrates a schematic top-down structure of an interface between a channel layer and a barrier layer in a wafer according to an embodiment of the present application.
Referring to fig. 6, in an embodiment of the present application, the surface of the channel layer 4 (which may be considered as the interface between the channel layer 4 and the barrier layer 5 when the integrated circuit is a high electron mobility transistor) may include an active region a, an insulating region B disposed around the active region a, and a conductive channel C passing through the insulating region B and communicating with the edges of the active region a and the integrated circuit. The active region A can be communicated to the edge of the integrated circuit by forming the conductive channel C at the interface between the channel layer 4 and the barrier layer 5, so that electrostatic charges possibly generated in the active region A can be conducted away as soon as possible through the edge of the integrated circuit, and electrostatic damage and even burning of the integrated circuit caused by charge accumulation are avoided. Referring to fig. 7, in the process of preparing integrated circuits, before the wafer 100 is not cut into multiple independent integrated circuits, the conductive channels C may connect the active areas a originally separated from each other in each circuit area S to the scribe lines D between circuits (the wafer 100 is cut along the scribe lines D to form multiple independent integrated circuits), so that conduction between the active areas a in each circuit area S in the wafer 100 is achieved, and when charges reach the surface of the wafer 100, the charges can be conducted away as soon as possible through the conductive channels C, so that the active areas a in each circuit area S on the whole wafer 100 are in an equipotential state, and the charges cannot be accumulated in a single circuit area S to cause damage to the integrated circuits. And the charge accumulated in the scribe line D may be conducted away during the integrated circuit test or after the scribe line is grounded by other metal connection means.
In the embodiment of the present application, in order to achieve the purpose of conducting away the charges in the active area a as soon as possible, avoiding static damage caused by charge accumulation, the conductive channel C may select the shortest path, i.e. the conductive channel C is generally connected to the first edge of the active area a and the second edge of the integrated circuit closest to the first edge. Specifically, the first edge and the second edge may be located at any position on the upper side, the lower side, the left side and the right side of the integrated circuit, fig. 6 illustrates that the conductive channels C are located at the left side of the integrated circuit, and the number of the conductive channels C may be one or multiple, which is not limited herein. The width of the conductive path C may be any value, and is not limited herein.
Fig. 8 schematically illustrates another schematic top-view structure of an interface between a channel layer and a barrier layer in an integrated circuit according to an embodiment of the present application, and fig. 9 schematically illustrates another schematic top-view structure of an interface between a channel layer and a barrier layer in an integrated circuit according to an embodiment of the present application.
Specifically, when the wafer is cut into a plurality of integrated circuits, the width of the scribe line arranged in the wafer is generally larger than the cutting width due to a certain alignment offset error, for example, the width of the scribe line is 80um, the width of the wafer is 60um by using a blade or a laser, if no or a small amount of offset exists, a scribe line of about 10um may remain on one edge of the integrated circuit after cutting along one scribe line, and the remaining scribe line can be used as a conductive channel due to the conduction of the scribe line; if a certain offset occurs during the dicing process, i.e., dicing lanes at the edge of the integrated circuit may be completely cut during dicing, no dicing lanes may remain at a certain edge of the integrated circuit. Thus, referring to fig. 8, in the finally formed integrated circuit, scribe line D may be present at least one edge of the integrated circuit, and in fig. 8, it is schematically illustrated that scribe line D is located at one edge of the integrated circuit, and scribe line D may be located at a plurality of edges of the integrated circuit. Referring to fig. 9, when dicing is performed along the edge of the integrated circuit with a small dicing offset, scribe lines D disposed around the insulating region B may be formed in the finally formed integrated circuit.
Fig. 10 schematically illustrates another schematic top view of the interface between the channel layer and the barrier layer in the wafer according to the embodiment of the present application, and fig. 11 schematically illustrates a schematic cross-sectional structure along the OO direction in fig. 10.
Referring to fig. 10 and 11, in order to form an insulating region B isolating each integrated circuit at an interface between the barrier layer 5 and the channel layer 4, after the barrier layer 5 and the channel layer 4 are epitaxially grown on the wafer 100, nitrogen ions or argon ions may be implanted at a position of the surface of the epitaxial structure corresponding to the insulating region B (a region of the filling point in fig. 11 is a region of nitrogen ion or argon ion implantation, a two-dimensional electron gas formed at an interface between the barrier layer 5 and the channel layer 4 is shown by a transverse dotted line in fig. 11), nitrogen ions or argon ions are not implanted at a position corresponding to the active region a and the conductive channel C, and the barrier layer 5 and the channel layer 4 are insulating materials into which nitrogen ions or argon ions are implanted at a position corresponding to the insulating region B. Also, in order to ensure that the electrostatic charges generated in the active region a may be conducted away by the conductive vias C being connected to the scribe lanes D, at least a portion of the scribe lanes D need to ensure conductivity, for example, all of the scribe lanes D shown in fig. 10 have conductivity, or only the scribe lanes D in the column direction may have conductivity when the conductive vias C are located at the left and/or right sides of the circuit region S, or only the scribe lanes in the row direction may have conductivity when the conductive vias C are located at the upper and/or lower sides of the circuit region S, and nitrogen ions or argon ions may not be injected at positions corresponding to the scribe lanes having conductivity.
Fig. 12 schematically shows another cross-sectional structure along OO direction in fig. 10.
Referring to fig. 12, in another embodiment of the present application, after nitrogen ions or argon ions are implanted in the location corresponding to the insulating region B on the surface of the epitaxial structure on the wafer 100, in order to make the surface conductivity of the integrated circuit better, silicon ions may be implanted in the location corresponding to the active region a and the conductive channel C on the surface of the epitaxial structure, so that the portions of the barrier layer 5 and the channel layer 4 close to the barrier layer 5 are N-type semiconductor materials implanted with silicon ions in the location corresponding to the active region a and the conductive channel C, and the conductivity of the active region a and the conductive channel C is better. Similarly, silicon ions may be implanted into the surface of the epitaxial structure at a position corresponding to the scribe line D, thereby improving the conductivity of the scribe line D. Alternatively, after nitrogen ions or argon ions are implanted in the position corresponding to the insulating region B on the surface of the epitaxial structure on the wafer 100, in order to make the surface conductivity of the integrated circuit better, magnesium ions may be implanted in the position corresponding to the active region a and the conductive channel C on the surface of the epitaxial structure, so that the portions of the barrier layer 5 and the channel layer 4 close to the barrier layer 5 are P-type semiconductor materials implanted with magnesium ions in the position corresponding to the active region a and the conductive channel C, and the conductivity of the active region a and the conductive channel C is better. Similarly, magnesium ions can be implanted into the surface of the epitaxial structure at the position corresponding to the scribe line D, so as to improve the conductivity of the scribe line D. In fig. 12, the region filled with dense dots is a region in which nitrogen ions or argon ions are implanted, the region filled with open dots is a region in which silicon ions are implanted or a region in which magnesium ions are implanted, and a transverse dotted line shows two-dimensional electron gas formed at an interface between the barrier layer and the channel layer. It should be noted that, when no silicon ions or magnesium ions are implanted into the surface of the integrated circuit, the barrier layer 5 is an insulating material, and when silicon ions or magnesium ions are implanted into the surface of the integrated circuit, the barrier layer 5 is an N-type semiconductor material or a P-type semiconductor material.
In order to facilitate understanding of the integrated circuit provided by the embodiments of the present application, a method for manufacturing the same is described in detail below with reference to the accompanying drawings. Fig. 13 is a schematic flow chart of a method for manufacturing an integrated circuit according to an embodiment of the present application.
Referring to fig. 13, an integrated circuit may be prepared using a method comprising the steps of:
s1, forming a channel layer on a substrate, wherein the substrate is divided into a plurality of circuit areas which are arranged in an array manner and scribing channels which are positioned between the circuit areas.
Alternatively, the integrated circuit may be a field effect transistor in particular, or may be a high electron mobility transistor as well. When the integrated circuit is a high electron mobility transistor, a nucleation layer may be formed on the substrate first, then a channel layer is formed, and a barrier layer is formed on the channel layer. Further, a buffer layer may also be formed on the nucleation layer, followed by forming a channel layer.
In particular, the substrate material may be selected from high-resistance substrates, such as high-insulation SiC substrates, having a resistivity of about 10 9 Ω·cm 2 High heightA Si-resistant substrate having a resistivity of about 10 3 Ω·cm 2 Alternatively, the substrate may be a conductive substrate, such as a sapphire substrate, which is not limited herein. The nucleation layer can be made of AlN and other materials, the buffer layer can be made of AlGaN and other insulating materials, the channel layer can be made of GaN and other conductive materials, and the barrier layer can be made of AlGaN and other insulating materials. The nucleation layer, buffer layer, channel layer and barrier layer may all be obtained by epitaxial growth on the substrate.
S2, nitrogen ions or argon ions are injected into a partial area in the circuit area, so that an insulating area is formed on the surface of the channel layer at the ion injection position, an active area and a conductive channel are formed at the position which is not injected with ions, the insulating area is arranged around the active area, and the conductive channel penetrates through the insulating area and is communicated with the active area and the scribing channel. I.e., the scribe line, active region and conductive via are not implanted with ions.
Specifically, when the integrated circuit is a high electron mobility transistor, the two-dimensional electron gas formed at the interface between the channel layer and the barrier layer is entirely conductive before the nitrogen ion or argon ion implantation is performed, and electrostatic damage does not exist. After the insulating region is formed at the interface between the channel layer and the barrier layer, the conductive channel can communicate the active regions originally separated from each other in each circuit region to the dicing channel between the circuits, so that conduction between the active regions in each circuit region in the wafer is realized, when charges reach the surface of the wafer, the charges can be conducted away as soon as possible through the conductive channel, the active regions in each circuit region on the whole wafer are in an equipotential state, and the charges cannot be accumulated in a single circuit region to cause damage to the integrated circuit. And, the charge accumulated in the scribe line can be conducted away during the testing process of the integrated circuit or after the scribe line is grounded by adopting other metal connection modes.
Further, after nitrogen ions or argon ions are implanted in the position of the wafer corresponding to the insulating region, in order to make the surface conductivity of the integrated circuit better, silicon ions can be implanted in the positions of the active region, the conductive channel and the dicing channel, so that the parts, close to the barrier layer, of the barrier layer and the channel layer are N-type semiconductor materials implanted with the silicon ions in the positions corresponding to the active region, the conductive channel and the dicing channel, and the conductivity of the active region, the conductive channel and the dicing channel is better. Alternatively, after nitrogen ions or argon ions are implanted in the positions of the wafer corresponding to the insulating regions, in order to make the surface conductivity of the integrated circuit better, magnesium ions may be implanted in the positions of the active region, the conductive channels and the dicing channels, so that the portions of the barrier layer and the channel layer, which are close to the barrier layer, are P-type semiconductor materials implanted with magnesium ions in the positions corresponding to the active region, the conductive channels and the dicing channels, and the conductivity of the active region, the conductive channels and the dicing channels is better.
A passivation layer may also be formed on the barrier layer to mitigate the current collapse effect. Specifically, the passivation layer is etched away at the locations corresponding to the scribe lanes.
S3, cutting the substrate along the scribing channel to form a plurality of integrated circuits.
Specifically, when dicing into a plurality of integrated circuits, since a certain alignment offset error is allowed, the width of the scribe line provided in the wafer is generally larger than the dicing width, for example, the width of the scribe line is 80um, the width of the wafer is 60um by using a blade or a laser, if there is no or a small amount of offset, a scribe line of about 10um may remain on one edge of the integrated circuit after dicing along one scribe line, and the remaining scribe line may be used as a conductive path because the scribe line is conductive; if a certain offset occurs during the dicing process, i.e., dicing lanes at the edge of the integrated circuit may be completely cut during dicing, no dicing lanes may remain at a certain edge of the integrated circuit. Thus, in the final integrated circuit, dicing streets may be present at least one edge of the integrated circuit, dicing streets may also be present at multiple edges of the integrated circuit, and dicing streets disposed around the insulating regions may be formed in the final integrated circuit with less dicing offset when dicing along the edges of the integrated circuit.
The embodiment of the application also provides electronic equipment, which can comprise a circuit board and any integrated circuit provided by the embodiment of the application, wherein the integrated circuit is arranged on the circuit board. Since the principle of the electronic device for solving the problem is similar to that of the aforementioned integrated circuit, the implementation of the electronic device can be referred to the implementation of the aforementioned integrated circuit, and the repetition is omitted.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (15)
- An integrated circuit, comprising:a substrate;a channel layer over the substrate;the surface of the channel layer comprises an active region, an insulating region and a conductive channel, wherein the insulating region is arranged around the active region, and the conductive channel penetrates through the insulating region and is communicated with the active region and the edge of the integrated circuit.
- The integrated circuit of claim 1, wherein a surface of the channel layer further comprises: dicing streets located at least one edge of the integrated circuit.
- The integrated circuit of claim 2, wherein the scribe line is disposed around the insulating region.
- The integrated circuit of any of claims 1-3, wherein the conductive via communicates a first edge of the active region with a second edge of the integrated circuit nearest the first edge.
- The integrated circuit of any of claims 1-4, further comprising a barrier layer over the channel layer, the barrier layer and the channel layer being an insulating material implanted with nitrogen ions or argon ions at locations corresponding to the insulating region.
- The integrated circuit of any of claims 1-5, further comprising a barrier layer over the channel layer, the barrier layer being an insulating material.
- The integrated circuit of any of claims 1-5, further comprising a barrier layer over the channel layer, the barrier layer and a portion of the channel layer proximate the barrier layer being an N-type semiconductor material implanted with silicon ions at a location corresponding to the active region and the conductive channel.
- The integrated circuit of any of claims 1-5, further comprising a barrier layer over the channel layer, the barrier layer and a portion of the channel layer proximate the barrier layer being a P-type semiconductor material implanted with magnesium ions at a location corresponding to the active region and the conductive channel.
- The integrated circuit of any of claims 1-8, further comprising: a nucleation layer located between the substrate and the channel layer.
- The integrated circuit of any of claims 1-9, wherein the substrate is a high resistance substrate.
- A method of manufacturing an integrated circuit, comprising:forming a channel layer on a substrate, wherein the substrate is divided into a plurality of circuit areas which are arranged in an array manner and scribing channels which are positioned between the circuit areas;nitrogen ions or argon ions are implanted into a partial region in the circuit region, so that an insulating region is formed on the surface of the channel layer at the ion implantation position, an active region and a conductive channel are formed at the position which is not implanted with ions, the insulating region is arranged around the active region, and the conductive channel passes through the insulating region and is communicated with the active region and the scribing channel;and cutting the substrate along the scribing tracks to form a plurality of integrated circuits.
- The method of manufacturing of claim 11, further comprising, prior to forming the source, drain, and gate electrodes on the channel layer:and implanting silicon ions at the active region, the conductive channel and the dicing channel to form an N-type semiconductor material.
- The method of manufacturing of claim 11, further comprising, prior to forming the source, drain, and gate electrodes on the channel layer:and implanting magnesium ions at the active region, the conductive channel and the dicing channel to form a P-type semiconductor material.
- The method of manufacturing of any of claims 11-13, further comprising, prior to forming the channel layer on the substrate: forming a nucleation layer on the substrate;before the nitrogen ions or argon ions are injected into the partial region in the circuit region, the method further comprises: a barrier layer is formed on the channel layer.
- An electronic device comprising a circuit board and an integrated circuit as claimed in any one of claims 1-10 disposed on the circuit board.
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| PCT/CN2021/141529 WO2023122863A1 (en) | 2021-12-27 | 2021-12-27 | Integrated circuit, preparation method therefor, and electronic device |
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| US8389977B2 (en) * | 2009-12-10 | 2013-03-05 | Transphorm Inc. | Reverse side engineered III-nitride devices |
| CN108258035B (en) * | 2018-01-15 | 2020-09-29 | 中国科学院微电子研究所 | GaN-based enhanced field effect device and manufacturing method thereof |
| US11171203B2 (en) * | 2019-05-22 | 2021-11-09 | Virginia Tech Intellectual Properties, Inc. | High electron mobility transistors with charge compensation |
| CN113451129B (en) * | 2021-06-29 | 2022-05-10 | 厦门市三安集成电路有限公司 | High electron mobility transistor and preparation method thereof |
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