CN117219656A - Gallium arsenide heterojunction bipolar transistor and manufacturing method thereof - Google Patents
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 title claims abstract description 101
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 100
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 50
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 20
- 239000000203 mixture Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 230000007547 defect Effects 0.000 abstract description 3
- 229910002058 ternary alloy Inorganic materials 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910002059 quaternary alloy Inorganic materials 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention discloses a gallium arsenide heterojunction bipolar transistor, wherein a base region of the gallium arsenide heterojunction bipolar transistor adopts GaAsSb or InGaAs materials, and an emitting region adopts GaInP materials rich in Ga (namely Ga component is more than 51%). The invention also discloses a manufacturing method of the gallium arsenide heterojunction bipolar transistor. The bandwidth of the emitter region material is increased, the bandwidth of the base region material is reduced, the bandwidth difference between the emitter region and the base region of the device is increased, and the thermal stability and the reliability of the device are improved. In addition, the GaAsSb or InGaAs base region and the GaInP emitter region are both ternary alloys, the components are easier to control, the materials are easier to prepare, and the defect problem caused by the Al element and the N element in the prior art does not exist.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a gallium arsenide heterojunction bipolar transistor and a manufacturing method thereof.
Background
Gallium arsenide (GaAs) heterojunction bipolar transistor (HeterojunctionBipolarTransistor, HBT) has the advantages of high power density, high gain, low phase noise, good linearity, small chip area, low manufacturing cost and the like, and is widely applied to radio frequency devices of mobile phones, optical communication systems and radar systems. The structure of a traditional GaAs HBT comprises a semi-insulating GaAs substrate, an N-type GaAs sub-collector region, an N-type GaAs collector region, a P-type GaAs base region, an N-type GaInP emitter region, an N-type GaAs emitter region cover layer, an N-type InGaAs contact layer and a corresponding metal electrode, wherein the Ga component in the emitter region of the N-type GaInP is 51%. Fig. 1 is a plot of III-V semiconductor lattice parameter versus bandwidth. As shown in fig. 1, in the conventional GaAs HBT, the stress of the GaInP emitter region with a Ga composition of 51% is zero, and the stress of the GaAs base region is also zero, so that there is no stress in the material, and the material quality is the best.
However, for GaAs HBT devices, temperature stability is one of the important indicators. The index is related to the bandwidth difference deltaeg between the GaInP emitter region and the GaAs base region, namely, the larger deltaeg is, the better the temperature stability is. For lattice-perfectly matched GaInP and GaAs Δeg is 0.493eV. In order to increase Δeg, the current common technical solutions are: the bandwidth of the emitter region is increased, such as by using AlGaInP material, and the bandwidth of the base region is reduced, such as by using InGaAsN material. However, these quaternary alloy compositions are difficult to control and neither Al nor N introduce non-radiative recombination centers into the material, resulting in reduced material quality and device performance.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a gallium arsenide heterojunction bipolar transistor capable of improving the bandwidth difference between an emitter region and a base region and simultaneously guaranteeing the material quality and a manufacturing method thereof.
According to the gallium arsenide heterojunction bipolar transistor provided by the embodiment of the invention, the base region is made of a P-type GaAsSb or InGaAs material, and the emitter region is made of an N-type GaInP material, wherein in the N-type GaInP material, the Ga component is more than 51%.
In one example of the gallium arsenide heterojunction bipolar transistor provided in the above aspect, the gallium arsenide heterojunction bipolar transistor further comprises a substrate, a sub-collector region, a collector region, an emitter region cap layer, a contact layer, a collector region electrode, a base region electrode, and an emitter region electrode;
the collector region electrode is in contact with the sub-collector region, the base region electrode is in contact with the base region, and the emitter region electrode is in contact with the contact layer.
In one example of the gallium arsenide heterojunction bipolar transistor provided in the above aspect, the substrate is semi-insulating GaAs; and/or, the sub-collector region is N-type GaAs; and/or the collector region is N-type GaAs; and/or, the emitting region cover layer is N-type GaAs; and/or the contact layer is N-type InGaAs; and/or, the collector electrode is AuGe; and/or the base electrode is a combination of Ti/Pt/Au; and/or the emitter electrode is AuGe.
In one example of the gallium arsenide heterojunction bipolar transistor provided in the above aspect, when the base region is made of a P-type GaAsSb material, the Ga composition in the emitter region is 57%.
In one example of a gallium arsenide heterojunction bipolar transistor provided by the above aspect, when the base region is made of P-type InGaAs material, the Ga composition in the emitter region is 61%.
According to another aspect of the embodiment of the invention, the manufacturing method of the gallium arsenide heterojunction bipolar transistor comprises the following steps: providing a substrate; sequentially forming a laminated sub-collector region, a base region, an emitter region cover layer and a contact layer on the substrate; the base region is made of a P-type GaAsSb or InGaAs material, the emitter region is made of an N-type GaInP material, and the Ga component in the N-type GaInP material is more than 51%; and forming a collector region electrode in contact with the sub-collector region, a base region electrode in contact with the base region, and an emitter region electrode in contact with the contact layer.
In one example of the method for manufacturing a gallium arsenide heterojunction bipolar transistor provided in the above another aspect, the forming a collector electrode in contact with the sub-collector, a base electrode in contact with the base region, and an emitter electrode in contact with the contact layer includes: carrying out partial etching on the contact layer, the emitter region cover layer and the emitter region to expose part of the base region; carrying out local etching on the base region and the collector region in the exposed region of the base region to expose part of the sub-collector region; depositing the collector electrode on the exposed sub-collector, and depositing the base electrode on the exposed base, and depositing the emitter electrode on the contact layer.
In one example of the method for manufacturing a gallium arsenide heterojunction bipolar transistor provided in the above another aspect, the substrate is semi-insulating GaAs; and/or, the sub-collector region is N-type GaAs; and/or the collector region is N-type GaAs; and/or, the emitting region cover layer is N-type GaAs; and/or the contact layer is N-type InGaAs; and/or, the collector electrode is AuGe; and/or the base electrode is a combination of Ti/Pt/Au; and/or the emitter electrode is AuGe.
In one example of the method for manufacturing a gallium arsenide heterojunction bipolar transistor provided in the above another aspect, when the base region is made of a P-type GaAsSb material, the Ga component in the emitter region is 57%.
In one example of the method for manufacturing a gallium arsenide heterojunction bipolar transistor provided in the above another aspect, when the base region is made of P-type InGaAs material, the Ga component in the emitter region is 61%.
Advantageous effects: the base region of the GaAs HBT is made of GaAsSb or InGaAs materials, the bandwidth is smaller than that of GaAs, the emitter region is made of Ga-rich GaInP materials, the Ga component is larger than 51%, and the bandwidth is larger than that of the GaInP matched with the traditional lattice. The common effect of the two is that the bandwidth difference delta Eg of the emitter region and the base region is greatly increased, and the temperature stability of the device is improved. Furthermore, the base region of the GaAs HBT adopts GaAsSb or InGaAs materials, the lattice parameter is larger than that of GaAs, compressive stress is formed on a GaAs substrate, the emitter region adopts Ga-rich GaInP materials, the Ga component is larger than 51%, the lattice parameter is smaller than that of GaAs, tensile stress is formed on the GaAs substrate, the two layers are in contact, the mutual effect of the two layers is that the stresses counteract each other, the average stress of the materials is close to zero, and high-quality materials and devices are ensured. Furthermore, the GaAsSb or InGaAs base region and the GaInP emitter region are ternary alloys, the components are easier to control, the materials are easier to prepare, and the defect problem caused by the Al element and the N element in the prior art is avoided.
Drawings
The above and other aspects, features and advantages of embodiments of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings in which:
FIG. 1 is a graph of III-V semiconductor lattice parameter versus bandwidth;
fig. 2 is a schematic diagram of a gallium arsenide heterojunction bipolar transistor according to an embodiment of the invention;
fig. 3A to 3D are process diagrams of a method for fabricating a gaas heterojunction bipolar transistor according to an embodiment of the present invention.
Detailed Description
Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided to explain the principles of the invention and its practical application so that others skilled in the art will be able to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.
As used herein, the term "comprising" and variations thereof mean open-ended terms, meaning "including, but not limited to. The terms "based on", "in accordance with" and the like mean "based at least in part on", "in part in accordance with". The terms "embodiment," one example, "" one embodiment, "and" an embodiment "mean" at least one embodiment. The terms "another embodiment," another example, "" yet another example "mean" at least one other embodiment. The terms "first," "second," and the like, may refer to different or the same object. Other definitions, whether explicit or implicit, may be included below. Unless the context clearly indicates otherwise, the definition of a term is consistent throughout this specification.
It should be noted here that, in order to avoid obscuring the present invention due to unnecessary details, only structures and/or processing steps closely related to the scheme according to the present invention are shown in the drawings, while other details having little relevance are omitted.
Fig. 2 is a schematic diagram of a gallium arsenide heterojunction bipolar transistor according to an embodiment of the invention.
Referring to fig. 2, a gallium arsenide heterojunction bipolar transistor according to an embodiment of the invention comprises: a substrate 10; sub-collector region 20, collector region 30, base region 40, emitter region 50, emitter region cap layer 60, contact layer 70, collector region electrode 80, base region electrode 90, and emitter region electrode 100, which are sequentially stacked on substrate 10 (i.e., stacked in a direction away from substrate 10); wherein collector electrode 80 is in contact with sub-collector 20, base electrode 90 is in contact with base 40, and emitter electrode 100 is in contact with contact layer 70.
In one example, the substrate 10 is preferably a semi-insulating GaAs substrate. The sub-collector 20 is made of Si-doped GaAs with a Si doping concentration of 4×10 18 cm -3 The thickness was 400nm. Collector region 30 is made of Si-doped GaAs with a Si doping concentration of 2×10 16 cm -3 The thickness was 800nm. The base region 40 is C-doped GaAsSb having a Sb content of 5% and a C doping concentration of 3×10 19 cm -3 The thickness was 100nm. The emitter region 50 employs Si-doped GaInP with a Ga composition of 57% and a Si doping concentration of 3 x 10 17 cm -3 The thickness was 30nm. Emitter cap layer 60 is formed of Si doped GaAs having a Si doping concentration of 4×10 18 cm -3 The thickness was 100nm. The contact layer 70 is made of Te doped InGaAs with a Te doping concentration of 1×10 19 cm -3 The thickness was 100nm. The collector electrode 80 is AuGe with a thickness of 200 nm. The base electrode 90 is a combination of Ti (thickness 20 nm)/Pt (thickness 40 nm)/Au (thickness 200 nm). The emitter electrode 100 is AuGe with a thickness of 100nm.
In this example, the base region 40 with GaAsSb has a stress of +0.4% and the emitter region 50 with GaInP has a stress of-0.4% with the stresses exactly canceling, thus ensuring the quality of the material. Meanwhile, compared with the delta Eg (0.493 eV) of the GaInP/GaAs base region of the emitter region of the traditional GaAs HBT, the delta Eg of the emitter region 50 adopting GaInP/the base region 40 adopting GaAsSb in the example reaches 0.683eV, and the temperature stability of the device is better improved.
In another illustrationIn an example, the substrate 10 is preferably a semi-insulating GaAs substrate. The sub-collector 20 is made of Si-doped GaAs with Si doping concentration of 5×10 18 cm -3 The thickness was 500nm. Collector region 30 is made of Si-doped GaAs with Si doping concentration of 1×10 16 cm -3 The thickness was 600nm. The base region 40 is C-doped InGaAs with an In composition of 10% and a C doping concentration of 6X10 19 cm -3 The thickness was 60nm. The emitter region 50 employs Si-doped GaInP with a Ga composition of 61% and a Si doping concentration of 2 x 10 17 cm -3 The thickness was 25nm. Emitter cap layer 60 is formed of Si doped GaAs with Si having a doping concentration of 5×10 18 cm -3 The thickness was 100nm. The contact layer 70 is made of Te doped InGaAs with a Te doping concentration of 3×10 19 cm -3 The thickness was 80nm. The collector electrode 80 is AuGe with a thickness of 300 nm. The base electrode 90 is a combination of Ti (thickness 20 nm)/Pt (thickness 40 nm)/Au (thickness 300 nm). The emitter electrode 100 is AuGe with a thickness of 300 nm.
In this further example, the base region 40 using InGaAs has a stress of +0.72% and the emitter region 50 using GaInP has a stress of-0.71% with the stresses substantially offset, ensuring material quality. Meanwhile, compared with the delta Eg (0.493 eV) of the GaInP/base region GaAs of the emitter region GaInP of the traditional GaAs HBT, the delta Eg of the emitter region 50 adopting GaInP/base region 40 adopting InGaAs in the other example reaches 0.838eV, the delta Eg is improved by 70%, and the temperature stability of the device is greatly improved.
Hereinafter, a method of fabricating a gallium arsenide heterojunction bipolar transistor according to an embodiment of the present invention will be described in detail. Fig. 3A to 3D are process diagrams of a method for fabricating a gaas heterojunction bipolar transistor according to an embodiment of the present invention.
Step one: referring to fig. 3A, a substrate 10 is provided, the substrate 10 preferably being a semi-insulating GaAs substrate.
Step two: referring to fig. 3B, a sub-collector 20, a collector 30, a base 40, an emitter 50, an emitter cap 60, and a contact layer 70 forming a stack are grown sequentially from bottom to top on the substrate 10.
In one example, metal Organic Chemical Vapor Deposition (MOCVD)) As a growth process, the growth source is TMGa, TMIn, asH 3 And pH (potential of Hydrogen) 3 The N-type doping source is SiH 4 And DETe, the P-type doping source is CCl 4 . The growth temperature was 700℃and the reaction chamber pressure was 200Torr. After removing impurities on the surface of the substrate 10 by high temperature treatment, the gallium arsenide heterojunction bipolar transistor structure as shown in fig. 3B is grown in sequence:
(1) Sub-collector region 20, wherein sub-collector region 20 is made of Si-doped GaAs with Si doping concentration of 4X10 18 cm -3 The thickness was 400nm.
(2) Collector region 30, wherein collector region 30 employs Si-doped GaAs, wherein the Si doping concentration is 2×10 16 cm -3 The thickness was 800nm.
(3) A base region 40, wherein the base region 40 is C-doped GaAsSb having an Sb component of 5% and a C doping concentration of 3×10 19 cm -3 The thickness was 100nm.
(4) Emitter region 50, wherein emitter region 50 employs Si-doped GaInP having a Ga composition of 57% and a Si doping concentration of 3 x 10 17 cm -3 The thickness was 30nm.
(5) Emitter cap layer 60, wherein emitter cap layer 60 is formed from Si-doped GaAs having a Si doping concentration of 4×10 18 cm -3 The thickness was 100nm.
(6) A contact layer 70, wherein the contact layer 70 is made of Te doped InGaAs, wherein the Te doping concentration is 1×10 19 cm -3 The thickness was 100nm.
In one example of a fabrication method, the stress of the base region 40 using GaAsSb is +0.4%, the stress of the emitter region 50 using GaInP is-0.4%, and the stresses are exactly offset, thereby ensuring the quality of the material. Meanwhile, compared with the delta Eg (0.493 eV) of the GaInP/GaAs base region of the emitter region of the traditional GaAs HBT, the delta Eg of the emitter region 50 adopting GaInP/the base region 40 adopting GaAsSb reaches 0.683eV, and the temperature stability of the device is better improved.
In another example, metal Organic Chemical Vapor Deposition (MOCVD) is preferably used as the growth process, with a growth source of TMGa, TMIn, asH 3 And pH (potential of Hydrogen) 3 The N-type doping source is SiH 4 And DETe, the P-type doping source is CBr 4 . The growth temperature was 600℃and the reaction chamber pressure was 100Torr. After removing impurities on the surface of the substrate 10 by high temperature treatment, the gallium arsenide heterojunction bipolar transistor structure as shown in fig. 3B is grown in sequence:
(1) Sub-collector region 20, wherein sub-collector region 20 is made of Si-doped GaAs with Si doping concentration of 5×10 18 cm -3 The thickness was 500nm.
(2) Collector region 30, wherein collector region 30 employs Si-doped GaAs, wherein the Si doping concentration is 1×10 16 cm -3 The thickness was 600nm.
(3) A base region 40, wherein the base region 40 is C-doped InGaAs with an In composition of 10% and a C doping concentration of 6X10 19 cm -3 The thickness was 60nm.
(4) Emitter region 50, wherein emitter region 50 employs Si-doped GaInP with a Ga composition of 61% and a Si doping concentration of 2X 10 17 cm -3 The thickness was 25nm.
(5) Emitter cap layer 60, wherein emitter cap layer 60 is formed from Si-doped GaAs having a Si doping concentration of 5×10 18 cm -3 The thickness was 100nm.
(6) A contact layer 70, wherein the contact layer 70 is made of Te doped InGaAs, wherein the Te doping concentration is 3×10 19 cm -3 The thickness was 80nm.
In another example of a fabrication method, the base region 40 using InGaAs has a stress of +0.72% and the emitter region 50 using GaInP has a stress of-0.71% with the stresses substantially offset, ensuring material quality. Meanwhile, compared with the delta Eg (0.493 eV) of the GaInP/base region GaAs of the emitter region GaInP of the traditional GaAs HBT, the delta Eg of the emitter region 50 adopting GaInP/base region 40 adopting InGaAs in the other example reaches 0.838eV, the delta Eg is improved by 70%, and the temperature stability of the device is greatly improved.
Step three: referring to fig. 3C, contact layer 70, emitter cap layer 60, and emitter 50 are etched to expose a portion of base region 40; etching of the base region 40 and collector region 30 continues at the exposed region of the base region 40, exposing portions of the sub-collector region 20.
In one example, a wet etch process is used to etch contact layer 70,Emitter cap layer 60 and emitter region 50 are etched to partially expose base region 40, wherein contact layer 70 and emitter cap layer 60 are etched using an etchant of H 2 SO 4 +H 2 O 2 +H 2 The corrosion liquid adopted by the emission area 50 is HCl+H 2 O; wet etching is carried out on the base region 40 and the collector region 30 in the exposed region of the base region 40 to partially expose the sub-collector region 20, wherein the etching solution is H 2 SO 4 +H 2 O 2 +H 2 O。
In another example, the contact layer 70, emitter cap layer 60, and emitter 50 are etched using an Inductively Coupled Plasma (ICP) process to expose a portion of the base region 40; etching of the base region 40 and collector region 30 continues at the exposed region of the base region 40, exposing portions of the sub-collector region 20. Wherein the etching gas adopted in the ICP process is Cl 2 And BCl 3 。
Step four: referring to fig. 3D, collector electrode 80 is deposited on sub-collector 20, base electrode 90 is deposited on base region 40, and emitter electrode 100 is deposited on contact layer 70, respectively.
In one example, an electron beam evaporation process is used to deposit collector electrode 80 on sub-collector 20, base electrode 90 on base region 40, and emitter electrode 100 on contact layer 70, respectively. Wherein, the collector region electrode 80 is 200nmAuGe, the base region electrode 90 is Ti (20 nm)/Pt (40 nm)/Au (200 nm) combination, and the emitter region electrode 100 is 100nmAuGe.
In another example, an electron beam evaporation process is used to deposit collector electrode 80 on sub-collector 20, base electrode 90 on base region 40, and emitter electrode 100 on contact layer 70, respectively. Wherein the collector electrode 80 is 300nmAuGe, the base electrode 90 is a Ti (20 nm)/Pt (40 nm)/Au (300 nm) combination, and the emitter electrode 100 is 300nmAuGe.
In summary, in the GaAs heterojunction bipolar transistor and the method for fabricating the same according to the embodiments of the present invention, the base region of the GaAs HBT is made of GaAsSb or InGaAs material, the bandwidth is smaller than GaAs, the emitter region is made of Ga-rich GaInP material, the Ga component is greater than 51%, and the bandwidth is greater than the conventional lattice-matched GaInP. The common effect of the two is that the bandwidth difference delta Eg of the emitter region and the base region is greatly increased, and the temperature stability of the device is improved. Furthermore, the base region of the GaAs HBT adopts GaAsSb or InGaAs materials, the lattice parameter is larger than GaAs, compressive stress is formed on the GaAs substrate, the emitting region adopts Ga-rich GaInP materials, the Ga component is larger than 51%, the lattice parameter is smaller than GaAs, tensile stress is formed on the GaAs substrate, the two layers are contacted, the mutual effect of the two layers is that the stresses are counteracted, the average stress of the materials is close to zero, and high-quality materials and devices are ensured. Furthermore, the GaAsSb or InGaAs base region and the GaInP emitter region are both ternary alloys, the components are easier to control, the materials are easier to prepare, and the defect problem caused by the Al element and the N element in the prior art does not exist.
The terms "exemplary," "example," and the like, as used throughout this specification, mean "serving as an example, instance, or illustration," and do not mean "preferred" or "advantageous" over other embodiments. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described embodiments.
The alternative implementation of the embodiment of the present invention has been described in detail above with reference to the accompanying drawings, but the embodiment of the present invention is not limited to the specific details of the foregoing implementation, and various simple modifications may be made to the technical solutions of the embodiment of the present invention within the scope of the technical concept of the embodiment of the present invention, and these simple modifications all fall within the protection scope of the embodiment of the present invention.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The gallium arsenide heterojunction bipolar transistor is characterized in that a base region of the gallium arsenide heterojunction bipolar transistor is made of a P-type GaAsSb or InGaAs material, an emitting region of the gallium arsenide heterojunction bipolar transistor is made of an N-type GaInP material, and in the N-type GaInP material, the Ga component is more than 51%.
2. The gallium arsenide heterojunction bipolar transistor of claim 1, further comprising a substrate, a sub-collector, a collector, an emitter cap, a contact layer, a collector electrode, a base electrode, and an emitter electrode;
the collector region electrode is in contact with the sub-collector region, the base region electrode is in contact with the base region, and the emitter region electrode is in contact with the contact layer.
3. The gallium arsenide heterojunction bipolar transistor of claim 2, wherein the substrate is semi-insulating GaAs; and/or, the sub-collector region is N-type GaAs; and/or the collector region is N-type GaAs; and/or, the emitting region cover layer is N-type GaAs; and/or the contact layer is N-type InGaAs; and/or, the collector electrode is AuGe; and/or the base electrode is a combination of Ti/Pt/Au; and/or the emitter electrode is AuGe.
4. A gallium arsenide heterojunction bipolar transistor as claimed in any one of claims 1 to 3, wherein the Ga composition in said emitter region is 57% when said base region is of GaAsSb material of P-type.
5. A gallium arsenide heterojunction bipolar transistor as claimed in any one of claims 1 to 3, wherein the Ga composition in said emitter region is 61% when said base region is of InGaAs material of P type.
6. The manufacturing method of the gallium arsenide heterojunction bipolar transistor is characterized by comprising the following steps of:
providing a substrate;
sequentially forming a laminated sub-collector region, a base region, an emitter region cover layer and a contact layer on the substrate; the base region is made of a P-type GaAsSb or InGaAs material, the emitter region is made of an N-type GaInP material, and the Ga component in the N-type GaInP material is more than 51%;
and forming a collector region electrode in contact with the sub-collector region, a base region electrode in contact with the base region, and an emitter region electrode in contact with the contact layer.
7. The method of manufacturing a gallium arsenide heterojunction bipolar transistor according to claim 6, wherein forming a collector electrode in contact with the sub-collector, a base electrode in contact with the base region, and an emitter electrode in contact with the contact layer comprises:
carrying out partial etching on the contact layer, the emitter region cover layer and the emitter region to expose part of the base region;
carrying out local etching on the base region and the collector region in the exposed region of the base region to expose part of the sub-collector region;
depositing the collector electrode on the exposed sub-collector, and depositing the base electrode on the exposed base, and depositing the emitter electrode on the contact layer.
8. The method of fabricating a gallium arsenide heterojunction bipolar transistor as claimed in claim 6, wherein said substrate is semi-insulating GaAs; and/or, the sub-collector region is N-type GaAs; and/or the collector region is N-type GaAs; and/or, the emitting region cover layer is N-type GaAs; and/or the contact layer is N-type InGaAs; and/or, the collector electrode is AuGe; and/or the base electrode is a combination of Ti/Pt/Au; and/or the emitter electrode is AuGe.
9. The method according to any one of claims 6 to 8, wherein when the base region is made of P-type GaAsSb material, the Ga composition in the emitter region is 57%.
10. The method of manufacturing a gallium arsenide heterojunction bipolar transistor as claimed in any one of claims 6 to 8, wherein the Ga composition in the emitter region is 61% when the base region is of InGaAs material of P type.
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