CN117219575A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and can improve the electrical contact effect of a conductive column and a semiconductor device and reduce the process difficulty and cost of the semiconductor structure. The manufacturing method comprises the following steps: a first substrate is provided. At least one recess is formed in the first substrate surface. And filling conductive materials in the at least one groove to form a plurality of conductive posts. Along the extending direction of the conductive column, a first cavity is formed in a structure where at least one of the opposite ends of the conductive column is located, and the first cavity exposes the end face of the conductive column. A first semiconductor device is formed in the first cavity, the first semiconductor device being electrically connected to the conductive pillar.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for fabricating the same.

Background

The traditional packaging technology mounts various active devices and passive devices on a substrate, the occupied area is large, the reliability is poor, the trend of increasingly miniaturization of a packaging system cannot be met, a three-dimensional heterogeneous packaging technology based on a standard Silicon technology, such as a system-in-package (System In a Package, for short, SIP) technology and a cavity structure are used for integrating semiconductor devices with different functions on different substrates, stacking and interconnection of chips can be realized in a small area, the occupied area of the semiconductor devices is greatly reduced, the reliability of the semiconductor devices is increased, and therefore, how to optimize the technology of the three-dimensional heterogeneous packaging technology becomes the future development direction of the industry.

Three-dimensional isomerism techniques based on cavity structures often require the formation of multiple conductive pillars within the cavity. In this way, the semiconductor device embedded in the cavity can be electrically connected with the conductive column, and further, different semiconductor devices can be electrically connected through the conductive column; alternatively, the semiconductor device is heat-dissipated or grounded through the conductive pillars. Wherein the semiconductor device must be in contact with the conductive pillars. However, the accuracy of the process conditions for forming the cavity and the conductive column is not easy to control, so that the contact surface of the conductive column and the semiconductor device is uneven, and the electrical effect is reduced; and the process steps for manufacturing the conductive column are more and difficult, so that the process cost is higher.

Disclosure of Invention

In view of this, the semiconductor structure and the manufacturing method thereof provided by the embodiment of the invention can improve the electrical contact effect between the conductive column and the semiconductor device, and reduce the process difficulty and cost of the semiconductor structure.

In order to achieve the above purpose, the technical scheme of the invention is realized as follows:

in one aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, where the method includes: a first substrate is provided. At least one recess is formed in the first substrate surface. And filling conductive materials in the at least one groove to form a plurality of conductive posts. Along the extending direction of the conductive column, a first cavity is formed in a structure where at least one of the opposite ends of the conductive column is located, and the first cavity exposes the end face of the conductive column. A first semiconductor device is formed in the first cavity, the first semiconductor device being electrically connected to the conductive pillar.

In some examples, the forming a first cavity in a structure in which at least one of the opposite ends of the conductive pillar is located includes: and forming a first semiconductor layer on the surface of the groove opening of the first substrate, and forming the first cavity on the first semiconductor layer.

In some examples, the forming a first cavity in a structure in which at least one of the opposite ends of the conductive pillar is located includes:

and the distance between the surface of one side of the first substrate far away from the surface of the groove opening and the plane of the bottom of the groove is larger than or equal to the thickness of the semiconductor device, and the first cavity is formed on the surface of one side of the first substrate far away from the surface of the groove opening. Or, the distance between the surface of the first substrate, which is far away from the surface of the groove opening, and the plane of the bottom of the groove is smaller than the thickness of the semiconductor device, and a second semiconductor layer is formed on the surface of the first substrate, which is far away from the surface of the groove opening, so as to form the first cavity penetrating through the second semiconductor layer and extending to the end face of the conductive column.

In some examples, the first substrate includes a first surface and a second surface, the first surface forming the recess. A support layer is bonded to the first surface prior to the second surface forming the first cavity. After the first cavity is formed in the second surface, the support layer is removed.

In some examples, the first substrate includes a first surface and a second surface, the first surface forming the recess. After the conductive posts are formed in the grooves, the first semiconductor layer is formed on the first surface. And thinning one side of the first substrate away from the first surface to expose an end face of the conductive post close to the second surface of the first substrate. The first cavity is formed on the surface of one side of the first semiconductor layer away from the first substrate.

In some examples, the method of making further comprises: forming a third semiconductor layer on the thinned surface of the first substrate, and forming a second cavity on the third semiconductor layer; the bottom of the second cavity exposes an end face of the conductive post proximate to the first surface of the first substrate. And forming a second semiconductor device in the second cavity, wherein the second semiconductor device is electrically connected with the conductive column.

In some examples, the plurality of conductive posts includes a plurality of groups, the conductive posts of a group being the same height; the heights of the conductive posts of different groups are the same or different. The first cavity comprises a plurality of first cavities, and a plane of the bottom of one first cavity is approximately flush with the end face of the group of conductive posts, which is close to the first cavity.

According to the manufacturing method of the semiconductor structure, after the at least one groove is formed on the surface of one side of the first substrate and the at least one conductive post is formed in the at least one groove, one end face of the conductive post is approximately flush with the surface of one side of the first substrate. The first cavity is arranged on the structure at the other end of the conductive column through a subsequent process or is arranged on the surface of the first substrate at the groove opening through a subsequent process by judging the distance between the plane at the bottom of the groove (namely the other end face of the conductive column along the extending direction of the conductive column) and the surface of the first substrate at the side far away from the groove opening and the thickness of the first semiconductor device. In this way, the formed conductive column can be directly electrically connected with a first semiconductor device formed in the first cavity, a deeper groove and a higher conductive column do not need to be formed first, and then the conductive column with redundant height is removed in the subsequent process, so that the process steps and cost of the conductive column and the first cavity are reduced, the problem that the end face of the conductive column is uneven due to the process condition in the process of removing the conductive column with redundant length is avoided, and the probability of poor electrical connection effect of the conductive column and the first semiconductor device is further reduced.

In another aspect, an embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes a semiconductor base structure, a first semiconductor device, and at least one conductive pillar. The first semiconductor device portion extends through the semiconductor base structure. At least one conductive pillar portion penetrates through the semiconductor substrate structure and is provided with a first end face and a second end face which are oppositely arranged along the extending direction of the conductive pillar; the first end face is substantially flush with a surface of the semiconductor base structure remote from the first semiconductor device, and the second end face is in contact with and electrically connected to the first semiconductor device.

In some examples, the semiconductor base structure includes a first base; alternatively, the semiconductor base structure includes a first base and a semiconductor layer stacked along the extending direction of the conductive pillar.

In some examples, the semiconductor base structure includes the first base and a first semiconductor layer stacked along a direction in which the conductive pillars extend, the conductive pillars extending through the first base, the first semiconductor device extending through the first semiconductor layer; alternatively, the semiconductor substrate structure includes a first substrate and a second semiconductor layer stacked along an extension direction of the conductive pillar, the conductive pillar penetrates through the first substrate, and the first semiconductor device penetrates through the second semiconductor layer and partially penetrates through the first substrate.

In some examples, the semiconductor structure further includes a second semiconductor device and a third semiconductor layer; the second semiconductor device penetrates through the third semiconductor layer; the third semiconductor layer and the semiconductor substrate structure are stacked along the extending direction of the conductive column; the second end face of the conductive post is in contact with and electrically connected to the second semiconductor device.

In some examples, a surface of the first semiconductor device remote from the conductive pillar is substantially flush with a surface of the semiconductor base structure remote from the conductive pillar; and/or a surface of the second semiconductor device away from the conductive pillar is substantially flush with a surface of the third semiconductor layer away from the conductive pillar.

In some examples, the plurality of conductive posts includes a plurality of groups, the conductive posts of a group being the same height; the heights of the conductive posts of different groups are the same or different.

In some examples, the semiconductor structure further includes at least one insulating layer, one of the at least one insulating layer encasing a sidewall of one of the conductive pillars.

In the semiconductor structure provided by the embodiment of the invention, the conductive columns and the first semiconductor device are sequentially arranged along the extending direction of the conductive columns (namely the thickness direction of the semiconductor substrate structure), wherein at least one conductive column part penetrates through the semiconductor substrate structure, and the height of the conductive column is smaller than the thickness of the semiconductor substrate structure; and, the first semiconductor device portion extends through the semiconductor base structure and is in contact with and electrically connected to the at least one conductive pillar. Thus, the first semiconductor device can be stably embedded in the semiconductor substrate structure, and good contact with the conductive column and stable electric connection are achieved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a cross-sectional view of a semiconductor structure according to one embodiment of the present invention;

FIG. 2 is a cross-sectional view of another semiconductor structure according to one embodiment of the present invention;

fig. 3 is a cross-sectional view of yet another semiconductor structure provided in accordance with an embodiment of the present invention;

FIG. 4 is a cross-sectional view of a second semiconductor structure according to one embodiment of the present invention;

fig. 5 is a cross-sectional view of a third semiconductor structure according to an embodiment of the present invention;

fig. 6 is a cross-sectional view of yet another semiconductor structure according to an embodiment of the present invention;

fig. 7 is a cross-sectional view of yet another semiconductor structure according to an embodiment of the present invention;

fig. 8 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;

fig. 9 is a flowchart illustrating another method for fabricating a semiconductor structure according to an embodiment of the present invention;

fig. 10 is a flowchart illustrating a method for fabricating a semiconductor structure according to another embodiment of the present invention;

fig. 11 is a schematic structural cross-sectional view of a semiconductor structure in the manufacturing process according to an embodiment of the present invention;

Fig. 12 is a schematic cross-sectional view of another semiconductor structure according to an embodiment of the present invention during fabrication;

fig. 13 is a schematic cross-sectional view of a semiconductor structure during fabrication according to another embodiment of the present invention;

fig. 14 is a schematic cross-sectional view of a semiconductor structure during a manufacturing process according to another embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the invention; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

The traditional packaging technology mounts various active devices and passive devices on a substrate, the occupied area is large, the reliability is poor, the trend of increasingly miniaturization of a packaging system cannot be met, the three-dimensional heterogeneous packaging technology (system-in-package SIP) based on the standard silicon technology integrates semiconductor devices with different functions on different substrates together by using a TSV technology and a cavity structure, stacking and interconnection of chips can be realized in a small area, the occupied area of the semiconductor devices is greatly reduced, the reliability of the semiconductor devices is increased, and therefore, the technology for optimizing the three-dimensional heterogeneous packaging technology becomes the future development direction of the industry.

Three-dimensional isomerism techniques based on cavity structures often require the formation of multiple conductive pillars within the cavity. In this way, the semiconductor device embedded in the cavity can be electrically connected with the conductive column, and further, different semiconductor devices can be electrically connected through the conductive column; alternatively, the semiconductor device is heat-dissipated or grounded through the conductive pillars. Wherein the semiconductor device must be in contact with the conductive pillars. For example, the process of forming the cavity and the conductive pillar is to form a deep recess in a substrate, form an initial conductive pillar in the recess, and then remove the upper half of the initial conductive pillar (the remaining portion is electrically connected to the semiconductor device as a conductive pillar) by etching. The accuracy of the process conditions for etching the conductive column is not easy to control, so that the contact surface of the conductive column and the semiconductor device is uneven, and the electrical connection effect is reduced; and the deeper grooves and the conductive columns filled in the grooves are complicated in forming process steps, and a plurality of process steps increased due to the redundant structure are generated, so that the process cost is high.

Based on the above, the embodiment of the application provides a semiconductor structure and a manufacturing method thereof, which can improve the electrical connection effect of a conductive column and a semiconductor device and reduce the process difficulty and cost of the semiconductor structure.

In some embodiments, as shown in fig. 1-7, the present application provides a semiconductor structure 100. The semiconductor structure 100 has a plurality of spaced apart device regions 10 and a peripheral region 20 surrounding the device regions 10. The device region 10 is used for setting functional devices.

And, as shown in fig. 1, the semiconductor structure 100 includes a semiconductor base structure 110, a first semiconductor device 120, and at least one conductive pillar 130.

The semiconductor base structure 110 may be a composite layer of one or more stacks of materials that provide support for the subsequent fabrication of the conductive pillars 130 and the first semiconductor device 120 and space for fabrication of the connected structure. The structure of the semiconductor base structure 110 may be set according to practical requirements, and is not limited herein. The semiconductor substrate structure 110 may be made of one or more of glass, quartz, silicon carbide, silicon oxide, and other inorganic materials, or may be made of epoxy or polyurethane.

The first semiconductor device 120 partially penetrates the semiconductor base structure 110, and the first semiconductor device 120 is disposed in the device region 10. Here, the semiconductor base structure is similar to a "concave" structure, and the thickness H1 of the semiconductor base structure 110 in the device region 10 is smaller than the thickness H2 of the semiconductor base structure in the peripheral region 20, and the first semiconductor device 120 penetrates through the portion of the semiconductor base structure 110 in the device region 10, so as to implement that the first semiconductor device 120 is embedded in the semiconductor base structure 110, and is in stable contact with and electrically connected to the conductive pillar 130.

By way of example, the first semiconductor device 120 includes one or more of sensors, transformers, integrated circuits, and capacitors.

With continued reference to fig. 1, at least one conductive pillar 130 extends partially through the semiconductor base structure 110. The conductive post 130 has a first end face 131 and a second end face 132 disposed opposite along the extending direction M of the conductive post 130. The first end face 131 is substantially flush with the surface of the semiconductor base structure 110 remote from the first semiconductor device 120, and the second end face 132 is in contact and electrically connected with the first semiconductor device 120.

It will be appreciated that the case where the second end surface 132 of the at least one conductive pillar 130 contacts and is electrically connected to the first semiconductor device 120 includes, in a case where the first end surface 131 of the conductive pillar 130 is substantially flush with a surface of the semiconductor base structure 110 remote from the first semiconductor device 120, the second end surface 132 of the conductive pillar 130 may be substantially flush with another side surface of the portion of the semiconductor base structure 110 located in the device region 10 (i.e., a bottom surface of a recess of another side surface of the semiconductor base structure 110), and the second end surface 132 may also be spaced apart from another side surface of the portion of the semiconductor base structure 110 located in the device region 10 (i.e., the second end surface 132 protrudes from a bottom surface of a recess of another side surface of the semiconductor base structure 110), so as to ensure good contact between the second end surface 132 of the conductive pillar 130 and the first semiconductor device 120.

Illustratively, the conductive pillars 130 comprise copper.

At least one conductive pillar 130 in the semiconductor structure 100 partially penetrates the semiconductor base structure 110; and, the first semiconductor device 120 partially penetrates the semiconductor base structure 110 and is in contact and electrically connected with the at least one conductive pillar 130. In this way, the conductive pillars 130 and the first semiconductor device 120 are arranged along the extending direction M of the conductive pillars 130 (i.e., the thickness direction of the semiconductor base structure 110), that is, the sum of the height (approximately H1 in fig. 1) of the conductive pillars 130 and the thickness H3 of the first semiconductor device 120 is approximately equal to the thickness H2 of the semiconductor base structure 110. The first semiconductor device 120 is embedded in the semiconductor substrate structure 110, so as to achieve stable contact and electrical connection with the conductive pillars 120, thereby achieving a good electrical connection effect.

In some examples, as shown in fig. 1, the plurality of conductive posts 130 includes multiple groups, with the heights of one group of conductive posts 130 being the same. The heights of the different sets of conductive pillars 130 are the same or different.

As illustrated in fig. 1, the plurality of conductive pillars 130 includes two groups, one group of conductive pillars 130 includes three conductive pillars 130, and the conductive pillars 130 in the group have the same height. Since the semiconductor devices to be electrically connected to the different groups of conductive pillars 130 may be different, the thicknesses of the different semiconductor devices may also be different, and the height of each group of conductive pillars 130 may be set according to the actual situation, so that the semiconductor devices partially penetrate through the semiconductor base structure 110 and are in close contact with the conductive pillars 130, thereby ensuring good electrical connection effect between the semiconductor devices and the conductive pillars 130.

Further, referring to fig. 1, the semiconductor structure 100 further includes at least one insulating layer 160, and one of the at least one insulating layer 160 wraps around a sidewall of the conductive pillar 130. The insulating layer 160 is used for insulating the conductive pillars 130 from the semiconductor base structure 110, so as to ensure good conductive effect of the conductive pillars 130.

In some examples, semiconductor structure 100 includes one semiconductor device at one of opposite ends of conductive pillar 130. It will be appreciated that, since the semiconductor structure 100 needs to be thermally dissipated or electrically connected to other signal lines after being fabricated, even if the semiconductor structure 100 includes one semiconductor device, both end surfaces of the conductive pillars 130 inside thereof along the extending direction M (see fig. 1) need to be exposed, and thus the insulating layer 160 is disposed only on the sidewalls of the conductive pillars 130. One end of the conductive pillar 130 is electrically connected to the first semiconductor device 120, and the connection structure of the other end is not limited in this example.

As shown in fig. 1 to 3, the semiconductor base structure 110 includes a first base 111; alternatively, the semiconductor base structure 110 includes a first base 111 and a semiconductor layer 112 stacked along the extending direction M of the conductive pillars 130.

The semiconductor layer 112 may be made of one or more of inorganic materials such as glass, quartz, silicon carbide, silicon oxide, and polysilicon, organic materials such as epoxy or polyurethane, and composite layers of multiple stacked film layers for realizing the resonator function.

Illustratively, as shown in fig. 1, the semiconductor base structure 110 includes a first base 111, the first base 111 including a portion located in the device region 10 and a portion located in the peripheral region 20. The conductive pillars 130 partially penetrate the first substrate 111, that is, a portion of the first substrate 111 located in the peripheral region 20 has a thickness H2 greater than a thickness H1 of a portion thereof located in the device region 10. The conductive pillar 130 is located in the device region 10 and penetrates through a portion of the first substrate 111 located in the device region 10. In this way, the height of the conductive pillars 130 is equal to the thickness H1 of the portion of the first substrate 111 located in the device region 10. Also, the difference between the thickness H1 of the portion of the first substrate 111 located in the device region 10 and the thickness H2 of the portion thereof located in the peripheral region 20 is greater than or equal to the thickness H3 of the first semiconductor device 120.

For example, with continued reference to fig. 1, a surface of the first substrate 111 is substantially flush with the first end surface 131 of the conductive pillar 130, and a distance between a surface of the other side of the first substrate 111 and the second end surface 132 of the conductive pillar 130 is greater than or equal to the thickness H3 of the first semiconductor device 120, and after the conductive pillar 130 is formed on the surface of the one side of the first substrate 111, a similar continuously extending "concave-convex" shape is formed on the surface of the opposite side of the surface, and the first semiconductor device 120 is disposed in the concave region. Thus, the first semiconductor device 120 is stably located in the first substrate 111 and stably connected to the conductive pillars 130 without adding an additional semiconductor material layer on the first substrate 111 and without performing secondary processing on the structure of the conductive pillars 130.

Also illustratively, as shown in fig. 2 and 3, the semiconductor base structure 110 includes a first base 111 and a semiconductor layer 112 stacked along the extension direction M of the conductive pillars 130.

The first substrate 111 includes a portion located in the device region 10 and a portion located in the peripheral region 20. The semiconductor layer 112 includes a first semiconductor layer 1121 or a second semiconductor layer 1122.

As illustrated in fig. 2, the semiconductor base structure 110 includes a first base 111 and a first semiconductor layer 1121 stacked along the extending direction M of the conductive pillars 130.

At one side surface of the first substrate 111 is substantially flush with one end surface of the conductive post 130, and the conductive post 130 penetrates the first substrate 111. Here, one side surface of the first substrate 111 is substantially flush with the first end surface 131 of the conductive pillar 130, and the other side surface of the first substrate 111 is substantially flush with the second end surface 132 of the conductive pillar 130, that is, the thickness H1 of the portion of the first substrate 111 located in the device region 10 is equal to the thickness H2 of the portion thereof located in the peripheral region 20. In this way, the first semiconductor layer 1121 provided on one side of the first substrate 111, the first semiconductor device 120 penetrates the first semiconductor layer 1121, that is, the surface of the first semiconductor device 120 in contact with the conductive pillar 130 is the same surface as the surface of the first semiconductor layer 1121 in contact with the conductive pillar 130.

Alternatively, as shown in fig. 3, the semiconductor base structure 110 includes a first base 111 and a second semiconductor layer 1122 stacked along the extending direction M of the conductive pillars 130.

The first substrate 111 has a side surface substantially flush with one end surface of the conductive pillar 130, and a distance between the other side surface of the first substrate 111 and the other end surface of the conductive pillar 130 (i.e., a difference between H2 and H1) is smaller than the thickness H3 of the first semiconductor device 120. Here, one side surface of the first substrate 111 is substantially flush with the first end surface 131 of the conductive pillar 130, and a distance between the other side surface of the first substrate 111 and the second end surface 132 of the conductive pillar 130 (i.e., a difference between H2 and H1) is smaller than a thickness H3 of the first semiconductor device 120, i.e., the other side surface of the portion of the first substrate 111 located in the peripheral region 20 is farther from the second end surface 132 of the conductive pillar 130 than the other side surface of the portion of the first substrate 111 located in the device region 10. Thus, the conductive pillars 130 extend through the portion of the first substrate 111 that is located in the device region 10. The first semiconductor device 120 penetrates the second semiconductor layer 1122 and partially penetrates the first substrate 111.

The first semiconductor layer 1121 and the second semiconductor layer 1122 are determined to be disposed on the first end surface 131 or the second end surface 132 of the conductive pillar 130 according to the relationship between the distance between the second end surface 132 of the conductive pillar 130 and the side surface of the first substrate 111 that is closer to the second end surface 132 (i.e., the difference between H2 and H1) and the thickness of the semiconductor device, and the first semiconductor structure 120 is disposed in the structure of the first end surface 131 or the second end surface 132 of the conductive pillar 130. The materials and the structure types (e.g., thickness, number of stacked layers, etc.) of the first semiconductor layer 1121 and the second semiconductor layer 1122 are not limited. For example, the thickness H3 of the first semiconductor layer 1121 is set in a case where the second end face 132 of the conductive pillar is substantially flush with one side surface of the first substrate 111. The second semiconductor layer 1122 is provided in a case where a distance between the second end surface 132 of the conductive pillar and one side surface of the first substrate 111 is greater than 0mm and less than a thickness of the semiconductor device so that the semiconductor device can be embedded in the semiconductor base structure 110.

In other examples, semiconductor structure 100 includes two semiconductor devices located at opposite ends of conductive pillar 130. For example, as shown in fig. 4 to 6, the first semiconductor device 120 and the second semiconductor device 140 are located at opposite ends of the conductive pillar 130. The conductive pillars 130 electrically connect the first semiconductor device 120 and the second semiconductor device 140 to achieve signal transmission. Also, the semiconductor structure 100 further includes a third semiconductor layer 150, and the third semiconductor layer 150 provides a disposition space for the second semiconductor device 140.

With continued reference to fig. 4-6, the semiconductor structure 100 includes a semiconductor base structure 110, a first semiconductor device 120, at least one conductive pillar 130, a second semiconductor device 140, and a third semiconductor layer 150.

The second semiconductor device 140 penetrates the third semiconductor layer 150. The third semiconductor layer 150 and the semiconductor base structure 110 are stacked along the extending direction M of the conductive pillar 130. As shown in fig. 4 and 6, the first end face 131 of the conductive pillar 130 is in contact with and electrically connected to the second semiconductor device 140, and the second end face 132 of the conductive pillar 130 is in contact with and electrically connected to the first semiconductor device 120. Alternatively, as shown in fig. 5, the first end face 131 of the conductive post 130 is in contact with and electrically connected to the first semiconductor device 120, and the second end face 132 of the conductive post 130 is in contact with and electrically connected to the second semiconductor device 140.

Based on this, as shown in fig. 4 to 6, the surface of the first semiconductor device 120 away from the conductive pillar 130 is substantially flush with the surface of the semiconductor base structure 110 away from the conductive pillar 130; and/or the surface of the second semiconductor device 140 remote from the conductive pillar 130 is substantially flush with the surface of the third semiconductor layer 150 remote from the conductive pillar 130.

For example, as shown in fig. 4, the surface of the first semiconductor device 120 remote from the conductive pillars 130 is substantially flush with the surface of the semiconductor base structure 110 remote from the conductive pillars 130.

For example, referring to fig. 4, the semiconductor substrate structure 110 includes a first substrate 111, a surface of the first semiconductor device 120 away from the conductive pillar 130 is substantially flush with a surface of the first substrate 111 away from the conductive pillar 130, and the conductive pillar 130 partially penetrates the first substrate 111. The first semiconductor device 120 is in contact with and electrically connected to the second end face 132 of the conductive post 130. And, the third semiconductor layer 150 is disposed at a side of the first substrate 111 remote from the first semiconductor device 120. The second semiconductor device 140 is in contact with and electrically connected to the first end surface 131 of the conductive pillar 130 through the third semiconductor layer 160.

Alternatively, as shown in fig. 5, the semiconductor base structure 110 includes a first base 111 and a first semiconductor layer 1121. The surface of the first semiconductor device 120 away from the conductive pillar 130 is substantially flush with the surface of the first semiconductor layer 1121 away from the conductive pillar 130, and the conductive pillar 130 penetrates the first substrate 111. The third semiconductor layer 150 is disposed on a side of the first substrate 111 remote from the first semiconductor device 120. The second semiconductor device 140 is in contact with and electrically connected to the second end surface 132 of the conductive pillar 130 through the third semiconductor layer 160.

Alternatively, as shown in fig. 6, the semiconductor base structure 110 includes a first base 111 and a second semiconductor layer 1122. The surface of the first semiconductor device 120 away from the conductive pillar 130 is substantially flush with the surface of the second semiconductor layer 1122 away from the conductive pillar 130, and the conductive pillar 130 partially penetrates the first substrate 111. The first semiconductor device 120 is in contact with and electrically connected to the second end face 132 of the conductive post 130. And, the third semiconductor layer 150 is disposed at a side of the first substrate 111 remote from the first semiconductor device 120. The second semiconductor device 140 is in contact with and electrically connected to the first end surface 131 of the conductive pillar 130 through the third semiconductor layer 150.

In this way, the first semiconductor device 120 is surrounded by the first semiconductor layer 1121 or the second semiconductor layer 1122, which provides good support in the subsequent process of forming an encapsulation layer on the side of the first semiconductor layer 1121 or the second semiconductor layer 1122 away from the conductive pillar 130, which is beneficial for protecting the first semiconductor device 120.

As shown in fig. 4 to 6, the surface of the second semiconductor device 140 away from the conductive pillar 130 is substantially flush with the surface of the third semiconductor layer 150 away from the conductive pillar 130.

In this way, the second semiconductor device 140 is surrounded by the third semiconductor layer 150, and a good supporting effect is provided in a subsequent process of forming an encapsulation layer on a side of the third semiconductor layer 150 away from the conductive pillar 130, which is beneficial for protecting the second semiconductor device 150.

As shown in fig. 4 to 6, the surface of the first semiconductor device 120 away from the conductive pillar 130 is substantially flush with the surface of the semiconductor base structure 110 away from the conductive pillar 130, and the surface of the second semiconductor device 140 away from the conductive pillar 130 is substantially flush with the surface of the third semiconductor layer 150 away from the conductive pillar 130. The above-mentioned examples are advantageous for protecting the first semiconductor device 120 and the second semiconductor device 140, and will not be described herein.

As shown in fig. 8 to 14, the present application further provides a method for manufacturing the semiconductor structure 100. The manufacturing method comprises S100-S700.

S100: as shown in fig. 8 to 10, fig. 11 (a), fig. 12 (a), fig. 13 (a), and fig. 14 (a), a first substrate 210 is provided. It will be appreciated that in connection with the semiconductor base structure 110 provided in the above embodiments, the first substrate 210 referred to in this example is an untreated base. For example, the first substrate 210 is an untreated first base 111.

S200: as shown in fig. 8 to 10, 11 (b), 12 (b), 13 (b), and 14 (b), at least one groove 211 is formed on the surface of the first substrate 210. Illustratively, the first substrate 210 includes a first surface 212 and a second surface 213, the first surface 212 forming a recess 211.

Illustratively, an etching process is used to form at least one recess 211 on the first substrate 210. The depth of the at least one groove 211 may be the same or different. Then, an insulating material is deposited in the at least one recess 211 to form an insulating layer (not shown).

S300: as shown in fig. 8 to 10, 11 (c), 12 (c), 13 (c), and 14 (c), at least one groove 211 is filled with a conductive material to form a plurality of conductive pillars 130.

For example, after the at least one recess 211 is filled with a conductive material by a deposition process to form a plurality of conductive pillars 130, a chemical mechanical polishing (Chemical Mechanical Polishing, abbreviated as CMP) process is used to process the end surfaces of the conductive pillars 130, so as to obtain relatively flat end surfaces, which is beneficial to improving the electrical connection effect between the subsequent conductive pillars 130 and the semiconductor device.

In some examples, the plurality of conductive pillars 130 includes multiple sets, with the heights of one set of conductive pillars 130 being the same. The heights of the different sets of conductive posts 130 are the same or different. The height of the conductive pillars 130 depends on the depth of the grooves 211.

Note that the first substrate 210 includes a first surface 212 and a second surface 213, and the first surface 212 forms a groove 211. As shown in (d) of fig. 12, before the second surface 213 forms the first cavity 220, and after the plurality of conductive pillars 130 are formed, the manufacturing method further includes S310: the support layer 230 is bonded to the first surface 212.

With continued reference to fig. 12 (d), it is understood that a bonding layer 240 is further disposed between the first surface 212 and the supporting layer 230, and the bonding layer 240 can ensure good adhesion between the first substrate 210 and the supporting layer 230, and the bonding layer 240 protects the structure and the material properties of the first surface 212 of the first substrate 210 from being damaged during the removal of the supporting layer 230.

S400: as shown in fig. 9 and 10, a first cavity 220 is formed in a structure where at least one of opposite ends of the conductive post 130 is located along an extending direction of the conductive post 130, the first cavity 220 exposing an end surface of the conductive post 130.

For example, since the heights of the different sets of conductive pillars 130 are the same or different, the first cavity 220 includes a plurality of first cavities 220 having the same or different depths, and the bottom of one first cavity 220 is substantially flush with the end surface of the set of conductive pillars 130 adjacent to the first cavity 220. It is understood that the depth of the first cavity 220 is related to the thickness of the semiconductor device.

In some examples, S400 forming the first cavity 220 in the structure where at least one of the opposite ends of the conductive post 130 is located includes S410 and/or S420. It is understood that in the case where the semiconductor structure 100 includes S410 and S420, the order of S410 and S420 is not limited.

S410: as shown in fig. 9, 11 (d) and 14 (d), a first semiconductor layer 1121 is formed on a surface of the first substrate 210 where the recess 211 is opened, and a first cavity 220 is formed on the first semiconductor layer 1121. At this time, the processed first substrate 210 is the first base 111 in the case where the semiconductor base structure 100 mentioned in the above example (see fig. 2) includes the first base 111 and the first semiconductor layer 1121.

For example, S410 further includes S411, S412, and S413.

S411: as shown in (d) of fig. 11 and (d) of fig. 14, after the conductive pillars 130 are formed in the grooves 211, a first semiconductor layer 1121 is formed on the first surface 212.

S412: as shown in fig. 11 (e) and 14 (e), a side of the first substrate 210 remote from the first surface 212 is thinned to expose an end face of the conductive post 130 near the second surface 213 of the first substrate 210.

For example, by using the etching process twice, the side of the first substrate 210 away from the first surface 212 is thinned to expose one end of the conductive pillar 130, and then the insulating material on the end surface of the conductive pillar 130 may be removed to expose the conductive pillar 130, so as to facilitate the electrical connection between the subsequent semiconductor device and the conductive pillar 130. For example, a CMP process is used to remove the insulating material from the end surfaces of the conductive pillars 130.

S413: as shown in (f) of fig. 11 and (f) of fig. 14, a first cavity 220 is formed at a side surface of the first semiconductor layer 1211 remote from the first substrate 210.

S420: as shown in fig. 10 and 12 (b) to 12 (g), a distance between a surface of the first substrate 210, which is far from the surface of the recess 211, and a plane of the recess 211 bottom is greater than or equal to a thickness of the semiconductor device, and a first cavity 220 is formed in a surface of the first substrate 210, which is far from the surface of the recess 211.

At this time, the processed first substrate 210 is the first base 111 in the case where the semiconductor base structure 100 mentioned in the above example (see fig. 1) includes only the first base 111.

As illustrated in fig. 12 (b), the first substrate 210 includes a first surface 212 and a second surface 213, the first surface 212 forming a groove 211. As shown in (c) of fig. 12, in the case where the interval between the second surface 213 and the plane in which the bottom of the groove 211 is located is greater than or equal to the thickness of the semiconductor device, the first cavity 220 is formed at the second surface (see (e) of fig. 12).

Alternatively, the distance between the surface of the first substrate 210 away from the surface of the opening of the recess 211 and the plane of the bottom of the recess 211 is smaller than the thickness of the semiconductor device, and the second semiconductor layer 1122 is formed on the surface of the first substrate 210 away from the surface of the opening of the recess 211, so that the first cavity 220 (not shown) penetrating the second semiconductor layer 1122 and extending to the end face of the conductive post 130 is formed.

At this time, the processed first substrate 210 is the first base 111 in the case where the semiconductor base structure 100 mentioned in the above example (see fig. 3) includes the first base 111 and the second semiconductor layer 1122.

Illustratively, the first substrate 210 includes a first surface 212 and a second surface 213, the first surface 212 forming a recess 211. In the case where the distance between the second surface 213 and the plane of the bottom of the recess 211 is smaller than the thickness of the semiconductor device, a second semiconductor layer 1122 is formed on the second surface 213, and a first cavity 220 is formed in the second semiconductor layer 1122. The first cavity 220 penetrates the second semiconductor layer 1122 and extends to an end surface of the conductive pillar 130. I.e., the bottom of the first cavity 220, is located closer to the conductive post 130 than the second surface 213.

The first semiconductor layer 1121 and the second semiconductor layer 1122 are layer structures for distinguishing semiconductor materials of different thicknesses based on the relationship between the size of the space between the second end face 132 of the conductive pillar 130 and the side surface of the first substrate 111 closer thereto and the thickness of the semiconductor device, and the materials and the structure types of the first semiconductor layer 1121 and the second semiconductor layer 1122 are not limited. For example, the thickness H3 of the first semiconductor layer 1121 is set in a case where the second end face 132 of the conductive pillar is substantially flush with one side surface of the first substrate 111. The second semiconductor layer 1122 is provided in a case where a distance between the second end surface 132 of the conductive pillar and one side surface of the first substrate 111 is greater than 0mm and less than a thickness of the semiconductor device so that the semiconductor device can be embedded in the semiconductor base structure 110.

As shown in fig. 12 (e) to fig. 12 (g), after the first cavity 220 is formed on the second surface 213, the manufacturing method further includes S430: the support layer 230 is removed.

S500: as shown in fig. 8, 11 (g), 12 (f) and (g), 13 (f) and (g), and 14 (g), a first semiconductor device 120 is formed in the first cavity 220, and the first semiconductor device 120 is electrically connected to the conductive pillar 130.

In addition, after the first semiconductor device 120 is disposed in the first cavity 220, the first cavity 220 is filled with glue to fix the first semiconductor device 120 on the semiconductor base structure 110. Further, the plurality of semiconductor devices on the semiconductor structure 100 are mounted and then packaged, and applied to an electronic device.

In the method for manufacturing a semiconductor structure according to the above embodiment, after forming at least one recess 211 on one side surface of the first substrate 210 and forming at least one conductive pillar 130 in the at least one recess 211, one end surface of the conductive pillar 130 is substantially flush with one side surface of the first substrate 210. The first cavity 220 is determined by determining the relationship between the plane of the bottom of the groove 211 (i.e., the other end surface of the conductive pillar 130 along the extending direction thereof) and the surface of the first substrate 210 on the side away from the surface of the opening of the groove 211, and the thickness H3 of the first semiconductor device 120, by setting the first cavity 220 on the structure of the other end of the conductive pillar 130 through the subsequent process (forming the first semiconductor layer 1121 or the second semiconductor layer 1122) or setting the first cavity on the surface of the first substrate 210 on the opening of the groove 211 through the subsequent process (forming the first semiconductor layer 1121 or the second semiconductor layer 1122). In this way, the formed conductive pillar 130 can be directly electrically connected with the first semiconductor device 120 formed in the first cavity 220, and the deeper groove and the higher conductive pillar do not need to be made first, and then the conductive pillar with the redundant height is removed in the subsequent process, so that the process steps and the cost of the conductive pillar 130 and the first cavity 220 are reduced, the problem that the end face of the conductive pillar 130 is uneven due to the process condition in the process of removing the conductive pillar 130 with the redundant length is avoided, and the probability of poor electrical connection effect between the conductive pillar 130 and the first semiconductor device 120 is further reduced.

In another example, semiconductor structure 100 includes two semiconductor devices electrically connected by conductive pillars 130. After the electrical connection of one semiconductor device is achieved based on the fabrication method provided in the above example, the fabrication method further includes achieving the electrical connection of a second semiconductor device on the other side of the first substrate 210.

For example, S410 and S420 provided in the above example may also exist in the same manufacturing process of the semiconductor structure 100, and the resulting semiconductor structure is referred to in fig. 4 to 6. The specific manufacturing process can be referred to the above examples, and will not be described herein. It is understood that in the case where the semiconductor structure 100 includes S410 and S420, the order of S410 and S420 is not limited.

For another example, the two semiconductor structures 100 fabricated by S410 are reversely butted so that the second end faces 132 of the conductive pillars 130 in the two semiconductor structures 100 are in contact and electrically connected, and the resulting semiconductor structure is shown in fig. 7. The specific manufacturing process can be seen from (a) in fig. 14 to (h) in fig. 14, and will not be described here again.

As another example, as shown in (h) and (i) in fig. 9 and 13, in the case where the manufacturing method includes S410, S500, S600, and S700 are further included.

The method adopted in S500 is provided in the above example, and will not be described here again.

S600: as shown in (h) of fig. 9 and 13, a third semiconductor layer 150 is formed on the thinned surface of the first substrate 210, and a second cavity 230 is formed on the third semiconductor layer 150. The bottom of the second cavity 230 exposes the conductive post 130 near the end face of the first substrate 210.

The third semiconductor layer 150 may be made of one or more of inorganic materials such as glass, quartz, silicon carbide, silicon oxide, and polysilicon, organic materials such as epoxy or polyurethane, and composite layers of multiple stacked film layers for realizing the resonator function.

It should be noted that, the end surface of the conductive pillar 130 exposed by the second cavity 230 may be obtained after the insulating layer is removed by the CMP process in the process of the above example S412, or the insulating material on the end surface of the conductive pillar 130 may be removed after the second cavity 230 is formed, which may be set according to actual process conditions.

S700: as shown in (i) of fig. 9 and 13, a second semiconductor device 140 is formed in the second cavity 230, and the second semiconductor device 140 is electrically connected to the conductive pillar 130.

The above embodiment performs the arrangement of the third semiconductor layer 150 and the second semiconductor device 140 on the basis of the formed conductive pillars 130, and can achieve good contact and electrical connection effects without removing part of the height of the conductive pillars 130.

It should be noted that, the embodiment of the semiconductor structure provided by the invention and the embodiment of the manufacturing method of the semiconductor structure belong to the same conception; the features of the embodiments described in the present invention may be combined arbitrarily without any conflict. However, it should be further described that, in the semiconductor structure provided by the embodiment of the present invention, each technical feature combination of the semiconductor structure may solve the technical problem to be solved by the present invention; therefore, the method for manufacturing the semiconductor structure provided by the embodiment of the invention is not limited by the semiconductor structure provided by the embodiment of the invention, and any semiconductor structure manufactured by the method for manufacturing the semiconductor structure provided by the embodiment of the invention is within the protection scope of the invention.

The above description is not intended to limit the scope of the invention, but is intended to cover any modifications, equivalents, and improvements within the spirit and principles of the invention.

Claims (14)

1. A method of fabricating a semiconductor structure, comprising:

providing a first substrate;

forming at least one groove on the surface of the first substrate;

Filling conductive material in the at least one groove to form a plurality of conductive columns;

forming a first cavity in a structure where at least one of opposite ends of the conductive column is located along an extending direction of the conductive column, wherein the first cavity exposes an end face of the conductive column;

a first semiconductor device is formed in the first cavity, the first semiconductor device being electrically connected to the conductive pillar.

2. The method of claim 1, wherein forming a first cavity in the structure at least one of the opposite ends of the conductive post comprises:

and forming a first semiconductor layer on the surface of the groove opening of the first substrate, and forming the first cavity on the first semiconductor layer.

3. The method of claim 1 or 2, wherein forming a first cavity in the structure in which at least one of the opposite ends of the conductive pillar is located comprises:

the distance between the surface of one side of the first substrate far away from the surface of the groove opening and the plane of the bottom of the groove is larger than or equal to the thickness of the semiconductor device, and the first cavity is formed on the surface of one side of the first substrate far away from the surface of the groove opening;

Or, the distance between the surface of the first substrate, which is far away from the surface of the groove opening, and the plane of the bottom of the groove is smaller than the thickness of the semiconductor device, and a second semiconductor layer is formed on the surface of the first substrate, which is far away from the surface of the groove opening, so as to form the first cavity penetrating through the second semiconductor layer and extending to the end face of the conductive column.

4. The method of manufacturing of claim 3, wherein the first substrate comprises a first surface and a second surface, the first surface forming the recess;

bonding a support layer to the first surface prior to forming the first cavity in the second surface;

after the first cavity is formed in the second surface, the support layer is removed.

5. The method of manufacturing of claim 2, wherein the first substrate comprises a first surface and a second surface, the first surface forming the recess;

forming the first semiconductor layer on the first surface after forming the conductive pillars in the grooves;

thinning one side of the first substrate away from the first surface to expose an end surface of the conductive post near the second surface of the first substrate;

The first cavity is formed on the surface of one side of the first semiconductor layer away from the first substrate.

6. The method of manufacturing of claim 5, further comprising:

forming a third semiconductor layer on the thinned surface of the first substrate, and forming a second cavity on the third semiconductor layer; the bottom of the second cavity exposes the end face of the conductive post close to the first surface of the first substrate;

and forming a second semiconductor device in the second cavity, wherein the second semiconductor device is electrically connected with the conductive column.

7. The method of manufacturing of claim 1, wherein the plurality of conductive posts comprises a plurality of groups, a height of one group of the conductive posts being the same; the heights of the conductive posts in different groups are the same or different;

the first cavity comprises a plurality of first cavities, and a plane of the bottom of one first cavity is approximately flush with the end face of the group of conductive posts, which is close to the first cavity.

8. A semiconductor structure, comprising:

a semiconductor base structure;

a first semiconductor device partially penetrating the semiconductor base structure;

at least one conductive pillar partially penetrating the semiconductor base structure and having a first end face and a second end face disposed opposite to each other along an extending direction of the conductive pillar; the first end face is substantially flush with a surface of the semiconductor base structure remote from the first semiconductor device, and the second end face is in contact with and electrically connected to the first semiconductor device.

9. The semiconductor structure of claim 8, wherein the semiconductor base structure comprises a first base;

or,

the semiconductor substrate structure comprises a first substrate and a semiconductor layer which are stacked along the extending direction of the conductive column.

10. The semiconductor structure of claim 9, wherein the semiconductor base structure comprises the first base and a first semiconductor layer stacked along a direction in which the conductive pillars extend, the conductive pillars extending through the first base, the first semiconductor device extending through the first semiconductor layer;

or,

the semiconductor substrate structure comprises a first substrate and a second semiconductor layer which are stacked along the extending direction of the conductive column; the conductive pillars penetrate through the first substrate, and the first semiconductor device penetrates through the second semiconductor layer and partially penetrates through the first substrate.

11. The semiconductor structure of claim 8, further comprising a second semiconductor device and a third semiconductor layer; the second semiconductor device penetrates through the third semiconductor layer; the third semiconductor layer and the semiconductor substrate structure are stacked along the extending direction of the conductive column; the second end face of the conductive post is in contact with and electrically connected to the second semiconductor device.

12. The semiconductor structure of claim 11, wherein a surface of the first semiconductor device remote from the conductive pillar is substantially flush with a surface of the semiconductor base structure remote from the conductive pillar;

and/or the number of the groups of groups,

a surface of the second semiconductor device remote from the conductive pillar is substantially flush with a surface of the third semiconductor layer remote from the conductive pillar.

13. The semiconductor structure of claim 8, wherein a plurality of said conductive pillars comprises a plurality of groups, a height of a group of said conductive pillars being the same; the heights of the conductive posts of different groups are the same or different.

14. The semiconductor structure of claim 8, further comprising at least one insulating layer, one of the at least one insulating layer encasing a sidewall of one of the conductive pillars.