CN117219569A

CN117219569A - Wafer, chip and electronic equipment

Info

Publication number: CN117219569A
Application number: CN202311477440.1A
Authority: CN
Inventors: 王利颖; 郭健强
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2023-11-08
Filing date: 2023-11-08
Publication date: 2023-12-12
Anticipated expiration: 2043-11-08
Also published as: CN117219569B

Abstract

The application discloses a wafer, a chip and electronic equipment, relates to the technical field of semiconductor devices, and is used for solving the problem that cracks formed at a wafer cutting position are easy to extend to a structure of the chip. The wafer comprises a substrate, a dielectric layer, a plurality of isolation trenches and an isolation medium. The dielectric layer is arranged on one side of the substrate and comprises a plurality of circuit areas which are arranged at intervals. And a cutting channel is formed between two adjacent circuit areas. A plurality of isolation trenches are located at the periphery of the plurality of circuit regions, and the isolation trenches penetrate through the dielectric layer and extend into a portion of the substrate. The isolation medium is filled in the isolation groove. The wafer is used for manufacturing chips. When the wafer is cut, the same isolation medium is filled in the isolation groove, so that layering cannot occur, layering or cracks can be stopped at the isolation groove, and the wafer cannot extend to the structure of the chip continuously.

Description

Wafer, chip and electronic equipment

Technical Field

The present disclosure relates to semiconductor devices, and particularly to a wafer, a chip, and an electronic device.

Background

Chips are an important device in electronic equipment. In the chip manufacturing process, a wafer cutting method can be adopted for manufacturing. Specifically, a plurality of chips are generally arranged on the wafer at intervals, and the chips are separated from the wafer by dicing.

However, when dicing a wafer, cracks are easily formed at the dicing site, and the cracks propagate to functional areas of the chip, which may cause failure of the chip.

Disclosure of Invention

The embodiment of the application provides a wafer, a chip and electronic equipment, which are used for solving the problem that cracks formed at a wafer cutting position are easy to extend to a structural position of the chip.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:

in a first aspect, an embodiment of the present application provides a wafer, including a substrate, a dielectric layer, a plurality of isolation trenches, and an isolation medium. The dielectric layer is arranged on one side of the substrate and comprises a plurality of circuit areas which are arranged at intervals. And a cutting channel is formed between two adjacent circuit areas. A plurality of isolation trenches are located at the periphery of the plurality of circuit regions, and the isolation trenches penetrate through the dielectric layer and extend into a portion of the substrate. The isolation medium is filled in the isolation groove.

The wafer and the substrate provided by the embodiment of the application can play a role of supporting the dielectric layer. The dielectric layer is arranged on one side of the substrate and comprises a plurality of circuit areas which are arranged at intervals, and in the process of manufacturing the chip, the circuit areas in the dielectric layer and the corresponding substrate part form the basic structure of the chip by cutting along the cutting path. Because the periphery of a plurality of circuit areas is provided with the isolation groove, the isolation groove penetrates through the dielectric layer and stretches into a part of the substrate. Therefore, when the wafer is cut, the same isolation medium is filled in the isolation groove, layering cannot be generated, the layering or cracking can be stopped at the isolation groove, and the layering or cracking cannot continue to extend to the structure of the chip.

In a possible implementation manner of the first aspect, a sealing area is further formed on the periphery of the circuit area, and the sealing area is disposed around the circuit area in a circle. The isolation groove may be located inside the sealing region. Thus, the delamination crack may pass through the sealing region and then through the isolation groove. At this time, the isolation groove is far away from the cutting position, and the stress is weakened when the layering crack is transferred to the isolation groove, and the isolation medium in the isolation groove can play better isolation effect.

In a possible implementation manner of the first aspect, a sealing area is further formed on the periphery of the circuit area, and the sealing area is disposed around the circuit area in a circle. The isolation groove may be located outside the sealing region. At this time, the isolation medium in the isolation groove can isolate the layering crack at the outside of the sealing area, so that the sealing area positioned at one side of the isolation groove is not easy to crack, and the layering crack in the circuit area at the inner side of the sealing area is avoided.

In a possible implementation manner of the first aspect, the portion of the isolation trench located in the dielectric layer may be opened at a cutting position of the dicing street, and the isolation medium completely fills the portion of the isolation trench located in the dielectric layer. Therefore, when cutting is carried out, the isolation medium in the isolation groove is cut, and as the isolation medium is made of the same material, no interface layering exists, layering cracks can not be generated when cutting is carried out, and therefore the fact that layering cracks can not be generated in a circuit area is guaranteed.

In a possible implementation manner of the first aspect, at least part of the isolation trench is provided with a wafer test structure in a portion of the substrate. In this way, the quality of the wafer may be tested by the wafer test structures within the substrate while dicing the wafer. Meanwhile, the part of the wafer test structure in the isolation groove located in the substrate can transfer the generated cracks to the substrate, but the substrate is generally made of the same material directly and can play a role in blocking the cracks to a certain extent.

In a possible implementation manner of the first aspect, the wafer further includes a plurality of trench isolation structures. The trench isolation structure is positioned in the substrate and penetrates through the surface of one side of the substrate, which is close to the dielectric layer, and the trench isolation structure is positioned between the wafer test structure and the circuit area. Thus, when the wafer test structure in the isolation groove is cut, if the material of the substrate cannot prevent cracks, the cracks can be blocked by the groove isolation structure when extending to the groove isolation structure, and the cracks are prevented from extending to the position, opposite to the circuit area, in the substrate, and the functional area in the substrate is prevented from being damaged.

In a possible implementation manner of the first aspect, the isolation groove may be disposed around a periphery of the line area. Thus, when the wafer is cut, the isolation groove can separate cracks at all positions on the periphery of the circuit area, and the cracks are prevented from expanding to the circuit area.

In a possible implementation manner of the first aspect, at least part of the dicing streets have wafer testing structures therein. The isolation groove is arranged between the wafer test structure and the circuit area. Because the dicing street has the wafer test structure and is easier to generate layering cracks when dicing, the dicing street has no wafer test structure and is not easy to generate cracks or has lighter crack degree when dicing. Therefore, the isolation groove can be only arranged at the position of the dicing channel with one side of the wafer testing structure, and the layered crack generated by the wafer testing structure is prevented from being transmitted to the circuit area.

In a possible implementation manner of the first aspect, the isolation trench is formed with a trench bottom and a trench wall in the substrate and the dielectric layer. The isolation medium may be disposed on the groove bottom and on the groove wall on the side of the isolation groove relatively close to the line area. Alternatively, the isolation medium may be provided on the bottom of the isolation groove and on all the groove walls. Based on the two schemes, the isolation medium is only arranged at the bottom of the isolation groove and on the groove wall, but not completely fills the inside of the isolation groove, so that the isolation effect can be achieved while the material loss of the isolation medium is saved.

In a possible implementation manner of the first aspect, the isolation medium completely fills the isolation trench. Because the isolation medium is completely filled in the isolation groove, the thickness of the isolation medium is thicker, and a better isolation effect can be achieved.

In a possible implementation manner of the first aspect, a plurality of isolation grooves are arranged between the cutting positions of the cutting tracks and the line area at intervals. At this time, the isolation medium in the plurality of isolation grooves may separate the delamination cracks, respectively.

In a possible implementation manner of the first aspect, the isolation trench is formed with a trench bottom and a portion of a trench wall in the substrate; the section of the part of the isolation groove in the substrate is in a non-right-angle trapezoid shape; the bottom of the isolation groove is the bottom edge of the trapezoid. The section is perpendicular to the cutting direction of the cutting path. The material of the dielectric layer is filled in the part of the isolation groove in the substrate, and the isolation medium is filled in the part of the isolation groove in the dielectric layer. The cross section of the isolation groove in the substrate is trapezoid with the bottom of the groove as the bottom edge, so that materials of the dielectric layer can directly fall to the bottom of the isolation groove, the materials of the dielectric layer are prevented from being accumulated on the wall of the isolation groove, the filling is more convenient, and the filling effect is better.

In a possible implementation manner of the first aspect, the isolation medium may be one of copper, PI, and PBO.

In a possible implementation manner of the first aspect, the isolation medium is PI, and the isolation medium further covers a surface of the dielectric layer on a side away from the substrate. At this time, the edge position of PI parcel chip can realize the point of chip and glue, and lifting plate level stress promotes the board level point of chip and glues the scheme, strengthens the reliability of solder joint.

In a second aspect, embodiments of the present application provide a chip, which is formed by dicing any of the wafers described above.

In a third aspect, an embodiment of the present application provides an electronic device, including the above chip.

In a fourth aspect, an embodiment of the present application provides a method for manufacturing a wafer, including: a substrate is fabricated and a portion of the isolation trench is formed on the substrate. And manufacturing a dielectric layer and manufacturing another part forming the isolation groove on the dielectric layer. And filling an isolation medium in the isolation groove.

In a possible implementation manner of the fourth aspect, fabricating a substrate and fabricating a portion of forming the isolation trench on the substrate includes the steps of: and manufacturing a substrate, and forming a part of the isolation groove on the surface of one side of the substrate by adopting a dry etching groove.

In a possible implementation manner of the fourth aspect, fabricating a substrate and fabricating a portion of forming the isolation trench on the substrate includes the steps of: and manufacturing a substrate, and photoetching a part of the isolation groove on the substrate by utilizing negative photoresist. And deepening the part of the isolation groove in the substrate by adopting isotropic wet etching. Annealing is performed for stress relief and defect compensation.

In a possible implementation manner of the fourth aspect, fabricating a substrate and fabricating a portion of forming the isolation trench on the substrate includes the steps of: and manufacturing a substrate, etching an isolation groove on the substrate by a dry method, and then eliminating defects by high-temperature annealing. Or manufacturing a substrate, forming a porous structure on the substrate by anodic oxidation, and then forming the isolation groove by high-temperature annealing.

The technical effects brought by the design manners of the second aspect, the third aspect and the fourth aspect can be referred to the technical effects brought by the different design manners of the first aspect, and are not repeated here.

Drawings

FIG. 1 is a schematic diagram of a wafer according to the related art;

FIG. 2 is a schematic diagram of another wafer according to the related art;

FIG. 3 is a schematic diagram of a wafer according to an embodiment of the present application;

FIG. 4 is a schematic diagram of another wafer according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another wafer according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another wafer according to an embodiment of the present application;

FIG. 7 is a schematic diagram of another wafer according to an embodiment of the present application;

FIG. 8 is a schematic diagram of another wafer according to an embodiment of the present application;

fig. 9 is a schematic plan view of a wafer after dicing according to an embodiment of the present application;

FIG. 10 is a schematic plan view of another wafer after dicing according to an embodiment of the present application;

FIG. 11 is a schematic view of a planar structure of another wafer after dicing according to an embodiment of the present application;

FIG. 12 is a schematic view of a planar structure of another wafer after dicing according to an embodiment of the present application;

FIG. 13 is a schematic diagram of an isolation medium filled in an isolation trench according to an embodiment of the present application;

FIG. 14 is a schematic diagram of another embodiment of an isolation medium filled in an isolation trench;

FIG. 15 is a schematic diagram of another embodiment of an isolation medium filled in an isolation trench;

FIG. 16 is a schematic diagram of a wafer fabrication process with copper as the isolation medium;

FIG. 17 is a schematic diagram of a wafer manufacturing process when PI is used as an isolation medium;

FIG. 18 is a schematic diagram of another process flow of a wafer when PI is used as an isolation medium;

FIG. 19 is a schematic view of a process flow of the wafer shown in FIG. 5;

fig. 20 is a schematic diagram of a wafer manufacturing process when PI is used as an isolation medium.

Reference numerals:

010-wafer; 011-chip; 012-test structure;

100-wafer; 10-a substrate; 101-functional region; 102-a wafer test structure; 103-trench isolation structures; 20-a dielectric layer; 201-line area; 202-a conductive structure; 203-sealing region; 30-isolating grooves; 40-isolating medium; 50-passivation layer.

Detailed Description

In embodiments of the present application, the terms "exemplary" or "such as" and the like are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the description of embodiments of the application, the term "at least one" means one or more, and "a plurality" means two or more. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

In describing embodiments of the present application, it should be noted that, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" should be construed broadly, and for example, "connected" may be either detachably connected or non-detachably connected; may be directly connected or indirectly connected through an intermediate medium. Wherein, "fixedly connected" means that the relative positional relationship is unchanged after being connected with each other. "rotationally coupled" means coupled to each other and capable of relative rotation after coupling. "slidingly coupled" means coupled to each other and capable of sliding relative to each other after being coupled.

References to directional terms in the embodiments of the present application, such as "inner", "outer", "upper", "lower", "front", "rear", "left", "right", etc., are merely with reference to the directions of the drawings, and thus are used for better, more clear explanation and understanding of the embodiments of the present application, rather than to indicate or imply that the apparatus or components referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the embodiments of the present application.

In the description of embodiments of the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the process of manufacturing chips, dicing the wafer is required to separate the chips on the wafer. In the related art, as shown in fig. 1, fig. 1 is a schematic structural diagram of a wafer 010 in the related art, and scribe lines are formed between adjacent chips 011. In dicing, a plurality of chips 011 are manufactured by dicing along dicing lines k on dicing streets.

However, the wafer 010 has a multilayer structure as a whole, and the wafer 010 is formed layer by layer. Therefore, when dicing the wafer 010, delamination or cracking is likely to occur at the dicing site. For example, cutting thick metal present at the cutting street with physical cutting can cause curling. Or when laser cutting low dielectric constant (LowK) layers, delamination of the LowK layers occurs when the LowK layers are subjected to thermal stress. Such delamination or crack propagation to the functional area of the chip 011 may cause the chip 011 to fail, ultimately affecting the yield and production efficiency of the chip 011.

In order to monitor the quality of the wafer 010, as shown in fig. 2, fig. 2 is a schematic structural diagram of another wafer 010 in the related art, and a test structure 012 is disposed on the scribe line of the wafer 010. When cutting, the cutting is performed along the test structure 012 to obtain relevant parameters. The test structure 012 is more likely to generate delamination cracks when dicing, which affects the quality of the diced chip 011.

In addition, collision is easy to occur during transportation and assembly, and corners of the chip 011 may also form cracks during collision, which may easily cause failure of the chip 011 after extending to functional areas of the chip 011.

Based on the above, the embodiment of the application provides electronic equipment, which comprises a chip. The electronic device includes, but is not limited to, a smart phone, a tablet computer, a workstation device, a large screen device (e.g., a smart screen, a smart television, etc.), a wearable device (e.g., a smart bracelet, a smart watch, etc.), a game console, a virtual reality device, an augmented reality device, a hybrid display device, a vehicle-mounted terminal device, a digital camera, a video camera, a motion camera, a recorder, a monitoring camera, etc.

The chip in the electronic equipment provided by the embodiment of the application can be manufactured by cutting a wafer. Accordingly, a wafer is provided in the embodiment of the present application, as shown in fig. 3, fig. 3 is a schematic structural diagram of a wafer 100 provided in the embodiment of the present application, and the wafer 100 may include a substrate 10, a dielectric layer 20, a plurality of isolation trenches 30, and an isolation medium 40.

The substrate 10 may function as a support for the dielectric layer 20. The material of the substrate 10 may be selected to be suitable according to practical situations. Illustratively, the material of the substrate 10 may be silicon (Si). Alternatively, the material of the substrate 10 may be sapphire (Al ₂ O ₃ ) Or silicon carbide (SiC). In which the functional region 101 may be formed inside the substrate 10, the functional region 101 may be located near a side surface of the substrate 10, and the functional region 101 may have an electronic device (e.g., a transistor, etc.) inside.

With continued reference to fig. 3, dielectric layer 20 is disposed on one side of substrate 10 and includes a plurality of spaced apart line regions 201. A scribe line is formed between two adjacent line areas 201. It can be understood that the circuit region 201 in the dielectric layer 20 refers to a partial region of the dielectric layer 20 that can be used to manufacture a chip after being cut. In the process of manufacturing the chip, dicing is performed along dicing streets, and the wiring region 201 in the dielectric layer 20 and the corresponding portion of the substrate 10 constitute the basic structure of the chip.

As shown in fig. 3, the functional region 101 may be located at a surface of the substrate 10 near the dielectric layer 20, and the functional region 101 and the wiring region 201 are disposed opposite to each other in the thickness direction of the substrate 10. Accordingly, a conductive structure 202 may be formed within the wiring region 201. The conductive structures 202 may be connected to the electronic devices in the functional region 101, functioning as leads, electrically connecting the electronic devices in the functional region 101 to devices external to the chip.

For example, as shown in fig. 3, the dielectric layer 20 may have a multi-layered structure, and the material of the multi-layered structure may be silicon oxide or silicon nitride. Wherein the silicon oxide may be doped with carbon or hydrogen to form a lowk layer. The conductive structure 202 may be disposed in the above-mentioned multilayer structure by etching and punching.

As can be seen from fig. 3, the dielectric layer 20 has a multi-layer structure, and the dielectric layer 20 is fabricated layer by layer during the process of fabricating the wafer 100. Thus, as described above, when dicing (e.g., mechanical dicing or laser dicing) the dicing streets of the dielectric layer 20, delamination or cracks are easily formed after the dielectric layer 20 is subjected to mechanical force and thermal stress, and the propagation to the wiring region 201 of the dielectric layer 20 may cause device failure.

For this reason, as shown in fig. 3, in the wafer 100 provided in the embodiment of the present application, a plurality of isolation trenches 30 are located at the periphery of a plurality of circuit regions 201, penetrate through the dielectric layer 20, and extend into a portion of the substrate 10. Isolation medium 40 fills isolation trenches 30. Thus, when dicing the wafer 100, the isolation trenches 30 are filled with the same type of isolation medium 40, so that no delamination occurs, and the delamination or cracking can be terminated at the isolation trenches 30, and does not continue to the chip structure.

With continued reference to fig. 3, in some embodiments, isolation trenches 30 may be on one side of dicing site m of dicing lanes, where delamination cracks pass to isolation trenches 30, isolated by isolation medium 40 within isolation trenches 30, and do not continue to propagate to the structural locations of the chip.

In some embodiments, as shown in fig. 4, fig. 4 is a schematic structural diagram of another wafer 100 according to an embodiment of the present application, where a portion of the isolation trench 30 located in the dielectric layer 20 may also be opened at a cutting position m of the scribe line. At this time, the isolation medium 40 may completely fill the portion of the isolation trench 30 within the dielectric layer 20. In this way, when dicing is performed, the isolation medium 40 in the isolation trench 30 is diced, and since the isolation medium 40 is made of the same material, there is no interfacial delamination, and no delamination crack is generated when dicing is performed, thereby ensuring that the line area 201 does not generate delamination crack.

Based on the above, when the wafer 100 is diced along the isolation trenches 30, as shown in fig. 4, in some embodiments, at least a portion of the isolation trenches 30 within the portion of the substrate 10 may have wafer test structures 102. In this way, the quality of the wafer 100 may be tested by the wafer test structures 102 within the substrate 10 while dicing the wafer 100. Meanwhile, since the wafer test structure 102 is located in the portion of the isolation groove 30 located in the substrate 10, the generated crack will be transferred to the substrate 10, but since the substrate 10 is generally made of the same material, the wafer test structure can also play a role of blocking the crack to a certain extent.

For example, when the portion of the isolation trench 30 located in the substrate 10 is provided with the wafer test structure 102, the wafer test structure 102 may be directly formed during the process of manufacturing the dielectric layer 20, that is, a portion of the isolation trench 30 is first manufactured on the substrate 10, and then during the process of manufacturing the dielectric layer 20, the material of the wafer test structure 102 may fall into the portion of the isolation trench 30 located in the substrate 10, and the wafer test structure 102 is formed on the portion of the isolation trench 30 located in the substrate 10.

Based on the above, when the isolation trench 30 has the wafer test structure 102 in the portion of the substrate 10, in some embodiments, as shown in fig. 5, fig. 5 is a schematic structural diagram of another wafer 100 according to an embodiment of the present application, where the wafer 100 further includes a plurality of trench isolation structures 103. The trench isolation structure 103 is located in the substrate 10, penetrates through the surface of the substrate 10 near the side of the dielectric layer 20, and is located between the wafer test structure 102 and the circuit region 201.

Thus, if the material of the substrate 10 cannot prevent the crack when cutting the wafer test structure 102 in the isolation trench 30, the crack is blocked by the trench isolation structure 103 when extending to the trench isolation structure 103, so that the crack is prevented from extending to the position opposite to the line region 201 in the substrate 10, and the functional region 101 in the substrate 10 is prevented from being damaged. The trench isolation structure 103 may be filled with the same material, such as silicon dioxide or silicon nitride.

When the isolation trench 30 is not provided with the wafer test structure 102 in the portion of the substrate 10, as shown in fig. 6, fig. 6 is a schematic diagram of another wafer 100 according to an embodiment of the present application, and in some embodiments, the isolation medium 40 may completely fill the entire isolation trench 30. In this way, the portion of the isolation trench 30 extending into the substrate 10 will also cut the isolation medium 40 when cutting, without delamination cracks occurring in the isolation medium 40, so that the functional region 101 in the substrate 10 can be protected.

Alternatively, when the isolation trench 30 is not formed in the portion of the substrate 10 without the wafer test structure 102, in other embodiments, as shown in fig. 7, fig. 7 is a schematic diagram of another wafer 100 according to an embodiment of the present application, where the material of the portion of the isolation trench 30 extending into the substrate 10 may also be the material of the dielectric layer 20. That is, during the process of manufacturing the dielectric layer 20, the manufacturing material of the dielectric layer 20 directly enters the inside of the isolation trench 30 pre-opened on the substrate 10 to be filled. In this case, since the substrate 10 is generally made of the same material as described above, it is possible to block the crack by the substrate 10, and it is difficult to propagate the crack after it reaches the material of the substrate 10. Alternatively, as shown in fig. 7, a trench isolation structure 103 may be disposed on the substrate 10 for isolation.

In some embodiments, as shown in fig. 3, fig. 3 is a schematic structural diagram of another wafer 100 according to an embodiment of the present application, and a plurality of isolation trenches 30 disposed at intervals may be disposed between a cutting position m of a scribe line and a line area 201. At this time, the isolation medium 40 in the plurality of isolation trenches 30 may block the delamination cracks, respectively.

When a plurality of isolation trenches 30 are provided between the cutting position m of the dicing streets and the wiring region 201, as shown in fig. 3, a portion of the isolation trenches 30 within the dielectric layer 20 may be filled with the isolation dielectric 40. The portion of isolation trench 30 within substrate 10 may be filled with the material of dielectric layer 20. At this time, the material of the substrate 10, which is spaced between portions of the plurality of isolation trenches 30 within the substrate 10, may act as a barrier.

Of course, in other embodiments, as shown in fig. 8, a separation groove 30 may be provided between the cutting position m of the dicing street and the wiring region 201 (fig. 7). Wherein isolation medium 40 may completely fill isolation trenches 30. Alternatively, when an isolation trench 30 is disposed between the cutting position of the scribe line and the line region 201, the isolation medium 40 may be filled only in the portion of the isolation trench 30 located in the dielectric layer 20, and the portion of the isolation trench 30 located in the substrate 10 may be filled with the material of the dielectric layer 20. Since there is a space between the cutting position m of the dicing street and the portion of the isolation trench 30 within the substrate 10, isolation can be performed by using the material of the substrate 10 between the cutting position m and the portion of the isolation trench 30 within the substrate 10.

In some embodiments, the height of the portion of the isolation trench 30 located in the substrate 10 may be 2 μm or less in a direction perpendicular to the surface of the substrate 10 near the side of the dielectric layer 20, i.e., in the lamination direction of the substrate 10 and the dielectric layer 20. In general, the thickness of the functional region 101 formed inside the surface of the substrate 10 near the side of the dielectric layer 20 is generally thin. When the height of the portion of the isolation trench 30 located in the substrate 10 is within the above range, it is ensured that the functional region 101 is not affected.

The specific height of the portion of the isolation trench 30 located in the substrate 10 along the direction perpendicular to the surface of the substrate 10 near the dielectric layer 20 can be designed according to practical requirements. Illustratively, the height of the isolation trench 30 in the substrate 10 may be 2 μm, 1.5 μm, 1 μm, or the like in a direction perpendicular to the surface of the substrate 10 near the dielectric layer 20 side. Of course, in other embodiments, the height of the portion of the isolation trench 30 within the substrate 10 may be greater than 2 μm in a direction perpendicular to the surface of the substrate 10 adjacent to the dielectric layer 20.

As shown in fig. 7, the isolation trench 30 has trench walls and trench bottoms formed in the substrate 10 and the dielectric layer 20. The isolation trench 30 forms a trench bottom and a part of a trench wall on the substrate 10, and forms another part of the trench wall in the dielectric layer 20.

In some embodiments, as shown in fig. 7, the cross-section of the portion of isolation trench 30 within substrate 10 may be shaped as a trapezoid other than a right angle, with the bottom of isolation trench 30 being the base of the trapezoid. The section is perpendicular to the cutting direction of the cutting path. Wherein, the material of the dielectric layer 20 may be filled in the portion of the isolation trench 30 located in the substrate 10, and the isolation dielectric 40 is filled in the portion of the isolation trench 30 located in the dielectric layer 20.

It will be appreciated that the trapezoid has two sides parallel to each other, a bottom side and a top side. Wherein the length of the bottom edge is greater than the length of the top edge. That is, as shown in fig. 7, the distance between the two waists of the trapezoid of the cross-sectional shape of the portion of the isolation trench 30 located in the substrate 10 gradually decreases from bottom to top. For example, as shown in fig. 7, the cross-section of the portion of the isolation trench 30 within the substrate 10 may be in the shape of an isosceles trapezoid.

Based on the scheme shown in fig. 7, when the dielectric layer 20 is manufactured, the material of the dielectric layer 20 may fall into the portion of the isolation trench 30 located in the substrate 10, and since the cross-sectional shape of the portion of the isolation trench 30 located in the substrate 10 is a trapezoid with the bottom of the trench as the bottom, the subsequent processing of the material of the dielectric layer 20 is inconvenient. Thus, based on the scheme shown in fig. 7, the portion of the isolation trench 30 within the substrate 10 may be directly filled with the material of the dielectric layer 20 for convenience of fabrication.

Meanwhile, in the process of manufacturing the dielectric layer 20, as shown in fig. 7, since the cross section of the part of the isolation groove 30 in the substrate 10 is trapezoid with the bottom of the groove as the bottom, the material of the dielectric layer 20 can directly drop to the bottom of the isolation groove 30, so that the material of the dielectric layer 20 is prevented from being accumulated on the wall of the isolation groove 30, the filling is more convenient, and the filling effect is also better.

Based on the scheme shown in fig. 7, when a part of the isolation trench 30 is fabricated on the substrate 10, a negative photoresist may be selectively coated on the surface of the substrate, the trapezoid trench shown in fig. 7 is photoetched by using the characteristic of the negative photoresist exposure retention, then the trapezoid trench is deepened by chemical etching of isotropic wet etching, and finally annealing is performed for stress release and defect compensation.

In some embodiments, as shown in fig. 8, fig. 8 is a schematic structural diagram of another wafer 100 according to an embodiment of the present application, a section of a portion of the isolation trench 30 located in the substrate 10 may be an isosceles trapezoid with a bottom of the trench as a top edge. Wherein the section is perpendicular to the cutting direction of the cutting channel.

Thus, as shown in fig. 8, the isolation trench 30 becomes larger gradually in a direction perpendicular to the surface of the substrate 10 on the side closer to the dielectric layer 20 and away from the substrate 10. In this way, the isolation trenches 30 are more conveniently fabricated during the fabrication of the wafer 100. Of course, in other embodiments, the cross-sectional shape of the isolation groove 30 may be rectangular. In this case, the isolation groove 30 is also convenient to manufacture.

Based on the above, in the process of manufacturing the wafer 100, dry etching may be performed on the substrate 10 to manufacture a portion of the isolation trench 30 within the substrate 10, that is, to etch the substrate 10 using plasma. Next, in the process of manufacturing the dielectric layer 20 layer by layer, the portion of the isolation trench 30 in the dielectric layer 20 is formed layer by layer, and finally the manufacturing of the isolation trench 30 is completed.

Meanwhile, based on the scheme shown in fig. 8, since the size of the isolation trench 30 becomes gradually larger, it is convenient to remove the material of the dielectric layer 20 falling into the isolation trench 30 during the process of manufacturing the dielectric layer 20. In this way, when the isolation medium 40 is filled later, it is convenient to fill the isolation medium 40 into the portion of the isolation trench 30 located in the substrate 10, and the effect that the isolation medium 40 completely fills the isolation trench 30 is achieved as shown in fig. 8.

Based on the scheme shown in fig. 8, in some embodiments, the base of the isosceles trapezoid may be 50nm-2 μm in length. At this time, the size of the isolation groove 30 is moderate, and the manufacture is convenient. It will be appreciated that the length of the base of the isosceles trapezoid may be designed according to practical situations. By way of example, the base of an isosceles trapezoid may be 50nm, 100nm, 500nm, 1 μm, 1.5 μm, 2 μm in length.

In addition, as shown in fig. 8, when the height of the portion of the isolation trench 30 located in the substrate 10 is too high, the size of the opening formed on the surface of the dielectric layer 20 by the isolation trench 30 is also large, which occupies a large area of the dielectric layer 20, thereby reducing the number of chips that can be fabricated by the wafer 100 and affecting the number of chips fabricated by the wafer 100.

Therefore, based on the scheme shown in fig. 8, since the size of the isolation trench 30 becomes gradually larger, the height of the isolation trench 30 at the inner portion of the substrate 10 may be smaller (for example, 2 μm or less as described above) in the direction perpendicular to the surface of the substrate 10 on the side closer to the dielectric layer 20. Thus, the isolation trench 30 does not occupy a large size of the wafer 100, and the efficiency of manufacturing chips by the wafer 100 is not affected.

In some embodiments, as shown in fig. 9, fig. 9 is a schematic plan view of a cut wafer 100 according to an embodiment of the present application, a sealing area 203 may be formed on the periphery of a circuit area 201, and the sealing area 203 is disposed around the circuit area 201. It will be appreciated that the seal 203 is located on the side of the dicing street that is relatively close to the land 201 in the dicing location, as shown in fig. 9, and is separated along with the land 201 during dicing. Thus, after the wafer 100 is cut, the sealing area 203 is located at the periphery of the circuit area 201, so that the sealing area 203 can play a role of blocking the water vapor on the side edge of the circuit area 201, and avoid the influence of the water vapor on the circuit area 201.

The structure of the sealing area 203 can be designed according to practical situations, and is not further limited herein. Illustratively, as shown in fig. 7, the sealing region 203 in the dielectric layer 20 may be a multi-layer structure having a conductive structure 202.

Of course, in other embodiments, the periphery of the circuit region 201 may not be provided with the sealing region 203. In this way, the size occupation of the dielectric layer 20 can be reduced, so that the design number of the circuit regions 201 can be increased, the utilization efficiency of the wafer 100 can be improved, and more chips can be cut and manufactured by using a single wafer 100.

In some embodiments, as shown in fig. 9, the isolation groove 30 may be located outside of the sealing region 203. At this time, the isolation medium 40 (fig. 8) in the isolation trench 30 may isolate the delamination crack outside the sealing region 203, so that the sealing region 203 located at one side of the isolation trench 30 is not easy to crack, and further the delamination crack is prevented from occurring in the line region 201 inside the sealing region 203. Wherein, when the isolation groove 30 is located at the outer side of the sealing region 203, the interval between the isolation groove 30 and the sealing region 203 may be greater than 2 μm to avoid the isolation groove 30 from affecting the structure of the sealing region 203.

In other embodiments, as shown in fig. 10, fig. 10 is a schematic plan view of another cut wafer 100 according to the embodiment of the present application, and the isolation groove 30 may also be located inside the sealing region 203. Thus, the delamination crack may pass through the sealing region 203 and then through the isolation groove 30. At this time, the isolation groove 30 is far from the cutting position, and the stress is weakened when the delamination crack is transferred to the isolation groove 30, so that the isolation medium 40 in the isolation groove 30 can have a good isolation effect.

In some embodiments, as shown in fig. 9, the isolation trenches 30 may be disposed around the periphery of the line area 201. In this way, the isolation trenches 30 can block cracks at various locations around the periphery of the line area 201 while dicing the wafer 100, avoiding propagation of cracks to the line area 201.

For example, when the dielectric layer 20 is formed with the sealing region 203, as shown in fig. 9, the isolation groove 30 may be disposed around the periphery of the line region 201 and disposed at the periphery of the sealing region 203. Alternatively, as shown in fig. 10, the isolation groove 30 may be provided around the periphery of the wiring region 201 and inside the sealing region 203. When the isolation groove 30 is disposed around the periphery of the sealing region 203, the isolation groove 30 may be located at the cutting position of the dicing street or may be located at one side of the cutting position of the dicing street.

Of course, the isolation trench 30 may be selectively formed on the periphery of the circuit area 201, and in some embodiments, as shown in fig. 11, fig. 11 is a schematic plan view of another wafer 100 after dicing, in which at least part of the dicing streets have wafer test structures 102. Isolation trenches 30 may be disposed between wafer test structure 102 and wiring region 201.

Because delamination cracks are more likely to occur when dicing is performed at the dicing street with the wafer test structures 102, cracks are less likely to occur or the degree of cracks that occur is less likely to occur when dicing is performed at the locations in the dicing street without the wafer test structures 102. Therefore, the isolation trench 30 may be disposed only at the position of the dicing street having the wafer test structure 102, so as to avoid the transmission of the delamination crack generated by the wafer test structure 102 to the circuit area 201.

For example, as shown in fig. 11, the isolation groove 30 may be provided at a partial position of the periphery of the sealing region 203. Alternatively, as shown in fig. 12, fig. 12 is a schematic plan view of another cut wafer 100 according to an embodiment of the present application, where the isolation groove 30 may be disposed at a portion of the inner side of the sealing region 203.

In the wafer 100 provided in the embodiment of the present application, the isolation medium 40 may be selectively filled in the isolation trench 30 in different manners. In some embodiments, as shown in fig. 13, fig. 13 is a schematic structural diagram of an isolation medium 40 filled in an isolation trench 30 according to an embodiment of the present application, the isolation medium 40 may be disposed on a trench bottom and a trench wall on a side (i.e., a left side in fig. 13) of the isolation trench 30 relatively close to a line area 201 (fig. 12).

At this time, the delamination crack propagates from the groove wall on the side of the isolation groove 30 relatively close to the cutting position (i.e., the right side in fig. 13), and the stress transmitted to the groove bottom along the groove wall on the side of the isolation groove 30 relatively close to the cutting position is isolated by the isolation medium 40, and the propagation is stopped. Stress waves transmitted through the gaps inside the isolation trenches 30 to the walls of the trenches 30 relatively close to the functional region 101 are also isolated by the isolating medium 40 on the walls of the trenches.

Alternatively, in some embodiments, as shown in fig. 14, fig. 14 is a schematic structural diagram of another isolation medium 40 filled in the isolation groove 30 according to the embodiment of the present application, and the isolation medium 40 may be disposed on the groove bottom and all groove walls. At this time, stress is transmitted from the cutting position to the bottom of the isolation groove 30 and isolated at the groove wall on the side of the cutting position relatively close to the dicing lane. Based on the above two schemes, the isolation medium 40 is only disposed on the bottom and the wall of the isolation groove 30, and does not completely fill the inside of the isolation groove 30, so that the isolation effect can be achieved while saving the material loss of the isolation medium 40.

In some embodiments, as shown in fig. 15, fig. 15 is a schematic structural diagram of another isolation medium 40 filled in an isolation trench 30 according to an embodiment of the present application, where the isolation medium 40 may also completely fill the isolation trench 30. At this time, since the isolation medium 40 completely fills the isolation groove 30, the isolation medium 40 has a relatively thick thickness, and a relatively good isolation effect can be achieved.

In addition, when the isolation medium 40 completely fills the isolation groove 30 and the isolation groove 30 is disposed along the periphery of the circuit area 201, moisture, pollution, etc. on the side edge of the circuit area 201 can be isolated, so that the sealing area 203 is not required to be disposed, and the utilization efficiency of the wafer 100 is improved.

In the wafer 100 provided in the embodiment of the present application, the material of the isolation medium 40 may be selected according to the actual situation, and in some embodiments, the isolation medium 40 may be metallic copper, polyimide (PI) or poly-p-phenylene benzobisoxazole, PBO. Where isolation medium 40 is metallic copper, isolation medium 40 may be grounded. In this way, the charge generated by the isolation medium 40 can be conducted away in time, avoiding charge accumulation.

Of course, other materials may be selected for the isolation medium 40 as long as delamination does not occur, and the isolation medium has an effect of blocking stress generated by delamination cracks. For example, isolation medium 40 may also be metallic aluminum, silicon oxide, or nitrogen oxide, or an organic material.

It will be appreciated that the material of the isolation medium 40 may vary, as may the manner in which it is filled. For example, when the filling medium is copper, the filling may be performed by electroplating. When the filling medium is aluminum, the filling can be performed by sputtering. When the isolation medium 40 is PI, the filling may be performed by spin coating.

In some embodiments, where isolation medium 40 is PI, isolation medium 40 may also cover the surface of medium layer 20 on the side remote from substrate 10. At this time, the edge position of PI parcel chip can realize the point of chip and glue, and lifting plate level stress promotes the board level point of chip and glues the scheme, strengthens the reliability of solder joint.

In some embodiments, as shown in fig. 15, the wafer 100 may further include a passivation layer 50. Passivation layer 50 is located on the surface of dielectric layer 20 on the side remote from substrate 10. The passivation layer 50 may serve to insulate the surface layer from moisture and contamination. Based on this scheme, for example, as shown in fig. 13, 14 and 15, the passivation layer 50 may be first fabricated so that the passivation layer 50 is formed on the groove wall and the groove bottom of the isolation groove 30 when the isolation groove 30 is filled. Then, the isolation medium 40 is filled in the isolation trench 30.

When the wafer 100 includes the passivation layer 50, as shown in fig. 15, when PI is selected for the isolation medium 40, the isolation medium 40 may cover the passivation layer 50 on a side away from the dielectric layer 20.

Based on the structure shown in fig. 5 or 6, when the isolation groove 30 is located at the cutting position of the dicing street, the isolation medium 40 selects PI or PBO, cutting can be performed in a mechanical cutting manner, without using laser cutting, and thus cutting cost can be reduced. Meanwhile, since the isolation groove 30 is directly arranged at the dicing position, other positions of the dicing channels are not required to be occupied, and further, the area of part of the dicing channels can be reserved for wiring, so that fan-out type packaging (fan out wafer level package, FOWLP) is realized, and the wafer 100 is not required to be rearranged.

On the other hand, the embodiment of the application provides a method for manufacturing a wafer, which comprises the steps S100-S300.

S100: a substrate is fabricated and a portion of the isolation trench is formed on the substrate.

S200: and manufacturing a dielectric layer and manufacturing another part forming the isolation groove on the dielectric layer.

S300: and filling an isolation medium in the isolation groove.

In some embodiments, step S100 may include step S101.

S101: and manufacturing a substrate, and forming a part of the isolation groove on the surface of one side of the substrate by adopting a dry etching groove. When the part of the isolation groove in the substrate is manufactured in the mode, the part of the isolation groove in the substrate can be made into a rectangle or an isosceles trapezoid with the bottom of the groove as the top edge. Wherein, the isolation trench may have a depth of approximately 2 μm in a direction perpendicular to the substrate side surface, for example.

As can be seen from the above description, the dielectric layer is made layer by layer in a multi-layer structure, and step S200 may include step S201:

s201, manufacturing a single-layer structure of the dielectric layer, and forming isolation grooves by opening holes.

When the fill medium is copper, step S300 may include steps S301-S302.

S301: copper is filled in the isolation groove in an electroplating mode. Illustratively, the copper fill may be performed using a damascene process.

S302: polishing treatment is performed. For example, a CMP process may be used to polish and level the dielectric layer surface.

Based on the above scheme, the steps S201, S301 and S302 are performed multiple times to complete the wafer fabrication and the isolation trench filling. Thus, the filling of the isolation medium in the whole isolation groove can be completed through the filling of copper for a plurality of times. Wherein, although copper fills layer by layer in the manufacturing process, as only copper is filled, a layering interface can not exist, and the effect of blocking layering cracks is further achieved.

After performing the above-mentioned steps S201, S301 and S302 a plurality of times, the manufacturing method may further include steps S400 to S500.

S400: and carrying out grounding treatment on copper. In this way, accumulation of charge can be avoided.

S500: and a passivation layer is paved on the surface of one side of the dielectric layer, which is far away from the substrate layer. Thus, the passivation layer can play a role in isolating surface water vapor and pollution.

Based on the above steps, when copper is used as the isolation medium, the structural schematic diagram of the complete wafer fabrication process can be referred to fig. 16, fig. 16 is a schematic diagram of the wafer fabrication flow when copper is used as the isolation medium, and the fabrication sequence is (a) - (f) in fig. 16. The manufacturing process comprises the following steps:

Step S101 is performed, where the substrate 10 is fabricated to obtain (a) in fig. 16, and then the isolation trench 30 is opened on the substrate 10 to obtain (b) in fig. 16.

Step S201 is performed to produce a single-layer structure of the dielectric layer 20 on the substrate 10, to obtain (c) in fig. 16.

Step S301 is performed to etch and fill the single-layer structure of the dielectric layer 20 with copper metal, resulting in (d) in fig. 16.

The above steps S201 and S301 are repeated, resulting in (e) in fig. 16.

Finally, steps S400 and S500 are performed, and the passivation layer 50 is laid on the surface of the dielectric layer 20 on the side away from the substrate 10, to obtain (f) in fig. 16.

In other embodiments, when the isolation medium is PI and aluminum is used as the metal material in the dielectric layer, step S200 may include steps S201, S203, S204.

S201: and manufacturing a single-layer structure of the dielectric layer, and forming isolation grooves by opening holes.

S203: evaporating metallic aluminum.

S204: etching the metal aluminum.

The whole dielectric layer can be manufactured by executing the steps for multiple times.

Based on the above manner, after the fabrication of the dielectric layer is completed, the fabrication method further includes step S600.

S600: and a passivation layer is paved on the surface of one side of the dielectric layer, which is far away from the substrate, on the bottom of the isolation groove and on the groove wall.

Meanwhile, step S300 may include step S303.

S303; and filling PI in the isolation groove.

Based on the above steps, when PI is used as the isolation medium and aluminum is used as the metal material in the medium layer, the schematic structural diagram of the wafer manufacturing process can be referred to fig. 17, fig. 17 is a schematic diagram of the wafer manufacturing flow when PI is used as the isolation medium, and the manufacturing sequence is (a) - (i) in fig. 17. The manufacturing process comprises the following steps:

step S101 is performed, where the substrate 10 is fabricated to obtain (a) in fig. 17, and then the isolation trench 30 is opened on the substrate 10 to obtain (b) in fig. 17.

Step S201 is performed to produce a single-layer structure of the dielectric layer 20 on the substrate, to obtain (c) in fig. 17.

Step S203 is performed to evaporate aluminum metal to obtain (d) in fig. 17.

Step S204 is performed to etch the metal aluminum to remove the metal aluminum in the isolation trench 30.

Step S201 is performed again, and the single-layer dielectric of the dielectric layer 20 is produced to obtain (e) in fig. 17, and the single-layer structure is perforated to obtain (f) in fig. 17.

After sequentially executing steps S203 and S204, fig. 17 (g) and (h) can be sequentially obtained.

Next, step S600 is performed to cover the passivation layer 50 on the surface of the dielectric layer 20 on the side away from the substrate 10 and the bottom and wall of the isolation trench 30, resulting in (i) in fig. 17.

Step S303 is performed. The filling mode of the PI can be selected according to actual conditions. As shown in fig. 15, PI may completely fill isolation trenches 30. Alternatively, as shown in fig. 13, PI may be provided on the groove bottom and the groove wall on the side relatively close to the line area in the isolation groove 30. Alternatively, as shown in fig. 14, PI may be provided on the bottom of the isolation groove 30 and all the groove walls.

In other embodiments, step S100 may include steps S102-S104.

S102: and manufacturing a substrate, and photoetching a part of the isolation groove on the substrate by utilizing negative photoresist.

S103: and deepening the part of the isolation groove in the substrate by adopting isotropic wet etching.

S104: annealing is performed for stress relief and defect compensation.

In this way, a trapezoid groove as shown in fig. 3 can be formed on the substrate. Based on the trapezoidal trench shown in fig. 3, during the dielectric layer process of step 200, the material of the dielectric layer may enter the portion of the filled isolation trench within the substrate, while another portion of the isolation trench is correspondingly formed on the dielectric layer.

In performing step 300, PI may fill the portion of the isolation trench within the dielectric layer.

Based on the above steps, the schematic structural diagram of the wafer manufacturing process can be referred to fig. 18, fig. 18 is a schematic diagram of another wafer manufacturing process when PI is used as the isolation medium, and the manufacturing sequence is (a) - (c) in fig. 18. The manufacturing process comprises the following steps:

Steps S102 to S104 are performed to form a trapezoid isolation trench 30 having a narrow upper portion and a wide lower portion on the substrate 10, thereby obtaining (a) in fig. 18.

After step S200 is performed, the single-layer structure of the dielectric layer 20 is formed, and fig. 18 (b) is obtained, and the single-layer structure is formed a plurality of times, and fig. 18 (c) is obtained. The structure shown in fig. 3 can be obtained by executing steps S600 and S303.

In other embodiments, step S100 may include S105:

s105, forming isolation grooves on the substrate by dry etching, and then eliminating defects by high-temperature annealing. Thus, the subsequent reprocessing is convenient.

Alternatively, in other embodiments, step S100 may include S106:

s106: and manufacturing a substrate, forming a porous structure on the substrate by utilizing anodic oxidation, and then forming the isolation groove by high-temperature annealing. Illustratively, the isolation trenches are formed by forming a porous structure on the surface of monocrystalline silicon in an HF solution, and then annealing at 1100 ℃ in a vacuum environment to mass transfer the silicon atoms of the porous silicon.

Wherein, step S107 may be further included before S105.

S107, manufacturing a groove isolation structure on the substrate.

Based on the above-mentioned scheme, reference may be made to fig. 19 for a schematic structural diagram in the process of manufacturing the wafer shown in fig. 5, fig. 19 is a schematic flow diagram of manufacturing the wafer shown in fig. 5, and the manufacturing sequence is (a) - (c) in fig. 19. The manufacturing steps comprise:

Step S107 is performed to obtain fig. 19 (a) by first manufacturing the substrate 10, and to obtain fig. 19 (b) by manufacturing the trench isolation structure 103 on the substrate 10.

Step S105 or S106 is performed to form a part of the isolation trench 30 on the substrate 10, thereby obtaining fig. 19 (c).

Then, steps S200, S600 and S300 are sequentially performed to obtain the wafer shown in fig. 5.

In other embodiments, the method for manufacturing a wafer according to the embodiments of the present application may include the steps of:

s700: a dielectric layer is fabricated on the substrate.

S800: and forming an isolation groove on the dielectric layer, and enabling the isolation groove to extend into the substrate.

S303; and filling PI in the isolation groove.

Based on the steps, the isolation groove is manufactured by etching after the dielectric layer is manufactured. At this time, the schematic structural diagram of the wafer manufacturing process may refer to fig. 20, fig. 20 is a schematic flow diagram of the wafer manufacturing process when PI is another type of PI as the isolation medium, and the manufacturing sequence is (a) - (c) in fig. 20. The manufacturing process comprises the following steps:

step S700 is performed to produce the dielectric layer 20 on the substrate 10, resulting in (a) in fig. 20.

Step S200 is performed to fabricate the isolation trench 30, so that the isolation trench 30 penetrates the dielectric layer 20 and extends into a portion of the substrate 10, resulting in (b) in fig. 20.

Next, step S600 is performed to cover the passivation layer 50 on the surface of the dielectric layer 20 on the side away from the substrate 10 and the bottom and wall of the isolation trench 30, resulting in (c) in fig. 20.

Step S303 is performed. The filling mode of the PI can be selected according to actual conditions. As shown in fig. 15, PI may completely fill the isolation trenches. Alternatively, as shown in fig. 13, PI may be provided on the groove bottom and the groove wall on the side relatively close to the line area in the isolation groove. Alternatively, PI may be provided on the groove bottom as well as the groove wall, as shown in fig. 14.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A wafer, comprising:

a substrate;

the dielectric layer is arranged on one side of the substrate and comprises a plurality of circuit areas which are arranged at intervals; a cutting channel is formed between two adjacent circuit areas;

the isolation grooves are positioned at the periphery of the circuit areas; the isolation groove penetrates through the dielectric layer and extends into a part of the substrate; the method comprises the steps of,

and the isolation medium is filled in the isolation groove.

2. The wafer of claim 1, wherein a seal region is formed at a periphery of the wire region; the sealing area is arranged around the circuit area in a circle; the isolation groove is positioned on the inner side of the sealing area.

3. The wafer of claim 1, wherein a seal region is formed at a periphery of the wire region; the sealing area is arranged around the circuit area in a circle; the isolation groove is positioned outside the sealing area.

4. A wafer according to claim 1 or 3, wherein the isolation trenches are located in the dielectric layer at the dicing sites of the dicing streets; the isolation medium completely fills the portion of the isolation trench within the dielectric layer.

5. The wafer of claim 4, wherein at least a portion of the isolation trenches have wafer test structures within a portion of the substrate.

6. The wafer of claim 5, further comprising:

the groove isolation structures are positioned in the substrate and penetrate through the surface of the substrate, which is close to one side of the dielectric layer; the trench isolation structure is located between the wafer test structure and the circuit region.

7. A wafer according to any of claims 1-3, wherein the isolation trenches are arranged around the periphery of the line area.

8. The wafer of any one of claims 1-3, wherein at least some of the streets have wafer test structures therein; the isolation groove is arranged between the wafer test structure and the circuit area.

9. The wafer of any one of claims 1-3, wherein the isolation trench is formed with trench walls and trench bottoms in the substrate and the dielectric layer;

the isolating medium is arranged on the groove bottom and the groove wall on one side, which is relatively close to the circuit area, of the isolating groove; or,

the isolation medium is arranged at the bottom of the groove and on all the groove walls.

10. A wafer according to any of claims 1-3, wherein the isolation medium completely fills the isolation trenches.

11. A wafer according to any one of claims 1-3, wherein a plurality of spaced apart isolation trenches are provided between the dicing locations of the dicing streets and the wire-line areas.

12. The wafer of claim 1, wherein the isolation trench is formed with a trench bottom and a portion of a trench wall in the substrate; the section of the part of the isolation groove located in the substrate is in a trapezoid shape which is not right-angled; the bottom of the isolation groove is the bottom edge of the trapezoid; the section is perpendicular to the cutting direction of the cutting channel;

the material of the dielectric layer is filled in the part of the isolation groove in the substrate, and the isolation medium is filled in the part of the isolation groove in the dielectric layer.

13. The wafer of claim 1, wherein the isolation medium is one of copper, PI, PBO.

14. The wafer of claim 13, wherein the isolation medium is PI; the isolation medium also covers the surface of the medium layer far away from the side of the substrate.

15. A chip, characterized in that it is manufactured by dicing a wafer according to any one of claims 1-14.

16. An electronic device comprising the chip of claim 15.