CN117219002A

CN117219002A - Display panel and display device

Info

Publication number: CN117219002A
Application number: CN202311345545.1A
Authority: CN
Inventors: 牟鹏程; 李飞
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2021-12-29
Filing date: 2021-12-29
Publication date: 2023-12-12
Also published as: CN114267283B; CN114267283A

Abstract

The embodiment of the application discloses a display panel and a display device.A first display area of the display panel comprises a plurality of pixel setting areas, a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of first reset connecting parts and a plurality of second reset connecting parts, wherein each pixel setting area is provided with a pixel driving circuit; the pixel driving circuits in the same row are electrically connected with the same first reset signal line and the same second reset signal line; the first reset connecting part is used for connecting two adjacent first reset signal lines, and the second reset connecting part is used for connecting two adjacent second reset signal lines; the sum of the numbers of the first reset connection parts between two adjacent first reset signal lines and the second reset connection parts between two adjacent second reset signal lines is smaller than the number of pixel arrangement regions located in the same row. The application can improve the light transmittance of the display panel and ensure the normal work of the under-screen light sensing sensor while ensuring the display effect of the display panel.

Description

Display panel and display device

The application provides a divisional application with the name of a display panel and a display device, which is applied for the application of 2021, 12, 29 and 202111644402.1.

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.

Background

With the development of display technology, display devices gradually develop towards the direction of narrow frames, so that the screen occupation ratio is improved, and the viewing experience is improved.

In order to improve the screen ratio, the light sensing sensor is generally arranged below the display panel in the prior art, which puts forward higher requirements on the light transmittance of the display panel, and how to improve the light transmittance of the display panel while ensuring the display effect of the display panel is a problem to be solved urgently.

Disclosure of Invention

The embodiment of the invention provides a display panel and a display device, which are used for improving the light transmittance of the display panel and ensuring the normal work of an under-screen photosensitive sensor while ensuring the display effect of the display panel.

In a first aspect, an embodiment of the present invention provides a display panel, including a first display area, where the first display area in the display panel includes:

a plurality of pixel arrangement regions arranged in an array along a row direction and a column direction; each pixel setting area is provided with a pixel driving circuit;

the pixel driving circuits positioned in the same row are electrically connected with the same first reset signal line and the same second reset signal line;

A plurality of first reset connection portions and a plurality of second reset connection portions; the first reset connecting part and the second reset connecting part extend along the column direction, the first reset connecting part is used for connecting two adjacent first reset signal lines, and the second reset connecting part is used for connecting two adjacent second reset signal lines; the sum of the numbers of the first reset connection parts between two adjacent first reset signal lines and the second reset connection parts between two adjacent second reset signal lines is smaller than the number of pixel arrangement regions located in the same row.

In a second aspect, an embodiment of the present invention further provides a display apparatus, including the display panel provided in the first aspect.

According to the embodiment of the invention, the first reset connecting part and the second reset connecting part are arranged, the first reset connecting part is used for connecting the adjacent two first reset signal lines, the second reset connecting part is used for connecting the adjacent two second reset signal lines, the number of the first reset connecting parts between the adjacent two first reset signal lines and the number of the second reset connecting parts between the adjacent two second reset signal lines are smaller than the number of pixel arrangement areas positioned in the same row, so that the signal uniformity of the first reset signal lines and the second reset signal lines at all positions in the row direction can be improved, more consistent first reset signals and more consistent second reset signals are provided for all pixel driving circuits in the same row, the display uniformity is improved, the display effect of a display panel is ensured, the light transmittance is improved, and the requirement of a light sensing sensor on the light transmission quantity is met.

Drawings

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 2 is an enlarged schematic view of the area A of FIG. 1;

fig. 3 is a schematic circuit diagram of a pixel driving circuit according to an embodiment of the present invention;

FIG. 4 is a driving timing diagram of the pixel driving circuit shown in FIG. 3;

FIG. 5 is a schematic diagram of a pixel arrangement region corresponding to the first reset connection portion in FIG. 2;

FIG. 6 is a schematic diagram of a layout of a pixel arrangement region corresponding to the second reset connection portion in FIG. 2;

fig. 7 is a schematic structural diagram of a reset signal line and a reset connection portion according to an embodiment of the present invention;

FIG. 8 is a schematic layout of a display panel consistent with the arrangement of the reset connection portions of FIG. 2;

FIG. 9 is a schematic view of another enlarged construction of the area A in FIG. 1;

FIG. 10 is a schematic view of another enlarged construction of the area A of FIG. 1;

FIG. 11 is a schematic layout diagram of a display panel consistent with the arrangement of the reset connection portions of FIG. 10;

FIG. 12 is a schematic view of another enlarged construction of the area A in FIG. 1;

FIG. 13 is a schematic layout of a display panel consistent with the arrangement of the reset connection portions of FIG. 12;

FIG. 14 is a schematic view of another enlarged construction of the area A of FIG. 1;

FIG. 15 is another enlarged schematic view of area A of FIG. 1;

FIG. 16 is a schematic diagram of a partial layout structure of a display panel according to an embodiment of the present invention;

FIG. 17 is a schematic diagram of a partial layout structure of another display panel according to an embodiment of the present invention;

FIG. 18 is a schematic diagram of a partial layout structure of another display panel according to an embodiment of the present invention;

FIG. 19 is a schematic diagram of a partial layout structure of another display panel according to an embodiment of the present invention;

fig. 20 is a schematic structural diagram of a display device according to an embodiment of the present invention;

fig. 21 is a schematic structural diagram of another display device according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

Fig. 1 is a schematic structural view of a display panel according to an embodiment of the present invention, and fig. 2 is an enlarged structural view of a region a in fig. 1, as shown in fig. 1 and 2, a display panel 100 according to an embodiment of the present invention includes a first display area (e.g., region a), where the first display area in the display panel 100 includes a plurality of pixel setting areas P, a plurality of first reset signal lines Vref1, a plurality of second reset signal lines Vref2, a plurality of first reset connection portions 11, and a plurality of second reset connection portions 21; the plurality of pixel setting areas P are arranged in an array along a row direction x and a column direction y; each pixel arrangement region P is provided with one pixel driving circuit 10; the plurality of first reset signal lines Vref1 and the plurality of second reset signal lines Vref2 extend in the row direction x and are arranged in the column direction y, and the pixel driving circuits 10 located in the same row are electrically connected with the same first reset signal line Vref1 and the same second reset signal line Vref2; the first reset connection part 11 and the second reset connection part 21 extend along the column direction y, the first reset connection part 11 is used for connecting two adjacent first reset signal lines Vref1, and the second reset connection part 21 is used for connecting two adjacent second reset signal lines Vref2; the sum of the numbers of the first reset connection portions 11 between the adjacent two first reset signal lines Vref1 and the second reset connection portions 21 between the adjacent two second reset signal lines Vref2 is smaller than the number of the pixel setting regions P located in the same row.

The first display area refers to an area in the display panel with a high requirement for light transmittance due to the arrangement of the photosensitive sensor, and may specifically be a local display area in the display panel, such as an area a shown in fig. 1, or may be an entire display area.

The first reset signal line Vref1 is configured to provide a first reset signal for the pixel driving circuit 10, and the second reset signal line Vref2 is configured to provide a second reset signal for the pixel driving circuit 10, where the first reset signal and the second reset signal can respectively reset different nodes in the pixel driving circuit 10, so as to meet different requirements of different nodes on the reset signal, improve the reset effect, and improve the display residual image.

Fig. 3 is a schematic circuit diagram of a pixel driving circuit according to an embodiment of the present invention, where, as shown in fig. 3, the pixel driving circuit 10 includes a driving transistor T3, a first reset transistor T5, a second reset transistor T7, and a light emitting element D, and an exemplary first reset signal line Vref1 may be electrically connected to an input terminal of the first reset transistor T5 in the pixel driving circuit 10, for providing a first reset signal to a gate (N3 node) of the driving transistor T3, resetting the gate of the driving transistor T3, and a second reset signal line Vref2 may be electrically connected to an input terminal of the second reset transistor T7 in the pixel driving circuit 10, for providing a second reset signal to an anode (N4 node) of the light emitting element D, and resetting the anode of the light emitting element D.

As shown in fig. 2, in this embodiment, two adjacent first reset signal lines Vref1 are electrically connected through a plurality of first reset connection portions 11, and two adjacent second reset signal lines Vref2 are electrically connected through a plurality of second reset connection portions 21, so that signal uniformity of the first reset signal lines Vref1 and the second reset signal lines Vref2 at each position in the row direction x can be improved, a relatively consistent first reset signal and a relatively consistent second reset signal are provided for each pixel driving circuit 10 in the same row, display uniformity is improved, and display effect of the display panel is ensured.

Further, since the resolution of the display panel is high, so that the area of the pixel setting region P is limited, as can be seen from fig. 3, a plurality of thin film transistors and a plurality of signal lines are required to be designed in the pixel setting region P, and thus, in general, one pixel setting region P may be provided with one first reset connection portion 11 or one second reset connection portion 21 in correspondence with each other while ensuring the line width of the signal lines and the interval requirement between the signal lines. Referring to fig. 2, in the embodiment of the present invention, by setting the sum of the numbers of the first reset connection portions 11 between two adjacent first reset signal lines Vref1 and the numbers of the second reset connection portions 21 between two adjacent second reset signal lines Vref2 to be smaller than the number of the pixel setting regions P located in the same row, any one of the first reset connection portions 11 and the second reset connection portions 21 may not be set in a part of the pixel setting regions P, so that the setting density of the first reset connection portions 11 and the second reset connection portions 21 may be reduced, the light transmission area may be increased, the light transmittance may be improved, and the light transmittance of the display panel may be prevented from being low due to the corresponding setting of the first reset connection portions 11 or the second reset connection portions 21 in each pixel setting region P, which is insufficient to satisfy the requirement of the light sensing sensor for the light transmission amount.

The "number of pixel setting areas P located in the same row" specifically refers to the number of pixel setting areas P located in the same row in the first display area, and in the first display area, the setting density of the first reset connection portion 11 and the second reset connection portion 21 is lower, so that the light transmittance can be improved, and the requirement of the light sensing sensor on the light transmission amount can be met. The "adjacent two first reset signal lines Vref1" and the "adjacent two second reset signal lines Vref2" may be any two adjacent first reset signal lines and any two adjacent second reset signal lines Vref2.

In fig. 2, the pixel driving circuit 10 is shown as being located in the pixel setting region P, and in practice, the pixel setting region P is only a virtual region defined artificially, and the actual circuit layout of the pixel driving circuit 10 has a portion beyond the corresponding pixel setting region P.

In summary, the embodiment of the invention uses the first reset connection part to connect two adjacent first reset signal lines and uses the second reset connection part to connect two adjacent second reset signal lines, and the number of the first reset connection parts between the two adjacent first reset signal lines and the number of the second reset connection parts between the two adjacent second reset signal lines are smaller than the number of pixel arrangement areas in the same row, so that the signal uniformity of the first reset signal lines and the second reset signal lines at each position in the row direction can be improved, more consistent first reset signals and more consistent second reset signals can be provided for each pixel driving circuit in the same row, the display uniformity can be improved, the display effect of a display panel can be ensured, the light transmittance can be improved, and the requirement of a photosensitive sensor on the light transmission quantity can be met.

On the basis of the above-described embodiment, the specific arrangement of the first reset signal line Vref1, the second reset signal line Vref2, the first reset connection section 11, and the second reset connection section 21 will be described in detail below.

Fig. 5 is a schematic structural layout of a pixel arrangement region (e.g., a pixel arrangement region P1 in fig. 2) corresponding to the first reset connection portion in fig. 2, fig. 6 is a schematic structural layout of a pixel arrangement region (e.g., a pixel arrangement region P2 in fig. 2) corresponding to the second reset connection portion in fig. 2, and, referring to fig. 5 and 6, the display panel includes a substrate (not shown) and a driving circuit layer disposed on the substrate, the driving circuit layer including a semiconductor layer poly, a first metal layer M1, a capacitor metal layer Mc, a second metal layer M2, and a third metal layer M3 stacked in a direction away from the substrate; the first reset signal line Vref1 and the second reset signal line Vref2 are arranged on the same layer and are positioned on the first metal layer M1 or the capacitor metal layer Mc; the first reset connection portion 11 and the second reset connection portion 21 are arranged in the same layer and are located on the second metal layer M2 or the third metal layer M3.

The layout structure of the pixel driving circuit 10 in fig. 5 and fig. 6 is the same, and corresponds to fig. 3, and the exemplary pixel driving circuit 10 includes seven thin film transistors (T1 to T7) and one storage capacitor Cst, namely, a 7T1C circuit, which is illustrated as an example, and the difference is that only the pixel setting region P where the pixel driving circuit 10 shown in fig. 5 is located is provided with the first reset connection portion 11, and the pixel setting region P where the pixel driving circuit 10 shown in fig. 6 is located is provided with the second reset connection portion 21.

Fig. 4 is a driving timing chart of the pixel driving circuit shown in fig. 3, and the operation of the pixel driving circuit 10 will be briefly described with reference to fig. 3, 4 and 5. Referring to fig. 3, 4 and 5, taking a pixel driving circuit of any row as an example, first, the first Scan signal on the first Scan signal line Scan1 controls the first reset transistor T5 of the pixel driving circuit 10 to be turned on in the initialization stage, so as to write the first reset signal on the first reset signal line Vref1 to the gate of the driving transistor T3, and reset the gate potential of the driving transistor T3. Then, the second Scan signal on the second Scan signal line Scan2 controls the data writing transistor T2 and the threshold compensating transistor T4 of the pixel driving circuit 10 to be turned on in the data writing stage to write the data signal on the data signal line Vdata to the gate of the driving transistor T3 and to compensate the threshold voltage of the driving transistor T3. In some alternative designs of the pixel driving circuit, the second Scan signal on the second Scan signal line Scan2 may be further used to control the second reset transistor T7 to be turned on during the data writing phase, so as to write the second reset signal on the second reset signal line Vref2 to the anode of the light emitting element D, and reset the anode potential of the light emitting element D. Finally, the light emission control signal on the light emission control signal line Emit controls the first light emission control transistor T1 and the second light emission control transistor T6 of the pixel driving circuit 10 to be turned on in the light emission stage, so that the driving current generated by the driving transistor T3 is transmitted to the light emitting element D, and the light emitting element D is driven to Emit light.

Further, the power supply signal line PVDD is for supplying a power supply voltage to the driving transistor T3, and the voltage on the power supply signal line PVDD may be a positive voltage. The voltage on the common power signal terminal PVEE may be zero or negative. The voltages of the first reset signal on the first reset signal line Vref1 and the second reset signal on the second reset signal line Vref2 may be negative voltages.

It should be noted that, in the above embodiment, the P-type transistors are used as examples of the transistors in the pixel driving circuit 10, and in other alternative embodiments, the N-type transistors, or the P-type transistors and the N-type transistors may be used as examples of the transistors in the pixel driving circuit 10. Different enable levels may be provided depending on the type of transistor, the enable level being a level that enables the transistor to be turned on. For example, the enable level is high for an N-type transistor and low for a P-type transistor.

It should be noted that the pixel driving circuit 10 shown in fig. 3 and 5 is only an example, and is not intended to limit the present application.

As can be appreciated from the foregoing, the pixel driving circuit 10 may include a plurality of thin film transistors including an active layer, a gate electrode, and a source and drain electrode, and a storage capacitor Cst; the storage capacitor Cst comprises a first capacitor electrode plate and a second capacitor electrode plate; the display panel 100 further includes scanning signal lines (specifically, a first scanning signal line Scan1, a second scanning signal line Scan2, a light emission control signal line Emit, and the like, hereinafter the same), data signal lines Vdata, reset signal lines (specifically, a first reset signal line Vref1 and a second reset signal line Vref2, hereinafter the same), and a power signal line PVDD, and in this embodiment, the display panel 100 further includes reset connection portions (specifically, a first reset connection portion 11 and a second reset connection portion 21, hereinafter the same). Referring to fig. 5, an active layer of the thin film transistor is located at a semiconductor layer poly in a driving circuit layer. Further, the gate electrode of the thin film transistor, the first capacitor plate and the scanning signal line may be located in the first metal layer M1 in the driving circuit layer; the second capacitor plate may be located at the capacitor metal layer Mc in the driving circuit layer, the source and drain electrodes of the thin film transistor and the power signal line PVDD may be located at the second metal layer M2 in the driving circuit layer, and the data signal line Vdata may be located at the third metal layer M3 in the driving circuit layer. Further, the first reset signal line Vref1 and the second reset signal line Vref2 may be located in the first metal layer M1 or the capacitor metal layer Mc, and fig. 5 illustrates that the first reset signal line Vref1 and the second reset signal line Vref2 are located in the capacitor metal layer Mc as an example, so that the short circuit risk between the reset signal line and the scan signal line can be reduced by this arrangement; the first reset connection portion 11 and the second reset connection portion 21 may be located on the second metal layer M2 or the third metal layer M3, and fig. 5 illustrates an example in which the first reset connection portion 11 and the second reset connection portion 21 are located on the second metal layer M2. Because the reset connection part and the reset signal line are positioned on different film layers, the reset connection part and the reset signal line are electrically connected through the through hole, and the reset signal line and the reset connection part are respectively arranged on the adjacent capacitor metal layer Mc and the second metal layer M2, the setting difficulty of the through hole can be reduced, and the film layer structure of the display panel is simple.

Fig. 7 is a schematic structural view of a reset signal line and a reset connection portion provided in an embodiment of the present invention, and referring to fig. 5, 6 and 7, the pixel driving circuit 10 includes a pixel semiconductor portion 101 located in a semiconductor layer poly, the pixel semiconductor portion 101 including a first node N1 and a second node N2; the display panel 100 further includes a first connection bridge 111 and a second connection bridge 211 disposed on the second metal layer M2, the first node N1 is electrically connected to the first reset signal line Vref1 through the first connection bridge 111, and the second node N2 is electrically connected to the second reset signal line Vref2 through the second connection bridge 211; the first reset connection part 11 is located in the second metal layer M2 and partially multiplexes the first connection bridge 111; the second reset connection portion 21 is located in the second metal layer M2, and partially multiplexes the second connection bridge 211.

As described above, the semiconductor layer poly is an active layer in the thin film transistor, and the pixel semiconductor portion 101 constitutes the active layers of the plurality of thin film transistors, and fig. 7 exemplarily shows the pixel semiconductor portion 101 in the pixel driving circuit 10 of 2 rows by 3 columns. For convenience of distinction, in fig. 5, 6, and 7, reference numeral 101 denotes a pixel semiconductor portion 101 in the pixel driving circuit 10 of the present row (1 st row in fig. 7), reference numeral 101' denotes a pixel semiconductor portion in the pixel driving circuit 10 of the previous row of the pixel driving circuit 10 of the present row, reference numeral 101 "denotes a pixel semiconductor portion in the pixel driving circuit 10 of the next row of the pixel driving circuit 10 of the present row, and each of the thin film transistors identified in fig. 5 and 6 is a thin film transistor in the pixel driving circuit 10 of the present row.

As shown in fig. 3, 5 and 7, the pixel semiconductor portion 101 includes a first node N1 and a second node N2, and the first node N1 and the second node N2 may be connected to input terminals of different thin film transistors, for example, the first node N1 is connected to an input terminal (source or drain) of the first reset transistor T5, and the second node N2 is connected to an input terminal (source or drain) of the second reset transistor T7. Because the first node N1 is electrically connected to the first reset signal line Vref1 through the first connection bridge 111, so as to receive a first reset signal on the first reset signal line Vref1, and transmit the first reset signal to the gate of the driving transistor T3 when the first reset transistor T5 is turned on, and reset the gate of the driving transistor T3, similarly, because the second node N2 is electrically connected to the second reset signal line Vref2 through the second connection bridge 211, it is able to receive a second reset signal on the second reset signal line Vref2, and transmit the second reset signal to the anode of the light emitting element D when the second reset transistor T7 is turned on, so as to reset the light emitting element D, and ensure that the current display state of the display panel is not affected by the previous display state, and ensure that the display effect is good.

Further, as shown in fig. 5, 6 and 7, the first reset connection portion 11 is located on the second metal layer M2 and partially multiplexes the first connection bridge 111, and the second reset connection portion 21 is located on the second metal layer M2 and partially multiplexes the second connection bridge 211. Since the first connection bridge 111 is electrically connected to the first reset signal line Vref1, and the second connection bridge 211 is electrically connected to the second reset signal line Vref2, in this embodiment, the first connection bridge 111 is multiplexed into a part of the first reset connection portion 11, the second connection bridge 211 is reset into a part of the second reset connection portion 21, only two first connection bridges 111 adjacent to each other in the column direction y need to be electrically connected by a trace, two second connection bridges 211 adjacent to each other in the column direction y need to be electrically connected by a trace, and the first reset connection portion 11 and the second reset connection portion 21 can be formed, so that no trace (reset connection portion) need to be set in a region of the pixel setting region P except for the first connection bridge 111 and the second connection bridge 211 in the row direction x for being electrically connected to the reset signal line, thereby simplifying the manufacturing process, reducing the manufacturing difficulty, reducing the short-circuit risk of the trace, and reducing the loss of the light transmission region, and being beneficial to ensuring that the light transmittance of the display panel meets the requirements.

Referring to fig. 3, 5 and 6, the pixel driving circuit 10 includes a driving transistor T3, a first reset transistor T5 and a second reset transistor T7; one end of the first reset transistor T5 is electrically connected with the first node N1, and the other end of the first reset transistor T5 is electrically connected with the grid electrode of the driving transistor T3; one end of the second reset transistor T7 is electrically connected with the second node N2, and the other end of the second reset transistor T is electrically connected with the anode of the light-emitting element D; the driving transistor T3 is used for controlling the lighting of the light emitting element D, the first reset transistor T5 is used for controlling the first reset signal on the first reset signal line Vref1 to reset the gate potential of the driving transistor T3, and the second reset transistor T7 is used for controlling the second reset signal on the second reset signal line Vref2 to reset the anode potential of the light emitting element D; the display panel 100 further includes first Scan signal lines Scan1 extending in the row direction x and arranged in the column direction y, and two first Scan signal lines Scan1 adjacent to each other in the column direction y each have an overlapping region with the pixel semiconductor portion 101 in a vertical direction of a plane on which the substrate is located, and the two first Scan signal lines Scan1 and the pixel semiconductor portion 101 respectively constitute a first reset transistor T5 and a second reset transistor T7 through the overlapping region.

For example, as shown in reference to fig. 5, the area where the first Scan signal line Scan1 overlaps the pixel semiconductor portion 101 in the vertical direction of the plane of the substrate is the first reset transistor and the second reset transistor. In fig. 5, the upper and lower first scanning signal lines Scan1 are the first scanning signal line Scan1 corresponding to the pixel driving circuit 10 of the present row and the first scanning signal line Scan1 corresponding to the pixel driving circuit 10 of the next row, respectively. For example, a first Scan signal line Scan1 in the upper part in fig. 5 has overlapping regions with the pixel semiconductor portion 101 of the pixel driving circuit of the present row and the pixel semiconductor portion 101 'of the pixel driving circuit of the previous row, and the region overlapping the pixel semiconductor portion 101 of the present row constitutes the first reset transistor T5 in the pixel driving circuit of the present row and the region overlapping the pixel semiconductor portion 101' of the previous row constitutes the second reset transistor in the pixel driving circuit of the previous row. Similarly, the overlapping area of the second Scan signal line Scan1 below and the pixel semiconductor portion 101 of the present row forms the second reset transistor T7 of the pixel driving circuit, and the overlapping area of the second Scan signal line Scan1 and the pixel semiconductor portion 101 of the next row forms the first reset transistor of the pixel driving circuit of the next row, and fig. 5 only identifies the first reset transistor T5 and the second reset transistor T7 in the pixel driving circuit 10 of the present row. In general, the first Scan signal line Scan1 corresponding to a row of pixel driving circuits and the second Scan signal line Scan2 corresponding to a previous row of pixel driving circuits receive the same driving signals, in other words, the initialization phase of a row of pixel driving circuits is synchronous with the data writing phase of a previous row of pixel driving circuits, so that the driving period of a frame of picture can be saved, and the refresh frequency can be increased. As shown in fig. 5, the first Scan signal line Scan1 below receives the same driving signal as the second Scan signal line Scan2 in the figure, and thus the second reset transistor T7 can be controlled to be turned on in the data writing stage (Scan 2 enabling stage) of the pixel driving circuit of the present row to reset the anode potential of the light emitting element D.

The configuration of the remaining transistors in the pixel driving circuit 10 can be understood with reference to the configuration of the first reset transistor T5 and the second reset transistor T7, and will not be described in detail herein.

As shown in fig. 7, the first node N1 and the second node N2 in the pixel semiconductor portion 101 are located on opposite sides of the pixel semiconductor portion 101 in a first direction, respectively, and the first direction is parallel to the column direction y or forms an acute angle with the column direction y; along the column direction y, a set of reset signal line groups including a first reset signal line Vref1 and a second reset signal line Vref2 are provided on opposite sides of the pixel semiconductor section 101, respectively; the first node N1 is electrically connected to a first reset signal line Vref1 located on one side of the pixel semiconductor section 101, and the second node N2 is electrically connected to a second reset signal line Vref2 located on the other side of the pixel semiconductor section 101.

The first direction is not limited in the embodiment of the present invention, and the first direction may be parallel to the column direction y or form an acute angle with the column direction y, and fig. 7 illustrates an example in which the first direction is approximately parallel to the column direction y, that is, an acute angle is formed between the first direction and the column direction y. In this way, the first node N1 in the pixel semiconductor portion 101 of the present row and the second node N2 in the pixel semiconductor portion 101' of the previous row may be disposed side by side in the row direction x, so that the distance between two adjacent pixel semiconductor portions of the row direction y may be reduced, the compactness of the pixel semiconductor portion is ensured, and the number of pixel semiconductor portions per unit area, that is, the resolution of the display panel, and the display effect of the display panel are improved. Further, in this embodiment, by disposing a first reset signal line Vref1 and a second reset signal line Vref2 on both sides of the pixel semiconductor section 101 along the column direction y, the first node N1 is electrically connected to the first reset signal line Vref1 nearest thereto, and the second node N2 is electrically connected to the second reset signal line Vref2 nearest thereto, which is beneficial to reducing wiring difficulty.

When the first reset connection portion 11 and the second reset connection portion 21 are located in the second metal layer M2, and the first reset connection portion 11 partially multiplexes the first connection bridge 111 and the second reset connection portion 21 partially multiplexes the second connection bridge 211, it is required to ensure that the first reset connection portion 11 is not in contact with the other conductive structures except the first connection bridge 111 in the second metal layer M2; the second reset connection portion 21 is not in contact with the rest of the conductive structures except the second connection bridge 211 in the second metal layer M2, so as to avoid the short circuit between the wires from affecting the performance of the display panel.

As illustrated with reference to fig. 3 and 5, the first reset connection portion 11 is specifically required to be free from contact with the following conductive structures: a second connection bridge 211 in the second metal layer M2 for electrically connecting with the second node N2 in the adjacent pixel semiconductor portion (e.g., 101'), a power signal line PVDD in the second metal layer M2, a bridge structure 41 in the second metal layer M2 for connecting the output terminal (source or drain) of the threshold compensation transistor T4 with the gate of the driving transistor T3, a conductive structure 42 in the second metal layer M2 for subsequently connecting the anode of the light emitting element D with the output terminal (source or drain) of the second light emission control transistor T6, and a conductive structure 43 in the second metal layer M2 for connecting the input terminal (source or drain) of the data writing transistor T2 with the data signal line Vdata.

As illustrated with reference to fig. 3 and 6, the first reset connection portion 11 is specifically required to be free from contact with the following conductive structures: a first connection bridge 111 in the second metal layer M2 for electrically connecting with the first node N1 in the adjacent pixel semiconductor portion (e.g., 101), a power signal line PVDD in the second metal layer M2, a bridge structure 41 in the second metal layer M2 for connecting the output terminal (source or drain) of the threshold compensation transistor T4 with the gate of the driving transistor T3, a conductive structure 42 in the second metal layer M2 for subsequently connecting the anode of the light emitting element D with the output terminal (source or drain) of the second light emission control transistor T6, and a conductive structure 43 in the second metal layer M2 for connecting the input terminal (source or drain) of the data writing transistor T2 with the data signal line Vdata.

It should be noted that, the conductive structures that the first reset connection portion 11 and the second reset connection portion 21 need to avoid are only schematic, and not limited, and those skilled in the art can avoid the first reset connection portion 11 and the second reset connection portion 21 according to the specific structure of the metal film layer where they are located, so as to avoid a routing short circuit and ensure the quality of the display panel.

Referring to fig. 5, 6 and 7, the capacitor metal layer Mc includes a capacitor plate (the area marked Cst is a capacitor plate) and a shielding structure 102, the pixel semiconductor portion 101 includes a straight line portion 1011 having a top view projection position located at one side of the capacitor plate, and the display panel 100 further includes an anode metal layer (not shown) at a side of the third metal layer M3 away from the substrate, which will be described later; the optional first reset connection portion 11 and the second reset connection portion 21 overlap with an orthographic projection of at least one of the anode of the light emitting element in the anode metal layer, the straight line portion 1011 in the pixel semiconductor portion 101, the capacitor plate, and the shielding structure 102 on the substrate.

The shielding structure 102 is electrically connected to the power signal line PVDD, and is configured to receive a fixed potential on the power signal line PVDD, so as to avoid an influence of a data signal jump on the data signal line Vdata on the potential of the N3 node, and improve the working stability of the pixel driving circuit 10.

By providing the first reset connection portion 11 and the second reset connection portion 21 overlapping with other metal or orthographic projections of a structure having low light transmittance (such as the pixel semiconductor portion 101) on the substrate, occupation of the light transmitting area by the first reset connection portion 11 and the second reset connection portion 21 can be reduced, and influence of the arrangement of the first reset connection portion 11 and the second reset connection portion 21 on the light transmittance can be further reduced.

Fig. 5 illustrates an example in which the first reset connection portion 11 overlaps the shielding structure 102 and the straight line portion 1011 in the pixel semiconductor portion 101, and fig. 6 illustrates an example in which the second reset connection portion 21 overlaps the shielding structure 102 and the straight line portion 1011 in the pixel semiconductor portion 101. In other embodiments, the first reset connection portion 11 and the second reset connection portion 21 may overlap with other light-impermeable structural projections to reduce the effect on light transmittance.

In summary, the above embodiments describe the specific layout structure arrangement manner of the first reset signal line Vref1, the second reset signal line Vref2, the first reset connection section 11 and the second reset connection section 21 in the display panel in detail. On this basis, the arrangement of the first reset connection portion 11 and the second reset connection portion 21 in the first display area will be further described below.

As one possible arrangement, fig. 8 is a schematic layout structure of a display panel consistent with the arrangement of the reset connection portions in fig. 2, and as shown in fig. 2 and 8, each pixel setting region P in the selectable one-column pixel setting region is correspondingly provided with a first reset connection portion 11, or is correspondingly provided with a second reset connection portion 21; the first reset connection portions 11 adjacent in the column direction y communicate with each other to form a first reset connection line 110; the second reset connection portions 21 adjacent in the column direction y communicate with each other to form a second reset connection line 210.

Fig. 8 exemplarily shows a layout structure of pixel setting areas of 2 rows by 4 columns, as shown in fig. 2 and 8, the pixel setting areas P of part of the columns are correspondingly provided with a first reset connection part 11 or a second reset connection part 21, and the pixel setting areas P of the other columns are not provided with any one of the first reset connection part 11 and the second reset connection part 21, so that the light transmittance can be improved, and the requirement of the light sensing sensor on the light transmission quantity can be met.

Further, as can be seen from fig. 8, in this embodiment, by setting the first reset connection portion 11 or the second reset connection portion 21 in each pixel setting region P in a column of pixel setting regions, the first reset connection portions 11 adjacent in the column direction y are connected to form the first reset connection line 110, and the second reset connection portions 21 adjacent in the column direction y are connected to form the second reset connection line 210, so that layout structures of the reset connection portions correspondingly set in any column of pixel setting regions are consistent, and the reset connection portions are the first reset connection portions 11, or the second reset connection portions 21, or the reset connection portions are not set, so that preparation difficulty can be reduced, for example, preparation difficulty of a mask can be reduced.

Further, as shown in fig. 2 and 8, the optional first reset connection lines 110 and the second reset connection lines 210 are alternately arranged in the row direction x. By this arrangement, the uniformity of the reset signal on the reset signal line can be improved, and the display uniformity can be improved.

In a specific embodiment, the optional first reset connection lines 110 and the second reset connection lines 210 are alternately arranged along the row direction x, and n columns of pixel arrangement areas are spaced between any one first reset connection line 110 and two adjacent second reset connection lines 210; wherein n is a positive integer. By such arrangement, the first reset connection lines 110 and the second reset connection lines 210 can be uniformly distributed in the first display area, which is beneficial to ensuring the signal uniformity of the first reset signal lines Vref1 at each position along the row direction x and the signal uniformity of the second reset signal lines Vref2 at each position along the row direction x, so as to provide uniform first reset signals and uniform second reset signals for each pixel driving circuit 10 in the same row, ensure the reset effect on the gate driving transistors T3 and the light emitting elements D, improve the display uniformity, and improve the display effect of the display panel.

For example, fig. 2 and 8 illustrate an example in which a row of pixel arrangement regions is spaced between any one first reset connection line 110 and two second reset connection lines 210 adjacent thereto, and in other embodiments, a greater number of rows of pixel arrangement regions P may be spaced between the first reset connection line 110 and two second reset connection lines 210 adjacent thereto, so as to reduce the arrangement density of the first reset connection portions 11 and the second reset connection portions 21 as much as possible while ensuring display uniformity, and improve light transmittance. Fig. 9 is another enlarged schematic view of the area a in fig. 1, and fig. 9 illustrates an example of a pixel arrangement region spaced by two columns between any one first reset connection line 110 and two second reset connection lines 210 adjacent thereto.

As another possible arrangement, fig. 10 is another enlarged schematic structural view of the area a in fig. 1, and fig. 11 is a schematic structural view of a layout of a display panel consistent with the arrangement of the reset connection portions in fig. 10, where the first reset connection portions 11 corresponding to two adjacent first reset signal line groups are arranged in a staggered manner along the column direction y; the first reset signal line group comprises two adjacent first reset signal lines Vref1, and the two adjacent first reset signal line groups comprise the same first reset signal line Vref1; the second reset connection parts 21 corresponding to the two adjacent second reset signal line groups are arranged in a staggered manner along the column direction y; the second reset signal line group includes two adjacent second reset signal lines Vref2, and the two adjacent second reset signal line groups include the same second reset signal line Vref2.

As shown in fig. 10, from top to bottom, the first reset signal line Vref1 and the second reset signal line Vref1 form one first reset signal line group, the second first reset signal line Vref1 and the third reset signal line Vref1 form another first reset signal line group, the two first reset signal line groups are adjacent, and the first reset connection parts 11 corresponding to the two first reset signal line groups are arranged in a staggered manner along the column direction y. From top to bottom, the first second reset signal line Vref2 and the second reset signal line form a second reset signal line group, the second reset signal line Vref2 and the third second reset signal line Vref2 form another second reset signal line group, the two second reset signal line groups are adjacent, and the second reset connection parts 21 corresponding to the two second reset signal line groups are arranged in a staggered manner along the column direction y.

Specifically, in this embodiment, in order to ensure that the sum of the numbers of the first reset connection portions 11 between two adjacent first reset signal lines Vref1 and the second reset connection portions 21 between two adjacent second reset signal lines Vref2 is smaller than the number of the pixel setting regions P located in the same row, the first reset connection portions 11 corresponding to two adjacent first reset signal line groups may be offset by at least one pixel setting region P along the column direction y, and the second reset connection portions 21 corresponding to two adjacent second reset signal line groups may be offset by at least one pixel setting region P along the column direction y, so as to ensure the requirement of the first display region on the light transmittance.

In this embodiment, the first reset connection portions 11 corresponding to the two adjacent first reset signal line groups are arranged in a staggered manner along the column direction y, and the second reset connection portions 21 corresponding to the two adjacent second reset signal line groups are arranged in a staggered manner along the column direction y, so that the dispersibility of the first reset connection portions 11 and the second reset connection portions 21 is improved, the signal uniformity on each first reset signal line Vref1 and each second reset signal line Vref2 is further improved, and the display effect is ensured.

As a possible offset arrangement, with continued reference to fig. 10 and 11, the first reset connection portions 11 and the second reset connection portions 21 may alternatively be arranged in the column direction y within a column of pixel arrangement regions. As can be seen from comparing fig. 10 and 2, the number of pixel arrangement regions P in fig. 10 where the reset connection portions are not provided is the same as that in fig. 2, and thus the light transmittance is substantially uniform, but by providing the first reset connection portions 11 and the second reset connection portions 21 alternately arranged in the column direction y in one column of pixel arrangement regions in this embodiment, the distribution of the reset connection portions in the first display region can be made more uniform under the condition that the light transmittance is substantially uniform, and thus the signal uniformity on the reset signal lines can be further improved, and the display uniformity can be ensured.

As another possible misalignment arrangement, fig. 12 is another enlarged schematic structural view of the area a in fig. 1, and fig. 13 is a schematic layout view of a display panel consistent with the arrangement of the reset connection portions in fig. 12, and referring to fig. 12 and 13, the first reset connection portion 11 and the second reset connection portion 21 may be selected to be located in different columns of the pixel arrangement regions P. So set up, not only can make the distribution of connecting portion that resets in first display area more even, still can make the great pixel setting area P of luminousness that does not set up the connecting portion that resets evenly disperse in first display area, be favorable to the transmission of the light of all directions, improve the reliability of the optical signal of the collection of photosensitive sensor.

Referring to fig. 10 to 13, the pixel arrangement regions P optionally located in the same row and spaced between two first reset connection portions 11 adjacent in the row direction x have the same column number; the columns of the pixel setting regions P located in the same row of the pixel setting regions and spaced between two second reset connection portions 21 adjacent in the row direction x are the same. By the arrangement, the first reset connection parts 11 between the same first reset signal line groups can be uniformly distributed, the second reset connection parts 21 between the same second reset signal line groups can be uniformly distributed, the signal uniformity on the first reset signal line Vref1 and the second reset signal line Vref2 is improved, and the display uniformity is ensured.

Still further, with continued reference to fig. 10 to 14, for two adjacent first reset signal line groups, one first reset connection portion 11 of one first reset signal line group and the column number of the pixel setting regions P spaced between two first reset connection portions 11 nearest to the first reset connection portion 11 of the other first reset signal line group may be selected to be the same. Similarly, for two adjacent second reset signal line groups, one second reset connection portion 21 in one second reset signal line group and the column number of the pixel setting region P spaced between two second reset connection portions 21 nearest to the second reset connection portion 21 in the other second reset signal line group may be selected to be the same. In this way, the uniformity of the distribution of the first reset connection portion 11 and the second reset connection portion 21 can be further improved, the uniformity of the signals on the first reset signal line Vref1 and the second reset signal line Vref2 can be improved, and the display uniformity can be ensured.

Fig. 10 to 13 illustrate, by way of example, three columns of pixel arrangement regions between two first reset connection portions 11 adjacent in the row direction x, one column of pixel arrangement regions between two first reset connection portions 11 adjacent in the two first reset signal line groups, three columns of pixel arrangement regions between two second reset connection portions 21 adjacent in the row direction x, and one column of pixel arrangement regions between two second reset connection portions 21 adjacent in the row direction x.

Fig. 14 is another enlarged schematic structural view of the area a in fig. 1, and fig. 15 is another enlarged schematic structural view of the area a in fig. 1, respectively showing the above two offset manners, as shown in fig. 14 and 15, in this embodiment, two first reset connection portions 11 adjacent to each other in the row direction x are separated by five pixel arrangement regions, and two first reset connection portions 11 adjacent to each other in the row direction x are separated by two pixel arrangement regions; the pixel arrangement regions are located in the same row of pixel arrangement regions, five columns of pixel arrangement regions are spaced between two adjacent second reset connection portions 21 along the row direction x, and two columns of pixel arrangement regions are spaced between two nearest neighbor second reset connection portions 21 in two adjacent second reset signal line groups.

In summary, the above embodiment describes the arrangement of the first reset connection portion 11 and the second reset connection portion 21 in the first display area in detail. The above embodiments are applicable to any pixel arrangement type of display panel, such as a conventional YYG arrangement (real arrangement), a diamond arrangement (diamond arrangement), and other pixel arrangement types arbitrarily known to those skilled in the art, and the embodiments of the present invention are not limited thereto. Regardless of the pixel arrangement type, by adopting the technical scheme of the embodiment of the invention, the light transmittance of at least part of the area of the display panel can be improved while the display uniformity is ensured, so as to meet the requirement of the under-screen light sensing sensor on the light transmission quantity.

As a specific implementation, the technical scheme of the embodiment of the invention is further described below by means of diamond arrangement.

Fig. 16 is a schematic view of a partial layout structure of a display panel according to an embodiment of the present invention, referring to fig. 16, the display panel 100 includes a plurality of first sub-pixels 31, a plurality of second sub-pixels 32, and a plurality of third sub-pixels 33; the first sub-pixel 31 has a center coinciding with the center of a virtual quadrangle (quadrangle constituted by broken lines in the figure), the second sub-pixel 32 is spaced apart from the first sub-pixel 31 and has a center at a first vertex a of the virtual quadrangle, and the third sub-pixel 33 is spaced apart from the first sub-pixel 31 and the second sub-pixel 32 and has a center at a second vertex b of the virtual quadrangle, the first vertex a and the second vertex b being adjacent; four first sub-pixels 31, two second sub-pixels 32, and two third sub-pixels 33 constitute one pixel repeating unit; the pixel repeating units are correspondingly arranged in two adjacent rows and four adjacent columns of pixel arrangement areas P, four pixel driving circuits in the first row of pixel arrangement areas are respectively a second sub-pixel 32, a first sub-pixel 31, a third sub-pixel 33 and a pixel driving circuit of a second sub-pixel 32, and four pixel driving circuits in the second row of pixel arrangement areas are respectively a third sub-pixel 33, a first sub-pixel 31, a second sub-pixel 32 and a pixel driving circuit of the first sub-pixel 31; the two nearest neighboring first reset connection parts 11 in the two adjacent first reset signal line groups are separated by a column of pixel setting areas along the row direction x, and the two nearest neighboring second reset connection parts 21 in the two adjacent second reset signal line groups are separated by a column of pixel setting areas along the row direction x; the first reset connection parts 11 correspond to the same sub-pixels, and the projection positions and the projection shapes on the corresponding sub-pixels are the same; each second reset connection portion 21 corresponds to the same sub-pixel, and the projection position and the projection shape on the corresponding sub-pixel are the same.

In fig. 16, the first reset connection portion 11 and the second reset connection portion 21 are arranged in the same manner as in fig. 11, and in order to facilitate the relative positional relationship of the respective structures, fig. 16 only shows the structures of the pixel semiconductor portion 101, the first reset signal line Vref1, the second reset signal line Vref2, the first reset connection portion 11, the second reset connection portion 21, and the anode metal layer, and the other structures may be arranged with reference to fig. 11.

Specifically, the sub-pixel includes a pixel driving circuit 10 and a light emitting element D, and an anode of the light emitting element D is electrically connected to an output terminal of a second light emission control transistor T6 in the pixel driving circuit 10 (see fig. 3). The first subpixel 31, the second subpixel 32, and the third subpixel 33 each include light emitting elements having different emission colors. The first subpixel 31 may be a green subpixel, i.e. the light emitting element emits green light; the second sub-pixel 32 may be a blue sub-pixel, i.e. the light emitting element emits blue light; the third sub-pixel 33 may be a red sub-pixel, i.e. the color of the light emitted by the light emitting element is red. The solid line boxes indicated by the marks 31, 32, and 33 in fig. 16 can be understood as the opening boundaries (pixel openings) of the pixel defining layers to illustrate the shape and relative positions of the light emitting layers of the light emitting elements in the corresponding sub-pixels.

Specifically, as shown in fig. 3, 11 and 16, the first anode 310 of the light emitting element D in the first subpixel 31 may be electrically connected to the first connection structure 311 corresponding to the pixel arrangement region P in fig. 11 through a via hole, and the first connection structure 311 is located in the third metal layer M3 and is electrically connected to the output terminal (source or drain) of the second light emitting control transistor T6 through a via hole, so that the output terminal of the second light emitting control transistor T6 may be electrically connected to the first anode 310 of the light emitting element D in the first subpixel 31; similarly, the second anode 320 of the light emitting element D in the second sub-pixel 32 may be electrically connected to the second connection structure 321 corresponding to the pixel setting region P in fig. 11 through a via hole, and the third anode 330 of the light emitting element D in the third sub-pixel 33 may be electrically connected to the third connection structure 331 corresponding to the pixel setting region P in fig. 11, where the second connection structure 321 and the third connection structure 331 are electrically connected to the output end (source or drain) of the second light emitting control transistor T6 in the respective pixel driving circuit 10, and the connection manner is the same as that of the first connection structure 311, and will not be repeated herein.

For the same sub-pixel, if the environments (such as elements of a thin film transistor and the like, and the environment created by the layout of each signal line and the like) are different, the types of the sub-pixels are increased, and differences exist in the lamination structure of each film layer or in the electrical influence, so that the display differences are easily perceived by human eyes due to the different lamination structures, and the viewing experience is easily influenced due to the deterioration of the display uniformity caused by the electrical influence. Specifically, a subpixel is considered to be a type if the opening size, opening direction, opening shape, and environment in which the subpixel is located are identical.

In this embodiment, the first reset connection portion 11 and the second reset connection portion 21 may increase the types of the sub-pixels, so as to avoid this, in the embodiment of the present invention, a row of pixel setting areas is spaced along the row direction x from the nearest neighboring two first reset connection portions 11 in the adjacent two first reset signal line groups, and a row of pixel setting areas is spaced along the row direction x from the nearest neighboring two second reset connection portions 21 in the adjacent two second reset signal line groups; the first reset connection parts 11 correspond to the same sub-pixels, and the projection positions and the projection shapes on the corresponding sub-pixels are the same; each second reset connection portion 21 corresponds to the same sub-pixel, and the projection position and the projection shape on the corresponding sub-pixel are the same.

Specifically, referring to fig. 16, when the first reset connection portion 11 and the second reset connection portion 21 are not provided, one pixel repeating unit includes two types of first sub-pixels 31 (two types of first sub-pixels 31 are included because four first sub-pixels 31 have two opening directions), one type of second sub-pixels 32, and one type of third sub-pixels 33. Because the pixel setting areas P corresponding to the first sub-pixels 31, the second sub-pixels 32 and the third sub-pixels 33 of the same type are respectively located in two adjacent rows of pixel setting areas, and are each separated by one row of pixel setting areas along the row direction y, in the embodiment of the invention, by setting the first reset connection portions 11 corresponding to two adjacent first reset signal line groups to be arranged in a staggered manner along the row direction y, and the two nearest neighboring first reset connection portions 11 in the two adjacent first reset signal line groups to be separated by one row of pixel setting areas along the row direction x, the second reset connection portions 21 corresponding to the two adjacent second reset signal line groups are arranged in a staggered manner along the row direction y, and the two nearest neighboring second reset connection portions 21 in the two adjacent second reset signal line groups are each separated by one row of pixel setting areas along the row direction x, the same reset connection portions can be arranged in the pixel setting areas P corresponding to the same sub-pixels, so that the first reset connection portions 11 are guaranteed to correspond to the same sub-pixels, projection positions and projection shapes of the same type on the corresponding sub-pixels are the same, the second reset connection portions 21 are respectively arranged in the row direction x, and the projection positions of the second reset connection portions corresponding to the two adjacent first reset signal line groups are prevented from being arranged in the row direction y, and the pixel setting areas are the same in the row direction x, and the pixel setting areas are arranged in the row by the row direction, and the pixel setting areas are arranged in the pixel setting in the row direction, and the pixel setting areas. The projection of the reset connection on the corresponding sub-pixel is understood to be the projection of the reset connection on the pixel opening of the corresponding sub-pixel.

In fig. 16, the first reset connection portions 11 are disposed corresponding to the pixel setting areas P of the second sub-pixels 32 in two adjacent first reset signal line groups, the second reset connection portions 21 are disposed corresponding to the pixel setting areas P of the third sub-pixels 33 in two adjacent second reset signal line groups, and the layout designs of the first reset connection portions 11 and the second reset connection portions 21 are the same, so that the environments of the two second sub-pixels 32 are unchanged, the environments of the two third sub-pixels 33 are unchanged, and the environments of the four first sub-pixels 31 are unchanged, so that the pixel repeating unit still has the two types of the first sub-pixels 31, the one type of the second sub-pixels 32 and the one type of the third sub-pixels 33, thereby avoiding the increase of the types of the sub-pixels and being beneficial to ensuring good display effect.

The structure shown in fig. 16 is only schematic, but not limited to, and fig. 17-19 are schematic diagrams of partial layout structures of display panels, showing three other possible arrangements of the first reset connection portion 11 and the second reset connection portion 21, which can also keep the types of sub-pixels arranged in diamonds from increasing, and ensure the display effect.

For example, referring to fig. 17, the first reset connection portions 11 are disposed corresponding to the pixel disposition regions P of the first sub-pixels (e.g., 3101) of one type among the optional adjacent two first reset signal line groups, and the second reset connection portions 21 are disposed corresponding to the pixel disposition regions P of the first sub-pixels (3102) of the other type among the adjacent two second reset signal line groups. In summary, fig. 16 and 17 may be arranged in a first offset arrangement manner, so that the first reset connection portions 11 and the second reset connection portions 21 are alternately arranged in the column direction y in a column of pixel arrangement regions, and a column of pixel arrangement regions is ensured between nearest neighboring reset connection portions in two adjacent reset signal line groups.

For example, referring to fig. 18, in optional two adjacent first reset signal line groups, the first reset connection portion 11 is disposed corresponding to the pixel disposition region P of one type of the first sub-pixel (e.g., 3101), and in two adjacent second reset signal line groups, the second reset connection portion 21 is disposed corresponding to the pixel disposition region P of the third sub-pixel 33; referring to fig. 19, the first reset connection portions 11 are each disposed corresponding to the pixel disposition region P of the second sub-pixel 32 in the optional two adjacent first reset signal line groups, and the second reset connection portions 21 are each disposed corresponding to the pixel disposition region P of the other type of the first sub-pixel (3102) in the two adjacent second reset signal line groups. In summary, fig. 18 and 19 may be arranged in a second staggered arrangement manner, so that the first reset connection portion 11 and the second reset connection portion 21 are located in the pixel arrangement regions P of different columns, and a row of pixel arrangement regions is ensured between the nearest neighboring reset connection portions in the adjacent two reset signal line groups.

Finally, referring to fig. 16 to 19, the anodes (e.g., the first anode 310, the second anode 320, and the third anode 330) of the light emitting element D are positioned on the anode metal layer on the side of the third metal layer M3 away from the substrate, and optionally the first reset connection 11 and the second reset connection 21 overlap with the orthographic projection of the anodes in the anode metal layer on the substrate to reduce the loss of light transmittance. The positions of the anodes of the light emitting elements D with respect to the pixel arrangement regions P are different in different pixel arrangements, and only the diamond arrangement is shown here as an example, and the present application is not limited thereto.

Based on the same inventive concept, the embodiment of the present application further provides a display device, and fig. 20 is a schematic structural diagram of the display device provided by the embodiment of the present application, where the display device 200 includes the display panel 100 provided by any one of the embodiments, so that the display device has the same beneficial effects as the display panel, and the same points can be referred to the description of the embodiment of the display panel and are not repeated herein. The display device 200 provided in the embodiment of the present application may be a mobile phone as shown in fig. 20, or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., which are not particularly limited in this embodiment of the application.

Further, fig. 21 is a schematic structural diagram of another display device according to an embodiment of the present invention, as shown in fig. 21, where the display device further includes a sensor 201; the display panel 100 further includes a sensor reserved area, and the sensor is disposed in the sensor reserved area; the first display area (a area) is multiplexed as a sensor reserved area.

The sensor is specifically a photosensitive sensor, and may be a fingerprint recognition sensor for fingerprint recognition, for example. By adopting the technical scheme, the light transmittance of the first display area is higher, the requirement of the fingerprint identification sensor on the light transmittance can be met, and meanwhile, the display uniformity can be ensured.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A display panel comprising a first display area, wherein the first display area in the display panel comprises:

a plurality of first reset signal lines and a plurality of second reset signal lines, wherein the plurality of first reset signal lines and the plurality of second reset signal lines extend along the row direction and are arranged along the column direction, and the pixel driving circuits positioned in the same row are electrically connected with the same first reset signal line and the same second reset signal line;

a plurality of first reset connection portions and a plurality of second reset connection portions; the first reset connecting part and the second reset connecting part extend along the column direction, the first reset connecting part is used for connecting two adjacent first reset signal lines, and the second reset connecting part is used for connecting two adjacent second reset signal lines; the sum of the numbers of the first reset connection parts between two adjacent first reset signal lines and the second reset connection parts between two adjacent second reset signal lines is smaller than the number of the pixel setting areas positioned in the same row;

The first reset connection parts corresponding to the adjacent two first reset signal line groups are arranged in a staggered manner along the column direction; the first reset signal line group comprises two adjacent first reset signal lines, and the two adjacent first reset signal line groups comprise the same first reset signal line;

the second reset connection parts corresponding to the two adjacent second reset signal line groups are arranged in a staggered manner along the column direction; the second reset signal line group comprises two adjacent second reset signal lines, and the two adjacent second reset signal line groups comprise the same second reset signal line;

the display panel comprises a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels;

the first subpixel is spaced apart from the second subpixel and the third subpixel, the second subpixel is spaced apart from the first subpixel and has a center at a first vertex of the virtual quadrilateral, and the third subpixel is spaced apart from the first subpixel and the second subpixel and has a center at a second vertex of the virtual quadrilateral, the first vertex and the second vertex being adjacent;

Four first sub-pixels, two second sub-pixels and two third sub-pixels form a pixel repeating unit; the pixel repeating units are correspondingly arranged with the pixel arrangement areas of two adjacent rows and four adjacent columns, four pixel driving circuits in the pixel arrangement area of the first row are respectively the pixel driving circuits of the second sub-pixel, the first sub-pixel, the third sub-pixel and the first sub-pixel, and four pixel driving circuits in the pixel arrangement area of the second row are respectively the pixel driving circuits of the third sub-pixel, the first sub-pixel, the second sub-pixel and the first sub-pixel;

the two nearest neighboring first reset connection parts in the two adjacent first reset signal line groups are separated by a row of pixel setting areas along the row direction, and the two nearest neighboring second reset connection parts in the two adjacent second reset signal line groups are separated by a row of pixel setting areas along the row direction;

the first reset connection parts correspond to the same sub-pixels, and the projection positions and the projection shapes on the corresponding sub-pixels are the same; the second reset connection parts correspond to the same sub-pixels, and the projection positions and the projection shapes on the corresponding sub-pixels are the same.

2. The display panel according to claim 1, wherein each pixel arrangement region in a column of the pixel arrangement regions is provided with the first reset connection portion correspondingly, or is provided with the second reset connection portion correspondingly;

the first reset connection parts adjacent along the column direction are communicated with each other to form a first reset connection line; the second reset connection parts adjacent along the column direction are mutually communicated to form a second reset connection line.

3. The display panel according to claim 2, wherein the first reset connection lines and the second reset connection lines are alternately arranged in the row direction.

4. A display panel according to claim 3, wherein n columns of the pixel arrangement regions are spaced between any one of the first reset connection lines and two adjacent second reset connection lines; wherein n is a positive integer.

5. The display panel according to claim 1, wherein the columns of the pixel arrangement regions located in the same row and spaced between two of the first reset connection portions adjacent in the row direction are the same;

the columns of the pixel setting areas which are positioned in the same row and are spaced between two adjacent second reset connection parts along the row direction are the same.

6. The display panel according to claim 1, wherein the first reset connection portions and the second reset connection portions are alternately arranged in the column direction within one column of the pixel arrangement region.

7. The display panel of claim 1, wherein the first reset connection and the second reset connection are located in different columns of the pixel arrangement areas.

8. The display panel according to claim 1, wherein the display panel includes a substrate and a driver circuit layer provided over the substrate, the driver circuit layer including a semiconductor layer, a first metal layer, a capacitor metal layer, a second metal layer, and a third metal layer which are stacked in a direction away from the substrate;

the first reset signal line and the second reset signal line are arranged on the same layer and are positioned on the first metal layer or the capacitance metal layer; the first reset connecting part and the second reset connecting part are arranged on the same layer and are positioned on the second metal layer or the third metal layer.

9. The display panel according to claim 8, wherein the pixel driving circuit includes a pixel semiconductor portion located in the semiconductor layer, the pixel semiconductor portion including a first node and a second node;

The display panel further comprises a first connecting bridge and a second connecting bridge which are positioned on the second metal layer, wherein the first node is electrically connected with the first reset signal line through the first connecting bridge, and the second node is electrically connected with the second reset signal line through the second connecting bridge;

the first reset connection part is positioned on the second metal layer and is used for partially multiplexing the first connection bridge; the second reset connection portion is located in the second metal layer and partially multiplexes the second connection bridge.

10. The display panel of claim 9, wherein the first reset connection is not in contact with the remaining conductive structures of the second metal layer except for the first connection bridge;

the second reset connection portion is not in contact with the rest of the conductive structures except the second connection bridge in the second metal layer.

11. The display panel of claim 9, wherein the capacitive metal layer comprises a capacitive plate and a shielding structure, the pixel semiconductor portion comprises a straight line portion having a top view projection on a side of the capacitive plate, and the display panel further comprises an anode metal layer on a side of the third metal layer away from the substrate;

The first reset connection portion and the second reset connection portion overlap with an orthographic projection of at least one of an anode of a light emitting element in the anode metal layer, a straight line portion in the pixel semiconductor portion, the capacitor plate, and the shielding structure on the substrate.

12. The display panel according to claim 9, wherein the pixel driving circuit includes a driving transistor for controlling lighting of a light emitting element, a first reset transistor for controlling a first reset signal on the first reset signal line to reset a gate potential of the driving transistor, and a second reset transistor for controlling a second reset signal on the second reset signal line to reset an anode potential of the light emitting element;

the display panel further comprises first scanning signal lines extending along the row direction and arranged along the column direction, wherein two adjacent first scanning signal lines along the column direction and the pixel semiconductor part have overlapping areas in the vertical direction of the plane of the substrate, and the two first scanning signal lines and the pixel semiconductor part respectively form the first reset transistor and the second reset transistor through the overlapping areas;

One end of the first reset transistor is electrically connected with the first node, and the other end of the first reset transistor is electrically connected with the grid electrode of the driving transistor; one end of the second reset transistor is electrically connected with the second node, and the other end of the second reset transistor is electrically connected with the anode of the light-emitting element.

13. The display panel according to claim 9, wherein the first node and the second node in the pixel semiconductor portion are located on opposite sides of the pixel semiconductor portion in a first direction, respectively, the first direction being parallel to the column direction or forming an acute angle with the column direction;

along the column direction, a group of reset signal line groups are respectively arranged on two opposite sides of the pixel semiconductor part, and each reset signal line group comprises a first reset signal line and a second reset signal line; the first node is electrically connected to a first reset signal line located at one side of the pixel semiconductor portion, and the second node is electrically connected to a second reset signal line located at the other side of the pixel semiconductor portion.

14. A display device comprising the display panel of any one of claims 1-13.

15. The display device according to claim 14, wherein the display device further comprises: a sensor;

The display panel further comprises a sensor reserved area, and the sensor is arranged in the sensor reserved area; the first display area is multiplexed to the sensor reserved area.