WO2018163938A1 - Active substrate and display device equipped with same - Google Patents

Active substrate and display device equipped with same Download PDF

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Publication number
WO2018163938A1
WO2018163938A1 PCT/JP2018/007596 JP2018007596W WO2018163938A1 WO 2018163938 A1 WO2018163938 A1 WO 2018163938A1 JP 2018007596 W JP2018007596 W JP 2018007596W WO 2018163938 A1 WO2018163938 A1 WO 2018163938A1
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Prior art keywords
shift register
scanning signal
output
active substrate
gate
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PCT/JP2018/007596
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French (fr)
Japanese (ja)
Inventor
崇嗣 楠見
卓哉 渡部
晶 田川
泰章 岩瀬
洋平 竹内
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シャープ株式会社
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Publication of WO2018163938A1 publication Critical patent/WO2018163938A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present invention relates to an active substrate in which a drive circuit for driving a scanning signal line is monolithically formed on a substrate, and a display device including the active substrate.
  • oxide semiconductor layers such as oxide semiconductor layers containing indium (In), gallium (Ga), and zinc (Zn) have been developed to improve performance and improve screen uniformity due to high mobility. Has been.
  • a gate driver monolithic that is, a gate driver is formed directly on the TFT array, thereby reducing the number of components and improving reliability. Yes.
  • gate drivers are formed on both sides of the display region, and each gate driver The gate signal is alternately input to the odd lines and even lines of the bus line to narrow the frame.
  • the gate signal may become larger due to the resistance and capacitance of the gate bus line, so that it is difficult to increase the driving speed.
  • Patent Document 1 discloses a technique for improving the characteristics of the gate signal and increasing the driving speed.
  • the output characteristics (signal rounding) of the gate driver are improved by using a reset TFT.
  • Japanese Patent Publication Japanese Patent Laid-Open No. 2010-20282 (published Jan. 28, 2010)”
  • One embodiment of the present invention provides an active substrate that can increase the drive speed by shortening the time until the reset TFT starts to operate and by accelerating the fall of the gate signal output from the shift register. The purpose is to do.
  • an active substrate includes a plurality of switching elements each including a semiconductor layer and a driving circuit that drives a plurality of scanning signal lines connected to each of the switching elements.
  • the drive circuit includes two shift register blocks each provided with a plurality of shift registers that output an output signal to one of the plurality of scanning signal lines.
  • the two shift register blocks are arranged so as to face each other through the active region in which the switching element is formed, the shift register provided in one of the two shift register blocks, and the other
  • the shift register provided in the circuit is alternately connected to the plurality of scanning signal lines, and is connected to the one shift register block.
  • a reset switching element is connected to the opposite side of the shift register block across the active region of the scanning signal line connected to the shift register, and the reset switching element is connected to the reset switching element. It is characterized in that it rises in synchronization with the falling edge of the scanning signal output to the scanning signal line, and that the rising edge and the falling edge are turned on by a steep signal.
  • FIG. 2 is a timing chart for explaining the circuit operation of the active substrate shown in FIG. 1.
  • FIG. 2 is a six-phase connection diagram of the active substrate shown in FIG. 1. It is a graph which shows the effect of the active substrate concerning Embodiment 1 of the present invention obtained by the simulation result. It is a graph which shows the size of reset TFT obtained from the simulation result, and the relationship between falling.
  • Embodiment 1 Hereinafter, embodiments of the present invention will be described in detail.
  • FIG. 3 is a schematic configuration diagram of the active substrate 101 according to the present embodiment.
  • the clock has three phases on one side, six phases on both sides, and duty 3/6.
  • the active substrate 101 includes a pixel region (active region) 10 and a shift register disposed opposite to each other through the pixel region 10 using amorphous silicon, polycrystalline silicon, CG silicon, microcrystalline silicon, or the like on a glass substrate. Blocks 11 and 12 are formed on the same substrate.
  • the active substrate 101 including an oxide semiconductor layer containing indium (In), gallium (Ga), and zinc (Zn) will be described. Thereby, power consumption can be significantly reduced.
  • the circuit since the mobility is high, the circuit can be made smaller and a narrower frame can be realized.
  • a plurality of pixels are arranged in a matrix, and a plurality of scanning signal lines Qn (n is an integer) for supplying a scanning signal to each pixel are formed.
  • This is an active region that is activated by supplying outputs (gate signals) from the shift register blocks 11 and 12 to the scanning signal line Qn.
  • the shift register block 11 includes a plurality of stages of shift registers 11a that output an output signal to one of the scanning signal lines Qn. Each shift register 11a is connected in cascade.
  • the shift register block 12 includes a plurality of stages of shift registers 12a that output an output signal to one of the scanning signal lines Qn. Each shift register 12a is connected in cascade.
  • the plurality of shift registers 11a included in the shift register block 11 are connected to the scanning signal lines Qn-4, Qn-2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, and Qn + 10 in the pixel region 10, respectively. That is, the plurality of shift registers 11a included in the shift register block 11 are connected to every other scanning signal line Qn.
  • the plurality of shift registers 12 a included in the shift register block 12 are connected to the scanning signal lines Qn ⁇ 3, Qn ⁇ 1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, and Qn + 9 in the pixel region 10. That is, the plurality of shift registers 12a included in the shift register block 12 are also connected to every other scanning signal line Qn.
  • Each shift register 11a of the shift register block 11 includes a set input terminal S, an output terminal Q, a reset input terminal R, a clock input terminal GCK, and a low power input terminal VSS.
  • the clock input terminal GCK is supplied with a clock signal GCK
  • the Low power input terminal VSS is supplied with a Low power supply VSS (for the sake of convenience, the same reference numeral as the Low power input terminal VSS) from a circuit (not shown).
  • the low power supply VSS may be a negative potential, a GND potential, or a positive potential. However, in order to surely turn off the TFT, it is set to a negative potential here.
  • each shift register 12a of the shift register block 12 has the same configuration as the shift register 11a, detailed description thereof is omitted.
  • the outputs from the output terminals Q of the Qn-4, Qn-2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, Qn + 10th stage shift registers 11a are the scanning signal lines Qn-4, Qn-, respectively. 2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, and scanning signal Qn-4, Qn-2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, and Qn + 10 output to Qn + 10.
  • the outputs from the output terminals Q of the Qn-3, Qn-1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, Qn + 9 stage shift registers 12a are the scanning signal lines Qn-3, Qn-, respectively.
  • 1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, and Qn + 9 are the scanning signals Qn-5, Qn-3, Qn-1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, and Qn + 9.
  • the shift register block 11 and the shift register block 12 together are in a state where all the shift registers are cascade-connected via the scanning signal line, and constitute one gate driver as a whole.
  • the scanning signal line connected to each shift register 11a of the shift register block 11 passes through the pixel region 10 on the side opposite to the shift register block 11 (shift register block 12 side).
  • a switching element 11b for resetting is provided for performing low drawing.
  • the scanning signal line connected to each shift register 12a of the shift register block 12 passes through the pixel region 10 on the side opposite to the shift register block 12 (shift register block 11 side).
  • a switching element 12b for resetting is provided for performing low pulling.
  • FIG. 1 is a schematic configuration diagram of the active substrate 101.
  • the shift register 11a outputs the scanning signal Qn and the shift register 12a outputs the scanning signal Qn + 1 will be described.
  • the shift registers 11a and 12a include transistors M1, M5, M6, M8, M9, M10, and M14, a capacitor CAP1, and a transistor M13, respectively. All the transistors are n-channel TFTs.
  • the Q-stage shift register 11a is configured as follows. That is, in the transistor M1, the gate is connected to the input terminal Qn-2, the drain is connected to the High power input terminal VDD, and the source is connected to the node netA and the drain of the transistor M9. In the transistor M5, the gate and drain are connected to the high power input terminal VDD, and the source is connected to the node netB. In the transistor M6, the gate is connected to the node netA, the drain is connected to the node netB, and the source is connected to the low power input terminal VSS. In the transistor M8, the gate is connected to the node netB, the drain is connected to the node netA, and the source is connected to the low power supply input terminal VSS.
  • the gate is connected to the input terminal Qn + 4, the drain is connected to the node netA, and the source is connected to the Low power input terminal VSS.
  • the gate is connected to the node netA, the drain is connected to the clock signal input terminal CKA, and the source is connected to the scanning signal line Qn.
  • the gate is connected to the node netB, the drain is connected to the scanning signal line Qn, and the source is connected to the Low power input terminal VSS.
  • the gate is connected to the input terminal Qn + 3, the drain is connected to the scanning signal line Qn, and the source is connected to the Low power input terminal VSS.
  • stage Qn + 1 stage shift register 12a is configured as follows. That is, in the transistor M1, the gate is connected to the input terminal Qn-1, the drain is connected to the High power input terminal VDD, and the source is connected to the node netA and the drain of the transistor M9. In the transistor M5, the gate and drain are connected to the high power input terminal VDD, and the source is connected to the node netB. In the transistor M6, the gate is connected to the node netA, the drain is connected to the node netB, and the source is connected to the low power input terminal VSS. In the transistor M8, the gate is connected to the node netB, the drain is connected to the node netA, and the source is connected to the low power supply input terminal VSS.
  • the gate is connected to the input terminal Qn + 5, the drain is connected to the node netA, and the source is connected to the Low power input terminal VSS.
  • the gate is connected to the node netA, the drain is connected to the clock signal input terminal CKA, and the source is connected to the scanning signal line Qn + 1.
  • the gate is connected to the node netB, the drain is connected to the scanning signal line Qn + 1, and the source is connected to the Low power input terminal VSS.
  • the gate is connected to the input terminal Qn + 4
  • the drain is connected to the scanning signal line Qn + 1, and the source is connected to the Low power input terminal VSS.
  • the output of the Qn stage shift register 11a is the scanning signal Qn
  • the Set signal (the signal input to the gate of the transistor M1) is the scanning signal Qn-2 output from the Qn-2 stage shift register 11a.
  • the signal for resetting the transistor M9 (signal input to the gate) is the scanning signal Qn + 4 output from the shift register 11a in the fourth stage, and the signal for resetting the transistor M13 (signal input to the gate) is the Qn + third stage.
  • the output of the Qn + 1 stage shift register 12a is the scanning signal Qn
  • the Set signal (the signal input to the gate of the transistor M1) is the scanning signal Qn-1 output from the Qn-1 stage shift register 12a, and the transistor M9.
  • the reset signal (signal input to the gate) is the scanning signal Qn + 5 output from the Qn + 5 stage shift register 12a
  • the reset signal (signal input to the gate) of the transistor M13 is the Qn + 4 stage shift.
  • the scanning signal Qn + 4 is output from the register 11a.
  • FIG. 2 shows a waveform diagram of each signal when the shift registers 11a and 12a are operating at this time.
  • FIG. 4 is a graph comparing the fall time of the gate output with and without the reset TFT (transistor M13) obtained by the simulation result.
  • the scanning signal outputted from the shift register is low-drawn on the self-stage side, and the scanning signal is not low-drawn on the opposite side through the pixel region.
  • the scanning signal output from the shift register is low-drawn on the self-stage side, and the scanning signal low-side drawing is also performed on the opposite side through the pixel region.
  • the signal immediately after the output of the shift register on the opposite side (the signal having a sharp rise and fall) is input to the gate of the reset TFT via the pixel area of the shift register of its own stage, It becomes possible to make the fall more steep.
  • the gate output can be lowered more quickly when the transistor M13 is provided as a reset TFT than when the transistor M13 is not provided. Thereby, the driving speed of the display device on which the active substrate 101 is mounted can be increased.
  • FIG. 5 is a graph showing the relationship between the size of the reset TFT and the fall time of the scanning signal, obtained from the simulation results. From this graph, it can be seen that when the width W of the reset TFT is 400 ⁇ m, it is less than the target fall time at the screen edge, immediately after the GDM output (immediately after the shift register output), and at the center of the screen. Note that the width W of the reset TFT is not limited to 400 ⁇ m, and varies depending on the set value of the target fall time or the like.
  • the clock has been described as having 6 phases and duty 3/6, but the present invention is not limited to this, and the clock needs to be an even number of 6 phases or more and the numerator of the duty must be an odd number. Good.
  • FIG. 6 is a schematic configuration diagram of an active substrate 201 according to the present embodiment.
  • the clock has four phases on one side, eight phases on both sides, and duty 4/8.
  • the active substrate 201 uses a glass substrate made of amorphous silicon, polycrystalline silicon, CG silicon, microcrystalline silicon, or the like to form a pixel region (active region) 20 and a pixel region.
  • Shift register blocks 21 and 22 arranged to face each other via 20 are formed on the same substrate.
  • a plurality of pixels are arranged in a matrix, and a plurality of scanning signal lines Qn (n is an integer) for supplying a scanning signal to each pixel are formed.
  • This is an active region that is activated by supplying outputs (gate signals) from the shift register blocks 21 and 22 to the scanning signal line Qn.
  • the shift register block 21 includes a plurality of stages of shift registers 21a for outputting an output signal to one of the scanning signal lines Qn. Each shift register 21a is connected in cascade.
  • the shift register block 22 includes a plurality of stages of shift registers 22a that output an output signal to one of the scanning signal lines Qn. Each shift register 22a is connected in cascade.
  • the plurality of shift registers 21 a included in the shift register block 21 are connected to the scanning signal lines Qn ⁇ 4, Qn ⁇ 2, Qn, Qn + 2, Qn + 4, Qn + 6, and Qn + 8 in the pixel region 20, respectively. That is, the plurality of shift registers 21a included in the shift register block 21 are connected to every other scanning signal line Qn.
  • the plurality of shift registers 22a included in the shift register block 22 are connected to the scanning signal lines Qn-5, Qn-3, Qn-1, Qn + 1, Qn + 3, Qn + 5, and Qn + 7 of the pixel region 20, respectively. That is, the plurality of shift registers 22a included in the shift register block 22 are also connected to every other scanning signal line Qn.
  • Each shift register 21a of the shift register block 21 includes a set input terminal S, an output terminal Q, a reset input terminal R, a clock input terminal GCK, and a Low power input terminal VSS.
  • the clock input terminal GCK is supplied with a clock signal GCK
  • the Low power input terminal VSS is supplied with a Low power supply VSS (for the sake of convenience, the same reference numeral as the Low power input terminal VSS) from a circuit (not shown).
  • the low power supply VSS may be a negative potential, a GND potential, or a positive potential. However, in order to surely turn off the TFT, it is set to a negative potential here.
  • each shift register 22a of the shift register block 22 has the same configuration as the shift register 21a, detailed description thereof is omitted.
  • the outputs from the output terminals Q of the Qn-4, Qn-2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, and Q + 10 stage shift registers 21a are the scanning signal lines Qn-4 and Qn-, respectively.
  • 2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, and Q + 10 are output as scanning signals Qn-4, Qn-2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, and Q + 10.
  • the outputs from the output terminal Q of the Qn-3, Qn-1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, Q + 9 stage shift register 22a are the scanning signal lines Qn-3, Qn-, respectively.
  • the scanning signals Qn ⁇ 3, Qn ⁇ 1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, and Q + 9 output to 1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, and Q + 9 are obtained.
  • the shift register block 21 and the shift register block 22 together are in a state where all the shift registers are cascade-connected via the scanning signal lines, and constitute one gate driver as a whole.
  • the scanning signal line connected to each shift register 21a of the shift register block 21 passes through the pixel region 20 to the side opposite to the shift register block 21 (shift register block 22 side).
  • a switching element 21b for resetting is provided for performing low drawing.
  • the scanning signal line connected to each shift register 22a of the shift register block 22 passes through the pixel region 20 to the opposite side of the shift register block 22 (shift register block 21 side).
  • a switching element 22b for resetting is provided for performing low pulling.
  • the active substrate 201 having the above configuration also includes a reset TFT (transistor M13).
  • the gate of the transistor M13 is connected to the shift register of its own stage via the pixel region 20. Since the signal immediately after the output of the shift register on the opposite side (signal with a sharp rise) is input, there is an effect that the fall of the scanning signal can be made steeper.
  • FIG. 7 is a diagram illustrating a schematic configuration of a liquid crystal display device 1 as an example of a display device including the active substrate 101 according to the first embodiment.
  • the liquid crystal display device 1 includes an active substrate 101, a flexible printed circuit board 102, and a control substrate 103 that constitute a display panel.
  • the pixel region 10 of the active substrate 101 is a region where a plurality of pixels PIX... Are arranged in a matrix.
  • the pixel PIX includes a TFT 21, which is a picture element selection element, a liquid crystal capacitor CL, and an auxiliary capacitor Cs.
  • the gate of the TFT 21 is connected to a gate line (scanning signal line) GL, and the source of the TFT 21 is connected to a source line (data signal line) SL.
  • the liquid crystal capacitor CL and the auxiliary capacitor Cs are connected to the drain of the TFT 21.
  • the plurality of gate lines GL are gate lines GL1, GL2, GL3,... GLn, and gate lines GL1, GL3, GL5,. Connected to the output of the shift register block 11 as a driver, the second group of gate lines GL... Consisting of the remaining gate lines GL2, GL4, GL6. Connected to the output of block 12.
  • the plurality of source lines SL are composed of source lines SL1, SL2, SL3,..., SLm, and are connected to the output of the source driver 13 described later.
  • the falling edge of the scanning signal can be made steep, so that the liquid crystal display device 1 can be driven at high speed. Can do.
  • active substrate 201 described in the second embodiment may be used instead of the active substrate 101.
  • An active substrate (101, 201) includes a plurality of switching elements including a semiconductor layer and a driving circuit (shift register block) for driving a plurality of scanning signal lines connected to each of the switching elements.
  • 11 and 12) are active substrates (101, 201) formed on the same substrate, and the drive circuit (shift register blocks 11, 12) outputs an output signal to one of the plurality of scanning signal lines.
  • Shift registers 11a and 12a include two shift register blocks 11 and 12 each having a plurality of stages, and the two shift register blocks 11 and 12 include active regions (pixel regions) in which the switching elements are formed. 10) and arranged to face each other and provided in one of the two shift register blocks 11 and 12.
  • the shift register 11 a and the shift register 12 a provided on the other side are alternately connected to the plurality of scanning signal lines, and the scanning signal is connected to the shift register 11 a included in the one shift register block 11.
  • a switching element 11b for reset is connected to the opposite side of the shift register block 11 across the active area (pixel area 10) of the line, and the switching element 11b is connected to the switching element 11b for reset. It is characterized in that it rises in synchronization with the falling edge of the scanning signal output to the scanning signal line and is turned on by a signal whose rising edge is steep.
  • the reset switching element connected to the opposite side of the shift register block via the active region of the scanning signal line connected to the shift register included in one shift register block is The time when the scanning signal falls can be shortened by being turned on by a signal that rises and rises in synchronism with the falling edge of the scanning signal output to the scanning signal line to which the switching element is connected. . That is, there is no delay until the reset by the reset switching element starts to work.
  • the active substrate according to aspect 2 of the present invention is the active substrate according to aspect 1, wherein the reset switching elements 11b and 12b are different from the shift register 11a and 12a to which the switching elements 11b and 12b are connected. It may be turned on by a signal immediately after the output of the shift registers 11a and 12a on the opposite side across 10).
  • clock signals of three phases or more may be input to the two shift register blocks 11 and 12, respectively.
  • An active substrate according to aspect 4 of the present invention is provided in any one of the aspects 1 to 3 described above, in each of the semiconductor layers provided in each of the plurality of switching elements and in each transistor of the shift registers 11a and 12a.
  • the semiconductor layer may be an oxide semiconductor layer.
  • the oxide semiconductor layer may include indium, gallium, and zinc.
  • Liquid crystal display device (display device) 10 pixel area (active area) 11.12 Shift register block 11a, 12a Shift register 11b, 12b Switching element 20 Pixel region (active region) 21/22 Shift register block 21a / 22a Shift register 21b / 22b Switching element 101/201 Active substrate

Abstract

The purpose of the present invention is to increase the fall rate of a gate signal output from a shift register. A signal immediately after an output from a shift register (12a) in a shift resister block (12) turns on a reset switching element (11b) connected opposite a scanning signal line connected to a shift register (11a) in a shift register block (11) across a pixel region (10) on an active substrate (102).

Description

アクティブ基板、それを備えた表示装置Active substrate and display device including the same
　本発明は、走査信号線を駆動する駆動回路が基板上にモノリシックに形成されたアクティブ基板及び上記アクティブ基板を備えた表示装置に関する。 The present invention relates to an active substrate in which a drive circuit for driving a scanning signal line is monolithically formed on a substrate, and a display device including the active substrate.
　近年、高移動度による性能向上、画面均一性の向上などから、酸化物半導体層、例えばインジウム（Ｉｎ）、ガリウム（Ｇａ）及び亜鉛（Ｚｎ）を含む酸化物半導体層を備えたＴＦＴアレイが開発されている。 In recent years, TFT arrays with oxide semiconductor layers, such as oxide semiconductor layers containing indium (In), gallium (Ga), and zinc (Zn), have been developed to improve performance and improve screen uniformity due to high mobility. Has been.
　酸化物半導体層を備えたＴＦＴアレイにおいては、ゲートドライバモノリシック（以下、ＧＤＭと称する）、すなわち、ゲートドライバをＴＦＴアレイ上に直接形成することにより、部品点数の削減、信頼性向上を実現している。 In a TFT array including an oxide semiconductor layer, a gate driver monolithic (hereinafter referred to as GDM), that is, a gate driver is formed directly on the TFT array, thereby reducing the number of components and improving reliability. Yes.
　上記のようなＴＦＴアレイを用いた表示装置を、例えばノートパソコンのモニタ等のような小型サイズの表示装置に適用した場合、表示領域の両側にゲートドライバを形成し、それぞれのゲートドライバから、ゲートバスラインの奇数行、偶数行で交互にゲート信号を入力するようにして、狭額縁化を図っている。 When the display device using the TFT array as described above is applied to a small-sized display device such as a monitor of a notebook personal computer, gate drivers are formed on both sides of the display region, and each gate driver The gate signal is alternately input to the odd lines and even lines of the bus line to narrow the frame.
　しかしながら、ゲートバスラインが長くなれば、ゲートバスラインの抵抗および容量により、ゲート信号が大きくなまる虞があるため、駆動の高速化を図ることが難しい。 However, if the gate bus line becomes longer, the gate signal may become larger due to the resistance and capacitance of the gate bus line, so that it is difficult to increase the driving speed.
　そこで、ゲート信号の特性を改善し、駆動の高速化を図るための技術が、例えば特許文献１に開示されている。特許文献１に開示されたゲートドライバでは、リセット用のＴＦＴを用いて、ゲートドライバの出力特性（信号のなまり）を改善している。 Therefore, for example, Patent Document 1 discloses a technique for improving the characteristics of the gate signal and increasing the driving speed. In the gate driver disclosed in Patent Document 1, the output characteristics (signal rounding) of the gate driver are improved by using a reset TFT.
日本国公開特許公報「特開２０１０－２０２８２号公報（２０１０年１月２８日公開）」Japanese Patent Publication “Japanese Patent Laid-Open No. 2010-20282 (published Jan. 28, 2010)”
　しかしながら、特許文献１のゲートドライバでは、ある程度のゲート信号の特性は改善されるものの、リセット用のＴＦＴのゲートには、ゲートバスラインを通ったシフトレジスタの出力が入力されるため、リセット用のＴＦＴが効き始めるまでに時間を要する。この結果、シフトレジスタが出力したゲート信号の立ち下がりが遅くなるため、駆動の高速化を図るのが難しい。 However, in the gate driver of Patent Document 1, although the characteristics of the gate signal are improved to some extent, the output of the shift register that has passed through the gate bus line is input to the gate of the reset TFT. It takes time for the TFT to start working. As a result, the fall of the gate signal output from the shift register is delayed, and it is difficult to increase the driving speed.
　本発明の一態様は、リセット用のＴＦＴが効き始めるまでの時間を短くして、シフトレジスタが出力したゲート信号の立ち下がりを速くすることで、駆動の高速化を可能とするアクティブ基板を提供することを目的とする。 One embodiment of the present invention provides an active substrate that can increase the drive speed by shortening the time until the reset TFT starts to operate and by accelerating the fall of the gate signal output from the shift register. The purpose is to do.
　上記の課題を解決するために、本発明の一態様に係るアクティブ基板は、半導体層を備えた複数のスイッチング素子と、上記スイッチング素子の各々に接続された複数の走査信号線を駆動する駆動回路とが、同一基板上に形成されたアクティブ基板であって、上記駆動回路は、上記複数の走査信号線の一つに出力信号を出力するシフトレジスタが、複数段備えられたシフトレジスタブロックを２個含み、上記２個のシフトレジスタブロックは、上記スイッチング素子が形成されたアクティブ領域を介して、対向するように配置され、上記２個のシフトレジスタブロックの一方に備えられたシフトレジスタと、他方に備えられたシフトレジスタは、上記複数の走査信号線に対して交互に接続されており、上記一方のシフトレジスタブロックに含まれるシフトレジスタに接続された走査信号線の、上記アクティブ領域を挟んで、当該シフトレジスタブロックと反対側にリセット用のスイッチング素子が接続され、上記リセット用のスイッチング素子は、当該スイッチング素子が接続された走査信号線に出力された走査信号の立ち下がりに同期して立ち上がり、且つ立ち上がりおよび立ち下がりが急峻な信号によりオンされることを特徴としている。 In order to solve the above problems, an active substrate according to one embodiment of the present invention includes a plurality of switching elements each including a semiconductor layer and a driving circuit that drives a plurality of scanning signal lines connected to each of the switching elements. Are active substrates formed on the same substrate, and the drive circuit includes two shift register blocks each provided with a plurality of shift registers that output an output signal to one of the plurality of scanning signal lines. The two shift register blocks are arranged so as to face each other through the active region in which the switching element is formed, the shift register provided in one of the two shift register blocks, and the other The shift register provided in the circuit is alternately connected to the plurality of scanning signal lines, and is connected to the one shift register block. A reset switching element is connected to the opposite side of the shift register block across the active region of the scanning signal line connected to the shift register, and the reset switching element is connected to the reset switching element. It is characterized in that it rises in synchronization with the falling edge of the scanning signal output to the scanning signal line, and that the rising edge and the falling edge are turned on by a steep signal.
　本発明の一態様によれば、リセット用のＴＦＴが効き始めるまでの時間を短くして、シフトレジスタが出力したゲート信号の立ち下がりを速くすることで、駆動の高速化を可能にできるという効果を奏する。 According to one embodiment of the present invention, it is possible to increase the drive speed by shortening the time until the reset TFT starts to be effective and increasing the fall of the gate signal output from the shift register. Play.
本発明の実施形態１に係るアクティブ基板の概略構成ブロック図である。It is a schematic block diagram of the active substrate which concerns on Embodiment 1 of this invention. 図１に示すアクティブ基板の回路動作を説明するタイミングチャートである。2 is a timing chart for explaining the circuit operation of the active substrate shown in FIG. 1. 図１に示すアクティブ基板の６相結線図である。FIG. 2 is a six-phase connection diagram of the active substrate shown in FIG. 1. シミュレーション結果によって得られた、本発明の実施形態１に係るアクティブ基板の効果をグラフである。It is a graph which shows the effect of the active substrate concerning Embodiment 1 of the present invention obtained by the simulation result. シミュレーション結果によって得られた、リセットＴＦＴのサイズと立ち下げの関係を示すグラフである。It is a graph which shows the size of reset TFT obtained from the simulation result, and the relationship between falling. 本発明の実施形態２に係るアクティブ基板の８相結線図である。It is an 8-phase connection diagram of the active substrate which concerns on Embodiment 2 of this invention. 図１に示すアクティブ基板を用いた液晶表示装置の概略構成図である。It is a schematic block diagram of the liquid crystal display device using the active substrate shown in FIG.
　〔実施形態１〕
　以下、本発明の実施の形態について、詳細に説明する。 Embodiment 1
Hereinafter, embodiments of the present invention will be described in detail.
　（アクティブ基板の概要）
　図３は、本実施形態に係るアクティブ基板１０１の概略構成図である。本実施形態では、クロックは片側３相、両側６相、ｄｕｔｙ３／６とする。 (Outline of active substrate)
FIG. 3 is a schematic configuration diagram of the active substrate 101 according to the present embodiment. In this embodiment, the clock has three phases on one side, six phases on both sides, and duty 3/6.
　アクティブ基板１０１は、ガラス基板上にアモルファスシリコン、多結晶シリコン、ＣＧシリコン、微結晶シリコンなどを用いて画素領域（アクティブ領域）１０、および、画素領域１０を介して対向して配置されたシフトレジスタブロック１１・１２が同一基板上に形成されている。本実施形態では、インジウム（Ｉｎ）、ガリウム（Ｇａ）及び亜鉛（Ｚｎ）を含む酸化物半導体層を備えたアクティブ基板１０１として説明する。これにより、消費電力を大幅に削減することが可能になる。しかも、移動度が高いため、より回路が小さくでき、より狭額縁化を実現出来る。 The active substrate 101 includes a pixel region (active region) 10 and a shift register disposed opposite to each other through the pixel region 10 using amorphous silicon, polycrystalline silicon, CG silicon, microcrystalline silicon, or the like on a glass substrate. Blocks 11 and 12 are formed on the same substrate. In this embodiment, the active substrate 101 including an oxide semiconductor layer containing indium (In), gallium (Ga), and zinc (Zn) will be described. Thereby, power consumption can be significantly reduced. In addition, since the mobility is high, the circuit can be made smaller and a narrower frame can be realized.
　画素領域１０は、複数の画素（図示せず）がマトリクス状に配置されており、各画素に走査信号を供給するための複数ラインの走査信号線Ｑｎ（ｎは、整数）が形成され、これら走査信号線Ｑｎに、シフトレジスタブロック１１・１２からの出力（ゲート信号）を供給することにより、アクティブになるアクティブ領域である。 In the pixel region 10, a plurality of pixels (not shown) are arranged in a matrix, and a plurality of scanning signal lines Qn (n is an integer) for supplying a scanning signal to each pixel are formed. This is an active region that is activated by supplying outputs (gate signals) from the shift register blocks 11 and 12 to the scanning signal line Qn.
　シフトレジスタブロック１１は、走査信号線Ｑｎの一つに出力信号を出力するシフトレジスタ１１ａを複数段備えている。各シフトレジスタ１１ａは、縦続接続されている。同様に、シフトレジスタブロック１２は、走査信号線Ｑｎの一つに出力信号を出力するシフトレジスタ１２ａを複数段備えている。各シフトレジスタ１２ａは、縦続接続されている。 The shift register block 11 includes a plurality of stages of shift registers 11a that output an output signal to one of the scanning signal lines Qn. Each shift register 11a is connected in cascade. Similarly, the shift register block 12 includes a plurality of stages of shift registers 12a that output an output signal to one of the scanning signal lines Qn. Each shift register 12a is connected in cascade.
　シフトレジスタブロック１１が備える複数のシフトレジスタ１１ａは、画素領域１０の走査信号線Ｑｎ－４、Ｑｎ－２、Ｑｎ、Ｑｎ＋２、Ｑｎ＋４、Ｑｎ＋６、Ｑｎ＋８、Ｑｎ＋１０のそれぞれに接続されている。つまり、シフトレジスタブロック１１が備える複数のシフトレジスタ１１ａは、走査信号線Ｑｎを一つおきに接続されていることになる。 The plurality of shift registers 11a included in the shift register block 11 are connected to the scanning signal lines Qn-4, Qn-2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, and Qn + 10 in the pixel region 10, respectively. That is, the plurality of shift registers 11a included in the shift register block 11 are connected to every other scanning signal line Qn.
　同様に、シフトレジスタブロック１２が備える複数のシフトレジスタ１２ａは、画素領域１０の走査信号線Ｑｎ－３、Ｑｎ－１、Ｑｎ＋１、Ｑｎ＋３、Ｑｎ＋５、Ｑｎ＋７、Ｑｎ＋９のそれぞれに接続されている。つまり、シフトレジスタブロック１２が備える複数のシフトレジスタ１２ａも、走査信号線Ｑｎを一つおきに接続されていることになる。 Similarly, the plurality of shift registers 12 a included in the shift register block 12 are connected to the scanning signal lines Qn−3, Qn−1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, and Qn + 9 in the pixel region 10. That is, the plurality of shift registers 12a included in the shift register block 12 are also connected to every other scanning signal line Qn.
　シフトレジスタブロック１１の各シフトレジスタ１１ａは、セット入力端子Ｓ、出力端子Ｑ、リセット入力端子Ｒ、クロック入力端子ＧＣＫ、および、Ｌｏｗ電源入力端子ＶＳＳを備えている。クロック入力端子ＧＣＫには、クロック信号ＧＣＫ、Ｌｏｗ電源入力端子ＶＳＳには、Ｌｏｗ電源ＶＳＳ（便宜上、Ｌｏｗ電源入力端子ＶＳＳと同じ符号で代用する）が図示ない回路から供給される。Ｌｏｗ電源ＶＳＳは負電位でもよいし、ＧＮＤ電位でも、正電位でもよいが、ＴＦＴを確実にＯＦＦ状態とするためにここでは負電位とする。 Each shift register 11a of the shift register block 11 includes a set input terminal S, an output terminal Q, a reset input terminal R, a clock input terminal GCK, and a low power input terminal VSS. The clock input terminal GCK is supplied with a clock signal GCK, and the Low power input terminal VSS is supplied with a Low power supply VSS (for the sake of convenience, the same reference numeral as the Low power input terminal VSS) from a circuit (not shown). The low power supply VSS may be a negative potential, a GND potential, or a positive potential. However, in order to surely turn off the TFT, it is set to a negative potential here.
　シフトレジスタブロック１２の各シフトレジスタ１２ａは、シフトレジスタ１１ａと同じ構成であるため、詳細な説明は省略する。 Since each shift register 12a of the shift register block 12 has the same configuration as the shift register 11a, detailed description thereof is omitted.
　シフトレジスタブロック１１において、Ｑｎ－４、Ｑｎ－２、Ｑｎ、Ｑｎ＋２、Ｑｎ＋４、Ｑｎ＋６、Ｑｎ＋８、Ｑｎ＋１０段目のシフトレジスタ１１ａの出力端子Ｑからの出力は、それぞれ走査信号線Ｑｎ－４、Ｑｎ－２、Ｑｎ、Ｑｎ＋２、Ｑｎ＋４、Ｑｎ＋６、Ｑｎ＋８、Ｑｎ＋１０に出力される走査信号Ｑｎ－４、Ｑｎ－２、Ｑｎ、Ｑｎ＋２、Ｑｎ＋４、Ｑｎ＋６、Ｑｎ＋８、Ｑｎ＋１０となる。 In the shift register block 11, the outputs from the output terminals Q of the Qn-4, Qn-2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, Qn + 10th stage shift registers 11a are the scanning signal lines Qn-4, Qn-, respectively. 2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, and scanning signal Qn-4, Qn-2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, and Qn + 10 output to Qn + 10.
　一方、シフトレジスタブロック１２において、Ｑｎ－３、Ｑｎ－１、Ｑｎ＋１、Ｑｎ＋３、Ｑｎ＋５、Ｑｎ＋７、Ｑｎ＋９段目のシフトレジスタ１２ａの出力端子Ｑからの出力は、それぞれ走査信号線Ｑｎ－３、Ｑｎ－１、Ｑｎ＋１、Ｑｎ＋３、Ｑｎ＋５、Ｑｎ＋７、Ｑｎ＋９に出力される走査信号Ｑｎ－５、Ｑｎ－３、Ｑｎ－１、Ｑｎ＋１、Ｑｎ＋３、Ｑｎ＋５、Ｑｎ＋７、Ｑｎ＋９となる。 On the other hand, in the shift register block 12, the outputs from the output terminals Q of the Qn-3, Qn-1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, Qn + 9 stage shift registers 12a are the scanning signal lines Qn-3, Qn-, respectively. 1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, and Qn + 9 are the scanning signals Qn-5, Qn-3, Qn-1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, and Qn + 9.
　シフトレジスタブロック１１とシフトレジスタブロック１２とを合わせて、全てのシフトレジスタが走査信号線を介して縦続接続された状態となっており、全体で１つのゲートドライバを構成している。 The shift register block 11 and the shift register block 12 together are in a state where all the shift registers are cascade-connected via the scanning signal line, and constitute one gate driver as a whole.
　また、シフトレジスタブロック１１の各シフトレジスタ１１ａに接続された走査信号線の、上記画素領域１０を介して、当該シフトレジスタブロック１１と反対側（シフトレジスタブロック１２側）に、当該走査信号線のロー引きを行うための、リセット用のスイッチング素子１１ｂが設けられている。同様に、シフトレジスタブロック１２の各シフトレジスタ１２ａに接続された走査信号線の、上記画素領域１０を介して、当該シフトレジスタブロック１２と反対側（シフトレジスタブロック１１側）に、当該走査信号線のロー引きを行うための、リセット用のスイッチング素子１２ｂが設けられている。 In addition, the scanning signal line connected to each shift register 11a of the shift register block 11 passes through the pixel region 10 on the side opposite to the shift register block 11 (shift register block 12 side). A switching element 11b for resetting is provided for performing low drawing. Similarly, the scanning signal line connected to each shift register 12a of the shift register block 12 passes through the pixel region 10 on the side opposite to the shift register block 12 (shift register block 11 side). A switching element 12b for resetting is provided for performing low pulling.
　（アクティブ基板の詳細）
　図１は、アクティブ基板１０１の概略構成図である。ここでは、シフトレジスタ１１ａが走査信号Ｑｎを出力し、シフトレジスタ１２ａが走査信号Ｑｎ＋１を出力する例について説明する。 (Details of active substrate)
FIG. 1 is a schematic configuration diagram of the active substrate 101. Here, an example in which the shift register 11a outputs the scanning signal Qn and the shift register 12a outputs the scanning signal Qn + 1 will be described.
　シフトレジスタ１１ａ、１２ａは、それぞれトランジスタＭ１、Ｍ５、Ｍ６、Ｍ８、Ｍ９、Ｍ１０、Ｍ１４、容量ＣＡＰ１、およびトランジスタＭ１３を備えている。上記トランジスタは全てｎチャネル型のＴＦＴである。 The shift registers 11a and 12a include transistors M1, M5, M6, M8, M9, M10, and M14, a capacitor CAP1, and a transistor M13, respectively. All the transistors are n-channel TFTs.
　具体的には、Ｑ段のシフトレジスタ１１ａは、以下のように構成されている。すなわち、トランジスタＭ１において、ゲートは入力端子Ｑｎ－２に接続され、ドレインはＨｉｇｈ電源入力端子ＶＤＤに接続され、ソースはノードｎｅｔＡおよびトランジスタＭ９のドレインに接続されている。トランジスタＭ５において、ゲートおよびドレインはＨｉｇｈ電源入力端子ＶＤＤに接続され、ソースはノードｎｅｔＢに接続されている。トランジスタＭ６において、ゲートはノードｎｅｔＡに接続され、ドレインはノードｎｅｔＢに接続され、ソースはＬｏｗ電源入力端子ＶＳＳに接続されている。トランジスタＭ８において、ゲートはノードｎｅｔＢに接続され、ドレインはノードｎｅｔＡに接続され、ソースはＬｏｗ電源入力端子ＶＳＳに接続されている。トランジスタＭ９において、ゲートは入力端子Ｑｎ＋４に接続され、ドレインはノードｎｅｔＡに接続され、ソースはＬｏｗ電源入力端子ＶＳＳに接続されている。トランジスタＭ１０において、ゲートはノードｎｅｔＡに接続され、ドレインはクロック信号入力端子ＣＫＡに接続され、ソースは走査信号線Ｑｎに接続されている。トランジスタＭ１４において、ゲートはノードｎｅｔＢに接続され、ドレインは走査信号線Ｑｎに接続され、ソースはＬｏｗ電源入力端子ＶＳＳに接続されている。さらに、トランジスタＭ１３において、ゲートは入力端子Ｑｎ＋３に接続され、ドレインは走査信号線Ｑｎに接続され、ソースはＬｏｗ電源入力端子ＶＳＳに接続されている。 Specifically, the Q-stage shift register 11a is configured as follows. That is, in the transistor M1, the gate is connected to the input terminal Qn-2, the drain is connected to the High power input terminal VDD, and the source is connected to the node netA and the drain of the transistor M9. In the transistor M5, the gate and drain are connected to the high power input terminal VDD, and the source is connected to the node netB. In the transistor M6, the gate is connected to the node netA, the drain is connected to the node netB, and the source is connected to the low power input terminal VSS. In the transistor M8, the gate is connected to the node netB, the drain is connected to the node netA, and the source is connected to the low power supply input terminal VSS. In the transistor M9, the gate is connected to the input terminal Qn + 4, the drain is connected to the node netA, and the source is connected to the Low power input terminal VSS. In the transistor M10, the gate is connected to the node netA, the drain is connected to the clock signal input terminal CKA, and the source is connected to the scanning signal line Qn. In the transistor M14, the gate is connected to the node netB, the drain is connected to the scanning signal line Qn, and the source is connected to the Low power input terminal VSS. Further, in the transistor M13, the gate is connected to the input terminal Qn + 3, the drain is connected to the scanning signal line Qn, and the source is connected to the Low power input terminal VSS.
　次段のＱｎ＋１段のシフトレジスタ１２ａ以下のように構成されている。すなわち、トランジスタＭ１において、ゲートは入力端子Ｑｎ－１に接続され、ドレインはＨｉｇｈ電源入力端子ＶＤＤに接続され、ソースはノードｎｅｔＡおよびトランジスタＭ９のドレインに接続されている。トランジスタＭ５において、ゲートおよびドレインはＨｉｇｈ電源入力端子ＶＤＤに接続され、ソースはノードｎｅｔＢに接続されている。トランジスタＭ６において、ゲートはノードｎｅｔＡに接続され、ドレインはノードｎｅｔＢに接続され、ソースはＬｏｗ電源入力端子ＶＳＳに接続されている。トランジスタＭ８において、ゲートはノードｎｅｔＢに接続され、ドレインはノードｎｅｔＡに接続され、ソースはＬｏｗ電源入力端子ＶＳＳに接続されている。トランジスタＭ９において、ゲートは入力端子Ｑｎ＋５に接続され、ドレインはノードｎｅｔＡに接続され、ソースはＬｏｗ電源入力端子ＶＳＳに接続されている。トランジスタＭ１０において、ゲートはノードｎｅｔＡに接続され、ドレインはクロック信号入力端子ＣＫＡに接続され、ソースは走査信号線Ｑｎ＋１に接続されている。トランジスタＭ１４において、ゲートはノードｎｅｔＢに接続され、ドレインは走査信号線Ｑｎ＋１に接続され、ソースはＬｏｗ電源入力端子ＶＳＳに接続されている。さらに、トランジスタＭ１３において、ゲートは入力端子Ｑｎ＋４に接続され、ドレインは走査信号線Ｑｎ＋１に接続され、ソースはＬｏｗ電源入力端子ＶＳＳに接続されている。 The following stage Qn + 1 stage shift register 12a is configured as follows. That is, in the transistor M1, the gate is connected to the input terminal Qn-1, the drain is connected to the High power input terminal VDD, and the source is connected to the node netA and the drain of the transistor M9. In the transistor M5, the gate and drain are connected to the high power input terminal VDD, and the source is connected to the node netB. In the transistor M6, the gate is connected to the node netA, the drain is connected to the node netB, and the source is connected to the low power input terminal VSS. In the transistor M8, the gate is connected to the node netB, the drain is connected to the node netA, and the source is connected to the low power supply input terminal VSS. In the transistor M9, the gate is connected to the input terminal Qn + 5, the drain is connected to the node netA, and the source is connected to the Low power input terminal VSS. In the transistor M10, the gate is connected to the node netA, the drain is connected to the clock signal input terminal CKA, and the source is connected to the scanning signal line Qn + 1. In the transistor M14, the gate is connected to the node netB, the drain is connected to the scanning signal line Qn + 1, and the source is connected to the Low power input terminal VSS. Further, in the transistor M13, the gate is connected to the input terminal Qn + 4, the drain is connected to the scanning signal line Qn + 1, and the source is connected to the Low power input terminal VSS.
　上記構成において、Ｑｎ段のシフトレジスタ１１ａの出力は走査信号Ｑｎ、Ｓｅｔ信号（トランジスタＭ１のゲートに入力される信号）はＱｎ－２段目のシフトレジスタ１１ａから出力された走査信号Ｑｎ－２、トランジスタＭ９のリセットを行う信号（ゲートに入力される信号）はＱｎ＋４段目のシフトレジスタ１１ａから出力された走査信号Ｑｎ＋４、トランジスタＭ１３のリセットを行う信号（ゲートに入力される信号）はＱｎ＋３段目のシフトレジスタ１２ａから出力される走査信号Ｑｎ＋３となる。また、Ｑｎ＋１段のシフトレジスタ１２ａの出力は走査信号Ｑｎ、Ｓｅｔ信号（トランジスタＭ１のゲートに入力される信号）はＱｎ－１段目のシフトレジスタ１２ａから出力された走査信号Ｑｎ－１、トランジスタＭ９のリセットを行う信号（ゲートに入力される信号）はＱｎ＋５段目のシフトレジスタ１２ａから出力された走査信号Ｑｎ＋５、トランジスタＭ１３のリセットを行う信号（ゲートに入力される信号）はＱｎ＋４段目のシフトレジスタ１１ａから出力される走査信号Ｑｎ＋４となる。 In the above configuration, the output of the Qn stage shift register 11a is the scanning signal Qn, and the Set signal (the signal input to the gate of the transistor M1) is the scanning signal Qn-2 output from the Qn-2 stage shift register 11a. The signal for resetting the transistor M9 (signal input to the gate) is the scanning signal Qn + 4 output from the shift register 11a in the fourth stage, and the signal for resetting the transistor M13 (signal input to the gate) is the Qn + third stage. The scanning signal Qn + 3 output from the shift register 12a. The output of the Qn + 1 stage shift register 12a is the scanning signal Qn, and the Set signal (the signal input to the gate of the transistor M1) is the scanning signal Qn-1 output from the Qn-1 stage shift register 12a, and the transistor M9. The reset signal (signal input to the gate) is the scanning signal Qn + 5 output from the Qn + 5 stage shift register 12a, and the reset signal (signal input to the gate) of the transistor M13 is the Qn + 4 stage shift. The scanning signal Qn + 4 is output from the register 11a.
　これにより、走査信号Ｑｎの立ち下げ時は、Ｑｎ段（自段）のシフトレジスタ１１ａの出力直後の信号によりトランジスタＭ１０でローに落として、画素領域１０を介して反対側では、Ｑｎ＋３段目のシフトレジスタ１２ａの出力直後の信号によりトランジスタＭ１３でローに落とすことになる。同様に、ゲート出力Ｑｎ＋１の立ち下げ時は、Ｑｎ＋１段（自段）のシフトレジスタ１２ａの出力直後の信号によりトランジスタＭ１０でローに落として、画素領域１０を介して反対側では、Ｑｎ＋４段目のシフトレジスタ１１ａの出力直後の信号によりトランジスタＭ１３でローに落とすことになる。このときのシフトレジスタ１１ａ、１２ａが動作しているときの各信号の波形図を図２に示す。 Thus, when the scanning signal Qn falls, the signal immediately after the output of the shift register 11a of the Qn stage (own stage) is dropped to low by the transistor M10, and on the opposite side via the pixel region 10, the Qn + third stage. The signal immediately after the output of the shift register 12a is pulled low by the transistor M13. Similarly, when the gate output Qn + 1 falls, the signal immediately after the output of the Qn + 1 stage (own stage) shift register 12a is dropped to low by the transistor M10, and on the opposite side via the pixel region 10, the Qn + 4th stage. The signal immediately after the output of the shift register 11a is pulled low by the transistor M13. FIG. 2 shows a waveform diagram of each signal when the shift registers 11a and 12a are operating at this time.
　（効果）
　図４は、シミュレーション結果によって得られた、リセットＴＦＴ（トランジスタＭ１３）の有無によるゲート出力の立ち下がり時間を比較したグラフである。ここで、リセットＴＦＴ無しでは、自段側でシフトレジスタから出力される走査信号のロー引きが行われ、画素領域を介して反対側で走査信号のロー引きは行われない。一方、リセットＴＦＴ有りでは、自段側でシフトレジスタから出力される走査信号のロー引きが行われ、画素領域を介して反対側でも走査信号のロー引きが行われる。しかも、リセットＴＦＴのゲートには、自段のシフトレジスタとは画素領域を介して反対側のシフトレジスタの出力直後の信号（立ち上がりおよび立ち下がりが急峻な信号）が入力されるため、走査信号の立ち下がりをより急峻にすることが可能となる。 (effect)
FIG. 4 is a graph comparing the fall time of the gate output with and without the reset TFT (transistor M13) obtained by the simulation result. Here, without the reset TFT, the scanning signal outputted from the shift register is low-drawn on the self-stage side, and the scanning signal is not low-drawn on the opposite side through the pixel region. On the other hand, when there is a reset TFT, the scanning signal output from the shift register is low-drawn on the self-stage side, and the scanning signal low-side drawing is also performed on the opposite side through the pixel region. In addition, since the signal immediately after the output of the shift register on the opposite side (the signal having a sharp rise and fall) is input to the gate of the reset TFT via the pixel area of the shift register of its own stage, It becomes possible to make the fall more steep.
　従って、図４に示すグラフのように、リセット用のＴＦＴとしてのトランジスタＭ１３がある場合のほうが、無い場合よりもゲート出力の立ち下げを高速化できる。これにより、アクティブ基板１０１を搭載した表示装置の駆動の高速化も図ることができる。 Therefore, as shown in the graph in FIG. 4, the gate output can be lowered more quickly when the transistor M13 is provided as a reset TFT than when the transistor M13 is not provided. Thereby, the driving speed of the display device on which the active substrate 101 is mounted can be increased.
　図５は、シミュレーション結果によって得られた、リセットＴＦＴのサイズと走査信号の立ち下げ時間との関係を示すグラフである。このグラフから、リセットＴＦＴの幅Ｗが４００μｍの場合に、画面端、ＧＤＭ出力直後（シフトレジスタ出力直後）、画面中央において、何れも目標立ち下げ時間を下回ることがわかる。なお、リセットＴＦＴの幅Ｗは、４００μｍに限定されるものではなく、目標立ち下げ時間の設定値等により変る。 FIG. 5 is a graph showing the relationship between the size of the reset TFT and the fall time of the scanning signal, obtained from the simulation results. From this graph, it can be seen that when the width W of the reset TFT is 400 μm, it is less than the target fall time at the screen edge, immediately after the GDM output (immediately after the shift register output), and at the center of the screen. Note that the width W of the reset TFT is not limited to 400 μm, and varies depending on the set value of the target fall time or the like.
　なお、本実施形態では、クロックを６相、ｄｕｔｙ３／６として説明したが、本発明はこれに限定されるものではなく、クロックが６相以上の偶数、ｄｕｔｙの分子は奇数である必要あればよい。 In this embodiment, the clock has been described as having 6 phases and duty 3/6, but the present invention is not limited to this, and the clock needs to be an even number of 6 phases or more and the numerator of the duty must be an odd number. Good.
　〔実施形態２〕
　本発明の他の実施形態について説明すれば、以下のとおりである。なお、説明の便宜上、前記実施形態にて説明した部材と同じ機能を有する部材については、同じ符号を付記し、その説明を省略する。 [Embodiment 2]
The following will describe another embodiment of the present invention. For convenience of explanation, members having the same functions as those described in the embodiment are given the same reference numerals, and descriptions thereof are omitted.
　（アクティブ基板の概要）
　図６は、本実施形態に係るアクティブ基板２０１の概略構成図である。本実施形態では、クロックは片側４相、両側８相、ｄｕｔｙ４／８とする。 (Outline of active substrate)
FIG. 6 is a schematic configuration diagram of an active substrate 201 according to the present embodiment. In this embodiment, the clock has four phases on one side, eight phases on both sides, and duty 4/8.
　アクティブ基板２０１は、前記実施形態１のアクティブ基板１０１と同様に、ガラス基板上にアモルファスシリコン、多結晶シリコン、ＣＧシリコン、微結晶シリコンなどを用いて画素領域（アクティブ領域）２０、および、画素領域２０を介して対向して配置されたシフトレジスタブロック２１・２２が同一基板上に形成されている。 Similar to the active substrate 101 of the first embodiment, the active substrate 201 uses a glass substrate made of amorphous silicon, polycrystalline silicon, CG silicon, microcrystalline silicon, or the like to form a pixel region (active region) 20 and a pixel region. Shift register blocks 21 and 22 arranged to face each other via 20 are formed on the same substrate.
　画素領域２０は、複数の画素（図示せず）がマトリクス状に配置されており、各画素に走査信号を供給するための複数ラインの走査信号線Ｑｎ（ｎは、整数）が形成され、これら走査信号線Ｑｎに、シフトレジスタブロック２１・２２からの出力（ゲート信号）を供給することにより、アクティブになるアクティブ領域である。 In the pixel region 20, a plurality of pixels (not shown) are arranged in a matrix, and a plurality of scanning signal lines Qn (n is an integer) for supplying a scanning signal to each pixel are formed. This is an active region that is activated by supplying outputs (gate signals) from the shift register blocks 21 and 22 to the scanning signal line Qn.
　シフトレジスタブロック２１は、走査信号線Ｑｎの一つに出力信号を出力するシフトレジスタ２１ａを複数段備えている。各シフトレジスタ２１ａは、縦続接続されている。同様に、シフトレジスタブロック２２は、走査信号線Ｑｎの一つに出力信号を出力するシフトレジスタ２２ａを複数段備えている。各シフトレジスタ２２ａは、縦続接続されている。 The shift register block 21 includes a plurality of stages of shift registers 21a for outputting an output signal to one of the scanning signal lines Qn. Each shift register 21a is connected in cascade. Similarly, the shift register block 22 includes a plurality of stages of shift registers 22a that output an output signal to one of the scanning signal lines Qn. Each shift register 22a is connected in cascade.
　シフトレジスタブロック２１が備える複数のシフトレジスタ２１ａは、画素領域２０の走査信号線Ｑｎ－４、Ｑｎ－２、Ｑｎ、Ｑｎ＋２、Ｑｎ＋４、Ｑｎ＋６、Ｑｎ＋８のそれぞれに接続されている。つまり、シフトレジスタブロック２１が備える複数のシフトレジスタ２１ａは、走査信号線Ｑｎを一つおきに接続されていることになる。 The plurality of shift registers 21 a included in the shift register block 21 are connected to the scanning signal lines Qn−4, Qn−2, Qn, Qn + 2, Qn + 4, Qn + 6, and Qn + 8 in the pixel region 20, respectively. That is, the plurality of shift registers 21a included in the shift register block 21 are connected to every other scanning signal line Qn.
　同様に、シフトレジスタブロック２２が備える複数のシフトレジスタ２２ａは、画素領域２０の走査信号線Ｑｎ－５、Ｑｎ－３、Ｑｎ－１、Ｑｎ＋１、Ｑｎ＋３、Ｑｎ＋５、Ｑｎ＋７のそれぞれに接続されている。つまり、シフトレジスタブロック２２が備える複数のシフトレジスタ２２ａも、走査信号線Ｑｎを一つおきに接続されていることになる。 Similarly, the plurality of shift registers 22a included in the shift register block 22 are connected to the scanning signal lines Qn-5, Qn-3, Qn-1, Qn + 1, Qn + 3, Qn + 5, and Qn + 7 of the pixel region 20, respectively. That is, the plurality of shift registers 22a included in the shift register block 22 are also connected to every other scanning signal line Qn.
　シフトレジスタブロック２１の各シフトレジスタ２１ａは、セット入力端子Ｓ、出力端子Ｑ、リセット入力端子Ｒ、クロック入力端子ＧＣＫ、および、Ｌｏｗ電源入力端子ＶＳＳを備えている。クロック入力端子ＧＣＫには、クロック信号ＧＣＫ、Ｌｏｗ電源入力端子ＶＳＳには、Ｌｏｗ電源ＶＳＳ（便宜上、Ｌｏｗ電源入力端子ＶＳＳと同じ符号で代用する）が図示ない回路から供給される。Ｌｏｗ電源ＶＳＳは負電位でもよいし、ＧＮＤ電位でも、正電位でもよいが、ＴＦＴを確実にＯＦＦ状態とするためにここでは負電位とする。 Each shift register 21a of the shift register block 21 includes a set input terminal S, an output terminal Q, a reset input terminal R, a clock input terminal GCK, and a Low power input terminal VSS. The clock input terminal GCK is supplied with a clock signal GCK, and the Low power input terminal VSS is supplied with a Low power supply VSS (for the sake of convenience, the same reference numeral as the Low power input terminal VSS) from a circuit (not shown). The low power supply VSS may be a negative potential, a GND potential, or a positive potential. However, in order to surely turn off the TFT, it is set to a negative potential here.
　シフトレジスタブロック２２の各シフトレジスタ２２ａは、シフトレジスタ２１ａと同じ構成であるため、詳細な説明は省略する。 Since each shift register 22a of the shift register block 22 has the same configuration as the shift register 21a, detailed description thereof is omitted.
　シフトレジスタブロック２１において、Ｑｎ－４、Ｑｎ－２、Ｑｎ、Ｑｎ＋２、Ｑｎ＋４、Ｑｎ＋６、Ｑｎ＋８、Ｑ＋１０段目のシフトレジスタ２１ａの出力端子Ｑからの出力は、それぞれ走査信号線Ｑｎ－４、Ｑｎ－２、Ｑｎ、Ｑｎ＋２、Ｑｎ＋４、Ｑｎ＋６、Ｑｎ＋８、Ｑ＋１０に出力される走査信号Ｑｎ－４、Ｑｎ－２、Ｑｎ、Ｑｎ＋２、Ｑｎ＋４、Ｑｎ＋６、Ｑｎ＋８、Ｑ＋１０となる。 In the shift register block 21, the outputs from the output terminals Q of the Qn-4, Qn-2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, and Q + 10 stage shift registers 21a are the scanning signal lines Qn-4 and Qn-, respectively. 2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, and Q + 10 are output as scanning signals Qn-4, Qn-2, Qn, Qn + 2, Qn + 4, Qn + 6, Qn + 8, and Q + 10.
　一方、シフトレジスタブロック２２において、Ｑｎ－３、Ｑｎ－１、Ｑｎ＋１、Ｑｎ＋３、Ｑｎ＋５、Ｑｎ＋７、Ｑ＋９段目のシフトレジスタ２２ａの出力端子Ｑからの出力は、それぞれ走査信号線Ｑｎ－３、Ｑｎ－１、Ｑｎ＋１、Ｑｎ＋３、Ｑｎ＋５、Ｑｎ＋７、Ｑ＋９に出力される走査信号Ｑｎ－３、Ｑｎ－１、Ｑｎ＋１、Ｑｎ＋３、Ｑｎ＋５、Ｑｎ＋７、Ｑ＋９となる。 On the other hand, in the shift register block 22, the outputs from the output terminal Q of the Qn-3, Qn-1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, Q + 9 stage shift register 22a are the scanning signal lines Qn-3, Qn-, respectively. The scanning signals Qn−3, Qn−1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, and Q + 9 output to 1, Qn + 1, Qn + 3, Qn + 5, Qn + 7, and Q + 9 are obtained.
　シフトレジスタブロック２１とシフトレジスタブロック２２とを合わせて、全てのシフトレジスタが走査信号線を介して縦続接続された状態となっており、全体で１つのゲートドライバを構成している。 The shift register block 21 and the shift register block 22 together are in a state where all the shift registers are cascade-connected via the scanning signal lines, and constitute one gate driver as a whole.
　また、シフトレジスタブロック２１の各シフトレジスタ２１ａに接続された走査信号線の、上記画素領域２０を介して、当該シフトレジスタブロック２１と反対側（シフトレジスタブロック２２側）に、当該走査信号線のロー引きを行うための、リセット用のスイッチング素子２１ｂが設けられている。同様に、シフトレジスタブロック２２の各シフトレジスタ２２ａに接続された走査信号線の、上記画素領域２０を介して、当該シフトレジスタブロック２２と反対側（シフトレジスタブロック２１側）に、当該走査信号線のロー引きを行うための、リセット用のスイッチング素子２２ｂが設けられている。 In addition, the scanning signal line connected to each shift register 21a of the shift register block 21 passes through the pixel region 20 to the side opposite to the shift register block 21 (shift register block 22 side). A switching element 21b for resetting is provided for performing low drawing. Similarly, the scanning signal line connected to each shift register 22a of the shift register block 22 passes through the pixel region 20 to the opposite side of the shift register block 22 (shift register block 21 side). A switching element 22b for resetting is provided for performing low pulling.
　上記構成のアクティブ基板２０１においても、前記実施形態１のアクティブ基板１０１と同様に、リセットＴＦＴ（トランジスタＭ１３）を備え、トランジスタＭ１３のゲートには、自段のシフトレジスタとは画素領域２０を介して反対側のシフトレジスタの出力直後の信号（立ち上がりが急峻な信号）が入力されるため、走査信号の立ち下がりをより急峻にすることが可能となるという効果を奏する。 Similarly to the active substrate 101 of the first embodiment, the active substrate 201 having the above configuration also includes a reset TFT (transistor M13). The gate of the transistor M13 is connected to the shift register of its own stage via the pixel region 20. Since the signal immediately after the output of the shift register on the opposite side (signal with a sharp rise) is input, there is an effect that the fall of the scanning signal can be made steeper.
　〔実施形態３〕
　本発明の他の実施形態について説明すれば、以下のとおりである。なお、説明の便宜上、前記実施形態にて説明した部材と同じ機能を有する部材については、同じ符号を付記し、その説明を省略する。 [Embodiment 3]
The following will describe another embodiment of the present invention. For convenience of explanation, members having the same functions as those described in the embodiment are given the same reference numerals, and descriptions thereof are omitted.
　図７は、前記実施形態１のアクティブ基板１０１を備えた表示装置の一例としての液晶表示装置１の概略構成を示す図である。 FIG. 7 is a diagram illustrating a schematic configuration of a liquid crystal display device 1 as an example of a display device including the active substrate 101 according to the first embodiment.
　液晶表示装置１は、表示パネルを構成するアクティブ基板１０１、フレキシブルプリント基板１０２、および、コントロール基板１０３を備えている。 The liquid crystal display device 1 includes an active substrate 101, a flexible printed circuit board 102, and a control substrate 103 that constitute a display panel.
　アクティブ基板１０１の画素領域１０は、複数の画素ＰＩＸ…がマトリクス状に配置された領域である。画素ＰＩＸは、絵素の選択素子であるＴＦＴ２１、液晶容量ＣＬ、および、補助容量Ｃｓを備えている。ＴＦＴ２１のゲートはゲートライン（走査信号線）ＧＬに接続されており、ＴＦＴ２１のソースはソースライン（データ信号線）ＳＬに接続されている。液晶容量ＣＬおよび補助容量ＣｓはＴＦＴ２１のドレインに接続されている。 The pixel region 10 of the active substrate 101 is a region where a plurality of pixels PIX... Are arranged in a matrix. The pixel PIX includes a TFT 21, which is a picture element selection element, a liquid crystal capacitor CL, and an auxiliary capacitor Cs. The gate of the TFT 21 is connected to a gate line (scanning signal line) GL, and the source of the TFT 21 is connected to a source line (data signal line) SL. The liquid crystal capacitor CL and the auxiliary capacitor Cs are connected to the drain of the TFT 21.
　複数のゲートラインＧＬ…はゲートラインＧＬ１・ＧＬ２・ＧＬ３・…・ＧＬｎからなり、そのうち１本おきに配置されたゲートラインＧＬ１・ＧＬ３・ＧＬ５…からなる第１のグループのゲートラインＧＬ…はゲートドライバとしてのシフトレジスタブロック１１の出力に接続されており、残りの１本おきに配置されたゲートラインＧＬ２・ＧＬ４・ＧＬ６…からなる第２のグループのゲートラインＧＬ…はゲートドライバとしてのシフトレジスタブロック１２の出力に接続されている。複数のソースラインＳＬ…はソースラインＳＬ１・ＳＬ２・ＳＬ３・…・ＳＬｍからなり、それぞれ後述するソースドライバ１３の出力に接続されている。 The plurality of gate lines GL are gate lines GL1, GL2, GL3,... GLn, and gate lines GL1, GL3, GL5,. Connected to the output of the shift register block 11 as a driver, the second group of gate lines GL... Consisting of the remaining gate lines GL2, GL4, GL6. Connected to the output of block 12. The plurality of source lines SL are composed of source lines SL1, SL2, SL3,..., SLm, and are connected to the output of the source driver 13 described later.
　なお、アクティブ基板１０１の詳細、特に、ゲートドライバ（シフトレジスタブロック）１１、１２の詳細については前記実施形態１において説明したので、ここでは省略する。 The details of the active substrate 101, particularly the details of the gate drivers (shift register blocks) 11 and 12, have been described in the first embodiment, and are omitted here.
　以上のように、本発明のアクティブ基板１０１を備えた液晶表示装置１では、走査信号の立ち下がりをより急峻にすることが可能となるので、当該液晶表示装置１の駆動の高速化も図ることができる。 As described above, in the liquid crystal display device 1 including the active substrate 101 of the present invention, the falling edge of the scanning signal can be made steep, so that the liquid crystal display device 1 can be driven at high speed. Can do.
　なお、アクティブ基板１０１の代わりに前記実施形態２において説明したアクティブ基板２０１を用いてもよい。 Note that the active substrate 201 described in the second embodiment may be used instead of the active substrate 101.
　〔まとめ〕
　本発明の態様１に係るアクティブ基板（１０１，２０１）は、半導体層を備えた複数のスイッチング素子と、上記スイッチング素子の各々に接続された複数の走査信号線を駆動する駆動回路（シフトレジスタブロック１１、１２）とが、同一基板上に形成されたアクティブ基板（１０１，２０１）であって、上記駆動回路（シフトレジスタブロック１１、１２）は、上記複数の走査信号線の一つに出力信号を出力するシフトレジスタ１１ａ・１２ａが、複数段備えられたシフトレジスタブロック１１・１２を２個含み、上記２個のシフトレジスタブロック１１・１２は、上記スイッチング素子が形成されたアクティブ領域（画素領域１０）を介して、対向するように配置され、上記２個のシフトレジスタブロック１１・１２の一方に備えられたシフトレジスタ１１ａと、他方に備えられたシフトレジスタ１２ａは、上記複数の走査信号線に対して交互に接続されており、上記一方のシフトレジスタブロック１１に含まれるシフトレジスタ１１ａに接続された走査信号線の、上記アクティブ領域（画素領域１０）を挟んで、当該シフトレジスタブロック１１と反対側にリセット用のスイッチング素子１１ｂが接続され、上記リセット用のスイッチング素子１１ｂは、当該スイッチング素子１１ｂが接続された走査信号線に出力された走査信号の立ち下がりに同期して立ち上がり、且つ立ち上がりが急峻な信号によりオンされることを特徴としている。 [Summary]
An active substrate (101, 201) according to an aspect 1 of the present invention includes a plurality of switching elements including a semiconductor layer and a driving circuit (shift register block) for driving a plurality of scanning signal lines connected to each of the switching elements. 11 and 12) are active substrates (101, 201) formed on the same substrate, and the drive circuit (shift register blocks 11, 12) outputs an output signal to one of the plurality of scanning signal lines. Shift registers 11a and 12a include two shift register blocks 11 and 12 each having a plurality of stages, and the two shift register blocks 11 and 12 include active regions (pixel regions) in which the switching elements are formed. 10) and arranged to face each other and provided in one of the two shift register blocks 11 and 12. The shift register 11 a and the shift register 12 a provided on the other side are alternately connected to the plurality of scanning signal lines, and the scanning signal is connected to the shift register 11 a included in the one shift register block 11. A switching element 11b for reset is connected to the opposite side of the shift register block 11 across the active area (pixel area 10) of the line, and the switching element 11b is connected to the switching element 11b for reset. It is characterized in that it rises in synchronization with the falling edge of the scanning signal output to the scanning signal line and is turned on by a signal whose rising edge is steep.
　上記の構成によれば、一方のシフトレジスタブロックに含まれるシフトレジスタに接続された走査信号線の、アクティブ領域を介して、当該シフトレジスタブロックと反対側に接続されたリセット用のスイッチング素子が、当該スイッチング素子が接続された走査信号線に出力された走査信号の立ち下がりに同期して、立ち上がり、且つ立ち上がりが急峻な信号によりオンされることで、走査信号が立ち下がる時間を早めることができる。つまり、リセット用のスイッチング素子によるリセットが効き始めるまでに遅延が生じない。 According to the above configuration, the reset switching element connected to the opposite side of the shift register block via the active region of the scanning signal line connected to the shift register included in one shift register block is The time when the scanning signal falls can be shortened by being turned on by a signal that rises and rises in synchronism with the falling edge of the scanning signal output to the scanning signal line to which the switching element is connected. . That is, there is no delay until the reset by the reset switching element starts to work.
　よって、シフトレジスタが出力したゲート信号の立ち下がりを速くすることで、駆動の高速化を可能にできるという効果を奏する。 Therefore, it is possible to increase the drive speed by making the fall of the gate signal output from the shift register faster.
　本発明の態様２に係るアクティブ基板は、上記態様１において、上記リセット用のスイッチング素子１１ｂ・１２ｂは、当該スイッチング素子１１ｂ・１２ｂが接続されたシフトレジスタ１１ａ・１２ａとは上記アクティブ領域（画素領域１０）を挟んで反対側のシフトレジスタ１１ａ・１２ａの出力直後の信号によりオンされてもよい。 The active substrate according to aspect 2 of the present invention is the active substrate according to aspect 1, wherein the reset switching elements 11b and 12b are different from the shift register 11a and 12a to which the switching elements 11b and 12b are connected. It may be turned on by a signal immediately after the output of the shift registers 11a and 12a on the opposite side across 10).
　上記の構成によれば、リセット用の信号を別途生成する必要がないため、狭額縁化を図ることができる。 According to the above configuration, it is not necessary to separately generate a reset signal, so that the frame can be narrowed.
　本発明の態様３に係るアクティブ基板は、上記態様１または２において、上記２個のシフトレジスタブロック１１・１２には、それぞれ３相以上のクロック信号が入力されてもよい。 In the active substrate according to aspect 3 of the present invention, in the above aspect 1 or 2, clock signals of three phases or more may be input to the two shift register blocks 11 and 12, respectively.
　本発明の態様４に係るアクティブ基板は、上記態様１から３の何れか１態様において、記複数のスイッチング素子の各々に備えられた半導体層及び上記シフトレジスタ１１ａ・１２ａの各々のトランジスタに備えられた半導体層は、酸化物半導体層であってもよい。 An active substrate according to aspect 4 of the present invention is provided in any one of the aspects 1 to 3 described above, in each of the semiconductor layers provided in each of the plurality of switching elements and in each transistor of the shift registers 11a and 12a. The semiconductor layer may be an oxide semiconductor layer.
　上記の構成によれば、消費電力を大幅に削減することが可能になる。 According to the above configuration, power consumption can be greatly reduced.
　本発明の態様５に係るアクティブ基板は、上記態様４において、上記酸化物半導体層は、インジウム、ガリウム及び亜鉛を含んでもよい。 In the active substrate according to aspect 5 of the present invention, in the aspect 4, the oxide semiconductor layer may include indium, gallium, and zinc.
　上記構成によれば、消費電力を大幅に削減することが可能になる。しかも、移動度が高いため、より回路が小さくでき、より狭額縁化を実現出来る。 According to the above configuration, power consumption can be greatly reduced. In addition, since the mobility is high, the circuit can be made smaller and a narrower frame can be realized.
　本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。さらに、各実施形態にそれぞれ開示された技術的手段を組み合わせることにより、新しい技術的特徴を形成することができる。 The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.
１　液晶表示装置（表示装置）
１０　画素領域（アクティブ領域）
１１・１２　シフトレジスタブロック
１１ａ・１２ａ　シフトレジスタ
１１ｂ・１２ｂ　スイッチング素子
２０　画素領域（アクティブ領域）
２１・２２　シフトレジスタブロック
２１ａ・２２ａ　シフトレジスタ
２１ｂ・２２ｂ　スイッチング素子
１０１・２０１　アクティブ基板 1 Liquid crystal display device (display device)
10 pixel area (active area)
11.12 Shift register block 11a, 12a Shift register 11b, 12b Switching element 20 Pixel region (active region)
21/22 Shift register block 21a / 22a Shift register 21b / 22b Switching element 101/201 Active substrate

Claims (6)

  1. 　半導体層を備えた複数のスイッチング素子と、上記スイッチング素子の各々に接続された複数の走査信号線を駆動する駆動回路とが、同一基板上に形成されたアクティブ基板であって、
    　上記駆動回路は、上記複数の走査信号線の一つに出力信号を出力するシフトレジスタが、複数段備えられたシフトレジスタブロックを２個含み、
    　上記２個のシフトレジスタブロックは、上記スイッチング素子が形成されたアクティブ領域を介して、対向するように配置され、
    　上記２個のシフトレジスタブロックの一方に備えられたシフトレジスタと、他方に備えられたシフトレジスタは、上記複数の走査信号線に対して交互に接続されており、
    　上記一方のシフトレジスタブロックに含まれるシフトレジスタに接続された走査信号線の、上記アクティブ領域を挟んで、当該シフトレジスタブロックと反対側にリセット用のスイッチング素子が接続され、
    　上記リセット用のスイッチング素子は、当該スイッチング素子が接続された走査信号線に出力された走査信号の立ち下がりに同期して立ち上がり、且つ立ち上がりが急峻な信号によりオンされることを特徴とするアクティブ基板。     A plurality of switching elements each including a semiconductor layer and a drive circuit that drives a plurality of scanning signal lines connected to each of the switching elements are active substrates formed on the same substrate,
    The drive circuit includes two shift register blocks each provided with a plurality of stages of shift registers that output an output signal to one of the plurality of scanning signal lines,
    The two shift register blocks are arranged to face each other through an active region in which the switching element is formed,
    The shift register provided in one of the two shift register blocks and the shift register provided in the other are alternately connected to the plurality of scanning signal lines,
    A switching element for reset is connected to the opposite side of the shift register block across the active region of the scanning signal line connected to the shift register included in the one shift register block,
    The reset switching element is activated in response to a signal that rises in synchronization with a falling edge of a scanning signal output to a scanning signal line connected to the switching element and has a sharp rising edge. .
  2. 　上記リセット用のスイッチング素子は、当該スイッチング素子が接続されたシフトレジスタとは上記アクティブ領域を挟んで反対側のシフトレジスタの出力直後の信号によりオンされることを特徴とする請求項１に記載のアクティブ基板。 The switching element for reset is turned on by a signal immediately after the output of the shift register on the opposite side across the active region with respect to the shift register to which the switching element is connected. Active substrate.
  3. 　上記２個のシフトレジスタブロックには、それぞれ３相以上のクロック信号が入力されることを特徴とする請求項１または２に記載のアクティブ基板。 3. The active substrate according to claim 1, wherein a clock signal having three or more phases is input to each of the two shift register blocks.
  4. 　上記複数のスイッチング素子の各々に備えられた半導体層及び上記シフトレジスタの各々のトランジスタに備えられた半導体層は、酸化物半導体層であることを特徴とする請求項１から３の何れか１項に記載のアクティブ基板。 4. The semiconductor layer included in each of the plurality of switching elements and the semiconductor layer included in each transistor of the shift register are oxide semiconductor layers. 5. Active substrate as described in
  5. 　上記酸化物半導体層は、インジウム、ガリウム及び亜鉛を含むことを特徴とする請求項４に記載のアクティブ基板。 The active substrate according to claim 4, wherein the oxide semiconductor layer contains indium, gallium, and zinc.
  6. 　請求項１～５の何れか１項に記載のアクティブ基板を備えたことを特徴とする表示装置。 A display device comprising the active substrate according to any one of claims 1 to 5.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114267283A (en) * 2021-12-29 2022-04-01 武汉天马微电子有限公司 Display panel and display device
CN114267283B (en) * 2021-12-29 2023-11-07 武汉天马微电子有限公司 Display panel and display device

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