CN117215168A - Configurable time domain pipeline analog-to-digital converter - Google Patents
Configurable time domain pipeline analog-to-digital converter Download PDFInfo
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Abstract
The invention relates to a configurable time domain pipelined analog-to-digital converter comprising: the system comprises a first configurable analog-to-digital converter and a plurality of cascaded second configurable analog-to-digital converters, wherein the first configurable analog-to-digital converter is used as a first stage of a configurable time domain pipeline analog-to-digital converter and is used for converting an input voltage signal into a time signal, quantizing the time signal and then transmitting the quantized time signal to the plurality of cascaded second configurable analog-to-digital converters; the second configurable analog-to-digital converter is used for amplifying and quantizing the input allowance time signal step by step to generate a corresponding digital code and an allowance time signal; the first configurable analog-to-digital converter and the second configurable analog-to-digital converter realize the function of configurable time gain through the set discharging and charging switch capacitor array. The invention adopts the structure of configurable TA and SA TDC, avoids the use of a voltage amplifier, has higher linearity, meets the precision configuration requirement of ADC, and does not need a time allowance generator.
Description
Technical Field
The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a configurable time domain pipeline analog-to-digital converter.
Background
With the rapid development of wireless receiving systems and sensor systems, various communication standards are being applied. Different communication standards require different bandwidths and data transfer rates, while new generation communication standards also require downward compatibility with previous generations, e.g., 5G requires compatibility with 4G and 3G. End users need devices that can support a variety of application scenarios and communication protocols to reduce manufacturing costs, improve system performance, and minimize chip size. The configurable analog-to-digital converter has been developed in this context, and the feature of high flexibility supports its simultaneous application to a variety of communication systems such as wireless local area networks, bluetooth transmissions, digital television receivers, and the like.
Currently, configurable analog-to-digital converters (Analog to Digital Converter, ADCs) use a voltage domain pipeline architecture and provide multiple parallel voltage amplifiers in a gain digital-to-analog converter (MDAC) that are turned on and off to achieve different conversion speeds of the ADC. However, the difficulty in designing high performance voltage amplifiers in voltage domain structures increases with decreasing process size; the traditional sub ADC with the pipeline structure has the defects of limited speed or larger power consumption and cannot meet the requirement of high speed and high precision at the same time; the multi-parallel amplifier structure occupies a larger area, the gain of the interstage circuit cannot be changed, and the precision configuration is limited; the traditional time domain pipeline structure needs to introduce a time allowance generator, so that the working speed of the ADC is reduced, and the nonlinearity of the allowance generator can influence the precision.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a configurable time domain pipelined analog-to-digital converter. The technical problems to be solved by the invention are realized by the following technical scheme:
the invention provides a configurable time domain pipelined analog-to-digital converter, comprising: a first configurable analog-to-digital converter and a plurality of cascaded second configurable analog-to-digital converters, wherein,
the first configurable analog-to-digital converter is used as a first stage of the configurable time domain pipeline analog-to-digital converter and is used for converting an input voltage signal into a time signal, quantizing the time signal and then transmitting the quantized time signal to the plurality of cascaded second configurable analog-to-digital converters;
the second configurable analog-to-digital converter is used for amplifying and quantizing the input allowance time signal step by step to generate a corresponding digital code and an allowance time signal;
the first configurable analog-to-digital converter and the second configurable analog-to-digital converter realize a function of configurable time gain through a set switched capacitor array.
Compared with the prior art, the invention has the beneficial effects that:
the configurable time domain pipeline analog-to-digital converter adopts the structures of a configurable time amplifier (configurable TA) and a successive approximation type time-to-digital converter (SA TDC), avoids the use of a voltage amplifier, and is suitable for the advanced process. Meanwhile, the invention relies on the transmission delay quantization of the circuit gate, and has the advantages of simple structure, small area and low power consumption. The time amplifier can be configured with gain, has higher linearity, meets the precision configuration requirement of an analog-to-digital converter (ADC), can naturally generate time allowance information after the SA TDC is quantized, and does not need a time allowance generator.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention, as well as the preferred embodiments thereof, together with the following detailed description of the invention, given by way of illustration only, together with the accompanying drawings.
Drawings
FIG. 1 is a block diagram of a configurable time domain pipelined analog-to-digital converter provided by an embodiment of the present invention;
FIG. 2 is a schematic diagram of a configurable voltage-to-time converter according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a successive approximation type time-to-digital converter according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a configurable time amplifier according to an embodiment of the present invention.
Detailed Description
In order to further describe the technical means and effects adopted by the present invention to achieve the preset purpose, a configurable time domain pipelined analog-to-digital converter according to the present invention is described in detail below with reference to the accompanying drawings and detailed description.
The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings. The technical means and effects adopted by the present invention to achieve the intended purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only, and are not intended to limit the technical scheme of the present invention.
Referring to fig. 1, fig. 1 is a block diagram of a configurable time domain pipelined analog-to-digital converter according to an embodiment of the present invention, where the configurable time domain pipelined analog-to-digital converter includes: a first configurable analog-to-digital converter 100 and a plurality of cascaded second configurable analog-to-digital converters 200. The first configurable analog-to-digital converter 100 is used as a first stage of a configurable time domain pipeline analog-to-digital converter, and is used for converting an input voltage signal into a time signal, quantizing the time signal and then transmitting the quantized time signal into a plurality of cascaded second configurable analog-to-digital converters; the second configurable analog-to-digital converter 200 is configured to amplify and quantize the input residual time signal step by step to generate a corresponding digital code and residual time signal; wherein the first configurable analog-to-digital converter 100 and the second configurable analog-to-digital converter 200 implement a time gain configurable function through a set switched capacitor array.
In an alternative embodiment, the first configurable analog-to-digital converter 100 comprises a cascaded configurable voltage-to-time converter (configurable VTC) and a successive approximation type time-to-digital converter (SA TDC). The configurable voltage-to-time converter is used for converting an input voltage signal into a time signal, and the time gain of the configurable voltage-to-time converter is configured by switching the capacitance of the switched capacitor array in the configurable voltage-to-time converter in the signal conversion process; the successive approximation type time-to-digital converter is used for successively quantizing the time signal to generate a corresponding digital code and a residual time signal.
In an alternative embodiment, the second configurable analog-to-digital converter 200 includes a cascaded configurable time amplifier (configurable TA) and a successive approximation type time-to-digital converter, where the configurable time amplifier is configured to amplify an input residual time signal to obtain an amplified time signal; and the successive approximation type time-digital converter is used for successively quantizing the input amplified time signal to generate a corresponding digital code and a corresponding allowance time signal.
The configurable time domain pipeline analog-to-digital converter provided by the embodiment of the invention integrally adopts the pipeline architecture to realize the improvement of speed and precision, wherein the SA TDC can naturally generate the characteristic of time allowance, the use of a time allowance generator in the traditional pipeline TDC is avoided, and the configurable time domain pipeline analog-to-digital converter has the advantages of low power consumption and small area. Meanwhile, the provided configurable analog-to-digital converter has the characteristics of multiple configuration modes and strong expansibility, and can be suitable for various application scenes.
Further, the structure and the working principle of each module of the configurable time domain pipelined analog-to-digital converter of the present embodiment are described in detail.
Referring to fig. 2, a schematic structural diagram of a configurable voltage-to-time converter according to an embodiment of the present invention is shown, where the configurable voltage-to-time converter according to the present invention includes two configurable voltage-to-time converting units with the same structure, and voltage signals are correspondingly input to the two configurable voltage-to-time converting units to be converted into time signals.
Optionally, the configurable voltage-time conversion unit includes: the first current source, the first switched capacitor array and the threshold detection circuit. The first end of the first current source is connected with a voltage signal through a clock switch, and the second end of the first current source is connected with a grounding end; the clock control switch is turned on and off according to an external clock signal (CLK 1); the upper electrode plate of the capacitor of the first switch capacitor array is connected with a voltage signal, the lower electrode plate of the capacitor is connected with a grounding end, and the number of capacitors connected to the voltage signal in the first switch capacitor array is controlled by an external first selection signal; the first input end of the threshold detection circuit inputs a voltage signal, the second input end inputs a threshold voltage, and the output end outputs a time signal.
In an embodiment, the number of capacitances connected to the input voltage signal (Vinn, vinp) is changed in a first switched capacitor array by switching the upper plates of the capacitors with a switch of a first current source (i.e. a discharge current source) closed when CLK1 arrives, the voltage across the capacitors in the first switched capacitor array begins to decrease, when it decreases to the threshold voltage V of the back-end threshold detection circuit TH After that, the output of the threshold detection circuit is inverted, thereby converting the voltage signal into a time signal. Using different first selection signals (Mode 1 [M:0]) Switching the capacitance may achieve a variety of different gain requirements.
Referring to fig. 3, a schematic structural diagram of a successive approximation type time-to-digital converter according to an embodiment of the present invention is shown, where the successive approximation type time-to-digital converter includes a plurality of cascaded time-to-digital conversion units and a switch array, and the time-to-digital conversion units include: the device comprises a time comparator, two delay units and two selectors.
The two input ends of the time comparator are correspondingly connected with the input ends of the two delay units, the output ends of the two delay units are correspondingly connected with the input ends of the two selectors, and the control signal ends of the two selectors are both connected with the output ends of the time comparator. The input ends of the two delay units of the first time-to-digital conversion unit correspond to input time signals, and the input ends of the two delay units of the other time-to-digital conversion units are correspondingly connected with the output ends of the two selectors of the previous time-to-digital conversion unit; the output ends of the two selectors of the all-time digital conversion unit are connected with the switch array; by means of an external control signal (Mode 2 [M:0]) The switch array is controlled to be closed and opened to output allowance time signals (Tresp, tresn) quantized by different precision modes.
In the present embodiment of the present invention, in the present embodiment,the time information is quantized using SA TDC and a digital code is obtained. The quantization process is as follows: the input time signal (T OP And T ON ) Comparison is performed while T OP And T ON The data is input to an alternative selector (MUX) after passing through different delay units. Controlling the output of the selector according to the comparison result of the time comparator to obtain time allowance information, preparing for the next comparison, and obtaining N-bit digital code B after the quantization is finished<N-1:0>. By means of an external control signal (Mode 2 [M:0]) The switch array is controlled to select different margin information to be passed to the next stage of configurable time amplifier to complete pipeline quantization.
In the present embodiment, the successive approximation type time-to-digital converters in the first configurable analog-to-digital converter 100 and the second configurable analog-to-digital converter 200 are identical in structure.
Referring to fig. 4, a schematic diagram of a configurable time amplifier according to an embodiment of the present invention is shown, where the configurable time amplifier of the present embodiment includes a cascaded configurable time-to-voltage converter (configurable TVC) and a cascaded configurable voltage-to-time converter (configurable VTC).
The configurable time-to-voltage converter is used for controlling the on time of the current source according to the input margin time signal and converting the on time of the current source into a voltage signal stored on the switch capacitor array; the configurable voltage-time converter is used for converting an input voltage signal into a time signal to obtain an amplified time signal; wherein the time gain of the configurable time amplifier is configured during signal amplification by the configurable time-to-voltage converter and the capacitance of the switched capacitor array in the configurable voltage-to-time converter.
As shown in fig. 4, the configurable time-to-voltage converter includes: the trigger unit, the logic gate, the charging current source, the discharging current source and two second switch capacitor arrays. In this embodiment, the trigger unit includes two triggers, the logic gate is an and gate, and the margin time signal (Tresp, tresn) is correspondingly input to twoThe clock end of the trigger, the input end of the two triggers inputs the external signal, the output end outputs the control signal of the current source, the control signal of the current source inputs the input end of AND gate, the output end of AND gate connects the reset end of the two triggers separately; the first end of the charging current source is connected with the power supply end, and the second end of the charging current source is connected with a capacitor upper polar plate of a second switch capacitor array through a current source control switch; the first end of the discharging current source is connected with the upper capacitor plate of the other second switched capacitor array through the current source control switch, and the second end of the discharging current source is connected with the grounding end; the capacitor lower polar plates of the two second switch capacitor arrays are connected with the grounding end; by an external second selection signal (Mode 3 [M:0]) Controlling the number of capacitors connected with the corresponding current sources in the second switch capacitor array; the upper capacitor plates of the two second switched capacitor arrays are used as output ends to be connected with the input ends of the configurable voltage-time converter.
In this embodiment, the input margin time signal is converted into a voltage signal stored on the second switched capacitor array by controlling the on time of the discharging/charging current source of the configurable TVC, and the voltage signal is converted into a time signal (i.e., an amplified time signal) after passing through the configurable VTC. The structure of the configurable VTC is identical to that of the configurable voltage-to-time converter in the configurable analog-to-digital converter 100, as shown in fig. 2, and will not be described here.
In this embodiment, by sizing the transistors so that the currents of the configurable time-to-voltage converter and the current source of the configurable voltage-to-time converter in the configurable time amplifier are equal, i.e., I TV ＝I VT At this time, the gain of the configurable time amplifier is related to the capacitance value only, and only the gain is controlled by the external selection signal (Mode 1 [M:0]、Mode 3 [M:0]) The configuration requirement of time gain is realized by switching the discharging/charging capacitor of the configurable TVC and the configurable VTC. Furthermore, since the gain of the configurable time amplifier is only related to the capacitance value, the linearity is good.
It should be noted that, in the present embodiment, the configurable voltage-to-time converter is of a discharge current source type, and in other embodiments, a charge current source type or a current starvation type may be used.
The configurable time domain pipeline analog-to-digital converter of the embodiment of the invention adopts the structure of configurable TA and SA TDC, avoids the use of a voltage amplifier, and is suitable for the prior process. Meanwhile, the invention relies on the transmission delay quantization of the circuit gate, and has the advantages of simple structure, small area and low power consumption. The time amplifier can be configured with gain, has higher linearity, meets the precision configuration requirement of ADC, can naturally generate time allowance information after SA TDC is quantized, and does not need a time allowance generator.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises the element. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (8)
1. A configurable time domain pipelined analog-to-digital converter comprising: a first configurable analog-to-digital converter and a plurality of cascaded second configurable analog-to-digital converters, wherein,
the first configurable analog-to-digital converter is used as a first stage of the configurable time domain pipeline analog-to-digital converter and is used for converting an input voltage signal into a time signal, quantizing the time signal and then transmitting the quantized time signal to the plurality of cascaded second configurable analog-to-digital converters;
the second configurable analog-to-digital converter is used for amplifying and quantizing the input allowance time signal step by step to generate a corresponding digital code and an allowance time signal;
the first configurable analog-to-digital converter and the second configurable analog-to-digital converter realize a function of configurable time gain through a set switched capacitor array.
2. The configurable time domain pipelined analog-to-digital converter of claim 1, wherein said first configurable analog-to-digital converter comprises a cascaded configurable voltage-to-time converter and a successive approximation type time-to-digital converter, wherein,
the configurable voltage-to-time converter is used for converting an input voltage signal into a time signal, and the time gain of the configurable voltage-to-time converter is configured by switching the capacitance of the switched capacitor array in the configurable voltage-to-time converter in the signal conversion process;
the successive approximation type time-to-digital converter is used for successively quantizing the time signal to generate a corresponding digital code and a residual time signal.
3. The configurable time domain pipeline analog-to-digital converter according to claim 2, wherein the configurable voltage-to-time converter comprises two configurable voltage-to-time conversion units with the same structure, and the voltage signal is correspondingly input to the two configurable voltage-to-time conversion units to be converted into the time signal;
the configurable voltage-to-time conversion unit includes: a first current source, a first switched capacitor array, and a threshold detection circuit, wherein,
the first end of the first current source is connected with the voltage signal through a clock switch, and the second end of the first current source is connected with the grounding end; the clock control switch is turned on and off according to an external clock signal;
the upper capacitor plate of the first switch capacitor array is connected with the voltage signal, the lower capacitor plate is connected with the grounding end, and the number of capacitors connected to the voltage signal in the first switch capacitor array is controlled by an external first selection signal;
the first input end of the threshold detection circuit inputs the voltage signal, the second input end inputs the threshold voltage, and the output end outputs the time signal.
4. The configurable time domain pipelined analog-to-digital converter of claim 2, wherein said successive approximation type time-to-digital converter comprises a plurality of cascaded time-to-digital conversion units, and a switch array, said time-to-digital conversion units comprising: a time comparator, two delay units and two selectors, wherein,
the two input ends of the time comparator are correspondingly connected with the input ends of the two delay units, the output ends of the two delay units are correspondingly connected with the input ends of the two selectors, and the control signal ends of the two selectors are both connected with the output ends of the time comparator;
the input ends of the two delay units of the first time-to-digital conversion unit are correspondingly input with the time signals, and the input ends of the two delay units of the other time-to-digital conversion units are correspondingly connected with the output ends of the two selectors of the previous time-to-digital conversion unit;
the output ends of the two selectors of all the time digital conversion units are connected with the switch array;
and controlling the on and off of the switch array by an external control signal to output a quantized allowance time signal of different precision modes.
5. The configurable time domain pipelined analog-to-digital converter of claim 1 wherein said second configurable analog-to-digital converter comprises a cascaded configurable time amplifier and successive approximation type time-to-digital converter wherein,
the configurable time amplifier is used for amplifying the input allowance time signal to obtain an amplified time signal;
the successive approximation type time-to-digital converter is used for successively quantizing the input amplified time signal to generate a corresponding digital code and a residual time signal.
6. The configurable time domain pipelined analog-to-digital converter of claim 5 wherein said configurable time amplifier comprises a cascaded configurable time-to-voltage converter and a configurable voltage-to-time converter wherein,
the configurable time-to-voltage converter is used for controlling the on time of the current source according to the input margin time signal and converting the on time of the current source into a voltage signal stored on the switch capacitor array;
the configurable voltage-time converter is used for converting an input voltage signal into a time signal to obtain an amplified time signal;
wherein the time gain of the configurable time amplifier is configured by the configurable time-to-voltage converter and the capacitance of the switched capacitor array in the configurable voltage-to-time converter during signal amplification.
7. The configurable time domain pipelined analog-to-digital converter of claim 6, wherein said configurable time-to-voltage converter comprises: a trigger unit, a logic gate, a charging current source, a discharging current source and two second switched capacitor arrays, wherein,
the trigger unit and the logic gate generate corresponding current source control signals according to the input allowance time signals;
the first end of the charging current source is connected with the power supply end, and the second end of the charging current source is connected with a capacitor upper polar plate of a second switch capacitor array through a current source control switch;
the first end of the discharge current source is connected with the upper capacitor plate of the other second switched capacitor array through the current source control switch, and the second end of the discharge current source is connected with the grounding end;
the capacitor lower polar plates of the two second switch capacitor arrays are connected with the grounding end;
controlling the quantity of capacitors connected with corresponding current sources in the second switch capacitor array through an external second selection signal;
and the upper capacitor plates of the two second switch capacitor arrays are used as output ends to be connected with the input ends of the configurable voltage-time converter.
8. The configurable time domain pipelined analog-to-digital converter of claim 7 wherein the currents of the configurable time-to-voltage converter and the current source of the configurable voltage-to-time converter in the configurable time amplifier are equal.
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