CN117202711A

CN117202711A - Display panel and display device

Info

Publication number: CN117202711A
Application number: CN202311259421.1A
Authority: CN
Inventors: 刘宁; 闫梁臣; 周斌
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2023-09-26
Filing date: 2023-09-26
Publication date: 2023-12-08

Abstract

The disclosure provides a display panel and a display device, and relates to the technical field of display. The display surface comprises a substrate base plate, a driving layer and a pixel layer which are arranged in a stacked mode; the driving layer is provided with an auxiliary electrode, a conductive structure and a source-drain metal layer; the conductive structure and the source-drain metal layer are positioned on different film layers and are electrically connected; the pixel layer comprises a pixel electrode layer, a light-emitting functional layer and a public electrode layer which are sequentially laminated on one side of the driving layer far away from the substrate; the pixel electrode layer is formed with a lap joint structure and a pixel electrode; the common electrode layer is electrically connected with the lap joint structure, the lap joint structure is electrically connected with the auxiliary electrode through the auxiliary electrode connecting hole, and the pixel electrode is electrically connected with the conductive structure through the via hole. The display panel can reduce the phenomenon of bad dark spots.

Description

Display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display panel and a display device.

Background

The transparent display product is widely applied to vehicle-mounted displays such as automobiles and subways, hotels, clothing stores, showcases and the like, and has the remarkable advantages of clear image quality, vivid display effect and the like. In order to improve the transparency effect, the cathode IZO (indium zinc oxide) is made thin, so that the large-size transparent display product has a large cathode IR drop (voltage drop) problem, and an effective solution is to effectively lap the cathode and an auxiliary electrode on the backboard, so that the IR drop problem is greatly reduced. At present, an effective lap joint mode is to prepare an I-shaped Rib structure on a backboard, so that a Tip angle protruding from the upper end can smoothly cut off a light-emitting material evaporated, then cathode IZO can be formed to be smoothly lapped with an auxiliary cathode, and the auxiliary cathode has strong conductivity, so that the problem of cathode IR drop can be smoothly solved.

However, in the current product design, only an ITO1 (indium tin oxide) film layer covers the Via hole of the pixel region, and as the ITO film layer is easy to crack, etching liquid is extremely easy to flow into the Via hole along the ITO crack above the Via Via hole when the Rib preparation etching process is carried out later, the etching liquid is contacted with the SD film layer (source drain metal layer), so that serious corrosion phenomenon is caused on the SD film layer below, and finally, the overlap joint defect is caused by the crack between the SD film layer of the source drain metal layer and the ITO film layer above, so that dark spot defect occurs, and the display effect of the product is seriously affected.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to overcoming the drawbacks of the prior art and providing a display panel and a display device.

According to a first aspect of the present disclosure, there is provided a display panel including: a substrate, a driving layer and a pixel layer which are stacked;

the driving layer is provided with an auxiliary electrode, a conductive structure and a source-drain metal layer; the conductive structure and the source-drain metal layer are positioned on different film layers and are electrically connected;

the pixel layer comprises a pixel electrode layer, a light-emitting functional layer and a common electrode layer which are sequentially laminated on one side of the driving layer far away from the substrate; the pixel electrode layer is formed with a lap joint structure and a pixel electrode; the common electrode layer is electrically connected with the lap joint structure, the lap joint structure is electrically connected with the auxiliary electrode through the auxiliary electrode connecting hole, and the pixel electrode is electrically connected with the conductive structure through the via hole.

According to one embodiment of the present disclosure, the pixel electrode layer includes a first electrode layer, an electrode buffer layer, a reflective electrode layer, and a second electrode layer sequentially stacked on a side of the driving layer away from the substrate base plate;

the first electrode layer is electrically connected with the driving layer through the conductive structure.

According to one embodiment of the disclosure, the driving layer is provided with a conductive protection layer, and the protection layer is located on one side of the source drain metal layer away from the substrate base plate;

the conductive structure is positioned on the protective layer.

According to one embodiment of the disclosure, the material of the protective layer is conductive metal oxide.

According to one embodiment of the disclosure, the protective layer is laminated on the surface of the source-drain metal layer, which is far away from one side of the substrate; and the orthographic projection of the protective layer on the substrate does not exceed the orthographic projection of the source-drain metal layer on the substrate.

According to one embodiment of the present disclosure, the driving layer is provided with a light shielding metal layer between the thin film transistor of the driving layer and the substrate;

the conductive structure is located on the shading metal layer and is electrically connected with the source drain metal layer through the via hole.

According to one embodiment of the disclosure, the driving layer is provided with a pixel driving circuit, and the auxiliary electrode is located on the source-drain metal layer;

the source drain metal layer further comprises a transfer pad serving as an output end of the pixel driving circuit, and the transfer pad is electrically connected with the pixel electrode through the conductive structure.

According to one embodiment of the present disclosure, the pixel electrode layer includes a first electrode layer, an electrode buffer layer, a barrier metal layer, a reflective electrode layer, and a second electrode layer sequentially stacked on a side of the driving layer away from the substrate base plate;

the pixel electrode includes an electrode body and a connection lead;

the electrode body comprises a first substructure located on the first electrode layer, a second substructure located on the electrode buffer layer, a third substructure located on the reflective electrode layer, and a fourth substructure located on the second electrode layer;

the connecting lead is located on the first electrode layer and is electrically connected with the conductive structure through the via hole.

the pixel electrode includes an electrode body and a connection lead;

the electrode body comprises a first electrode sub-layer positioned on the first electrode layer, a second electrode sub-layer positioned on the electrode buffer layer, a third electrode sub-layer positioned on the reflecting electrode layer and a fourth electrode sub-layer positioned on the second electrode layer;

the overlap joint structure comprises a first overlap joint sublayer positioned on the first electrode layer, a second overlap joint sublayer positioned on the electrode buffer layer, a third overlap joint sublayer positioned on the partition metal layer, a fourth overlap joint sublayer positioned on the reflecting electrode layer and a fifth overlap joint sublayer positioned on the second electrode layer;

the connecting lead comprises a first lead sub-layer positioned on the first electrode layer, a second lead sub-layer positioned on the isolating metal layer, a third lead sub-layer positioned on the reflecting electrode layer and a fourth lead sub-layer positioned on the second electrode layer;

and the connecting lead is electrically connected with the source-drain metal layer through the via hole.

According to a second aspect of the present disclosure, there is provided a display panel, wherein the driving layer is not provided with the conductive structure, and the connection lead is directly and electrically connected to the source drain metal layer through a via hole.

According to a third aspect of the present disclosure, there is provided a display device including the display panel.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a schematic diagram of a film structure of a display panel in an exemplary implementation of the present disclosure.

Fig. 2 is a schematic diagram of a film structure of a display panel according to the prior art in an exemplary implementation of the present disclosure.

Fig. 3 is an enlarged view of a portion a of fig. 2.

Fig. 4 is an enlarged view of a portion B of fig. 3.

Fig. 5 is a schematic diagram of a structure of a via hole exposing a light shielding metal layer formed before a source drain metal layer is prepared in an exemplary embodiment of the present disclosure.

Fig. 6 is a schematic diagram of forming a source drain metal layer structure in an exemplary implementation of the present disclosure.

Fig. 7 is a schematic diagram of a structure of a via hole for forming a source drain metal layer and a via hole exposing a light shielding metal layer in an exemplary implementation of the present disclosure.

Fig. 8 is a schematic structural view of forming a first electrode layer in an exemplary implementation of the present disclosure.

Fig. 9 is a schematic diagram of a structure for forming a pixel layer in a first exemplary implementation of the present disclosure.

Fig. 10 is a schematic structural view of a display panel in a second exemplary embodiment of the present disclosure.

Fig. 11 is an enlarged view of a portion C of fig. 10.

Fig. 12 is a schematic structural view of a display panel according to a third exemplary embodiment of the present disclosure.

Fig. 13 is an enlarged view of a portion D of fig. 12.

Reference numerals illustrate:

SBT and substrate base plate; DRL, driving layer; AE. An auxiliary electrode; SD, source drain metal layer; LS, shading metal layer; PIXL, pixel layer; PEL, pixel electrode layer; ITOL1, a first electrode layer; BUFITOL, electrode buffer layer; RA, reflective electrode layer; ITOL2, a second electrode layer; PTSL, barrier metal layer; a PDL, pixel definition layer; EFL, light-emitting functional layer; COML, common electrode layer; PL, protective layer; PE, pixel electrode; PEB, electrode body; ES1, first electrode sub-layer; ES2, second electrode sublayers; ES3, third electrode sub-layer; ES4, fourth electrode sub-layer; RIB, lap joint construction; RIB1, first lap sublayer; RIB2, second lap sublayer; RIB3, third lap sublayer; RIB4, fourth lap sublayer; RIB5, fifth lap sublayer; CS, conductive structure; PVX, passivation layer; PLN, planarization layer; ILD, interlayer dielectric layer; BUF, buffer layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.

The disclosed embodiments provide a display panel including a display region and a non-display region located on at least one side of the display region, e.g., the non-display region surrounds the display region. In the display area, the display panel is provided with subpixels for display; in the non-display area, the display panel may not be provided with sub-pixels for display, or the sub-pixels provided are not used for displaying a picture.

In the embodiment of the present disclosure, the sub-pixels in the display panel are thin film type self-luminous light emitting elements, such as OLED (organic light emitting diode), PLED (polymer light emitting diode), QLED (quantum dot light emitting diode), etc., and it is understood that the types of the light emitting elements are different, and the materials and the film layers of the light emitting functional units are different. Further, the light emitting elements in the display area include light emitting elements of a plurality of different colors. For example, the light emitting elements include a red light emitting element for emitting red light, a blue light emitting element for emitting blue light, and a green light emitting element for emitting green light. It is understood that in other embodiments of the present disclosure, the light emitting elements in the display area may also be light emitting elements of only one color, or may also have light emitting elements of other colors (e.g., a yellow light emitting element for emitting yellow light, a cyan light emitting element for emitting cyan light, a white light emitting element for emitting white light, etc.).

In one embodiment of the present disclosure, referring to fig. 1, a display panel may include a driving substrate DBP (including a substrate SBT and a driving layer DRL) and a pixel layer PIXL, in which a light emitting element is disposed, which are sequentially stacked, the driving layer DRL being for driving the light emitting element in the pixel layer PIXL. The driving substrate DBP may drive the light emitting elements by active driving, or may drive the light emitting elements by passive driving.

In one embodiment of the present disclosure, referring to fig. 1, a driving substrate DBP includes a substrate SBT and a driving layer DRL provided at one side of the substrate SBT; the pixel layer PIXL is disposed on a side of the driving layer DRL away from the substrate SBT. The driving layer DRL is provided with a pixel driving circuit for driving the light emitting element; the respective light emitting elements may emit light to display a picture under the driving of the pixel driving circuit.

Alternatively, the substrate SBT may be a substrate of an inorganic material or a substrate of an organic material; of course, a composite substrate in which a base substrate of an inorganic material and a base substrate of an organic material are laminated may be used.

For example, in some embodiments of the present disclosure, the material of the substrate base plate SBT may be a glass material such as soda lime glass, quartz glass, sapphire glass, or the like. In further embodiments of the present disclosure, the material of the substrate base SBT may be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In other embodiments of the present disclosure, the substrate SBT may also be a flexible substrate, for example the material of the substrate SBT may comprise polyimide.

It is to be understood that the above examples of the substrate SBT are only one possible way of substrate SBT of embodiments of the present disclosure. In other embodiments of the present disclosure, the substrate SBT may also be other structures, for example, the substrate SBT may also be a passive driving glass substrate, a silicon-based driving substrate, or the like.

Alternatively, in the driving layer DRL, any one of the pixel driving circuits may include a thin film transistor and a storage capacitor. Further, the thin film transistor may be selected from a top gate thin film transistor, a bottom gate thin film transistor, or a double gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polysilicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

It will be appreciated that the type between any two transistors in the individual transistors in the pixel drive circuit may be the same or different. Illustratively, in some embodiments, in one pixel driving circuit, a portion of the transistors may be N-type transistors and a portion of the transistors may be P-type transistors. Still further exemplary, in other embodiments, in one pixel driving circuit, the material of the active layer of the partial transistor may be a low temperature polysilicon semiconductor material, and the material of the active layer of the partial transistor may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low temperature polysilicon transistor. In other embodiments of the present disclosure, a portion of the thin film transistors are low temperature polysilicon transistors and a portion of the thin film transistors are metal oxide transistors.

Alternatively, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source drain metal layer SD, a planarization layer PLN, and the like stacked between the substrate SBT and the pixel layer PIXL. Each of the thin film transistors and the storage capacitor may be formed of a film layer such as a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source drain metal layer SD, or the like. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor.

Further, the semiconductor layer SCL may be used to form a channel region of a transistor, and a part of the wiring may also be formed by conductor formation if necessary. The gate layer GT may be used to form one or more of the scan lines, the reset control lines, the light emission control lines, and the like, may be used to form a gate of a transistor, and may be used to form part or all of the electrode plates of the storage capacitor. The source drain metal layer SD may be used to form source drain metal layer traces such as data traces and driving power supply voltage traces, and may also be used to form part of electrode plates of the storage capacitor.

Of course, in other embodiments of the present disclosure, the driving layer DRL may further include other film layers as needed, and any one of the film layers of the semiconductor layer SCL, the gate layer GT, the source drain metal layer SD, etc. may also be multiple layers, for example, the driving layer DRL may include two different semiconductor layers SCL, or include two or three source drain metal layers SD, or include two or three gate layers GT; accordingly, the insulating film layer (e.g., gate insulating layer GI, interlayer dielectric layer ILD, planarizing layer PLN, etc.) in the driving layer DRL may be increased or decreased adaptively, or a new insulating film layer may be added as needed.

Optionally, the driving layer DRL may further include a passivation layer PVX, where the passivation layer PVX may be disposed on a surface of the source drain metal layer SD away from the substrate SBT, so as to protect the source drain metal layer SD.

As an example, referring to fig. 1, the driving layer DRL may include a buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source drain metal layer SD, and a planarization layer PLN, which are sequentially stacked, and thus the thin film transistor formed is a top gate thin film transistor.

Referring to fig. 1, the light emitting element in the pixel layer PIXL is a thin film type light emitting element, which may include two electrodes disposed in a stacked manner and a light emitting functional unit interposed between the two electrodes. For example, the pixel layer PIXL may include a pixel electrode layer PEL, a light emitting function layer EFL, and a common electrode layer COML, which are sequentially stacked. The pixel electrode layer PEL is provided with a plurality of pixel electrodes PE in a display area of the display panel; the portion of the light emitting function layer EFL connected to the pixel electrode PE serves as a light emitting function unit of the light emitting element, and the common electrode layer COML serves as a common electrode electrically connected to the light emitting function units of the respective light emitting elements.

Further, the pixel layer PIXL may further include a pixel defining layer PDL between the pixel electrode layer PEL and the light emitting function layer EFL. The pixel defining layer PDL has a plurality of through pixel openings provided in one-to-one correspondence with the plurality of pixel electrodes PE, and any one of the pixel openings exposes at least a partial region of the corresponding pixel electrode PE. For example, the pixel defining layer PDL covers the edge of the pixel electrode PE and exposes at least a part of the inner area of the pixel electrode PE, so that the pixel defining layer PDL can effectively define the actual effective area (the area directly connected to the light emitting functional unit) of the pixel electrode PE, thereby defining the light emitting area and the light emitting area of the light emitting element. The light emitting function layer EFL covers at least the pixel electrode PE exposed by the pixel defining layer PDL. The common electrode layer COML may cover the light emitting function layer EFL in the display region. The pixel electrode PE and the common electrode layer COML supply carriers such as electrons, holes, and the like to the light emitting function layer EFL to cause the light emitting function layer EFL to emit light. The portion of the light emitting function layer EFL between the pixel electrode PE and the common electrode layer COML may serve as a light emitting function unit. The pixel electrode PE, the common electrode layer COML, and the light emitting functional unit form a light emitting element. One of the pixel electrode PE and the common electrode layer COML serves as an anode of the light emitting element, and the other serves as a cathode of the light emitting element.

In some embodiments, the pixel layer PIXL may further include a light extraction layer on a side of the common electrode layer COML remote from the substrate SBT to enhance light extraction efficiency of the organic light emitting diode.

Referring to fig. 1, a thin film encapsulation layer TFE may be provided on a surface of the pixel layer PIXL remote from the substrate base plate SBT, which may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic packaging layer can effectively block external moisture and oxygen, and avoids aging of materials in the pixel layer PIXL caused by invasion of the moisture and the oxygen into the pixel layer PIXL.

Alternatively, the edges of the inorganic encapsulation layer may be located at the peripheral region. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers in order to achieve planarization and to attenuate stresses between the inorganic encapsulation layers. Wherein an edge of the organic encapsulation layer may be located between an edge of the display region and an edge of the inorganic encapsulation layer.

Further, referring to fig. 1, the display panel PNL further includes a thin film encapsulation layer TFE located on a side of the pixel layer PIXL away from the driving substrate DBP, where the thin film encapsulation layer TFE may encapsulate and protect the pixel layer PIXL. The thin film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2 laminated in this order on a side of the pixel layer PIXL remote from the substrate SBT. Of course, in other embodiments of the present disclosure, the display panel may not be provided with the thin film encapsulation layer TFT, and the pixel layer PIXL may be encapsulated and protected in other manners.

In some embodiments of the present disclosure, referring to fig. 1, the display panel may further include a touch functional layer TSL, and the touch functional layer TSL may be disposed on a side of the thin film encapsulation layer TFE away from the driving substrate DBP, so that the display panel has a touch function.

In the prior art, referring to fig. 2, 3 and 4, only the first electrode layer ITOL1 covers the via hole of the pixel region, but the first electrode layer ITOL1 is prone to crack, so that when the overlap joint structure RIB is prepared, etching liquid in the wet etching process flows onto the source drain metal layer SD through the via hole of the pixel region, which causes corrosion of the source drain metal layer SD, and when the first electrode layer ITOL1 overlaps the source drain metal layer SD, the overlap joint failure phenomenon between the source drain metal layer SD and the first electrode layer ITOL1 is prone to occur, thereby causing poor dark spots of the display panel.

Based on this, the present disclosure provides a display panel including a substrate SBT, a driving layer DRL, and a pixel layer PIXL that are stacked, referring to fig. 9, 10, and 12; the driving layer DRL is provided with an auxiliary electrode AE, a conductive structure CS and a source drain metal layer SD; the conductive structure CS and the source drain metal layer SD are positioned on different film layers and are electrically connected with each other; the pixel layer PIXL includes a pixel electrode layer PEL, a light emitting functional layer EFL, and a common electrode layer COML sequentially stacked on a side of the driving layer DRL away from the substrate SBT; the pixel electrode layer PEL is formed with a lap joint structure RIB and a pixel electrode PE; the common electrode layer COML is electrically connected with the landing structure RIB, which is electrically connected with the auxiliary electrode AE through the auxiliary electrode connection hole, and the pixel electrode PE is electrically connected with the conductive structure CS through the via hole.

The display panel provided by the disclosure has the driving layer DRL provided with the conductive structure CS, wherein the conductive structure CS and the source drain metal layer SD are positioned on different film layers, and the conductive structure CS is electrically connected with the source drain metal layer SD; the pixel electrode PE is not in direct contact with the source drain metal layer SD, so that the phenomenon of poor lap joint of the pixel electrode PE and the source drain metal layer SD is reduced, dark spot defects in the display panel are further reduced, and the display quality of the display panel is improved.

In one embodiment of the present disclosure, referring to fig. 9, the pixel electrode layer PEL includes a first electrode layer ITOL1, an electrode buffer layer BUFITOL, a reflective electrode layer RA, and a second electrode layer ITOL2 sequentially stacked on a side of the driving layer DRL away from the substrate base plate SBT; the first electrode layer ITOL1 is electrically connected with the driving layer DRL through the conductive structure CS; it is understood that in other embodiments of the present disclosure, the pixel electrode layer PEL may have other structures.

In one embodiment of the present disclosure, referring to fig. 10 and 11, the driving layer DRL is provided with a conductive protection layer PL, which is located on a side of the source drain metal layer SD away from the substrate SBT; the conductive structure CS is located on the protective layer PL; when the protective layer PL is prepared, a metal layer is prepared on the source-drain metal layer SD, and then the prepared metal layer is patterned to form the protective layer PL.

In one example of this embodiment, the material of the protective layer PL is a conductive metal oxide. Optionally, the oxide of the conductive metal may be ITO (indium tin oxide), which is, of course, not limited to this, but only capable of reducing the corrosion of the etching solution to the source/drain metal layer SD in the etching process when the RIB of the lap joint structure is prepared.

In one embodiment of the present disclosure, referring to fig. 10, a protective layer PL is laminated on a surface of the source drain metal layer SD on a side away from the substrate base plate SBT; the front projection of the protective layer PL on the substrate SBT does not exceed the front projection of the source drain metal layer SD on the substrate SBT, in other words, the pattern of the protective layer PL and the pattern of the source drain metal layer SD on the display area are consistent.

In another embodiment of the present disclosure, referring to fig. 9, the driving layer DRL may be further provided with a light shielding metal layer LS between the thin film transistor of the driving layer DRL and the substrate SBT; the conductive structure CS is located on the light shielding metal layer LS, and the conductive structure CS is electrically connected to the source drain metal layer SD through the via hole. The light shielding metal layer LS may be directly formed on the surface of the substrate SBT. The light shielding metal layer LS may be disposed to overlap with a channel region of the transistor in the semiconductor layer SCL so as to shield light irradiated to the channel region. Furthermore, the light shielding metal layer LS may further form a structure such as a wiring and be electrically connected to at least one of the gate layer GT, the semiconductor layer SCL, the source drain metal layer SD, and the like, so as to form a capacitor and/or be used as an electrical connection patch cord.

Referring to fig. 5, when preparing the light shielding metal layer LS, a substrate SBT is provided first, and then a light shielding metal layer LS is prepared on the substrate SBT, where the light shielding metal layer LS is located between the thin film transistor of the driving layer DRL and the substrate SBT, and the formed light shielding metal layer LS can shield the photosensitive device in the display panel, so as to help to improve the quality of the display panel. Next, a buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, and a gate layer GT are sequentially formed on the light shielding metal layer LS. And conducting treatment is carried out on the semiconductor layer SCL by adopting a self-alignment process, then an interlayer dielectric layer ILD is formed, and a via hole is etched at the buffer layer BUF and the interlayer dielectric layer ILD by adopting an etching process.

Referring to fig. 6, a metal layer is formed on the interlayer dielectric layer ILD, the source and drain metal layers SD are patterned to form a source and drain metal layer SD, then a metal layer is formed, the metal layer is patterned to form an auxiliary electrode AE, and referring to fig. 7, a passivation layer PVX and a planarization layer PLN are sequentially formed on the source and drain metal layer SD and the auxiliary electrode AE, specifically, the material of the planarization layer PLN is a resin.

In one embodiment of the present disclosure, the driving layer DRL is provided with a pixel driving circuit, and the auxiliary electrode AE is located on the source-drain metal layer SD; the source drain metal layer SD further includes a transfer pad as an output terminal of the pixel driving circuit, and the transfer pad is electrically connected to the pixel electrode PE through the conductive structure CS.

In one embodiment of the present disclosure, referring to fig. 8 and 9, the pixel electrode layer PEL includes a first electrode layer ITOL1, an electrode buffer layer BUFITOL, a barrier metal layer PTSL, a reflective electrode layer RA, and a second electrode layer ITOL2 sequentially stacked on a side of the driving layer DRL away from the substrate SBT; the pixel electrode PE includes an electrode body PEB and a connection lead; the electrode body PEB includes a first substructure located at the first electrode layer ITOL1, a second substructure located at the electrode buffer layer BUFITOL, a third substructure located at the reflective electrode layer RA, and a fourth substructure located at the second electrode layer ITOL2; the connecting lead is located on the first electrode layer ITOL1 and is electrically connected to the conductive structure CS through a via.

In another embodiment of the present disclosure, referring to fig. 9, the pixel electrode layer PEL includes a first electrode layer ITOL1, an electrode buffer layer BUFITOL, a barrier metal layer PTSL, a reflective electrode layer RA, and a second electrode layer ITOL2 sequentially stacked on a side of the driving layer DRL away from the substrate base plate SBT; the pixel electrode PE includes an electrode body PEB and a connection lead; the electrode body PEB includes a first electrode sub-layer ES1 located at the first electrode layer ITOL1, a second electrode sub-layer ES2 located at the electrode buffer layer BUFITOL, a third electrode sub-layer ES3 located at the reflective electrode layer RA, and a fourth electrode sub-layer ES4 located at the second electrode layer ITOL2; the lap joint structure RIB comprises a first lap joint sublayer RIB1 positioned at the first electrode layer ITOL1, a second lap joint sublayer RIB2 positioned at the electrode buffer layer BUFITOL, a third lap joint sublayer RIB3 positioned at the partition metal layer PTSL, a fourth lap joint sublayer RIB4 positioned at the reflective electrode layer RA and a fifth lap joint sublayer RIB5 positioned at the second electrode layer ITOL2; the connecting lead comprises a first lead sub-layer positioned at the first electrode layer ITOL1, a second lead sub-layer positioned at the partition metal layer PTSL, a third lead sub-layer positioned at the reflective electrode layer RA and a fourth lead sub-layer positioned at the second electrode layer ITOL2; the connection lead is electrically connected to the source drain metal layer SD through the via hole.

In another embodiment of the present disclosure, referring to fig. 12 and 13, the driving layer DRL is not provided with the conductive structure CS, and the connection lead is directly electrically connected to the source drain metal layer SD through the via hole. When the pixel electrode layer PEL is prepared, sequentially preparing a first electrode layer ITOL1 on the planarization layer PLN, and performing pattern processing on the first electrode layer ITOL1 to form a first electrode sub-layer ES1, a first lead sub-layer and a first lap joint sub-layer RIB1; preparing an electrode buffer layer BUFIOL at one side of the first electrode layer ITOL1 far away from the planarization layer PLN, and performing patterning treatment on the electrode buffer layer BUFIOL to form a second electrode sub-layer ES2 and a second lap joint sub-layer RIB2; forming a partition metal layer PTSL on one side of the electrode buffer layer BUFIOL far away from the first electrode layer ITOL1, and performing patterning treatment on the partition metal layer PTSL to form a second lead sub-layer and a third lap joint sub-layer RIB3; forming a reflective electrode layer RA on one side of the partition metal layer PTSL far away from the electrode buffer layer BUFIOL, and patterning the reflective electrode layer RA to form a third electrode sub-layer ES3, a third lead sub-layer and a fourth lap joint sub-layer RIB4; the second electrode layer ITOL2 is formed on the side of the reflective electrode layer RA away from the barrier metal layer PTSL, and the second electrode layer ITOL2 is patterned to form a fourth electrode sub-layer ES4, a fourth lead sub-layer, and a fifth overlap sub-layer RIB5. The formed landing structure RIB includes a first landing sub-layer RIB1 located at the first electrode layer ITOL1, a second landing sub-layer RIB2 located at the electrode buffer layer BUFITOL, a third landing sub-layer RIB3 located at the barrier metal layer PTSL, a fourth landing sub-layer RIB4 located at the reflective electrode layer RA, and a fifth landing sub-layer RIB5 located at the second electrode layer ITOL 2. The via hole of the source drain metal layer SD is covered by the first lead sub-layer, the second lead sub-layer, the third lead sub-layer and the fourth lead sub-layer, so that the phenomenon that etching liquid flows onto the source drain metal layer SD through the via hole of the source drain metal layer SD is reduced.

The present disclosure provides a display device including a display panel in an embodiment of the present disclosure.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. The display panel is characterized by comprising a substrate base plate, a driving layer and a pixel layer which are arranged in a stacked manner;

2. The display panel according to claim 1, wherein the pixel electrode layer includes a first electrode layer, an electrode buffer layer, a reflective electrode layer, and a second electrode layer sequentially stacked on a side of the driving layer away from the substrate;

3. The display panel according to claim 1, wherein the driving layer is provided with a conductive protective layer, the protective layer being located on a side of the source drain metal layer away from the substrate base plate;

the conductive structure is positioned on the protective layer.

4. The display panel according to claim 3, wherein the material of the protective layer is conductive metal oxide.

5. The display panel according to claim 3, wherein the protective layer is laminated on a surface of the source-drain metal layer on a side away from the substrate; and the orthographic projection of the protective layer on the substrate does not exceed the orthographic projection of the source-drain metal layer on the substrate.

6. The display panel according to claim 1, wherein the driving layer is provided with a light shielding metal layer between the thin film transistor of the driving layer and the substrate;

7. The display panel according to claim 1, wherein the driving layer is provided with a pixel driving circuit, and the auxiliary electrode is located in the source-drain metal layer;

8. The display panel according to claim 1, wherein the pixel electrode layer includes a first electrode layer, an electrode buffer layer, a barrier metal layer, a reflective electrode layer, and a second electrode layer which are sequentially stacked on a side of the driving layer away from the substrate;

the pixel electrode includes an electrode body and a connection lead;

9. The display panel according to claim 1, wherein the pixel electrode layer includes a first electrode layer, an electrode buffer layer, a barrier metal layer, a reflective electrode layer, and a second electrode layer which are sequentially stacked on a side of the driving layer away from the substrate;

the pixel electrode includes an electrode body and a connection lead;

10. The display panel according to claim 9, wherein the conductive structure is not provided in the driving layer, and the connection lead is directly electrically connected to the source drain metal layer through a via hole.

11. A display device comprising a display panel according to any one of claims 1-10.