CN117202697A

CN117202697A - Display substrate, preparation method thereof and display device

Info

Publication number: CN117202697A
Application number: CN202311117262.1A
Authority: CN
Inventors: 孙韬; 王涛; 洪瑞; 陈登云; 张慧娟; 余星星; 吴桐; 孙凯
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2023-08-31
Filing date: 2023-08-31
Publication date: 2023-12-08

Abstract

The disclosure provides a display substrate, a preparation method thereof and a display device, wherein the display substrate comprises: a substrate base; a plurality of pixels arranged in an array on the substrate, each pixel including a plurality of sub-pixels, each sub-pixel including a first electrode, an organic light emitting functional layer, and a second electrode stacked on the substrate; a pixel defining layer on the substrate, the pixel defining layer including a plurality of pixel openings, each pixel opening corresponding to a sub-pixel; the spacer is arranged on the pixel defining layer and is positioned in the interval area of the plurality of pixel openings; and the isolation columns are at least partially arranged on the isolation pad, are arranged around each sub-pixel and are used for isolating the organic light-emitting functional layers of the adjacent sub-pixels, each isolation column has conductive characteristic, the isolation columns around each sub-pixel are mutually conducted, and the second electrode of each sub-pixel is lapped on the isolation column and is conducted with the isolation column.

Description

Display substrate, preparation method thereof and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display substrate, a preparation method thereof and a display device.

Background

With the development of display technology, the requirements on the resolution of display products are increasing. In order to achieve high resolution, a high-precision Mask (Mask) design such as a high-precision Metal Mask (FMM) is generally adopted, but technical difficulties exist in process implementation, particularly after the resolution is more than 800ppi, high-precision screen-tensioning technology and vapor deposition alignment technology are difficult to achieve, and Mask material cost is high. Thus, a process of realizing sub-pixel patterning (pattern) by using a photolithography technique has been developed. Compared with the FMM technology, the method has higher precision and higher pixel aperture ratio, the color mixing problem and the crosstalk problem can be solved along with replacing the FMM, display definition and color and uniformity expression capability are improved, and the method is beneficial to further expanding the coverage of Organic Light-Emitting Diode (OLED) devices in application scenes with various sizes.

However, in the process of photolithography of an organic electroluminescent device such as an OLED, in order to prevent the organic light-emitting functional material evaporated during the process from being corroded by water and oxygen, the evaporation material is usually separated by a separation column and temporarily encapsulated, but the separation column separates the evaporation material and simultaneously an electrode layer formed on the organic light-emitting functional material is also separated to become a discontinuous film layer, which is easy to cause poor display.

Disclosure of Invention

The display substrate, the preparation method thereof and the display device can effectively solve the problems.

In a first aspect, some embodiments of the present disclosure provide a display substrate, including: a substrate base; a plurality of pixels arranged in an array on the substrate, each pixel including a plurality of sub-pixels, each sub-pixel including a first electrode, an organic light emitting functional layer, and a second electrode stacked on the substrate; a pixel defining layer on the substrate, the pixel defining layer including a plurality of pixel openings, each pixel opening corresponding to one of the sub-pixels, each pixel opening exposing at least a portion of a region of a first electrode of a corresponding sub-pixel; the spacer is arranged on the pixel defining layer and is positioned in the interval area of the pixel openings; and the isolation columns are at least partially positioned on the isolation pad, are arranged around the sub-pixels and are used for isolating the organic light-emitting functional layers of the adjacent sub-pixels, the isolation columns have conductive characteristics, the isolation columns around the sub-pixels are mutually conducted, and the second electrode of each sub-pixel is lapped on the isolation column and is conducted with the isolation column.

Optionally, at least part of the isolation posts are disposed obliquely with respect to a direction perpendicular to the substrate base plate.

Optionally, the spacer column on at least one side around each sub-pixel is inclined away from the corresponding pixel opening.

Optionally, each of the sub-pixels includes a first side and a second side disposed opposite to the first side, and the inclination directions of the isolation columns on the first side and the second side of each of the sub-pixels are the same.

Optionally, for a target sub-pixel of the plurality of sub-pixels, the isolation column surrounding the target sub-pixel is inclined with respect to a direction perpendicular to the substrate toward a direction away from the pixel opening of the target sub-pixel.

Optionally, for the obliquely arranged isolation column, an orthographic projection of a bottom surface of the isolation column on the substrate and an orthographic projection of the spacer on the substrate at least partially overlap, wherein the bottom surface is a surface relatively close to the substrate.

Optionally, for the obliquely arranged isolation column, one end of a bottom surface of the isolation column is lapped on the spacer, the other end is lapped on the pixel defining layer, and the bottom surface is relatively close to the surface of the substrate.

Optionally, the overlapping distance between the isolation column and the isolation pad is greater than or equal to 3 μm.

Optionally, the width of the spacer is less than one third of the distance between the pixel openings of adjacent sub-pixels; and the height of the spacer is 0.2-3 mu m along the direction vertical to the substrate.

Optionally, the spacer has a slope surface, the slope surface is inclined towards a direction away from the pixel opening, and the slope surface is an arc surface or a plane surface.

Optionally, the cross-sectional shape of the spacer is arched, or the cross-sectional shape of the spacer is trapezoidal, the trapezoid includes a first side and a second side that are disposed opposite to each other, the width of the first side is smaller than the width of the second side, and the second side is closer to the substrate than the first side.

Optionally, the isolation column includes a first metal layer, a second metal layer and a third metal layer that are stacked, edges of the first metal layer and the third metal layer protrude relative to the second metal layer, and at least a partial area of the first metal layer is set on the surface of the spacer along with the shape.

In a second aspect, some embodiments of the present disclosure provide a method for manufacturing a display substrate, where the display substrate includes a plurality of pixels arranged in an array, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a first electrode, an organic light emitting functional layer, and a second electrode that are stacked. The method comprises the following steps: providing a back plate, wherein the back plate comprises a substrate base plate; forming a first electrode of each sub-pixel on the back plate, and forming a pixel defining layer on the first electrode, the pixel defining layer including a plurality of pixel openings, each pixel opening exposing at least a portion of a region of the first electrode of one sub-pixel; forming a spacer on the pixel defining layer, and forming isolation columns on the spacer, wherein the isolation columns are arranged around each sub-pixel, at least part of the isolation columns are positioned on the spacer, the isolation columns have conductive characteristics, and the isolation columns around each sub-pixel are mutually communicated; forming organic light-emitting functional layers of all sub-pixels, wherein the organic light-emitting functional layers of adjacent sub-pixels are separated by the isolation columns; and forming a second electrode covering the organic light-emitting functional layer, wherein the second electrode of each sub-pixel is lapped on the isolation column and is communicated with the isolation column.

In a third aspect, some embodiments of the present disclosure provide a display apparatus, including: the display substrate provided in the first aspect.

In the display substrate, the preparation method thereof and the display device provided by some embodiments of the present disclosure, the spacer is additionally arranged to raise the spacer, so that the distance from the top of the spacer to the pixel defining layer can be lengthened, thereby increasing the film forming space of the second electrode, increasing the overlap area of the second electrode and the spacer, reducing the contact resistance, improving the luminous efficiency of the sub-pixel, and being beneficial to improving the problem of poor display caused by poor overlap of the second electrode and the spacer.

The foregoing description is merely an overview of the technical solutions provided by the embodiments of the present disclosure, and in order to make the technical means of the embodiments of the present disclosure more clear, it may be implemented according to the content of the specification, and in order to make the foregoing and other objects, features and advantages of the embodiments of the present disclosure more understandable, the following detailed description of the embodiments of the present disclosure will be given.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings that are required to be used in the description of the embodiments will be briefly described below. It will be apparent to those of ordinary skill in the art that the drawings in the following description are of some embodiments of the present disclosure and that other drawings may be derived from these drawings without undue effort.

FIG. 1 illustrates a schematic plan view of a display substrate of some embodiments of the present disclosure;

FIG. 2 illustrates an exemplary pixel layout diagram of some embodiments of the present disclosure;

FIG. 3 illustrates another exemplary pixel layout diagram of some embodiments of the present disclosure;

FIG. 4 illustrates a schematic diagram of a film layer stack relationship of a display substrate according to some embodiments of the present disclosure;

FIG. 5 illustrates a schematic cross-sectional view of a single spacer column in some embodiments of the present disclosure;

FIG. 6 illustrates a schematic layout of spacers and spacer columns in some embodiments of the present disclosure;

FIG. 7 illustrates a schematic diagram of a film layer stack relationship of a display substrate according to some embodiments of the present disclosure;

FIG. 8 illustrates a schematic diagram of a spacer column arrangement around a target subpixel in some embodiments of the present disclosure;

FIG. 9 illustrates a flowchart of a method of manufacturing a display substrate according to some embodiments of the present disclosure;

FIG. 10 illustrates a process diagram (one) of the fabrication of a first subpixel in some embodiments of the present disclosure;

FIG. 11 illustrates a process diagram (II) for the fabrication of a first subpixel in some embodiments of the present disclosure;

fig. 12 illustrates a substrate structure after forming the second sub-pixel and the third sub-pixel in some embodiments of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

It should be noted that, the term "and/or" appearing herein is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. The term "plurality" includes two or more than two cases. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. "up", "down", "left", "right" and the like are used only to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed accordingly.

As used herein, "about," "approximately," "substantially" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

As used herein, "parallel", "perpendicular", "equal" includes the stated case as well as the case that approximates the stated case, the range of which is within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the acceptable deviation range for approximately parallel may be, for example, a deviation within 5 °; "vertical" includes absolute vertical and near vertical, where the acceptable deviation range for near vertical may also be deviations within 5 °, for example. "equal" includes absolute equal and approximately equal, where the difference between the two, which may be equal, for example, is less than or equal to 5% of either of them within an acceptable deviation of approximately equal.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present between the layer or element and the other layer or substrate.

The display substrate provided by some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

Fig. 1 illustrates a schematic plan view of a display substrate of some embodiments of the present disclosure. As shown in fig. 1, the display substrate 10 includes: display area AA and non-display area SA. The non-display area SA is located on at least one side of the display area AA. For example, the non-display area SA may be located at one side of the display area AA, or may be located at multiple sides of the display area AA, e.g., the non-display area SA may surround the outside of the display area AA. For example, the non-display area SA may include: and a binding area PB located at one side of the display area AA. The bonding region PB includes a plurality of bonding pins for bonding connection with an external flexible circuit board (Flexible Printed Circuit, abbreviated as FPC).

The display area AA may include a plurality of pixels P arranged in an array. As shown in fig. 1, the display area AA is provided with a plurality of pixels P arrayed in the first direction and the second direction. For example, the first direction may be represented by the X-axis in fig. 1, and the second direction may be represented by the Y-axis in fig. 1. For example, the plurality of pixels P may be arranged in M rows and N columns, M, N being an integer greater than or equal to 2, and only a few pixels P are shown in fig. 1 as an example of arrangement, and ellipses represent the remaining pixels not shown. The first direction X is the pixel row direction and the second direction Y is the pixel column direction. The first direction X and the second direction Y intersect, e.g. are perpendicular to each other.

Each pixel P includes a plurality of sub-pixels, each of which may display a single color, e.g., red sub-pixel displaying red, green sub-pixel displaying green, and blue sub-pixel displaying blue. The brightness (gray scale) of the sub-pixels with different colors in each pixel can be adjusted, and the display with multiple colors can be realized through color combination and superposition, so that full-color display is realized.

For example, fig. 2 illustrates an exemplary pixel layout diagram of some embodiments of the present disclosure. As shown in fig. 2, each pixel P may include: two green sub-pixels G, one blue sub-pixel B, and one red sub-pixel R. For example, the blue and red sub-pixels B and R may have a hexagonal shape as shown in fig. 2, and the green sub-pixel G may have a pentagon shape as shown in fig. 2. For another example, fig. 3 illustrates another exemplary pixel layout diagram of some embodiments of the present disclosure. As shown in fig. 3, each pixel P may also include: the red sub-pixels R, the green sub-pixels G and the blue sub-pixels B are arranged in an RGB mode. It should be noted that the pixel arrangement manner and the shape of each sub-pixel shown in fig. 2 and 3 are only schematic, and not limited thereto, and may be specifically determined according to actual needs. For example, the shape of the sub-pixels may be a single pattern or a combination of patterns in a diamond shape, a circle shape, an oval shape, or the like, and may be determined by the wiring form of the isolation column 140.

Each sub-pixel may include a light emitting device 110 and a pixel driving circuit for driving the light emitting device 110. For example, the Light Emitting device 110 may be an Organic Light-Emitting Diode (OLED). Alternatively, the light Emitting device 110 may be a Micro organic light Emitting Diode (Micro Organic Light-Emitting Diode) or a quantum dot organic light Emitting Diode (Quantum Dot Light Emitting Diodes, QLED), or the like. For example, the red subpixel may include a light emitting device 110 for emitting red light, the green subpixel may include a light emitting device 110 for emitting green light, and the blue subpixel may include a light emitting device 110 for emitting red light.

The pixel driving circuit may include a plurality of electronic components such as transistors and capacitors. For example, the pixel driving circuits may each include three transistors and one capacitor, constituting 3T1C (i.e., one driving transistor, two switching transistors, and one capacitor). It is also possible to include more than three transistors and at least one capacitor, such as 4T1C (i.e., one driving transistor, three switching transistors, and one capacitor), 5T1C (i.e., one driving transistor, four switching transistors, and one capacitor), or 7T1C (i.e., one driving transistor, six switching transistors, and one capacitor), etc. The transistor may be a thin film transistor (Thin Film Transistor, TFT for short), a field effect transistor (metal oxide semiconductor, MOS for short), or other switching devices with the same characteristics.

It is understood that the transistor may include a control electrode, a first electrode, and a second electrode. Wherein the control electrode is a gate of a transistor, one of a source and a drain of a first electrode is a source and a drain of a transistor, and the second electrode is the other of the source and the drain of the transistor. Since the source and drain of a transistor may be symmetrical in structure, the source and drain may be indistinguishable in structure, and the source of the transistor may be referred to as a first pole or a second pole.

Fig. 4 illustrates a schematic diagram of a film layer stacking relationship of a display substrate 10 according to some embodiments of the present disclosure. As shown in fig. 4, the display substrate 10 may include: a back sheet 100, and a light emitting device layer and a package layer 150 stacked on the back sheet 100.

The back plate 100 includes a substrate base plate and a driving circuit layer that can be used to form the above-described pixel driving circuit of each sub-pixel. For example, the driving circuit layer may include a plurality of pixel driving circuits arrayed in the first direction X and the second direction Y. For example, the driving circuit layer may be used to form a sensor element such as an ambient light sensor and a driving element thereof integrated under a screen in addition to the pixel driving circuit, and the present embodiment is not limited thereto, particularly according to actual needs. For example, for the display substrate 10 having a fingerprint recognition function, the driving circuit layer may also be used to form a photosensor and a driving transistor for driving the photosensor to operate to realize fingerprint recognition.

For example, the substrate base may be a rigid substrate. The rigid substrate may include, for example, a glass substrate, a PMMA (Polymethyl methacrylate ) substrate, a silicon substrate, or the like. In this case, the display substrate 10 may be a rigid display substrate.

For another example, the substrate base may be a flexible substrate. The flexible substrate may include, for example, a PET (Polyethylene terephthalate ) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate, a PI (Polyimide) substrate, or the like. In this case, the display substrate 10 may be a flexible display substrate.

The substrate may have a single-layer structure or a multi-layer structure. For example, the substrate base may include at least one flexible substrate and at least one buffer layer, the flexible substrate and the buffer layer being alternately stacked.

The light emitting device layer is used to form the light emitting device 110 of each sub-pixel. The light emitting device layer and the driving circuit layer together form a plurality of pixels arranged in an array on the substrate.

The light emitting device layer may include: a pixel defining layer 120 (Pixel Define Layer, PDL), spacers 130, isolation pillars 140, and light emitting devices 110 for each sub-pixel. The pixel defining layer 120 includes a plurality of pixel openings 121, and each pixel opening 121 corresponds to one sub-pixel for defining a location of the light emitting device 110 of the sub-pixel.

The light emitting device 110 may include a first electrode 111 (e.g., anode), an organic light emitting functional layer 112, and a second electrode 113 (e.g., cathode) stacked on a substrate. Each pixel opening 121 exposes at least a partial region of the first electrode 111 of the corresponding sub-pixel. A part of the region of the organic light emitting functional layer 112 is located in the corresponding pixel opening 121, and is electrically connected to the corresponding first electrode 111. The organic light emitting function layer 112 may extend to the top of the pixel defining layer 120, to which the sidewall of the pixel defining layer 120 near the pixel opening 121 extends, until being blocked by the isolation pillars 140.

For example, the organic light emitting functional layer 112 may include a light emitting layer and a functional material layer. For example, the functional material layer may include: one or more of a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) are specifically set according to actual needs, and the present embodiment is not limited thereto.

For example, the first electrode 111 may be an anode and the second electrode 113 may be a cathode. For example, the first electrode 111 may have a structure of a composite structure formed by sequentially stacking a transparent conductive oxide film/a metal film/a transparent conductive oxide film. The material of the transparent conductive oxide film is, for example, any one of ITO (Indium tin oxide) and IZO (Indium zinc oxide Indium zinc oxide), and the material of the metal film is, for example, any one of gold (Au), silver (Ag), nickel (Ni), and platinum (Pt). For another example, the first electrode 111 may have a single-layer structure, and the material of the single-layer structure may be ITO, IZO, au, ag, ni, pt.

For example, the material of the second electrode 113 may be a metal thin film having a certain transmittance, such as any one of aluminum (Al), silver (Ag) and magnesium (Mg), or any one of a magnesium-silver alloy and an aluminum-lithium alloy, so that the light emitting device 110 achieves a strong microcavity effect, thereby achieving a good color gamut and light extraction rate. Of course, the cathode may be made of transparent conductive material, which is not limited in this embodiment

As shown in fig. 4, the spacers 130 are disposed on the pixel defining layer 120 and located in the spaced areas of the pixel openings 121. The spacer 140 is at least partially positioned over the spacers 130, e.g., a portion of the spacer 140 is positioned over the corresponding spacer 140, or may be positioned entirely over the corresponding spacer 130. The barrier ribs 140 are disposed around the respective sub-pixels for blocking the organic light emitting function layer 112 of the adjacent sub-pixels. It is understood that the barrier ribs 140 have an undercut structure, and the organic light emitting function layer 112 is continuously prepared on the pixel defining layer 120 provided with the barrier ribs 140 as described above, for example, when the organic light emitting function layer 112 may be prepared by an evaporation process, the prepared organic light emitting function layer 112 may be blocked at the positions of the barrier ribs 140.

The isolation pillars 140 have a conductive property, and the isolation pillars 140 surrounding the sub-pixels are electrically connected to each other. The second electrode 113 of each sub-pixel is overlapped on the isolation column 140 to be conducted with the isolation column 140, so that the conduction of the second electrode 113 of each sub-pixel can be realized through the isolation column 140.

By additionally arranging the spacer 130 to raise the spacer 140, the distance from the top of the spacer 140 to the pixel defining layer 120 can be lengthened, so that the film forming space of the second electrode 113 is increased, the overlap area of the second electrode 113 and the spacer 140 can be increased, the contact resistance is reduced, the luminous efficiency of the sub-pixel is improved, and the problem of poor display caused by poor overlap of the second electrode 113 and the spacer 140 is solved. For example, fig. 5 illustrates a cross-sectional schematic view of a single spacer column 140 in some embodiments of the present disclosure. Two different structures of the isolation column 140 are shown in fig. 5 (a) and (b), wherein (a) is a three-layer structure and (b) is a two-layer structure, and the isolation column 140 of the three-layer structure is mainly described herein as an example. For the two-layer structure of the spacer 140, the bottom width of the spacer 140 may be smaller than the top width of the spacer 130 as shown in fig. 5 (b), or the bottom width of the spacer 140 may be equal to the top width of the spacer 130 as shown in fig. 5 (c). As shown in fig. 5, by providing the spacers 130, the distance from the lower portion of the isolation column 140 unrercut to the pixel defining layer 120 can be increased from h1 to h2.

The spacers 130 are arranged in a continuous pattern according to the shape of the sub-pixels, and may be straight or meandering lines, and are disposed around the pixel openings 121. The electroluminescent material of the light emitting device 110 included in the sub-pixel may be sequentially evaporated on the spacer 130 and the isolation pillars 140 such that the shape of the sub-pixel is defined by the isolation pillars 140.

For example, the height H of the spacers 130 may be 0.2 μm to 3 μm in a direction perpendicular to the substrate, and may be set according to the material of the spacers 130 that is actually used. For example, the material of the spacer 130 may be an organic material, such as polyimide, epoxy, or acrylate material. At this time, the height H of the spacer 130 may be 1 to 3 μm, such as 1 μm, 2 μm, or 3 μm, in a direction perpendicular to the base substrate. For another example, the material of the spacers 130 may also be an inorganic material, such as may include, but not limited to, silicon nitride (SiN) _x ) Silicon oxynitride (SiON), silicon oxide (SiO) _x ) Alumina (AlO) _x ) One or more combinations of the above). At this time, the height H of the spacer 130 may be 0.2 to 1 μm, such as 0.2 μm, 0.5 μm, or 1 μm, in a direction perpendicular to the base substrate.

The isolation pillars 140 may have a single-layer or multi-layer structure, and the material at least comprises a conductive layer such as a metal layer, and has an undercut structure with a large upper portion and a small lower portion, or a concave middle portion and a convex upper portion and a convex lower portion. Due to the shadow effect of the pattern, the evaporation layer cannot be deposited on the isolation pillars 140 completely continuously, and thus the isolation of the evaporation layer such as the organic light emitting function layer 112 and the patterning of the pixels can be achieved. For example, in the three-layer structure of the spacer 140 shown in fig. 5 (a), the undercut width s may be at least 0.2 μm, such as 0.2 to 0.5 μm, the intermediate layer height h may be at least 0.6 μm, and the specific size may be set according to the partition requirement of the actual product, which is not limited in this embodiment.

Taking the isolation column 140 as an example of a three-layer structure, the isolation column 140 may include a first metal layer, a second metal layer, and a third metal layer sequentially stacked from bottom to top. For example, a titanium/aluminum/titanium metal laminate structure may be employed. Edges of the first metal layer and the third metal layer protrude with respect to the second metal layer. At this time, the second electrode 113 of the sub-pixel may overlap the first metal layer and/or the second metal layer, so as to realize conduction of the second electrode 113 of each sub-pixel.

At least a part of the area of the first metal layer is arranged on the surface of the spacer 130 in a conformal manner. For example, the surface of the spacer 130 in contact with the first metal layer is parallel to the plane of the substrate, and the surface of the first metal layer in contact with the spacer 130 is also parallel to the plane of the substrate. For another example, the surface of the spacer 130 contacting the first metal layer is an arc surface, and correspondingly, the surface of the first metal layer contacting the spacer 130 is also an arc surface. For another example, the surface of the spacer 130 contacting the first metal layer is a plane inclined with respect to the direction perpendicular to the substrate, and the surface of the first metal layer contacting the spacer 130 is a plane having the same inclination direction as the surface.

For example, the planar shapes of the spacers 130 and the barrier ribs 140 disposed around the sub-pixels may be continuous stripe shapes or zigzag shapes, and may be disposed according to the shape of the actual sub-pixels, which is not limited in this embodiment.

In an alternative embodiment, a spacer 130 may be disposed around each subpixel and a spacer 140 may be located at least partially over the spacer. Of course, in other embodiments, two spacers 130 and isolation columns 140 arranged in parallel may be disposed around each sub-pixel, and may be disposed according to the resolution of the actual product and the space between the pixel openings 121, and the number of spacers 130 and isolation columns 140 disposed around each sub-pixel is not limited in this embodiment.

Fig. 6 is a schematic diagram illustrating the arrangement of spacers and spacers in some embodiments of the present disclosure, fig. 7 is a schematic diagram illustrating the relationship of layers of the display substrate 10 in some embodiments of the present disclosure, and fig. 7 may be a cross-sectional view taken along the line A-A in fig. 6. As shown in fig. 6 and 7, in the display substrate 10 provided in some embodiments of the disclosure, at least a portion of the barrier ribs 140 may be disposed obliquely with respect to a direction perpendicular to the substrate, which is more advantageous for the contact of the second electrode 113, such as a cathode, with the barrier ribs 140, increasing a bonding area, and reducing resistance. For the obliquely disposed spacer 140, the orthographic projection of the bottom surface of the spacer 140 on the substrate may at least partially overlap with the orthographic projection of the spacer 130 on the substrate. Wherein the bottom surface is relatively close to the surface of the substrate with respect to the top surface. Taking the above three-layer structure of the isolation pillars 140 as an example, the surface of the first metal layer close to the substrate may be referred to as the bottom surface of the isolation pillars 140, and the surface of the third metal layer far from the substrate may be referred to as the top surface of the isolation pillars 140.

For example, as shown in fig. 7, one end of the bottom surface of the isolation column 140 is overlapped on the spacer 130, and the other end is overlapped on the pixel defining layer 120, so that the isolation column 140 is inclined with respect to the direction perpendicular to the substrate. At this time, the orthographic projection of the bottom surface of the isolation post 140 on the substrate overlaps with the orthographic projection of the spacer 130 on the substrate.

For example, D represents the width of the spacer 130, and D represents the distance between the pixel openings 121 of adjacent sub-pixels. Then D may be less than one third of D. For example, in some application scenarios, d may be between 3 and 10 μm, further, may be between 3 and 7 μm, still further, may be between 3 and 5 μm, such as 3 μm, 4 μm, 5 μm, etc. Of course, the actual size may be determined according to the requirements of the specific application scenario, which is not limited in this embodiment.

For example, the width d of the spacer 130 may be greater than the bottom design width of the spacer 140. For example, the overlap distance t between the spacer 140 and the spacer 130 may be greater than or equal to 3 μm, so that the spacer 140 may achieve a desired inclination and a better stability. Of course, the actual overlap distance may be determined according to the needs of a specific application scenario, which is not limited in this embodiment.

For example, the bottom surface of the isolation column 140 may be entirely located on the spacer 130, and the spacer 130 may raise the isolation column 140 and make the isolation column 140 located on the spacer 130 in an inclined state by a surface topography design. At this time, the orthographic projection of the bottom surface of the isolation post 140 on the substrate may be located within the orthographic projection of the spacer 130 on the substrate.

To facilitate processing of the spacer 140 in an inclined state, the spacer 130 may have a slope surface inclined toward a direction away from the pixel opening 121. The bottom surface of the isolation column 140 is arranged on the slope surface along with the shape, so that the inclination of the isolation column 140 can be realized. The inclination angle of the isolation column 140 is related to the slope angle of the ramp surface. For example, the ramp surface is a cambered surface or a flat surface.

For example, the cross-sectional shape of the spacer 130 may be arcuate as shown in fig. 7. For example, as shown in fig. 7, one end of the bottom surface of the isolation column 140 may overlap the arched top of the spacer 130, and the other end overlaps the pixel defining layer 120, i.e., covers half the width of the spacer 130, when the bottom surface of the isolation column 140 contacting the spacer 130 also presents an arc surface. The specific lap joint mode can be set according to actual needs.

For another example, the cross-sectional shape of the spacer 130 may be a trapezoid including oppositely disposed first and second sides, the first and second sides being substantially parallel to the substrate, the second side being closer to the substrate than the first side. The width of the first edge is smaller than the width of the second edge. That is, the side surface of the trapezoid spacer 130 is inclined toward a direction away from the pixel opening 121 with respect to a direction perpendicular to the substrate, and a distance between the upper end of the side surface and the pixel opening 121 is smaller than a distance between the lower end of the side surface and the pixel opening 121. Note that, when the cross-sectional shape of the spacer 130 is a trapezoid, the cross-sectional shape of the spacer 130 is substantially a trapezoid, and may be, for example, a standard trapezoid or a trapezoid-like shape having a cambered surface on a side surface. For example, one end of the bottom surface of the barrier rib 140 may overlap at a middle position of the first side, and the other end overlaps the pixel defining layer 120, as viewed in section. The specific lap joint mode can be set according to actual needs.

It should be noted that, the inclination direction of the isolation column 140 may have various embodiments, and may be actually set according to the requirements of the application scenario. The following description mainly uses two modes, which are only examples, but not limiting, and in other embodiments, other suitable inclined arrangements may be adopted, and the present embodiment is not limited thereto.

First, the isolation column 140 of at least one side around each sub-pixel is inclined in a direction away from the corresponding pixel opening 121. It can be understood that, for the sub-pixel, on the basis of the raised spacer 130, the inclination of the surrounding isolation pillars 140 toward the direction away from the pixel openings 121 can further increase the film forming space of the second electrode 113, thereby further increasing the overlap area between the second electrode 113 and the middle of the isolation pillars 140, reducing the resistance, and improving the luminous efficiency. Then, if the surrounding barrier ribs 140 are inclined to a direction away from the corresponding pixel opening 121 for each sub-pixel, the luminous efficiency of each sub-pixel can be effectively improved.

For example, each sub-pixel includes a first side and a second side disposed opposite the first side. The inclination direction of the barrier ribs 140 located at the first side and the second side of each sub-pixel is the same. The term "the same tilt direction" as used herein means that the tilt directions are the same, such as the tilt direction toward the positive X-axis direction in fig. 7, or the tilt directions are all the same, or the tilt angles may be different, or the tilt directions may be the same, which is not limited in this embodiment. For example, as shown in fig. 7, for each sub-pixel, the isolation post 140 of the first side may overlap one side of the corresponding spacer 130 near the pixel opening 121 thereof, and the isolation post 140 of the second side may overlap one side of the corresponding spacer 130 far from the pixel opening 121 thereof, such that the inclination directions of the isolation posts 140 of the first and second sides are the same.

Taking the red, green and blue sub-pixels that are sequentially adjacent as an example, the isolation columns 140 of the first and second sides of the red, green and blue sub-pixels may be inclined toward the right side (i.e., the positive X-axis direction) in fig. 7. Note that the tilt directions shown in fig. 7 are only schematic, and of course, the tilt directions may be all inclined to the left in fig. 7 (i.e., the negative X-axis direction), which is not limited in this embodiment. For example, if the first side is the left side in fig. 7 and the second side is the right side in fig. 7, the second side of the red sub-pixel and the first side of the green sub-pixel share one isolation column 140, and the second side of the green sub-pixel and the first side of the blue sub-pixel share one isolation column 140.

Second, it is possible to select a sub-pixel having a low luminous efficiency from among the sub-pixels on the display substrate 10 as a target sub-pixel at the time of design, and to purposefully tilt the isolation column 140 surrounding the target sub-pixel in a direction away from the pixel opening 121 thereof, so as to increase the film formation space of the second electrode 113 thereof as much as possible, thereby purposefully increasing the luminous efficiency of the target sub-pixel. For example, the target subpixel may be a blue subpixel, or may be another subpixel that needs to improve the light emitting efficiency, which is not limited in this embodiment.

Thus, in some embodiments of the present disclosure, for a target subpixel of the plurality of subpixels, the isolation column 140 surrounding the target subpixel may be inclined with respect to a direction perpendicular to the substrate toward a direction away from the pixel opening 121 of the target subpixel. For example, at least one set of the isolation pillars 140 located at opposite sides around the target subpixel are inclined in a direction away from the pixel opening 121, or one turn of the isolation pillars 140 around the target subpixel are inclined in a direction away from the pixel opening 121, so that the contact area between one turn of the isolation pillars 140 around the second electrode 113 in the target subpixel is increased.

For example, the isolation pillars 140 located at opposite sides of the target subpixel may overlap one side of the corresponding spacer 130 away from the pixel opening 121 thereof, respectively, such that the isolation pillars 140 at opposite sides are inclined toward a direction away from the pixel opening 121 of the target subpixel, so as to obtain a larger film formation space of the second electrode 113.

Fig. 8 illustrates a schematic diagram of a spacer column 140 arrangement around a target subpixel in some embodiments of the present disclosure. In fig. 8, pixel openings 121, 121a, 121b, and 121c of three adjacent sub-pixels are shown, and spacers 130 and spacers 140 overlapping the spacers 130, i.e., spacers 140a,140b,140c, and 140d, are disposed around the pixel openings 121. For example, if the sub-pixel located in the middle of fig. 8 is the target sub-pixel, the isolation columns 140b and 140c on both sides of the target sub-pixel are inclined toward the direction away from the pixel opening 121b with respect to the direction perpendicular to the substrate, and at this time, the isolation columns 140b and 140c are located on different sides of the corresponding arched spacers 130 (e.g., 140b overlaps the left side of the lower spacer 130 in fig. 8, and the isolation column 140c overlaps the right side of the lower spacer 130 in fig. 8), which is advantageous for increasing the overlapping area of the second electrode 113 of the target sub-pixel and the middle of the isolation columns 140 on both sides. And the isolation column 140a may be inclined toward the direction approaching the pixel opening 121a with respect to the direction perpendicular to the substrate, and the isolation column 140d may be inclined toward the direction approaching the pixel opening 121c with respect to the direction perpendicular to the substrate, as shown in fig. 8. Of course, the inclination directions of the isolation posts 140a and 140d may be different from those shown in fig. 8, and this embodiment is not limited thereto, depending on the actual pixel arrangement and the overlapping needs of the second electrodes 113 of the respective sub-pixels.

As shown in fig. 4 and 7, in some embodiments of the present disclosure, the display substrate 10 further includes an encapsulation layer 150 to protect the light emitting device 110 from water oxygen. For example, the encapsulation layer 150 may include a first encapsulation layer 151, a second encapsulation layer 152, and a third encapsulation layer 153, which are sequentially stacked. The first and third encapsulation layers 151 and 153 may be inorganic encapsulation layers, for example, inorganic materials such as nitrides, oxides, oxynitrides, nitrates, carbides, or any combination thereof may be used, and the preparation process may be a chemical vapor deposition (Chemical Vapor Deposition, CVD) process. The second encapsulation layer 152 may be an organic encapsulation layer, for example, an organic material such as acrylic, hexamethyldisiloxane, polyacrylate, polycarbonate, polystyrene, etc., and the preparation process may be an Ink Jet Printing (IJP) process.

Of course, in other embodiments, the display substrate 10 may further include other film structures, such as, but not limited to, a touch layer (not shown in the drawings) for providing a touch function, a color film layer (or polarizer) (not shown in the drawings) for providing a color filter function, and a cover plate layer (not shown in the drawings) for protecting the display substrate 10, which is not limited in this embodiment.

Fig. 9 illustrates a flowchart of a method of manufacturing the display substrate 10 according to some embodiments of the present disclosure. Some embodiments of the present disclosure further provide a method for manufacturing the display substrate 10, which is used for manufacturing the display substrate 10 provided in the foregoing embodiments. As shown in fig. 9, the method may include at least the steps of:

step S101, providing a backboard, wherein the backboard comprises a substrate base plate;

step S102, forming a first electrode of each sub-pixel on a backboard, and forming a pixel defining layer on the first electrode, wherein the pixel defining layer comprises a plurality of pixel openings, and each pixel opening exposes at least part of the area of the first electrode of one sub-pixel;

step S103, forming a spacer on the pixel defining layer, forming isolation columns on the spacer, wherein the isolation columns are arranged around each sub-pixel, at least part of the isolation columns are positioned on the spacer, the isolation columns have conductive characteristics, and the isolation columns around each sub-pixel are mutually communicated;

step S104, forming organic light-emitting functional layers of all sub-pixels, wherein the organic light-emitting functional layers of adjacent sub-pixels are separated by a separation column;

step S105, forming a second electrode covering the organic light-emitting function layer, wherein the second electrode of each sub-pixel is lapped on the isolation column and is conducted with the isolation column.

It should be noted that, the structures and the specific embodiments of the film layer mentioned in the above preparation process may be referred to the related descriptions in the above examples, which are not repeated here. In addition to the above-mentioned structures and film layers, the display substrate 10 may further include other film layer structures such as a packaging layer 150 and a touch control layer, which are not described in detail herein.

In the above preparation process, each subpixel may be prepared by a photolithography process. For ease of understanding, the following will mainly describe the preparation process by taking the preparation of the display substrate 10 shown in fig. 7 as an example.

FIG. 10 illustrates a process diagram (one) of the fabrication of a first subpixel in some embodiments of the present disclosure; FIG. 11 illustrates a process diagram (II) for the fabrication of a first subpixel in some embodiments of the present disclosure; fig. 12 is a diagram of a substrate structure after forming a second sub-pixel and a third sub-pixel in some embodiments of the present disclosure.

As shown in fig. 10, after the isolation column 140 is prepared, the relevant film layer of the first sub-pixel is evaporated and packaged. In fig. 10, open circles and broken lines indicate the vapor deposition gas outlet and the vapor deposition direction, respectively. For example, the deposition layer may include the organic light emitting functional layer 112a of the first subpixel, the second electrode 113, and the protective layer. For example, the organic light emitting functional layer 112 may include a hole transporting layer, a hole injecting layer, a light emitting layer, an electron injecting layer, and an electron transporting layer. The protective Layer may reduce light loss occurring when light emitted from the organic light emitting Layer in the light emitting device 110 is repeatedly reflected between the cathode and the anode, and may increase the light emitting rate of the light emitting device 110, for example, may also be referred to as a Capping Layer (CPL).

It is understood that the light emitting layers are arranged according to pixels of different colors, and thus, the relevant film layers of the sub-pixels of various colors, such as the relevant film layer of the red sub-pixel, the relevant film layer of the green sub-pixel and the relevant film layer of the blue sub-pixel, can be respectively evaporated.

As shown in fig. 11 and 12, the evaporation layer is cut off at the undercut position of the isolation column 140, the second electrode 113 is accumulated along with the thickness of the functional layer, the undercut structure is slowed down, the second electrode 113 can be in contact with the metal layer of the isolation column 140, and a larger contact area is realized by means of the angle of the inclined isolation column 140, so that the resistance is reduced, the conduction of the second electrode 113 of each sub-pixel is realized through the isolation pad 130 and the isolation column 140, and the luminous efficiency is improved.

Regarding the encapsulation of the sub-pixels, the single-layer temporary encapsulation can be performed according to the manufacturing process of the photoetching OLED, and the complete encapsulation is performed after the preparation of all the sub-pixels is completed. The temporary encapsulation layer may be used as the first encapsulation layer 151, for example, siN _x ，SiON，SiO _x Or AlO _x And the like.

For example, each pixel in the display substrate 10 includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In actual processing, the first sub-pixel p1, such as the red sub-pixel, may be first prepared, including the vapor deposition layer and the temporary packaging layer 151a of the first sub-pixel p1, and then the first sub-pixel is patterned by a photolithography process, and the vapor deposition layer and the temporary packaging layer at the positions of the second sub-pixel p2 and the third sub-pixel p3 are removed, so as to obtain the structure of the display substrate 10 shown in fig. 11. Then, the above steps are repeated, and the second sub-pixel p2, such as a green sub-pixel, and the third sub-pixel p3, such as a blue sub-pixel, are respectively prepared. After the preparation of the sub-pixels of the three colors, the structure of the display substrate 10 shown in fig. 12 is obtained. At this time, as shown in fig. 12, an inorganic encapsulation layer formed by splicing the temporary encapsulation layers of the sub-pixels is formed on the display substrate 10, and the inorganic encapsulation layer may be used as the first encapsulation layer 151, and then the second encapsulation layer 152 and the third encapsulation layer 153 are prepared, so as to obtain the display substrate 10 shown in fig. 7. For example, the second encapsulation layer 152 is an organic layer, and the third encapsulation layer 153 is an inorganic layer. The third encapsulation layer 153 may be made of the same material as the first encapsulation layer 151 or a different material. The third encapsulation layer 153 may entirely cover the second encapsulation layer 152, and the bezel is outside the boundary line of the second encapsulation layer 152.

In addition, some embodiments of the present disclosure further provide a display device including the display substrate 10 provided in any one of the above embodiments. For example, the display device may be any product or component with display function, such as a mobile phone, a notebook computer, a tablet computer, a display, a television, a digital photo frame, etc.

It should be noted that, the drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design. The above-described embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments without conflict. In the above description, technical details such as patterning of the respective layers of the product are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques.

While some embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

Claims

1. A display substrate, comprising:

a substrate base;

a plurality of pixels arranged in an array on the substrate, each pixel including a plurality of sub-pixels, each sub-pixel including a first electrode, an organic light emitting functional layer, and a second electrode stacked on the substrate;

a pixel defining layer on the substrate, the pixel defining layer including a plurality of pixel openings, each pixel opening corresponding to one of the sub-pixels, each pixel opening exposing at least a portion of a region of a first electrode of a corresponding sub-pixel;

the spacer is arranged on the pixel defining layer and is positioned in the interval area of the pixel openings;

the isolation columns are at least partially arranged on the isolation pad, are arranged around the sub-pixels and are used for isolating the organic light-emitting functional layers of the adjacent sub-pixels, the isolation columns have conductive characteristics, the isolation columns around the sub-pixels are mutually conducted, and the second electrode of each sub-pixel is lapped on the isolation column and is conducted with the isolation column.

2. The display substrate according to claim 1, wherein at least part of the spacer columns are disposed obliquely with respect to a direction perpendicular to the substrate.

3. A display substrate according to claim 2, wherein the spacers on at least one side around each sub-pixel are inclined away from the corresponding pixel opening.

4. A display substrate according to claim 3, wherein each of the sub-pixels comprises a first side and a second side disposed opposite to the first side, and the tilt directions of the spacers on the first side and the second side of each of the sub-pixels are the same.

5. The display substrate according to claim 2, wherein for a target sub-pixel of the plurality of sub-pixels, a surrounding isolation column around the target sub-pixel is inclined with respect to a direction perpendicular to the substrate toward a direction away from a pixel opening of the target sub-pixel.

6. The display substrate of claim 2, wherein for the obliquely disposed spacer columns, an orthographic projection of a bottom surface of the spacer column onto the substrate at least partially overlaps an orthographic projection of the spacer onto the substrate, wherein the bottom surface is a surface relatively close to the substrate.

7. The display substrate according to claim 2, wherein for the obliquely arranged spacer, one end of a bottom surface of the spacer is overlapped on the spacer, the other end is overlapped on the pixel defining layer, and the bottom surface is a surface relatively close to the substrate.

8. The display substrate according to claim 7, wherein a lap joint distance between the spacer and the spacer is 3 μm or more.

9. The display substrate according to claim 1 or 2, wherein the spacer has a width less than one third of a distance between pixel openings of adjacent sub-pixels; and the height of the spacer is 0.2-3 mu m along the direction vertical to the substrate.

10. A display substrate according to claim 1 or 2, wherein the spacer has a sloping surface which slopes towards a direction away from the pixel opening, the sloping surface being a cambered surface or a planar surface.

11. The display substrate of claim 10, wherein the spacer has an arcuate cross-sectional shape or a trapezoidal cross-sectional shape, the trapezoid including oppositely disposed first and second sides, the first side having a width less than a width of the second side, the second side being closer to the substrate than the first side.

12. The display substrate according to claim 1 or 2, wherein the spacer includes a first metal layer, a second metal layer, and a third metal layer stacked together, edges of the first metal layer and the third metal layer protrude with respect to the second metal layer, and at least a partial region of the first metal layer is conformally disposed on a surface of the spacer.

13. The preparation method of the display substrate is characterized in that the display substrate comprises a plurality of pixels which are arranged in an array, each pixel comprises a plurality of sub-pixels, each sub-pixel comprises a first electrode, an organic light-emitting functional layer and a second electrode which are stacked, and the method comprises the following steps:

providing a back plate, wherein the back plate comprises a substrate base plate;

forming a first electrode of each sub-pixel on the back plate, and forming a pixel defining layer on the first electrode, the pixel defining layer including a plurality of pixel openings, each pixel opening exposing at least a portion of a region of the first electrode of one sub-pixel;

forming a spacer on the pixel defining layer, and forming isolation columns on the spacer, wherein the isolation columns are arranged around each sub-pixel, at least part of the isolation columns are positioned on the spacer, the isolation columns have conductive characteristics, and the isolation columns around each sub-pixel are mutually communicated;

forming organic light-emitting functional layers of all sub-pixels, wherein the organic light-emitting functional layers of adjacent sub-pixels are separated by the isolation columns;

and forming a second electrode covering the organic light-emitting functional layer, wherein the second electrode of each sub-pixel is lapped on the isolation column and is communicated with the isolation column.

14. A display device, comprising: the display substrate of any one of claims 1-12.