CN117200798A - Analog-to-digital converter - Google Patents
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Abstract
The application relates to an analog-to-digital converter comprising a modulator for processing an analog signal to output a bit stream; the filter bank comprises a plurality of downsampling filters, and each downsampling filter is connected with the modulator respectively; the first control system is respectively connected with the downsampling filters and used for controlling the downsampling filters to be started in sequence, so that the downsampling filters are used for processing the bit stream after being started and outputting different processing results. The analog signal is described more finely using the analog-to-digital converter described above.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuits, in particular to an analog-to-digital converter.
Background
The development of analog-to-digital converters (Analog To Digital Converter, ADC) whose output results can be regarded as a description of the analog signal has greatly advanced by the rapid development of computer technology, communication technology, and microelectronics.
Currently, an oversampling analog-to-digital converter is a common analog-to-digital converter, and a Sigma-Delta ADC (Sigma-Delta analog-to-digital converter) is widely used. The sigma-delta ADC may include an anti-aliasing filter, a sigma-delta modulator, and a downsampling filter. Specifically, the analog signal is firstly attenuated by the anti-aliasing filter to obtain noise and components outside the frequency band, then the sigma-delta modulator performs over-sampling and noise shaping on the analog signal output by the anti-aliasing filter to convert the analog signal into a high-speed low-resolution bit stream (i.e. a 1bit data stream), and finally the bit stream is filtered by the down-sampling filter to remove high-frequency noise outside the frequency band and down-sampling and extraction processing to convert the bit stream into a low-speed high-resolution digital signal and output the digital signal. It will be appreciated that the output of the downsampling filter is descriptive of the analog signal. However, the conventional analog-to-digital converter has a problem in that the description of the analog signal is not fine enough, and there is a limitation.
Disclosure of Invention
In view of the foregoing, it is desirable to provide an analog-to-digital converter that is capable of finer description of analog signals.
An analog-to-digital converter, comprising:
a modulator for processing the analog signal to output a bit stream;
the filter bank comprises a plurality of downsampling filters, and each downsampling filter is connected with the modulator respectively;
the first control system is respectively connected with the downsampling filters and used for controlling the downsampling filters to be started in sequence, so that the downsampling filters are used for processing the bit stream after being started and outputting different processing results.
The analog-to-digital converter outputs a processing result after receiving or processing a section of bit stream through the down-sampling filter, and the down-sampling filters are started at different times because the bit stream is a continuous signal, so that the processing results obtained by the down-sampling filters are different; for the analog signals, more processing results output by the filter bank can be used for describing the analog signals, the waveforms of the analog signals can be finely restored, and the conversion rate is equivalently improved in a parallel-like manner.
Drawings
FIG. 1 is a schematic diagram of a conventional sigma-delta ADC in one embodiment;
FIG. 2 is a schematic diagram of a conventional sigma-delta ADC depicting an analog signal in one embodiment;
FIG. 3 is a schematic diagram of an analog-to-digital converter according to an embodiment;
FIG. 4 is a schematic diagram of data output of two downsampling filters in one embodiment;
FIG. 5 is a schematic diagram depicting an analog signal in one embodiment;
FIG. 6 is a schematic diagram of a conventional sigma-delta ADC depicting an analog signal in another embodiment;
FIG. 7 is a schematic diagram depicting an analog signal in another embodiment;
FIG. 8 is a schematic diagram of an analog-to-digital converter according to another embodiment;
FIG. 9 is a schematic diagram of a down-sampling filter outputting processing results in cycles in one embodiment;
FIG. 10 is a schematic diagram of a down-sampling filter according to another embodiment, wherein the down-sampling filter outputs processing results periodically;
FIG. 11 is a schematic diagram of a single output processing result of a downsampling filter in one embodiment;
FIG. 12 is a diagram showing a processing result of a first timer for turning on or off a masking function according to an embodiment;
FIG. 13 is a schematic diagram of the processing results of the first divider in the single-pass mode and the downsampling filter in the cyclic mode in one embodiment;
FIG. 14 is a schematic diagram of the processing results of the first dispenser in a cyclic mode in one embodiment;
FIG. 15 is a schematic diagram of an analog-to-digital converter according to another embodiment;
FIG. 16 is a signal transmission schematic of a second control system including a second timer according to one embodiment;
FIG. 17 is a signal transmission diagram showing the second timer in the single-shot mode and the first timer in the cyclic mode according to one embodiment;
FIG. 18 is a schematic diagram of signal transmission with a second timer in a cyclic mode in one embodiment;
FIG. 19 is a signal transmission schematic diagram of a second control system including a second dispenser in one embodiment;
FIG. 20 is a schematic diagram of a modulator and downsampling filter in one embodiment;
FIG. 21 is a schematic diagram of a modulator and downsampling filter in another embodiment;
fig. 22 is a schematic diagram of a modulator and a downsampling filter in yet another embodiment.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without any inventive effort, are intended to be within the scope of the application.
It should be noted that, in the embodiments of the present application, all directional indicators (such as up, down, left, right, front, and rear … …) are merely used to explain the relative positional relationship, movement conditions, and the like between the components in a specific posture (as shown in the drawings), if the specific posture is changed, the directional indicators correspondingly change, and the connection may be a direct connection or an indirect connection.
Furthermore, descriptions such as those referred to as "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying an order of magnitude of the indicated technical features in the present disclosure. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present application.
The terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first control system may be referred to as a second control system, and similarly, a second control system may be referred to as a first control system, without departing from the scope of the application. Both the first control system and the second control system are control systems, but they are not the same control system. The term "plurality" in the various embodiments of the present application is interpreted as at least two.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
In one embodiment, FIG. 1 is a schematic diagram of a conventional sigma-delta ADC in one embodiment. Conventional sigma-delta ADCs include an anti-aliasing filter, a sigma-delta modulator, and a downsampling filter. Fig. 2 is a schematic diagram depicting an analog signal for a conventional sigma-delta ADC in one embodiment. Each processing of the downsampling filter requires a certain time (denoted as Δt), so it is assumed that the downsampling filter outputs five processing results in this example, that is, the analog signal is described using only these five processing results, which is not fine enough, and there is a limitation. Therefore, an analog-to-digital converter in an embodiment of the present application is presented.
In one embodiment, as shown in fig. 3, a schematic diagram of an analog-to-digital converter in one embodiment is shown, which includes a modulator 110, a filter bank 120, and a first control system 130. The filter bank 120 includes a plurality of downsampling filters 1201. A modulator 110 for processing the analog signal to output a bit stream; a filter bank 120, wherein the filter bank 120 includes a plurality of downsampling filters 1201, and each downsampling filter 1201 is connected to the modulator 110; the downsampling filter 1201 is used to receive the bit stream; the first control system 130 is connected to each of the downsampling filters 1201, and is used for controlling the downsampling filters 1201 to start successively, so that each downsampling filter 1201 is used for processing the bit stream after starting, and different processing results are output.
Wherein the modulator 110 is for processing an analog signal to output a bit stream. The analog signal processed by modulator 110 may be the original signal (i.e., an unprocessed analog signal) or the analog signal processed by the anti-aliasing filter, which is not limited by the embodiment of the present application. A bit stream is a stream of data consisting of digital signals. The bit stream corresponds to the analog signal. Since the modulator 110 is connected to each of the downsampling filters 1201, respectively, the bit stream is simultaneously output to all of the downsampling filters 1201. It will be appreciated that the modulator 110 will continuously process the analog signal, i.e. will continuously output a bit stream to each downsampling filter 1201.
The filter bank 120 includes a plurality of downsampling filters 1201, for example, at least two downsampling filters 1201, and each downsampling filter 1201 is connected to the modulator 110. The downsampling filter 1201 is specifically a downsampling filter 1201. The downsampling filter 1201 refers to a filter that reduces the sampling rate. For example, FIR (Finite Impulse Response) filters, including, but not limited to CIC (Cascaded integrator-comb filter) filters, for example.
Each downsampling filter 1201 is operable to receive a bit stream, and to start up after receiving a signal from the control system, process the bit stream, and output a processing result. Wherein the received bit stream may be discarded when the downsampling filter 1201 is not activated. Alternatively, each downsampling filter 1201 is configured to start receiving the bit stream after receiving the signal of the control system, process the bit stream, and output the processing result. For example, the downsampling filter 1201 is configured to output a processing result for each processing of a bit stream after start-up.
Alternatively, each of the downsampling filters 1201 may be connected to the same processor, and the processing result output by each downsampling filter 1201 may be transmitted to the processor, where the processor sequentially stores the processing results in time sequence. Thus, more features can be obtained simultaneously during one bit stream transmission to represent the analog signal.
The first control system 130 is connected to each of the downsampling filters 1201 in the filter bank 120, and is configured to control the downsampling filters 1201 to start the data processing function in sequence, so that each downsampling filter 1201 processes the bit stream at a respective rate. Preferably, the respective rates comprise the same rate. Because the bit stream is a continuous digital signal, the downsampling filter 1201 is started at different time points by controlling the starting sequence of the downsampling filter 1201, so that the purpose of controlling the phase relation of data output is achieved; the conversion rate of each down-sampling filter 1201 is the same, so that the conversion time periods of each down-sampling filter 1201 are staggered, and the conversion rate is equivalently improved.
For example, as shown in fig. 4, a schematic diagram of the data output of two downsampling filters 1201 in one embodiment is shown. One downsampling filter 1201 (denoted as filter 1) and the other downsampling filter 1201 (denoted as filter 2) are activated sequentially, so that the bit streams processed by the filters 1 and 2 are different in concrete content, and thus the processing results output by the filters 1 and 2 are different.
In this embodiment, the downsampling filter receives or processes a section of bit stream and outputs a processing result, and since the bit stream is a continuous signal, the downsampling filters are started at different times, so that the processing results obtained by the downsampling filters are different; for the analog signals, more processing results output by the filter bank can be used for describing the analog signals, the waveforms of the analog signals can be finely restored, and the conversion rate is equivalently improved in a parallel-like manner.
It is assumed that in a practical scenario, the analog-to-digital converter processes a section of analog signal, and the downsampling filter 1201 in the analog-to-digital converter outputs the processing result periodically. The specific downsampling filter 1201 may output the processing results in cycles. In the conventional manner, as shown in fig. 2, the downsampling filter 1201 may output five processing results, that is, the analog signal is described using only the five processing results, which is not fine enough. However, in the embodiment of the present application, it is assumed that the number of the downsampling filters 1201 is three, and the downsampling filters 1201 have been controlled by the first control system 130 to periodically output the processing results. The processing time of the downsampling filter 1201 is also denoted as Δt. As shown in fig. 5, fig. 5 is a schematic diagram depicting an analog signal in one embodiment. Assuming that under the control of the control system 130, the first downsampling filter 1201 (denoted as downsampling filter 1) is activated 20 μs earlier than the second downsampling filter 1201 (denoted as downsampling filter 2), and the downsampling filter 2 is activated 20 μs earlier than the third downsampling filter 1201 (denoted as downsampling filter 3), then as shown in fig. 5, the three downsampling filters 1201 activated in succession output a total of fifteen different processing results, i.e. the same section of analog signal is described using the fifteen processing results, and thus is finer.
In this embodiment, it is assumed that an analog-to-digital converter is required to process a section of analog signal in a practical scenario, and the downsampling filter 1201 in the analog-to-digital converter is required to output a single processing result. In a conventional manner, as shown in fig. 6, fig. 6 is a schematic diagram of a conventional sigma-delta ADC describing an analog signal in another embodiment. The downsampling filter 1201 may output a single processing result describing the analog signal, which is not fine enough. However, in the embodiment of the present application, it is assumed that the number of the downsampling filters 1201 is three, and the downsampling filters 1201 have been controlled by the control system 130 to output a single processing result, and the processing time of the downsampling filters 1201 is also denoted as Δt. Fig. 7 is a schematic diagram illustrating an analog signal in another embodiment. Assuming that under the control of the first control system 130, the first downsampling filter 1201 (denoted as downsampling filter 1) is activated 10 μs earlier than the second downsampling filter 1201 (denoted as downsampling filter 2), and the downsampling filter 2 is activated 10 μs earlier than the third downsampling filter 1201 (denoted as downsampling filter 3), as shown in fig. 7, three downsampling filters 1201 activated in sequence output three different processing results in total, and the same section of analog signal is described using these three processing results, and thus is finer.
In one embodiment, the first control system 130 includes a first timer 1301; the first timer 1301 is configured to start timing after receiving the first trigger signal, and when the timing reaches a delay start value, control the downsampling filter 1201 corresponding to the delay start value to start; wherein, the delay start values corresponding to the down-sampling filters 1201 are different.
Wherein the first trigger signal is used to start the first timer 1301. The first timer 1301 is used to realize control of each downsampling filter 1201. The delay start value is a value corresponding to the time when the first timer 1301 starts counting. Each delay starting value and the corresponding downsampling filter are preset correspondingly. When the timing reaches the delay start value, the first timer 1301 sends a timing trigger signal, where the timing trigger signal is used to control the down-sampling filter 1201 corresponding to the delay start value to start. For example, when the delay start value is 100 μs, the timing when the first timer 1301 starts to count is regarded as 0, and when the count reaches 100 μs, the delay start value is reached. The first trigger signal is used to trigger the timing function of the first timer 1301.
Fig. 8 is a schematic diagram of an analog-to-digital converter according to another embodiment. The modulator 110, the filter bank 120 and the first control system 130 are included in fig. 8. The filter bank 120 includes a plurality of downsampling filters 1201. The first control system 130 may include a first timer 1301 and a first dispenser 1302 therein. Since the delay start value of the first timer 1301 is configured in advance, the start sequence of the plurality of downsampling filters can be controlled by one first trigger signal, which is easy to trigger. And under the condition that the time for customizing the output processing result is required or the starting sequence is not regular, the distributor can be triggered by the second trigger signal with the starting time configured, so that the distributor sequentially starts each downsampling filter according to the second trigger signal, and the use scene of the analog-to-digital converter is more flexible. The trigger source of the corresponding filter bank can be selected by setting a register. The filter bank trigger sources may be independently selected, need not be uniform, and preferably the filter bank is reinitialized when switching trigger sources. In addition, the first control system 130 may be connected to an external control system, for example, an MCU, an upper computer, etc., and the external control system sends a trigger signal to the control system 130. I.e. the first trigger signal is sent by the external control system to the first timer 1301.
Each downsampling filter 1201 is configured with a corresponding delay initiation value. When the first timer 1301 is triggered, the first timer 1301 starts counting from zero. In the timing process, when the timing reaches the downsampling filter 1201 with the minimum delay starting value, the downsampling filter 1201 is started; when the timing reaches the downsampling filter 1201 with the second smallest delay starting value, the downsampling filter 1201 is started; similarly, when the timing reaches the downsampling filter 1201 whose delay activation value is the largest, the downsampling filter 1201 is activated. In this way, the sequential activation of the plurality of downsampling filters 1201 may be controlled. For example, assuming that there are three downsampling filters 1201, and the processing duration of the downsampling filters 1201 is 1ms, delay start values of 100 μs, 400 μs, 700 μs may be set for the three downsampling filters 1201, respectively. Thus, when the first timer 1301 receives the first trigger signal to start timing from zero, in the timing process, when the timing reaches 100 μs, the downsampling filter 1201 corresponding to 100 μs is started, when the timing reaches 400 μs, the downsampling filter 1201 corresponding to 400 μs is started, until the timing reaches 700 μs, the downsampling filter 1201 corresponding to 700 μs is started, so that the control of the sequential starting of the three downsampling filters 1201 is completed, and the three downsampling filters 1201 output different processing results. It should be noted that the delay start value of each downsampling filter 1201 may be set reasonably, so long as the purpose of outputting different processing results can be achieved.
In this embodiment, the first timer is configured to start timing after receiving the first trigger signal, and when the timing reaches a delay start value, control the down-sampling filters corresponding to the delay start value to start, and control the plurality of down-sampling filters through one signal, that is, control the start time difference of each down-sampling filter, thereby controlling the output phase relationship, and being convenient to implement and low in cost.
In one embodiment, the first timer 1301 can be configured in a single mode or a loop mode; the first timer 1301 in the loop mode is used to restart the timing when the timing reaches a first preset threshold; the first timer 1301 in the single mode is used for stopping timing when the timing reaches a second preset threshold;
the downsampling filter 1201 can be configured in a single-pass mode or a cyclic mode; the downsampling filter 1201 in the single mode is used to output a single processing result; the downsampling filter 1201 in the cyclic mode is used for continuously processing the bit stream after being started and outputting a processing result according to the cycle;
the downsampling filter 1201 is configured to output a single processing result after start or output the processing result in cycles based on the mode of the first timer 1301 and the mode of the downsampling filter 1201. And outputting a single processing result, namely processing a section of bit stream, and outputting the processing result of the section of bit stream. The periodic output of the processing result may specifically be periodic output of the processing result.
Specifically, a register may be set to indicate the mode of the first timer 1301. For example, a register is connected to the first timer 1301, and when the value of the register is 1, the first timer 1301 is in the loop mode, and when the value of the register is 0, the first timer 1301 is in the single-pass mode. The first preset threshold value and the second preset threshold value may be the same or different. Likewise, a register may be set to indicate the mode of the downsampling filter 1201. For example, when the value of the register is 1, the downsampling filter 1201 is in the loop mode; when the value of the register is 0, the downsampling filter 1201 is in the single-pass mode. Alternatively, the downsampling filter 1201 outputs a single processing result after start-up or outputs a processing result in cycles by configuring the self-contained mode of the downsampling filter 1201. Then, the downsampling filter 1201 is configured to output a single processing result after the start based on the mode of the first timer 1301 and the mode of the downsampling filter 1201; or outputs the processing result in cycles after the start based on the mode of the first timer 1301 and the mode of the downsampling filter 1201.
In this embodiment, by configuring the mode of the first timer and the mode of the downsampling filter, the downsampling filter is used to output a single processing result after starting or output a processing result according to a period, and when describing an analog signal, the output mode of the processing result can be selected according to requirements, so that description of a certain section of analog signal or all analog signals is obtained, and adjustment is more flexible.
In one embodiment, the downsampling filter 1201 is configured to output the processing result in cycles when at least one of the first timer 1301 and the downsampling filter 1201 is in a cyclic mode.
Wherein, by configuring the first timer 1301 to be in a cyclic mode, the downsampling filter 1201 is in a single-pass mode, so that the downsampling filter 1201 is configured to output a processing result in cycles. Alternatively, by configuring the first timer 1301 in the single-pass mode, the downsampling filter 1201 is in the loop mode, so that the downsampling filter 1201 is configured to output the processing result on a periodic basis. Alternatively, by configuring the first timer 1301 in the cyclic mode, the downsampling filter 1201 is in the cyclic mode, so that the downsampling filter 1201 is configured to output the processing result on a periodic basis.
Specifically, the description will be given with the configuration of the first timer 1301 as a loop mode and the downsampling filter 1201 as a single-pass mode. When the first timer 1301 starts to count, the downsampling filter 1201 is started when the count reaches the delay start value corresponding to the downsampling filter 1201, and at this time, since the downsampling filter 1201 is in the single-pass mode, the processing result is output only once. The timer reaches a preset threshold, and the first timer 1301 is in a loop mode, and thus starts again. After restarting the timing, when the timing reaches the delay start value corresponding to the downsampling filter 1201 again, the downsampling filter 1201 is started again, and the downsampling filter 1201 outputs a processing result again. The timing then reaches the preset threshold again, the timing is restarted, and the subsequent process and so on. It can be appreciated that, in the foregoing configuration, the downsampling filter 1201 may output the processing result periodically with the processing duration as a period after being started.
In this embodiment, as shown in fig. 9, a schematic diagram of the downsampling filter 1201 outputting the processing result periodically in one embodiment is shown. The downsampling filter 1201 is described as a single-pass mode with the first timer 1301 as a loop mode. Three downsampling filters 1201 are provided, the delay start value of the first downsampling filter 1201 (denoted as downsampling filter 1) is set to t 1 The delayed start value of the second downsampling filter 1201 (denoted as downsampling filter 2) is set to t 2 The delayed start value of the third downsampling filter 1201 (denoted as downsampling filter 3) is set to t 3 Wherein t is 3 ＞t 2 ＞t 1 Also, the downsampling filter 1201 has been configured in a single mode by the first control system 130, and the processing time of the downsampling filter 1201 is noted as Δt. Assume that the preset threshold of the first timer 1301 is T, where T > T 3 The first timer 1301 has been configured by the system to loop mode +Δt. As shown in fig. 9, when the first timer 1301 receives the first trigger signal (this time is denoted as 0), the timer starts. In the timing process, when the timing reaches t 1 (i.e. t 1 Time), starting the down-sampling filter 1, and outputting a processing result after the down-sampling filter 1 processes the bit stream; then when the timing reaches t 2 (i.e. t 2 Time), starting the down-sampling filter 2, and outputting a processing result after the down-sampling filter 2 processes the bit stream; then when the timing reaches t 3 (i.e. t 3 Time instant), the downsampling filter 3 is started, and the downsampling filter 3 outputs a processing result after processing the bit stream. Then, when the count reaches the preset threshold T, the first timer 1301 starts to count again, and it can be understood that the count again reaches T after count again 1 、t 2 、t 3 Three delayed start values (i.e. t in the figure 1 Time T of +T 2 Time T of +T 3 Time +T), the downsampling filter 1, the downsampling filter 2 and the downsampling filter 3 are started for the second time, and the processing result is output for the second time. The subsequent processing and the like are not described in detail. It can be seen that the three downsampling filters 1201 are started sequentially, and the three downsampling filters 1201 output the processing results periodically with the preset threshold T as a period after the start.
In this embodiment, as shown in fig. 10, a schematic diagram of a down-sampling filter 1201 outputting a processing result according to a period in another embodiment is shown. The downsampling filter 1201 is described as a loop mode with the first timer 1301 as a single-pass mode. Three downsampling filters 1201 are provided, the delay start value of the first downsampling filter 1201 (denoted as downsampling filter 1) is set to t 1 The delayed start value of the second downsampling filter 1201 (denoted as downsampling filter 2) is set to t 2 The delayed start value of the third downsampling filter 1201 (denoted as downsampling filter 3) is set to t 3 Wherein t is 3 >t 2 >t 1 Also, the downsampling filter 1201 has been configured in a cyclic mode by the first control system 130, and the processing time of the downsampling filter 1201 is denoted as Δt. Assume that the preset threshold of the first timer 1301 is T, where T>t 3 The first timer 1301 has been configured by the system to a single mode. Thus, as shown in fig. 10, when the first timer 1301 receives the first trigger signal (this time is denoted as 0), the timer starts. In the timing process, when the timing reaches t 1 (i.e. t 1 Time), starting a down-sampling filter 1, continuously processing the bit stream by the down-sampling filter 1, and continuously outputting a processing result; then when the timing reaches t 2 (i.e. t 2 Time), starting the downsampling filter 2, and continuously processing the bit stream by the downsampling filter 2 to continuously output a processing result; then when the timing reaches t 3 (i.e. t 3 Time), starting a down-sampling filter 3, and continuously processing the bit stream by the down-sampling filter 3 to continuously output a processing result; and stopping timing when the timing reaches T. It can be seen that the three downsampling filters 1201 are started sequentially, and the three downsampling filters 1201 output the processing results periodically with the processing duration Δt thereof as a period after the start.
It can be understood that, the first timer 1301 is configured to be in a cyclic mode, and the downsampling filter 1201 is configured to be in a cyclic mode, so that the downsampling filter 1201 is configured to output the processing result periodically, which achieves a similar effect as that of fig. 10, and will not be described herein.
In this embodiment, at least one of the first timer and the downsampling filter is configured in a cyclic mode, so that the downsampling filter is configured to output the processing result according to a period, and can continuously process a bit stream, and obtain a plurality of different processing results, so that the described analog signal is finer and more accurate.
In one embodiment, the downsampling filter 1201 is configured to output a single processing result when the first timer 1301 and the downsampling filter 1201 are in a single mode.
Specifically, as shown in FIG. 11, a downsampling filter in one embodimentAnd outputting the processing result at a single time. Three downsampling filters 1201 are provided, the delay start value of the first downsampling filter 1201 (denoted as downsampling filter 1) is set to t 1 The delayed start value of the second downsampling filter 1201 (denoted as downsampling filter 2) is set to t 2 The delayed start value of the third downsampling filter 1201 (denoted as downsampling filter 3) is set to t 3 Wherein t is 3 >t 2 >t 1 Also, the downsampling filter 1201 has been configured in a single mode by the first control system 130, and the processing time of the downsampling filter 1201 is noted as Δt. Assume that the preset threshold of the first timer 1301 is T, where T>t 3 The first timer 1301 has been configured by the system to a single mode. As shown in fig. 11, when the first timer 1301 receives the first trigger signal for the first time (this time is denoted as 0), the timer starts. In the timing process, when the timing reaches t 1 (i.e. t 1 Time), starting the down-sampling filter 1, and outputting a processing result after the down-sampling filter 1 processes the bit stream; then when the timing reaches t 2 (i.e. t 2 Time), starting the down-sampling filter 2, and outputting a processing result after the down-sampling filter 2 processes the bit stream; then when the timing reaches t 3 (i.e. t 3 Time), starting the down-sampling filter 3, and outputting a processing result after the down-sampling filter 3 processes the bit stream; and stopping timing when the timing reaches T. It can be seen that the three downsampling filters 1201 are started in sequence, and the three downsampling filters 1201 output the processing result only once after being started.
Thereafter, when the first timer 1301 receives the first trigger signal for the second time (this time is denoted as T 1 ) Starting to count, when the counts respectively reach t 1 、t 2 、t 3 At three delayed start values (i.e., t in the figure) 1 +T 1 Time t 2 +T 1 Time t 3 +T 1 Time), the downsampling filter 1, the downsampling filter 2 and the downsampling filter 3 are started in sequence, the three components only output one processing result after starting, and then when the timing reaches a preset threshold value (namely T) 1 Time +t) the first timer 1301 stops counting.
In this embodiment, by configuring the first timer and the downsampling filter to be in a single mode, one section of analog signal can be selected for description, so as to improve the flexibility of use of the analog-to-digital converter.
In one embodiment, the first timer 1301 is further configured to:
when the shielding function is started, shielding the first trigger signal received again in the timing process;
when the masking function is turned off, the timing is restarted when the first trigger signal is received again during the timing.
Wherein other devices, such as registers, in the first control system 130 may be used to start or shut down the masking function of the first timer 1301. If the register is set to be 1, the shielding function is triggered to be started; by setting the register to 0, the mask function is triggered to close.
Specifically, the first timer 1301, which has started the masking function, masks the first trigger signal received again during the timing, i.e., does not restart the timing. In contrast, the first timer 1301 having closed the mask function restarts counting when receiving the first trigger signal again during counting. Taking a downsampling filter 1201 in a single processing mode as an example, as shown in fig. 12, a schematic diagram of the processing result of turning on or off the masking function of the first timer in one embodiment is shown. The first control system 130 has started the masking function of the first timer 1301 and configured the first timer 1301 to be in a single mode, when the first timer 1301 receives the first trigger signal (the time is recorded as 0), the first timer 1301 starts to count, and the delay start value (i.e. t) of the downsampling filter 1201 is reached during the counting process 1 Time of day) activates the downsampling filter 1201 to output a processing result, then at M 1 The first timer 1301 receives the second first trigger signal, and since the first timer 1301 has started the masking function at this time, the timer is not restarted, and then reaches the preset threshold T, and stops counting. Then, the first control system 130 turns off the masking function of the first timer 1301, so, assume that at t 2 At the moment of time of day,the first timer 1301 receives the third first trigger signal and starts counting, and during the counting, it is assumed that the time is M 2 The fourth first trigger signal is received at the moment (assuming that the timing has not reached the delay start value of the downsampling filter 1201 at this time), since the first timer 1301 has closed the masking function at this time, the first timer 1301 restarts timing, and when the timing has reached the delay start value of the downsampling filter 1201 (i.e., t 1 +M 2 Time instant) the downsampling filter 1201 is again enabled to output a processing result, and then at M 2 And (5) when the +T time reaches a preset threshold, stopping timing.
In this embodiment, the first timer starts to count after receiving the first trigger signal until reaching a preset threshold, and then in the counting process, when the first timer receives the first trigger signal again, it is determined whether the shielding function is turned on, and when the shielding function is started, the first trigger signal received again is shielded in the counting process; when the shielding function is closed, and the first trigger signal is received again in the timing process, the timing is restarted, so that the analog-to-digital converter is flexible to use.
In one embodiment, when the filter bank is enabled, if the register ESMx is 0, the timer is enabled and all of the downsampling filters are capable of receiving the start signal from the timer.
The working clock of the module can be divided by a preset register, and then the timer is driven to count. All time setting registers are clocked with divided clock cycles.
The first timer starts timing when receiving the trigger signal, and by setting the start time delay of each downsampling filter, the start time difference of each downsampling filter can be controlled, so that the phase relation of data output is controlled.
The timing period of the first timer can be set through a register, and is automatically cleared when the timer reaches the set time. By setting the register to 1, the timer can be automatically repeated.
If the trigger signal is received again during the timing process, the timer is immediately initialized and restarted. Subsequent trigger signals may be masked by setting the register to 1.
In one embodiment, the first control system 130 includes a first dispenser 1302; the first allocator 1302 is configured to control the start of each downsampling filter 1201 in the filter bank 120 according to a priority order when the second trigger signal is received.
Wherein the priority order is pre-stored in a register connected to the first control system 130. The priority order may be a low-order priority order or a high-order priority order. The priorities among the plurality of downsampling filters 1201 are predefined, for example, numbers are set for the downsampling filters 1201, the smaller or larger the numbers, the higher the priorities, etc. The order of priority for each downsampling filter 1201 in filter bank 120 is different.
The first control system 130 may be connected to an external control system, for example, an MCU, an upper computer, etc., and the external control system issues a second trigger signal to the first control system 130. That is, the external control system may also issue the second trigger signal directly to the first dispenser 1302.
Wherein the second trigger signal is an input signal of the first splitter 1302. The first splitter 1302 is configured to receive the second trigger signal, and send a split start signal to each decimation filter in the filter bank 120; the allocation initiation signal may be a pulse of the second trigger signal. The second trigger signal is used to control the activation of each downsampling filter 1201 in the filter bank 120 in order of priority. Each downsampling filter 1201 is capable of receiving a pulse of the second trigger signal and is activated on a pulse basis.
Specifically, when the second trigger signal is received, the first allocator 1302 is configured to control the start of each downsampling filter 1201 in the filter bank 120 according to the order of priority. For example, when the first divider 1302 receives the first pulse of the second trigger signal, the downsampling filter 1201 with the highest priority is activated; when the first divider 1302 receives the second pulse of the second trigger signal, the downsampling filter 1201 with the second highest priority is activated; and so on until the downsampling filter 1201 with the lowest priority is activated. In this way, the successive activation of a plurality of the downsampling filters 1201 can be controlled.
In this embodiment, the first distributor can control the starting of the plurality of downsampling filters 1201 by distributing the second trigger signal, so that the downsampling filters 1201 can output different processing results, and the described analog signal is finer.
In one embodiment, the analog-to-digital converter further comprises a register, which is connected to the first distributor 1302 for storing a down-sampling filter list comprising down-sampling filters 1201 arranged in a priority order;
the first allocator 1302 is configured to control activation of each downsampling filter 1201 in the filter bank 120 according to the list of downsampling filters when the second trigger signal is received.
Specifically, the extraction units in the extraction unit list are arranged in order of priority. The first allocator 1302 is configured to, when receiving the second trigger signal, sequentially send out allocation start signals according to a priority order, such as a low order priority order, according to the downsampling filter list currently opened by the register, so as to control each downsampling filter 1201 in the filter bank 120 to start.
In this embodiment, the first distributor is configured to control starting of each downsampling filter in the filter bank according to the downsampling filter list, so that starting times of the downsampling filters are staggered, and different processing results are obtained.
In one embodiment, the first dispenser 1302 can be configured in a single mode or a cyclic mode; the first distributor 1302 in the circulation mode is configured to output a distribution start signal in cycles; the first dispenser 1302 in the single-pass mode is configured to output a single-pass dispensing-start signal;
the downsampling filter 1201 can be configured in a single-pass mode or a cyclic mode; the downsampling filter 1201 in the single mode is used to output a single processing result; the downsampling filter 1201 in the cyclic mode is used for continuously processing the bit stream after being started and outputting a processing result according to the cycle;
The downsampling filter 1201 is configured to output a single processing result after start-up or output a processing result in cycles based on the mode of the first splitter 1302 and the mode of the downsampling filter 1201.
The single dispense initiation signal is a signal output after the first dispenser 1302 receives a single second trigger signal. The allocation initiation signal may be used to initiate all of the downsampling filters 1201 in a prioritized order or may be used to initiate some of the downsampling filters 1201 in a prioritized order.
Wherein the downsampling filter 1201 is configured to output the processing result in cycles when at least one of the first splitter 1302 and the downsampling filter 1201 is in a cyclic mode.
The downsampling filter 1201 is configured to output a single processing result when the first divider 1302 and the downsampling filter 1201 are in a single mode.
For example, the first divider 1302 is described as a single-pass mode and the downsampling filter 1201 is described as a loop mode. Assuming that three downsampling filters 1201 are provided, the priority is from high to low, namely a downsampling filter 1, a downsampling filter 2 and a downsampling filter 3; and, each of the three downsampling filters 1201 has been configured by the first control system 130 into a cyclic mode, and the processing time of the downsampling filters 1201 is denoted as Δt. In addition, it is assumed that the second trigger signal is a rising edge trigger, and thus, as shown in fig. 13, a schematic diagram of a processing result in which the first distributor is in a single mode and the downsampling filter is in a loop mode in one embodiment is shown. At t 1 The first distributor 1302 receives the first pulse of the second trigger signal at the moment when the downsampling filter 1201 with the highest priority and not activated is the downsampling filter 1, so that the downsampling filter 1 is activated, and the processing result is output periodically with Δt as a period because the downsampling filter 1 is in the cyclic mode. At t 2 The first distributor 1302 receives the second pulse of the second trigger signal at the moment when the downsampling filter 1201 with the highest priority and not activated is the downsampling filter 2, and similarly, the downsampling filter 2 outputs the processing result in cycles with Δt as a period. At t 3 Time of dayThe first divider 1302 receives the third pulse of the second trigger signal, and at this time, the downsampling filter 1201 which has the highest priority and is not activated is the downsampling filter 3, and similarly, the downsampling filter 3 outputs the processing result in cycles with Δt as a cycle. It can be seen that the three downsampling filters 1201 are started sequentially, and the three downsampling filters 1201 periodically output the processing result with the processing duration Δt thereof as a period after the start. It should be noted that, if the first dispatcher 1302 receives the second trigger signal, it may perform discarding processing or other reasonable processing.
In this embodiment, the first divider 1302 is taken as an example of the loop mode and the downsampling filter 1201 is taken as a single-pass mode. Assuming that three downsampling filters 1201 are provided, the priority is from high to low, namely a downsampling filter 1, a downsampling filter 2 and a downsampling filter 3; and, each of the three downsampling filters 1201 has been configured by the first control system 130 into a single mode, the processing time of the downsampling filters 1201 is denoted as Δt. In addition, it is assumed that the second trigger signal is a rising edge of the control signal received by the first dispenser 1302. Thus, as shown in fig. 14, a schematic diagram of the processing result of the first distributor in the circulation mode in one embodiment is shown. And when the first distributor is in the cyclic mode, the processing result is output according to the period no matter the downsampling filter is in the single-time mode or the cyclic mode. At t 1 The first distributor 1302 receives the first pulse of the second trigger signal at the moment when the downsampling filter 1201 of which priority is the most activated is the downsampling filter 1, and thus distributes the activation signal to the decimating filter 1 to activate the downsampling filter 1, and since the downsampling filter 1 is in the single mode, only one processing result is output. At t 2 The first distributor 1302 receives the second pulse of the second trigger signal at the moment when the downsampling filter 1201 with the highest priority and not activated is the downsampling filter 2, and similarly, the downsampling filter 2 outputs only one processing result. At t 3 The third pulse of the second trigger signal is received by the first distributor 1302 at the moment when the downsampling filter 1201 with the highest priority and not activated is the downsampling filter 3, and similarly, the downsampling filter 3 outputs onlyA processing result is output. It can be seen that the three downsampling filters 1201 are started in sequence, and the three downsampling filters 1201 output only one processing result after starting. Thereafter, the first dispensers 1302 are each at t 4 Time t 5 Time t 6 And when the second trigger signal is received at the moment, the downsampling filter 1, the downsampling filter 2 and the downsampling filter 3 are started in sequence, and only one processing result is output by the downsampling filter 3, the downsampling filter 2 and the downsampling filter 3.
In one embodiment, the number of first control systems 130 is a plurality; the number of filter banks corresponds to the number of first control systems 130; the analog to digital converter further comprises a second control system 140; the second control system 140 is respectively connected to the plurality of first control systems 130, and is used for controlling the first control systems 130 to be started sequentially.
Wherein the second control system 140 is not the same control system as the first control system 130. The second control system 140 may include a first timer and the first control system 130 includes a first timer. The second control system 140 includes a first dispenser and the first control system 130 also includes a first dispenser.
Specifically, as shown in fig. 15, a schematic structural diagram of an analog-to-digital converter according to another embodiment is shown. Fig. 15 includes a second control system 140 coupled to the plurality of first control systems 130. Each first control system 130 corresponds to one filter bank 120.
Then, as shown in fig. 16, a signal transmission schematic of the second control system including the second timer in one embodiment is shown. In fig. 16, a series of squares represent a series of signals, and an arrow represents a pulse or a trigger. The starting sequence among the first timers is a first timer A, a first timer B and a first timer C. The starting sequence of each downsampling filter in the filter bank is a downsampling filter 1, a downsampling filter 2, a downsampling filter 3, a downsampling filter 4, a downsampling filter 5, a downsampling filter 6 and a downsampling filter 7. It will be appreciated that the time at which the first timer 1301 transmits the timing start signal to the filter bank 120 is different, and the time at which the second timer 1401 transmits the timing start signal to each first timer 1301 is also different. Then, when the second timer 1401 receives the trigger signal, it starts to count, and in the counting process, when the count reaches the delay start value corresponding to the first timer a, it sends the first trigger signal to the first timer a, and starts the first timer a. The first timer a receives the first trigger signal, starts to count, and when reaching the delay start value corresponding to the downsampling filter 1, sends a timing start signal to the downsampling filter 1, so that the downsampling filter 1 starts first to process the bit stream. The downsampling filter 2 and the downsampling filter 3 follow, and are not described here again. After the downsampling filter 3 is started, the second timer is still counting, and when the delay starting value corresponding to the first timer B is reached, a first trigger signal is sent to the first timer B, and the first timer B is started. The first timer B sequentially issues a timing start signal to start the downsampling filter 4 and the downsampling filter 5. After the second timer reaches the delay starting value corresponding to the first timer C, the first timer C is started, and the first timer C sequentially sends out a timing starting signal to start the downsampling filter 6 and the downsampling filter 7.
FIG. 17 is a signal transmission diagram of the second timer in the single-shot mode and the first timer in the cyclic mode in one embodiment. The single mode of the second timer means that the timing is stopped when the timing reaches the delay starting value corresponding to the last first timer. As can be seen from fig. 17, when the second timer is in the single-shot mode, the first timer may output the timer start signal periodically.
Fig. 18 is a schematic diagram of signal transmission of the second timer in the cyclic mode in one embodiment. Specifically, in fig. 18, the second timer is in a cyclic mode, and the first timer may be in a cyclic mode or a single-time mode. As can be seen from fig. 18, when the second timer is in the loop mode, the first timer outputs a timer start signal in a periodic manner, and each filter can output a processing result in a periodic manner.
FIG. 19 is a signal transmission schematic diagram of a second control system including a second distributor according to one embodiment. Specifically, in fig. 19, the number of pulses of the trigger signal received by the second dispenser is the same as the number of pulses dispensed. The second distributor receives the trigger signals and distributes the second trigger signals with the same number of pulses as the number of filters in the filter group A to the first distributor A. The first distributor a sends distribution start signals with different pulse occurrence times to the downsampling filters 1, 2 and 3 based on the second trigger signals, so that the downsampling filters 1, 2 and 3 are started in sequence. The second distributor distributes the second trigger signals with the same pulse number as the filter number in the filter group B to the first distributor B, so that the downsampling filter 4 and the downsampling filter 5 are started in sequence. The second distributor distributes the second trigger signals with the same pulse number as the filter number in the filter group B to the first distributor B, so that the downsampling filter 4 and the downsampling filter 5 are started in sequence. The second distributor distributes the second trigger signals with the same pulse number as the filter number in the filter group C to the first distributor C, so that the downsampling filter 6 and the downsampling filter 7 are started in sequence.
In one embodiment, the switch module is for: so that a plurality of downsampling filters 120 are connected to the same modulator 110. Illustratively, as shown in fig. 20, a schematic diagram of the structure of the modulator and the downsampling filter in one embodiment is shown. Assuming that three modulators 110 (modulator 1, modulator 2, modulator 3, respectively) and three downsampling filters 120 (downsampling filters 1, 2, 3, respectively) are provided, and in case an analog signal 1 needs to be described in detail, three downsampling filters 120 can be controlled to be connected to the same modulator 110, see the previous discussion for specific implementations.
In one embodiment, the switch module is for: such that one portion of the plurality of downsampling filters 120 is coupled to the same modulator 110 and another portion is coupled to a different modulator 110. Illustratively, as shown in fig. 21, a schematic diagram of a modulator and a downsampling filter in another embodiment is shown. Assuming that three modulators 110 (modulator 1, modulator 2, modulator 3, respectively) and three downsampling filters 120 (downsampling filter 1, downsampling filter 2, downsampling filter 3, respectively) are provided, and in case that a user needs to describe the analog signal 1 finely, but does not need to describe the analog signal 2 finely, the modulators 1, 2 of the three modulators 110 can be controlled to be connected to the modulator 1, for specific implementation, see the foregoing discussion; modulator 3 of the three modulators 110 is controlled to be connected to modulator 2 at the same time.
In one embodiment, the switch module is for: such that the plurality of downsampling filters 120 connect different modulators. Illustratively, as shown in fig. 22, a schematic diagram of a modulator and a downsampling filter in a further embodiment is shown. Three modulators 110 (modulator 1, modulator 2, modulator 3, respectively) and three downsampling filters 120 (downsampling filters 1, 2, 3, respectively) are assumed. In addition, if it is not necessary to describe the analog signal 1, the analog signal 2, and the analog signal 3 in detail, it is possible to control the downsampling filter 1 to be connected to the modulator 1, the downsampling filter 2 to be connected to the modulator 2, and the downsampling filter 3 to be connected to the modulator 3.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the application, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
Claims (10)
1. An analog-to-digital converter, comprising:
a modulator for processing the analog signal to output a bit stream;
the filter bank comprises a plurality of downsampling filters, and each downsampling filter is connected with the modulator respectively;
The first control system is respectively connected with the downsampling filters and used for controlling the downsampling filters to be started in sequence, so that the downsampling filters are used for processing the bit stream after being started and outputting different processing results.
2. The analog-to-digital converter of claim 1, wherein the first control system comprises a first timer;
the first timer is used for starting timing after receiving a first trigger signal, and when the timing reaches a delay starting value, the downsampling filter corresponding to the delay starting value is controlled to be started; the delay starting values corresponding to the downsampling filters are different.
3. The analog-to-digital converter of claim 2, wherein the first timer is configurable in a single-pass mode or a cyclic mode; the first timer in the circulation mode is used for restarting timing when the timing reaches a first preset threshold; the first timer in the single mode is used for stopping timing when the timing reaches a second preset threshold;
the downsampling filter can be configured in a single mode or a cyclic mode; the downsampling filter in the single mode is used for outputting the single processing result; the downsampling filter in the cyclic mode is used for continuously processing the bit stream after starting and outputting the processing result according to the period;
The downsampling filter is used for outputting the processing result of a single time or outputting the processing result according to a period after starting based on the mode of the first timer and the mode of the downsampling filter.
4. An analog-to-digital converter according to claim 3, wherein the downsampling filter is configured to output the processing result on a periodic basis when at least one of the first timer and the downsampling filter is in the cyclic mode.
5. An analog-to-digital converter according to claim 3, wherein the downsampling filter is configured to output a single result of the processing when the first timer and the downsampling filter are both in the single mode.
6. The analog-to-digital converter of any of claims 2 to 5, wherein the first timer is further configured to:
when the shielding function is started, shielding the first trigger signal received again in the timing process;
when the shielding function is closed, restarting timing when the first trigger signal is received again in the timing process.
7. The analog-to-digital converter of claim 1, wherein the first control system comprises a first divider;
The first distributor is used for controlling each downsampling filter in the filter bank to start according to the priority order when receiving the second trigger signal.
8. The analog-to-digital converter of claim 7, further comprising a register coupled to said first divider for storing a list of downsampling filters, said list of downsampling filters comprising said downsampling filters arranged in a priority order;
the first distributor is used for controlling each downsampling filter in the filter bank to start according to the downsampling filter list when the second trigger signal is received.
9. The analog-to-digital converter according to any one of claims 1 to 5, 7 and 8, wherein the number including the first control system is a plurality; the number of the filter banks is consistent with the number of the first control systems;
the analog-to-digital converter further comprises a second control system; the second control system is respectively connected with the plurality of first control systems and used for controlling the first control systems to start successively.
10. The analog-to-digital converter according to any one of claims 1 to 5, 7 and 8, wherein the number of modulators is plural, the analog-to-digital converter further comprising a switching module;
The switch module is used for: so that a plurality of the downsampling filters are connected with the same modulator; or one part of the plurality of the downsampling filters is connected with the same modulator, and the other part is connected with different modulators; or to connect a plurality of said downsampling filters to different modulators.
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