CN117200753A - Low-overhead four-point flip self-recovery latch based on cross interlocking - Google Patents
Low-overhead four-point flip self-recovery latch based on cross interlocking Download PDFInfo
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- CN117200753A CN117200753A CN202311119821.2A CN202311119821A CN117200753A CN 117200753 A CN117200753 A CN 117200753A CN 202311119821 A CN202311119821 A CN 202311119821A CN 117200753 A CN117200753 A CN 117200753A
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Abstract
The invention discloses a low-overhead four-point flip self-recovery latch based on cross interlocking, which comprises a latch circuit formed by cross connection of 4 cross interlocking units and having 16 internal nodes in total, and an input circuit formed by 4 transmission gates and 4 transmission transistors; the input ends of the 4 transmission gates and the 4 transmission transistors are commonly connected with input signals, and the output ends of the 4 transmission gates and the input ends of the 4 transmission transistors are connected with 8 internal nodes of the latch circuit; in the transparent period, each transmission gate and each transmission transistor are conducted, and input signals are transmitted into 8 internal nodes and output through an output node Q; in the lock-in period, the 4 transmission gates and the 4 transmission transistors are turned off, and data are stored in the latch circuit; the invention plays the advantage of cross interlocking to realize 100% four-point overturn self-recovery, so that even under severe radiation environment, the latch can be prevented from being influenced by four-point overturn, and the soft error resistance of the latch is improved.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a four-point flip self-recovery latch applied to the field of radiation-resistant reinforcement circuits.
Background
With the rapid development of integrated circuits, the feature size of transistors is continuously reduced, which causes the supply voltage to be continuously reduced, the node capacitance to be continuously reduced, the critical charge of circuit nodes to be continuously reduced, and CMOS devices are more and more susceptible to soft errors, which may cause data corruption, execution errors, and even system breakdown in the worst case.
The single event effect (Single Event Effect, SEE) is an important cause of affecting the normal operation of advanced semiconductor integrated circuits, and can seriously affect the normal operation of integrated circuits in severe radiation environments. The single event effect mainly includes single event upset (Single Event Upset, SEU), single event transient (Single Event Transient, SET), single event burn out (Single Event Burnout, SEB), single event latch (Single Event Latch-up, SEL), etc., the SEU being an important cause of soft errors.
When radiation particles strike sensitive areas of the integrated circuit, false transient pulses or node flips may be generated, which is known as soft errors. Wherein, single point flipping (Single Node Upset, SNU) refers to flipping a single sensitive node logic value within a memory cell when a single radiation particle impinges on the memory cell. However, as feature sizes shrink and node pitch continues to decrease, the impact of one radiation particle may affect multiple node flips simultaneously due to charge sharing effects, a phenomenon known as single particle multi-point flipping. Multi-node flips include a dual-node flip (Double Node Upset, DNU), a three-node flip (Triple Node Upset, TNU), and a four-node flip (Quadruple Node Upset, QNU). Multi-point flipping can severely impact the reliability of integrated circuits and systems in harsh radiation environments.
Latches are logic cells in integrated circuits that are used very frequently, and are an important basis for the integrated circuits to function properly. However, with the rapid development of integrated circuits, three-point flip and four-point flip caused by charge sharing have become serious problems, so it is important to design advanced latches tolerant to four-point flip.
Disclosure of Invention
In order to avoid the defects of the prior art, the invention provides the single-particle four-point flip-flop reinforced latch, so that the integrated circuit can not be influenced by four-point flip to work normally even in a severe radiation environment.
The low-overhead four-point flip self-recovery latch based on cross interlocking comprises a latch circuit formed by cross connection of 4 cross interlocking units and having 16 internal nodes, and an input circuit formed by 4 transmission gates and 4 transmission transistors; the input ends of the 4 transmission gates and the 4 transmission transistors are commonly connected with input signals, and the output ends of the 4 transmission gates and the input ends of the 4 transmission transistors are connected with 8 internal nodes of the latch circuit; in the transparent period, each transmission gate and each transmission transistor are conducted, and input signals are transmitted into 8 internal nodes and output through an output node Q; during the lock-in period, the 4 transmission gates and the 4 transmission transistors are turned off, and data is stored in the latch circuit.
The latch circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube sixteenth NMOS transistor, seventeenth NMOS transistor, eighteenth NMOS transistor, nineteenth NMOS transistor, twenty-first NMOS transistor, twenty-second NMOS transistor, twenty-third NMOS transistor, twenty-fourth NMOS transistor, twenty-fifth NMOS transistor, twenty-sixth NMOS transistor, twenty-seventh NMOS transistor, twenty-eighth NMOS transistor, twenty-ninth NMOS transistor, thirty-first NMOS transistor, thirty-second NMOS transistor, node N1, node Q, node N3, node N4, node N5, node N6, node N7, node N8, node N9, node N10, node N11, node N12, node N13, node N14, node N15, node N16;
The node N1 is respectively connected with the grid electrode of the fourth PMOS tube, the grid electrode of the eighth NMOS tube, the grid electrode of the twenty-first NMOS tube, the grid electrode of the thirty-NMOS tube, the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube;
the node Q is respectively connected with the grid electrode of the first NMOS tube, the grid electrode of the seventh PMOS tube, the drain electrode of the second PMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube;
the node N3 is respectively connected with the grid electrode of the seventh NMOS tube, the grid electrode of the sixth PMOS tube, the drain electrode of the third PMOS tube, the drain electrode of the fifth NMOS tube and the drain electrode of the sixth NMOS tube;
the node N4 is respectively connected with the grid electrode of the first PMOS tube, the grid electrode of the second NMOS tube, the grid electrode of the twenty-seventh NMOS tube, the grid electrode of the seventh NMOS tube and the drain electrode of the eighth NMOS tube;
the node N5 is respectively connected with the grid electrode of the eighth PMOS tube, the grid electrode of the sixteenth NMOS tube, the grid electrode of the fifth NMOS tube, the grid electrode of the twenty-second NMOS tube, the drain electrode of the ninth NMOS tube and the drain electrode of the tenth NMOS tube;
The node N6 is respectively connected with the grid electrode of the ninth NMOS tube, the grid electrode of the fifteenth PMOS tube, the drain electrode of the sixth PMOS tube, the drain electrode of the eleventh NMOS tube and the drain electrode of the twelfth NMOS tube;
the node N7 is respectively connected with the grid electrode of the fifteenth NMOS tube, the grid electrode of the fourteenth PMOS tube, the drain electrode of the seventh PMOS tube, the drain electrode of the thirteenth NMOS tube and the drain electrode of the fourteenth NMOS tube;
the node N8 is respectively connected with the grid electrode of the fifth PMOS tube, the grid electrode of the tenth NMOS tube, the grid electrode of the third NMOS tube, the grid electrode of the nineteenth NMOS tube, the drain electrode of the fifteenth NMOS tube and the drain electrode of the sixteenth NMOS tube;
the node N9 is respectively connected with the grid electrode of the twelfth PMOS tube, the grid electrode of the twenty-fourth NMOS tube, the grid electrode of the thirteenth NMOS tube, the grid electrode of the twenty-ninth NMOS tube, the drain electrode of the seventeenth NMOS tube and the drain electrode of the eighteenth NMOS tube;
the node N10 is respectively connected with the grid electrode of the seventeenth NMOS tube, the grid electrode of the third PMOS tube, the drain electrode of the tenth PMOS tube, the drain electrode of the nineteenth NMOS tube and the drain electrode of the twentieth NMOS tube;
The node N11 is respectively connected with the grid electrode of the twenty-third NMOS tube, the grid electrode of the second PMOS tube, the drain electrode of the eleventh PMOS tube, the drain electrode of the twenty-first NMOS tube and the drain electrode of the twenty-second NMOS tube;
the node N12 is respectively connected with the grid electrode of the ninth PMOS tube, the grid electrode of the eighteenth NMOS tube, the grid electrode of the eleventh NMOS tube, the grid electrode of the twenty eighth NMOS tube, the drain electrode of the twenty third NMOS tube and the drain electrode of the twenty fourth NMOS tube;
the node N13 is respectively connected with the grid electrode of the sixteenth PMOS tube, the grid electrode of the thirty-second NMOS tube, the grid electrode of the sixth NMOS tube, the grid electrode of the fourteenth NMOS tube, the drain electrode of the twenty-fifth NMOS tube and the drain electrode of the twenty-sixth NMOS tube;
the node N14 is respectively connected with the grid electrode of the twenty-fifth NMOS tube, the grid electrode of the eleventh PMOS tube, the drain electrode of the fourteenth PMOS tube, the drain electrode of the twenty-seventh NMOS tube and the drain electrode of the twenty-eighth NMOS tube;
the node N15 is respectively connected with the grid electrode of the thirty-first NMOS tube, the grid electrode of the tenth PMOS tube, the drain electrode of the fifteenth PMOS tube, the drain electrode of the twenty-ninth NMOS tube and the drain electrode of the thirty-NMOS tube;
The node N16 is respectively connected with the grid electrode of the thirteenth PMOS tube, the grid electrode of the twenty-sixth NMOS tube, the grid electrode of the fourth NMOS tube, the grid electrode of the twelfth NMOS tube, the drain electrode of the thirty-first NMOS tube and the drain electrode of the thirty-second NMOS tube;
the source electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the seventh NMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the ninth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the source electrode of the fifteenth NMOS tube is connected with the drain electrode of the eighth PMOS tube, the source electrode of the seventeenth NMOS tube is connected with the drain electrode of the ninth PMOS tube, the source electrode of the twenty third NMOS tube is connected with the drain electrode of the twelfth PMOS tube, the source electrode of the twenty fifth NMOS tube is connected with the drain electrode of the thirteenth PMOS tube, and the source electrode of the thirty first NMOS tube is connected with the drain electrode of the sixteenth PMOS tube;
the sources of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube are all connected with the power supply voltage VDD;
The sources of the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the eighth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube, the fourteenth NMOS tube, the sixteenth NMOS tube, the eighteenth NMOS tube, the nineteenth NMOS tube, the twenty-first NMOS tube, the twenty-second NMOS tube, the twenty-fourth NMOS tube, the twenty-sixth NMOS tube, the twenty-seventh NMOS tube, the twenty-eighth NMOS tube, the twenty-ninth NMOS tube, the thirty-second NMOS tube are all connected with the ground GND.
The input circuit comprises a first transmission transistor, a second transmission transistor, a third transmission transistor, a fourth transmission transistor, a first transmission gate, a second transmission gate, a third transmission gate and a fourth transmission gate, wherein the signal input ends of the first transmission transistor, the second transmission transistor, the third transmission transistor, the fourth transmission transistor, the first transmission gate, the second transmission gate, the third transmission gate and the fourth transmission gate are connected with an input signal D, and the output ends of the first transmission transistor, the second transmission transistor, the third transmission transistor, the fourth transmission transistor, the first transmission gate, the second transmission gate, the third transmission gate and the fourth transmission gate are respectively connected with nodes N1, N5, N9, N13, Q, N6, N10 and N14; the input circuit is turned on when the clock signal clk=1, and is turned off when the clock signal clk=0.
The node N1 is surrounded by a first NMOS tube, a second NMOS tube and a first transmission transistor, and is a non-sensitive node (which cannot turn over when impacted by particles) when the logic value of the node N1 is 0; the node N4 is surrounded by a seventh NMOS tube and an eighth NMOS tube, and is a non-sensitive node when the logic value of the node N4 is 0; the node N5 is surrounded by a ninth NMOS tube, a tenth NMOS tube and a second transmission transistor, and is a non-sensitive node when the logic value of the node N5 is 0; the node N8 is surrounded by a fifteenth NMOS tube and a sixteenth NMOS tube, and is a non-sensitive node when the logic value of the node N8 is 0; the node N9 is surrounded by a seventeenth NMOS tube, an eighteenth NMOS tube and a third transmission transistor, and is a non-sensitive node when the logic value of the node N9 is 0; the node N12 is surrounded by a twenty-third NMOS tube and a twenty-fourth NMOS tube, and is a non-sensitive node when the logic value of the node N12 is 0; the node N13 is surrounded by a twenty-fifth NMOS tube, a twenty-sixth NMOS tube and a fourth transmission transistor, and is a non-sensitive node when the logic value of the node N13 is 0; the node N16 is surrounded by a thirty-first NMOS tube and a thirty-second NMOS tube, and is a non-sensitive node when the logic value of the node N16 is 0; when the latch works, four nodes are non-sensitive nodes, so that the number of sensitive nodes can be effectively reduced.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention has good fault tolerance, can 100% tolerate single-event single-point overturn, double-point overturn, three-point overturn and four-point overturn, and can recover 100%;
2. the invention effectively reduces the number of transistors based on the characteristic of cross interlocking, so that the power consumption and the area cost are smaller;
3. the invention utilizes the stacking characteristic of NMOS tubes to effectively reduce the number of sensitive nodes.
The invention can 100% tolerate the condition that any 4 internal nodes turn over simultaneously, and restore all the turning nodes to the correct logic value. The structure of the invention effectively reduces the number of sensitive nodes and uses fewer transistors, so the structure is a four-point flip self-recovery latch with low cost compared with the structure with smaller power consumption and area cost.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a schematic diagram of a latch circuit of a low overhead four-point flip-flop self-restore latch based on cross-interlocking in accordance with the present invention;
Fig. 2 is a schematic circuit diagram of an input circuit according to the present invention.
In the figure: 101-first PMOS tube, 102-first NMOS tube, 103-second NMOS tube, 104-second PMOS tube, 105-third NMOS tube, 106-fourth NMOS tube, 107-third PMOS tube, 108-fifth NMOS tube, 109-sixth NMOS tube, 110-fourth PMOS tube, 111-seventh NMOS tube, 112-eighth NMOS tube, 201-fifth PMOS tube, 202-ninth NMOS tube, 203-tenth NMOS tube, 204-sixth PMOS tube, 205-eleventh NMOS tube, 206-twelfth NMOS tube, 207-seventh PMOS tube, 208-thirteenth NMOS tube, 209-fourteenth NMOS tube, 210-eighth PMOS tube, 211-fifteenth NMOS tube, 212-sixteenth NMOS tube, 301-ninth PMOS tube, 302-seventeenth NMOS tube, 303-eighteenth NMOS tube, 304-tenth PMOS tube, 305-nineteenth NMOS transistor, 306-twenty-eighth NMOS transistor, 307-eleventh PMOS transistor, 308-twenty-first NMOS transistor, 309-twenty-second NMOS transistor, 310-twelfth PMOS transistor, 311-twenty-third NMOS transistor, 312-twenty-fourth NMOS transistor, 401-thirteenth PMOS transistor, 402-twenty-fifth NMOS transistor, 403-twenty-sixth NMOS transistor, 404-fourteenth PMOS transistor, 405-twenty-seventh NMOS transistor, 406-twenty-eighth NMOS transistor, 407-fifteenth PMOS transistor, 408-twenty-ninth NMOS transistor, 409-thirty-third NMOS transistor, 410-sixteenth PMOS transistor, 411-thirty-first NMOS transistor, 412-thirty-second NMOS transistor, 501-first transmission transistor, 502-second transmission transistor, 503-third transmission transistor, 504-fourth transmission transistor, 505-first transmission gate, 506-second transmission gate, 507-third transmission gate, 508-fourth transmission gate.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
Referring to fig. 1 and 2, a low overhead four-point flip-flop self-restore latch based on cross-interlocking includes a latch circuit and an input circuit. The latch circuit includes a first PMOS transistor 101, a first NMOS transistor 102, a second NMOS transistor 103, a second PMOS transistor 104, a third NMOS transistor 105, a fourth NMOS transistor 106, a third PMOS transistor 107, a fifth NMOS transistor 108, a sixth NMOS transistor 109, a fourth PMOS transistor 110, a seventh NMOS transistor 111, an eighth NMOS transistor 112, a fifth PMOS transistor 201, a ninth NMOS transistor 202, a tenth NMOS transistor 203, a sixth PMOS transistor 204, an eleventh NMOS transistor 205, a twelfth NMOS transistor 206, a seventh PMOS transistor 207, a thirteenth NMOS transistor 208, a fourteenth NMOS transistor 209, an eighth PMOS transistor 210, a fifteenth NMOS transistor 211, a sixteenth NMOS transistor 212, a ninth PMOS transistor 301, a seventeenth NMOS transistor 302, an eighteenth NMOS transistor 303, a PMOS transistor 304, a nineteenth NMOS transistor 306, an eleventh PMOS transistor 307, a twenty-first NMOS transistor 308, a twenty-second NMOS transistor 309, a twelfth NMOS transistor 310, a twenty-third NMOS transistor 311, a twenty-fourth NMOS transistor 312, a thirteenth NMOS transistor 401, a twenty-eighth NMOS transistor 403, a twenty-seventh NMOS transistor 402, a thirty-eighth NMOS transistor 408, a thirty-seventeenth NMOS transistor 408, a thirty-eighth NMOS transistor 410, a seventeenth transistor 410, node N1, node Q, node N3, node N4, node N5, node N6, node N7, node N8, node N9, node N10, node N11, node N12, node N13, node N14, node N15, node N16.
The node N1 is connected to the gate of the fourth PMOS transistor 110, the gate of the eighth NMOS transistor 112, the gate of the twenty-first NMOS transistor 308, the gate of the thirty-NMOS transistor 409, the drain of the first NMOS transistor 102, and the drain of the second NMOS transistor 103, respectively;
node Q is connected to the gate of the first NMOS transistor 102, the gate of the seventh PMOS transistor 207, the drain of the second PMOS transistor 104, the drain of the third NMOS transistor 105, and the drain of the fourth NMOS transistor 106, respectively;
node N3 is connected to the gate of the seventh NMOS transistor 111, the gate of the sixth PMOS transistor 204, the drain of the third PMOS transistor 107, the drain of the fifth NMOS transistor 108, and the drain of the sixth NMOS transistor 109, respectively;
the node N4 is connected to the gate of the first PMOS 101, the gate of the second NMOS 103, the gate of the twentieth NMOS 306, the gate of the twenty-seventh NMOS 405, the drain of the seventh NMOS 111, and the drain of the eighth NMOS 112, respectively;
node N5 is connected to the gate of the eighth PMOS transistor 210, the gate of the sixteenth NMOS transistor 212, the gate of the fifth NMOS transistor 108, the gate of the twenty-second NMOS transistor 309, the drain of the ninth NMOS transistor 202, and the drain of the tenth NMOS transistor 203, respectively;
Node N6 is connected to the gate of the ninth NMOS transistor 202, the gate of the fifteenth PMOS transistor 407, the drain of the sixth PMOS transistor 204, the drain of the eleventh NMOS transistor 205, and the drain of the twelfth NMOS transistor 206, respectively;
the node N7 is connected to the gate of the fifteenth NMOS transistor 211, the gate of the fourteenth PMOS transistor 404, the drain of the seventh PMOS transistor 207, the drain of the thirteenth NMOS transistor 208, and the drain of the fourteenth NMOS transistor 209, respectively;
the node N8 is connected to the gate of the fifth PMOS 201, the gate of the tenth NMOS 203, the gate of the third NMOS 105, the gate of the nineteenth NMOS 305, the drain of the fifteenth NMOS 211, and the drain of the sixteenth NMOS 212, respectively;
node N9 is connected to the gate of the twelfth PMOS transistor 310, the gate of the twenty-fourth NMOS transistor 312, the gate of the thirteenth NMOS transistor 208, the gate of the twenty-ninth NMOS transistor 408, the drain of the seventeenth NMOS transistor 302, and the drain of the eighteenth NMOS transistor 303, respectively;
node N10 is connected to the gate of the seventeenth NMOS transistor 302, the gate of the third PMOS transistor 107, the drain of the tenth PMOS transistor 304, the drain of the nineteenth NMOS transistor 305, and the drain of the twentieth NMOS transistor 306, respectively;
Node N11 is connected to the gate of the twenty-third NMOS transistor 311, the gate of the second PMOS transistor 104, the drain of the eleventh PMOS transistor 307, the drain of the twenty-first NMOS transistor 308, and the drain of the twenty-second NMOS transistor 309, respectively;
the node N12 is connected to the gate of the ninth PMOS transistor 301, the gate of the eighteenth NMOS transistor 303, the gate of the eleventh NMOS transistor 205, the gate of the twenty eighth NMOS transistor 406, the drain of the twenty third NMOS transistor 311, and the drain of the twenty fourth NMOS transistor 312, respectively;
node N13 is connected to the gate of the sixteenth PMOS transistor 410, the gate of the thirty-second NMOS transistor 412, the gate of the sixth NMOS transistor 109, the gate of the fourteenth NMOS transistor 209, the drain of the twenty-fifth NMOS transistor 402, and the drain of the twenty-sixth NMOS transistor 403, respectively;
node N14 is connected to the gate of the twenty-fifth NMOS transistor 402, the gate of the eleventh PMOS transistor 307, the drain of the fourteenth PMOS transistor 404, the drain of the twenty-seventh NMOS transistor 405, and the drain of the twenty-eighth NMOS transistor 406, respectively;
node N15 is connected to the gate of the thirty-first NMOS transistor 411, the gate of the tenth PMOS transistor 304, the drain of the fifteenth PMOS transistor 407, the drain of the twenty-ninth NMOS transistor 408, and the drain of the thirty-NMOS transistor 409, respectively;
Node N16 is connected to the gate of the thirteenth PMOS 401, the gate of the twenty-sixth NMOS 403, the gate of the fourth NMOS 106, the gate of the twelfth NMOS 206, the drain of the thirty-first NMOS 411, and the drain of the thirty-second NMOS 412, respectively;
the source of the first NMOS transistor 102 is connected to the drain of the first PMOS transistor 101, the source of the seventh NMOS transistor 111 is connected to the drain of the fourth PMOS transistor 110, the source of the ninth NMOS transistor 202 is connected to the drain of the fifth PMOS transistor 201, the source of the fifteenth NMOS transistor 211 is connected to the drain of the eighth PMOS transistor 210, the source of the seventeenth NMOS transistor 302 is connected to the drain of the ninth PMOS transistor 301, the source of the twenty third NMOS transistor 311 is connected to the drain of the twelfth PMOS transistor 310, the source of the twenty fifth NMOS transistor 402 is connected to the drain of the thirteenth PMOS transistor 401, and the source of the thirty first NMOS transistor 411 is connected to the drain of the sixteenth PMOS transistor 410;
the sources of the first PMOS transistor 101, the second PMOS transistor 104, the third PMOS transistor 107, the fourth PMOS transistor 110, the fifth PMOS transistor 201, the sixth PMOS transistor 204, the seventh PMOS transistor 207, the eighth PMOS transistor 210, the ninth PMOS transistor 301, the tenth PMOS transistor 304, the eleventh PMOS transistor 307, the twelfth PMOS transistor 310, the thirteenth PMOS transistor 401, the fourteenth PMOS transistor 404, the fifteenth PMOS transistor 407, and the sixteenth PMOS transistor 410 are all connected to the power supply voltage VDD;
The sources of the second NMOS transistor 103, the third NMOS transistor 105, the fourth NMOS transistor 106, the fifth NMOS transistor 108, the sixth NMOS transistor 109, the eighth NMOS transistor 112, the tenth NMOS transistor 203, the eleventh NMOS transistor 205, the twelfth NMOS transistor 206, the thirteenth NMOS transistor 208, the fourteenth NMOS transistor 209, the sixteenth NMOS transistor 212, the eighteenth NMOS transistor 303, the nineteenth NMOS transistor 305, the twenty-first NMOS transistor 306, the twenty-first NMOS transistor 308, the twenty-second NMOS transistor 309, the twenty-fourth NMOS transistor 312, the twenty-sixth NMOS transistor 403, the twenty-seventh NMOS transistor 405, the twenty-eighth NMOS transistor 406, the twenty-ninth NMOS transistor 408, the thirty-second NMOS transistor 409, and the thirty-second NMOS transistor 412 are all connected to the ground GND.
The input circuit includes a first transfer transistor 501, a second transfer transistor 502, a third transfer transistor 503, a fourth transfer transistor 504, a first transfer gate 505, a second transfer gate 506, a third transfer gate 507, and a fourth transfer gate 508; the signal inputs of the first transmission transistor 501, the second transmission transistor 502, the third transmission transistor 503, the fourth transmission transistor 504, the first transmission gate 505, the second transmission gate 506, the third transmission gate 507 and the fourth transmission gate 508 are connected to the input signal D, and the output ends are connected to the nodes N1, N5, N9, N13, Q, N6, N10 and N14, respectively; the input circuit is turned on when the clock signal clk=1, and turned off when the clock signal clk=0.
The node N1 is surrounded by the first NMOS transistor 102, the second NMOS transistor 103, and the first pass transistor 501, and is a non-sensitive node when the logic value of the node N1 is 0 (the node N1 will not flip when impacted by particles); the node N4 is surrounded 112 by a seventh NMOS tube 111 and an eighth NMOS tube, and is a non-sensitive node when the logic value of the node N4 is 0; the node N5 is surrounded by the ninth NMOS transistor 202, the tenth NMOS transistor 203, and the second pass transistor 502, and is a non-sensitive node when the logic value of the node N5 is 0; the node N8 is surrounded by a fifteenth NMOS transistor 211 and a sixteenth NMOS transistor 212, and is a non-sensitive node when the logic value of the node N8 is 0; the node N9 is surrounded by a seventeenth NMOS transistor 302, an eighteenth NMOS transistor 303, and a third pass transistor 503, and is a non-sensitive node when the logic value of the node N9 is 0; the node N12 is surrounded by a twenty-third NMOS transistor 311 and a twenty-fourth NMOS transistor 312, and is a non-sensitive node when the logic value of the node N12 is 0; the node N13 is surrounded by a twenty-fifth NMOS transistor 402, a twenty-sixth NMOS transistor 403, and a fourth pass transistor 504, and is a non-sensitive node when the logic value of the node N13 is 0; the node N16 is surrounded by a thirty-first NMOS transistor 411 and a thirty-second NMOS transistor 412, and is a non-sensitive node when the node N16 has a logic value of 0; when the latch works, four nodes are non-sensitive nodes, so that the number of sensitive nodes can be effectively reduced.
When the clock signal clk=1, the input circuit is turned on, the latch is in the transparent period, and the input signal is transmitted to the nodes N1, Q, N5, N6, N9, N10, N13 and N14 through the input circuit; when d=1 is input, the logic values of nodes N1, Q, N, N6, N9, N10, N13, and N14 are all 1, and drive the logic values of nodes N3, N4, N7, N8, N11, N12, N15, and N16 to 0; when d=0 is input, the logical values of nodes N1, Q, N, N6, N9, N10, N13, and N14 are all 0, and drive the logical values of nodes N3, N4, N7, N8, N11, N12, N15, and N16 to 1.
When the clock signal clk=0, the input circuit is turned off, the latch is in the latch period, and data is stored in the latch.
The self-recovery ability of the present invention for four-point flipping is analyzed as follows:
the latch consists of 4 cross interlocking units, each cross interlocking unit has 4 nodes and 16 nodes; when the latch works, each cross interlocking unit has a non-sensitive node which cannot be overturned, so that all four-point overturning conditions are classified into 4 types.
Case 1: one node in each of the four cross-interlocking units C1, C2, C3, C4 is flipped. When q=1, at this time, nodes N4, N8, N12, N16 are non-sensitive nodes, and the latch circuit transistor state is: the first PMOS transistor 101 is on, the first NMOS transistor 102 is on, the second NMOS transistor 103 is off, the second PMOS transistor 104 is on, the third NMOS transistor 105 is off, the fourth NMOS transistor 106 is off, the third PMOS transistor 107 is off, the fifth NMOS transistor 108 is on, the sixth NMOS transistor 109 is on, the fourth PMOS transistor 110 is off, the seventh NMOS transistor 111 is off, the eighth NMOS transistor 112 is on, the fifth PMOS transistor 201 is on, the ninth NMOS transistor 202 is on, the tenth NMOS transistor 203 is off, the sixth PMOS transistor 204 is on, the eleventh NMOS transistor 205 is off, the twelfth NMOS transistor 206 is off, the seventh PMOS transistor 207 is off, the thirteenth NMOS transistor 208 is on, the fourteenth NMOS transistor 209 is on, the eighth PMOS transistor 210 is off, the fifteenth NMOS transistor 211 is off, the sixteenth NMOS transistor 212 is on, the ninth PMOS transistor 301 is on seventeenth NMOS transistor 302 on, eighteenth NMOS transistor 303 off, tenth PMOS transistor 304 on, nineteenth NMOS transistor 305 off, twenty NMOS transistor 306 off, eleventh PMOS transistor 307 off, twenty first NMOS transistor 308 on, twenty second NMOS transistor 309 on, twelfth PMOS transistor 310 off, twenty third NMOS transistor 311 off, twenty fourth NMOS transistor 312 on, thirteenth PMOS transistor 401 on, twenty fifth NMOS transistor 402 on, twenty sixth NMOS transistor 403 off, fourteenth PMOS transistor 404 on, twenty seventh NMOS transistor 405 off, twenty eighth NMOS transistor 406 off, fifteenth PMOS transistor 407 off, twenty ninth NMOS transistor 408 on, thirty NMOS transistor 409 on, sixteenth PMOS transistor 410 off, thirty first NMOS transistor 411 off, thirty second NMOS transistor 412 on; taking the nodes N1, N6, N9, N14 as an example, when the nodes N1, N6, N9, N14 are turned over from the logic value 1 to the logic value 0, only the node N15 will be turned over from the logic value 0 to the logic value 1 because the fifteenth PMOS transistor 407 is turned on, the twenty-ninth NMOS transistor 408 is turned off, and the thirty-NMOS transistor 409 is turned off, and the rest of the nodes all maintain the correct logic value; node N1 is connected to VDD through the first PMOS tube 101, the first NMOS tube 102, the logic value is restored to 1, node N6 is connected to VDD through the sixth PMOS tube 204, the logic value is restored to 1, node N9 is connected to VDD through the ninth PMOS tube 301, the seventeenth NMOS tube 302, the logic value is restored to 1, node N14 is connected to VDD through the fourteenth PMOS tube 404, the logic value is restored to 1, then node N15 is connected to GND through the twenty-ninth NMOS tube 408, the thirty-first NMOS tube 409, the logic value is restored to 0, and all the flipped nodes are restored to the correct logic value.
Case 2: 2 nodes in the 1 cross interlocking units are overturned, and 1 node in the other 2 cross interlocking units is overturned; cross-interlocking units C2, C3, C4 are exemplified, respectively. When q=0, the nodes N1, N5, N9, N13 are non-sensitive nodes, and the latch circuit transistor states are: the first PMOS transistor 101 is turned off, the first NMOS transistor 102 is turned off, the second NMOS transistor 103 is turned on, the second PMOS transistor 104 is turned off, the third NMOS transistor 105 is turned on, the fourth NMOS transistor 106 is turned on, the third PMOS transistor 107 is turned on, the fifth NMOS transistor 108 is turned off, the sixth NMOS transistor 109 is turned off, the fourth PMOS transistor 110 is turned on, the seventh NMOS transistor 111 is turned on, the eighth NMOS transistor 112 is turned off, the fifth PMOS transistor 201 is turned off, the ninth NMOS transistor 202 is turned off, the tenth NMOS transistor 203 is turned on, the sixth PMOS transistor 204 is turned off, the eleventh NMOS transistor 205 is turned on, the twelfth NMOS transistor 206 is turned on, the seventh PMOS transistor 207 is turned on, the thirteenth NMOS transistor 208 is turned off, the fourteenth NMOS transistor 209 is turned off, the eighth PMOS transistor 210 is turned on, the fifteenth NMOS transistor 211 is turned on, the sixteenth NMOS transistor 212 is turned off, and the ninth PMOS transistor 301 is turned off seventeenth NMOS transistor 302 turns off, eighteenth NMOS transistor 303 turns on, tenth PMOS transistor 304 turns off, nineteenth NMOS transistor 305 turns on, twenty NMOS transistor 306 turns on, eleventh PMOS transistor 307 turns on, twenty first NMOS transistor 308 turns off, twenty second NMOS transistor 309 turns off, twelfth PMOS transistor 310 turns on, twenty third NMOS transistor 311 turns on, twenty fourth NMOS transistor 312 turns off, thirteenth PMOS transistor 401 turns off, twenty fifth NMOS transistor 402 turns off, twenty sixth NMOS transistor 403 turns on, fourteenth PMOS transistor 404 turns off, twenty seventh NMOS transistor 405 turns on, twenty eighth NMOS transistor 406 turns on, fifteenth PMOS transistor 407 turns on, twenty ninth NMOS transistor 408 turns off, thirty NMOS transistor 409 turns off, sixteenth PMOS transistor 410 turns on, thirty first NMOS transistor 411 turns on, thirty second NMOS transistor 412 turns off; taking the nodes N6, N7, N12, N16 as an example, when the node N6 is flipped from the logic value 0 to the logic value 1, the nodes N7, N12, N16 are flipped from the logic value 1 to the logic value 0, and the rest nodes all maintain the correct logic value; node N6 is connected to GND through eleventh NMOS tube 205, twelfth NMOS tube 206, the logic value is restored to 0, node N7 is connected to VDD through seventh PMOS tube 207, the logic value is restored to 1, node N12 is connected to VDD through twelfth PMOS tube 310, twenty-third NMOS tube 311, the logic value is restored to 1, node N16 is connected to VDD through sixteenth PMOS tube 410, thirty-first NMOS tube 411, the logic value is restored to 1, and all flipped nodes are restored to the correct logic value.
Case 3: two nodes in the two cross interlocking units are turned over respectively; taking cross-interlocking units C3, C4 as an example. When q=1, at this time, nodes N4, N8, N12, N16 are non-sensitive nodes, and the latch circuit transistor state is: the first PMOS transistor 101 is on, the first NMOS transistor 102 is on, the second NMOS transistor 103 is off, the second PMOS transistor 104 is on, the third NMOS transistor 105 is off, the fourth NMOS transistor 106 is off, the third PMOS transistor 107 is off, the fifth NMOS transistor 108 is on, the sixth NMOS transistor 109 is on, the fourth PMOS transistor 110 is off, the seventh NMOS transistor 111 is off, the eighth NMOS transistor 112 is on, the fifth PMOS transistor 201 is on, the ninth NMOS transistor 202 is on, the tenth NMOS transistor 203 is off, the sixth PMOS transistor 204 is on, the eleventh NMOS transistor 205 is off, the twelfth NMOS transistor 206 is off, the seventh PMOS transistor 207 is off, the thirteenth NMOS transistor 208 is on, the fourteenth NMOS transistor 209 is on, the eighth PMOS transistor 210 is off, the fifteenth NMOS transistor 211 is off, the sixteenth NMOS transistor 212 is on, the ninth PMOS transistor 301 is on seventeenth NMOS transistor 302 on, eighteenth NMOS transistor 303 off, tenth PMOS transistor 304 on, nineteenth NMOS transistor 305 off, twenty NMOS transistor 306 off, eleventh PMOS transistor 307 off, twenty first NMOS transistor 308 on, twenty second NMOS transistor 309 on, twelfth PMOS transistor 310 off, twenty third NMOS transistor 311 off, twenty fourth NMOS transistor 312 on, thirteenth PMOS transistor 401 on, twenty fifth NMOS transistor 402 on, twenty sixth NMOS transistor 403 off, fourteenth PMOS transistor 404 on, twenty seventh NMOS transistor 405 off, twenty eighth NMOS transistor 406 off, fifteenth PMOS transistor 407 off, twenty ninth NMOS transistor 408 on, thirty NMOS transistor 409 on, sixteenth PMOS transistor 410 off, thirty first NMOS transistor 411 off, thirty second NMOS transistor 412 on; taking the nodes N9, N10, N14 and N15 as examples, when the nodes N9, N10 and N14 are turned over from the logic value 1 to the logic value 0, the nodes N15 are turned over from the logic value 0 to the logic value 1, and the other nodes all keep the correct logic values; node N9 is connected to VDD through the ninth PMOS transistor 301, seventeenth NMOS transistor 302, the logic value is restored to 1, node N10 is connected to VDD through the tenth PMOS transistor 304, the logic value is restored to 1, node N14 is connected to VDD through the fourteenth PMOS transistor 404, the logic value is restored to 1, node N15 is connected to GND through the twenty-ninth NMOS transistor 408, thirty-NMOS transistor 409, the logic value is restored to 0, and all flipped nodes are restored to the correct logic value.
Case 4: 3 nodes in the 1 cross interlocking units are overturned, and 1 node in the other cross interlocking unit is overturned; taking cross-interlocking units C1, C2 as an example. When q=0, the nodes N1, N5, N9, N13 are non-sensitive nodes, and the latch circuit transistor states are: the first PMOS transistor 101 is turned off, the first NMOS transistor 102 is turned off, the second NMOS transistor 103 is turned on, the second PMOS transistor 104 is turned off, the third NMOS transistor 105 is turned on, the fourth NMOS transistor 106 is turned on, the third PMOS transistor 107 is turned on, the fifth NMOS transistor 108 is turned off, the sixth NMOS transistor 109 is turned off, the fourth PMOS transistor 110 is turned on, the seventh NMOS transistor 111 is turned on, the eighth NMOS transistor 112 is turned off, the fifth PMOS transistor 201 is turned off, the ninth NMOS transistor 202 is turned off, the tenth NMOS transistor 203 is turned on, the sixth PMOS transistor 204 is turned off, the eleventh NMOS transistor 205 is turned on, the twelfth NMOS transistor 206 is turned on, the seventh PMOS transistor 207 is turned on, the thirteenth NMOS transistor 208 is turned off, the fourteenth NMOS transistor 209 is turned off, the eighth PMOS transistor 210 is turned on, the fifteenth NMOS transistor 211 is turned on, the sixteenth NMOS transistor 212 is turned off, and the ninth PMOS transistor 301 is turned off seventeenth NMOS transistor 302 turns off, eighteenth NMOS transistor 303 turns on, tenth PMOS transistor 304 turns off, nineteenth NMOS transistor 305 turns on, twenty NMOS transistor 306 turns on, eleventh PMOS transistor 307 turns on, twenty first NMOS transistor 308 turns off, twenty second NMOS transistor 309 turns off, twelfth PMOS transistor 310 turns on, twenty third NMOS transistor 311 turns on, twenty fourth NMOS transistor 312 turns off, thirteenth PMOS transistor 401 turns off, twenty fifth NMOS transistor 402 turns off, twenty sixth NMOS transistor 403 turns on, fourteenth PMOS transistor 404 turns off, twenty seventh NMOS transistor 405 turns on, twenty eighth NMOS transistor 406 turns on, fifteenth PMOS transistor 407 turns on, twenty ninth NMOS transistor 408 turns off, thirty NMOS transistor 409 turns off, sixteenth PMOS transistor 410 turns on, thirty first NMOS transistor 411 turns on, thirty second NMOS transistor 412 turns off; taking the nodes N2, N3, N4, N8 as an example, when the node N2 is turned over from the logic value 0 to the logic value 1, and the nodes N3, N4, N8 are turned over from the logic value 1 to the logic value 0, only the node N1 will be turned over from the logic value 0 to the logic value 1 because the first PMOS transistor 101 is turned on, the first NMOS transistor 102 is turned on, and the second NMOS transistor 103 is turned off, and the other nodes all maintain the correct logic value; node N2 is connected to GND through third NMOS tube 105, fourth NMOS tube 106, the logic value is restored to 0, node N3 is connected to VDD through third PMOS tube 107, the logic value is restored to 1, node N4 is connected to VDD through fourth PMOS tube 110, seventh NMOS tube 111, the logic value is restored to 1, node N8 is connected to VDD through eighth PMOS tube 210, fifteenth NMOS tube 211, the logic value is restored to 1, then node N1 is connected to GND through second NMOS tube 103, the logic value is restored to 0, and all flip nodes are restored to the correct logic value.
In summary, it can be seen that the present invention can 100% tolerate the situation that any 4 internal nodes are flipped at the same time, and restore all flipped nodes to the correct logical value. The structure of the invention effectively reduces the number of sensitive nodes and uses fewer transistors, so the structure is a four-point flip self-recovery latch with low cost compared with the structure with smaller power consumption and area cost.
Claims (4)
1. A low-overhead four-point flip-flop self-recovery latch based on cross interlocking comprises a latch circuit formed by cross connection of 4 cross interlocking units and having 16 internal nodes, and an input circuit formed by 4 transmission gates and 4 transmission transistors; the input ends of the 4 transmission gates and the 4 transmission transistors are commonly connected with input signals, and the output ends of the 4 transmission gates and the input ends of the 4 transmission transistors are connected with 8 internal nodes of the latch circuit; in the transparent period, each transmission gate and each transmission transistor are conducted, and input signals are transmitted into 8 internal nodes and output through an output node Q; during the lock-in period, the 4 transmission gates and the 4 transmission transistors are turned off, and data is stored in the latch circuit.
2. A low overhead four-point flip-flop self-restoral latch based on cross-interlocking as defined by claim 1, wherein: the latch circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube sixteenth NMOS transistor, seventeenth NMOS transistor, eighteenth NMOS transistor, nineteenth NMOS transistor, twenty-first NMOS transistor, twenty-second NMOS transistor, twenty-third NMOS transistor, twenty-fourth NMOS transistor, twenty-fifth NMOS transistor, twenty-sixth NMOS transistor, twenty-seventh NMOS transistor, twenty-eighth NMOS transistor, twenty-ninth NMOS transistor, thirty-first NMOS transistor, thirty-second NMOS transistor, node N1, node Q, node N3, node N4, node N5, node N6, node N7, node N8, node N9, node N10, node N11, node N12, node N13, node N14, node N15, node N16;
The node N1 is respectively connected with the grid electrode of the fourth PMOS tube, the grid electrode of the eighth NMOS tube, the grid electrode of the twenty-first NMOS tube, the grid electrode of the thirty-NMOS tube, the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube;
the node Q is respectively connected with the grid electrode of the first NMOS tube, the grid electrode of the seventh PMOS tube, the drain electrode of the second PMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube;
the node N3 is respectively connected with the grid electrode of the seventh NMOS tube, the grid electrode of the sixth PMOS tube, the drain electrode of the third PMOS tube, the drain electrode of the fifth NMOS tube and the drain electrode of the sixth NMOS tube;
the node N4 is respectively connected with the grid electrode of the first PMOS tube, the grid electrode of the second NMOS tube, the grid electrode of the twenty-seventh NMOS tube, the grid electrode of the seventh NMOS tube and the drain electrode of the eighth NMOS tube;
the node N5 is respectively connected with the grid electrode of the eighth PMOS tube, the grid electrode of the sixteenth NMOS tube, the grid electrode of the fifth NMOS tube, the grid electrode of the twenty-second NMOS tube, the drain electrode of the ninth NMOS tube and the drain electrode of the tenth NMOS tube;
The node N6 is respectively connected with the grid electrode of the ninth NMOS tube, the grid electrode of the fifteenth PMOS tube, the drain electrode of the sixth PMOS tube, the drain electrode of the eleventh NMOS tube and the drain electrode of the twelfth NMOS tube;
the node N7 is respectively connected with the grid electrode of the fifteenth NMOS tube, the grid electrode of the fourteenth PMOS tube, the drain electrode of the seventh PMOS tube, the drain electrode of the thirteenth NMOS tube and the drain electrode of the fourteenth NMOS tube;
the node N8 is respectively connected with the grid electrode of the fifth PMOS tube, the grid electrode of the tenth NMOS tube, the grid electrode of the third NMOS tube, the grid electrode of the nineteenth NMOS tube, the drain electrode of the fifteenth NMOS tube and the drain electrode of the sixteenth NMOS tube;
the node N9 is respectively connected with the grid electrode of the twelfth PMOS tube, the grid electrode of the twenty-fourth NMOS tube, the grid electrode of the thirteenth NMOS tube, the grid electrode of the twenty-ninth NMOS tube, the drain electrode of the seventeenth NMOS tube and the drain electrode of the eighteenth NMOS tube;
the node N10 is respectively connected with the grid electrode of the seventeenth NMOS tube, the grid electrode of the third PMOS tube, the drain electrode of the tenth PMOS tube, the drain electrode of the nineteenth NMOS tube and the drain electrode of the twentieth NMOS tube;
The node N11 is respectively connected with the grid electrode of the twenty-third NMOS tube, the grid electrode of the second PMOS tube, the drain electrode of the eleventh PMOS tube, the drain electrode of the twenty-first NMOS tube and the drain electrode of the twenty-second NMOS tube;
the node N12 is respectively connected with the grid electrode of the ninth PMOS tube, the grid electrode of the eighteenth NMOS tube, the grid electrode of the eleventh NMOS tube, the grid electrode of the twenty eighth NMOS tube, the drain electrode of the twenty third NMOS tube and the drain electrode of the twenty fourth NMOS tube;
the node N13 is respectively connected with the grid electrode of the sixteenth PMOS tube, the grid electrode of the thirty-second NMOS tube, the grid electrode of the sixth NMOS tube, the grid electrode of the fourteenth NMOS tube, the drain electrode of the twenty-fifth NMOS tube and the drain electrode of the twenty-sixth NMOS tube;
the node N14 is respectively connected with the grid electrode of the twenty-fifth NMOS tube, the grid electrode of the eleventh PMOS tube, the drain electrode of the fourteenth PMOS tube, the drain electrode of the twenty-seventh NMOS tube and the drain electrode of the twenty-eighth NMOS tube;
the node N15 is respectively connected with the grid electrode of the thirty-first NMOS tube, the grid electrode of the tenth PMOS tube, the drain electrode of the fifteenth PMOS tube, the drain electrode of the twenty-ninth NMOS tube and the drain electrode of the thirty-NMOS tube;
The node N16 is respectively connected with the grid electrode of the thirteenth PMOS tube, the grid electrode of the twenty-sixth NMOS tube, the grid electrode of the fourth NMOS tube, the grid electrode of the twelfth NMOS tube, the drain electrode of the thirty-first NMOS tube and the drain electrode of the thirty-second NMOS tube;
the source electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the seventh NMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the ninth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the source electrode of the fifteenth NMOS tube is connected with the drain electrode of the eighth PMOS tube, the source electrode of the seventeenth NMOS tube is connected with the drain electrode of the ninth PMOS tube, the source electrode of the twenty third NMOS tube is connected with the drain electrode of the twelfth PMOS tube, the source electrode of the twenty fifth NMOS tube is connected with the drain electrode of the thirteenth PMOS tube, and the source electrode of the thirty first NMOS tube is connected with the drain electrode of the sixteenth PMOS tube;
the sources of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube are all connected with the power supply voltage VDD;
The sources of the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the eighth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube, the fourteenth NMOS tube, the sixteenth NMOS tube, the eighteenth NMOS tube, the nineteenth NMOS tube, the twenty-first NMOS tube, the twenty-second NMOS tube, the twenty-fourth NMOS tube, the twenty-sixth NMOS tube, the twenty-seventh NMOS tube, the twenty-eighth NMOS tube, the twenty-ninth NMOS tube, the thirty-second NMOS tube are all connected with the ground GND.
3. A low overhead four-point flip-flop self-restoral latch based on cross-interlocking as defined by claim 1, wherein: the input circuit comprises a first transmission transistor, a second transmission transistor, a third transmission transistor, a fourth transmission transistor, a first transmission gate, a second transmission gate, a third transmission gate and a fourth transmission gate, wherein the signal input ends of the first transmission transistor, the second transmission transistor, the third transmission transistor, the fourth transmission transistor, the first transmission gate, the second transmission gate, the third transmission gate and the fourth transmission gate are connected with an input signal D, and the output ends of the first transmission transistor, the second transmission transistor, the third transmission transistor, the fourth transmission transistor, the first transmission gate, the second transmission gate, the third transmission gate and the fourth transmission gate are respectively connected with nodes N1, N5, N9, N13, Q, N6, N10 and N14; the input circuit is turned on when the clock signal clk=1, and turned off when the clock signal clk=0.
4. A low overhead four-point flip-flop self-restoral latch based on cross-interlocking as defined by claim 1, wherein: the node N1 is surrounded by a first NMOS tube, a second NMOS tube and a first transmission transistor, and is a non-sensitive node when the logic value of the node N1 is 0; the node N4 is surrounded by a seventh NMOS tube and an eighth NMOS tube, and is a non-sensitive node when the logic value of the node N4 is 0; the node N5 is surrounded by a ninth NMOS tube, a tenth NMOS tube and a second transmission transistor, and is a non-sensitive node when the logic value of the node N5 is 0; the node N8 is surrounded by a fifteenth NMOS tube and a sixteenth NMOS tube, and is a non-sensitive node when the logic value of the node N8 is 0; the node N9 is surrounded by a seventeenth NMOS tube, an eighteenth NMOS tube and a third transmission transistor, and is a non-sensitive node when the logic value of the node N9 is 0; the node N12 is surrounded by a twenty-third NMOS tube and a twenty-fourth NMOS tube, and is a non-sensitive node when the logic value of the node N12 is 0; the node N13 is surrounded by a twenty-fifth NMOS tube, a twenty-sixth NMOS tube and a fourth transmission transistor, and is a non-sensitive node when the logic value of the node N13 is 0; the node N16 is surrounded by a thirty-first NMOS tube and a thirty-second NMOS tube, and is a non-sensitive node when the logic value of the node N16 is 0; when the latch works, four nodes are non-sensitive nodes, so that the number of sensitive nodes is effectively reduced;
When q=1 of the latch, four nodes of N4, N8, N12, N16 are non-sensitive nodes; when q=0, four nodes of N1, N5, N9, and N13 are non-sensitive nodes.
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| CN202311119821.2A CN117200753A (en) | 2023-09-01 | 2023-09-01 | Low-overhead four-point flip self-recovery latch based on cross interlocking |
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| CN202311119821.2A CN117200753A (en) | 2023-09-01 | 2023-09-01 | Low-overhead four-point flip self-recovery latch based on cross interlocking |
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