CN117199152B - Solar cell and preparation method thereof - Google Patents
Solar cell and preparation method thereof Download PDFInfo
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- CN117199152B CN117199152B CN202311167535.3A CN202311167535A CN117199152B CN 117199152 B CN117199152 B CN 117199152B CN 202311167535 A CN202311167535 A CN 202311167535A CN 117199152 B CN117199152 B CN 117199152B
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000003466 welding Methods 0.000 claims abstract description 78
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 229910000679 solder Inorganic materials 0.000 claims description 22
- 238000010438 heat treatment Methods 0.000 claims description 14
- 238000003475 lamination Methods 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 claims description 11
- 238000003825 pressing Methods 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910000831 Steel Inorganic materials 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 3
- 239000010959 steel Substances 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052709 silver Inorganic materials 0.000 abstract description 6
- 239000004332 silver Substances 0.000 abstract description 6
- 238000001035 drying Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052761 rare earth metal Inorganic materials 0.000 description 2
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 description 1
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 description 1
- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003345 natural gas Substances 0.000 description 1
- 239000003209 petroleum derivative Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Photovoltaic Devices (AREA)
Abstract
The invention discloses a solar cell and a preparation method thereof, which belong to the technical field of solar cells and comprise a silicon wafer and a plurality of rows of auxiliary grids, wherein the same row of auxiliary grids consists of a long positive electrode auxiliary grid and a short negative electrode auxiliary grid or consists of a long negative electrode auxiliary grid and a short positive electrode auxiliary grid; the adjacent two rows of auxiliary grids are respectively provided with a long positive auxiliary grid and a long negative auxiliary grid; the short negative electrode auxiliary grid is provided with a negative electrode main grid region in the length direction of the auxiliary grid and the long negative electrode auxiliary grid at the corresponding position; the short positive electrode auxiliary grid is provided with a positive electrode main grid area in the length direction of the auxiliary grid and a long positive electrode auxiliary grid at a corresponding position; the negative electrode main gate regions and the positive electrode main gate regions are alternately arranged; PAD points are distributed between the cathode main gate region and the anode main gate region. By the design of the long and short auxiliary grids, a positive main grid region and a negative main grid region are respectively formed at the short positive auxiliary grid and the short negative auxiliary grid, and connecting wires are not printed in the main grid regions, so that silver paste can be saved; meanwhile, due to the arrangement of the short positive electrode auxiliary grid and the short negative electrode auxiliary grid, poor welding short circuit can be prevented.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a solar cell and a preparation method thereof.
Background
Under the background that global climate is warming, renewable energy sources such as petroleum and natural gas are increasingly scarce and the like are increasingly severe, new energy development is urgent, and solar energy is an inexhaustible clean energy source. The improvement of photoelectric conversion efficiency is the key point of solar technology, and the back contact solar technology is to print the front grid line and the electrode of the battery on the back through a special technical means, so that the positive and negative electrodes are arranged alternately on the back of the battery. The technology can effectively improve the efficiency of the solar cell, so that the solar cell is more attractive, and meanwhile, the technology is compatible with PERC, TOPCON, HJT and other technologies.
The back of the existing back contact battery is transversely crossed with the positive electrode fine grid 101 and the negative electrode fine grid 201, the positive electrode main grid 100 and the negative electrode main grid 200 are longitudinally crossed, insulating glue is printed at the crossed position of the positive electrode and the negative electrode fine grid 201, insulating glue is printed at the crossed position of the negative electrode and the positive electrode fine grid 101, as shown in fig. 1, pad points 300 are arranged on the length directions of the positive electrode main grid 100 and the negative electrode main grid 200, the back of a battery piece faces upwards during welding, tin-lead welding strips are paved right above the positive electrode and the negative electrode, the welding strips are pressed by spring pressing pins, and welding is realized by heating an infrared lamp tube. This structure has the following problems: (1) When the placement position of the welding strip is deviated, the welding strip contacts with the insulation area to damage the insulation adhesive, so that short circuit is caused; (2) The infrared welding temperature is higher, the single-sided welding is caused by the larger deviation of the thermal expansion coefficients of the tin-lead welding strip and the battery piece, the battery piece after welding has serious warping, and hidden cracking is caused during lamination; (3) The battery piece warpage has stress, and follow-up subassembly is in outdoor use, has the failure risk because factors such as high low temperature is alternate, moisture.
In view of this, the present inventors have conducted intensive studies in response to this need, and have made the present invention.
Disclosure of Invention
In order to solve the problems that in the prior art, when the placement position of a welding strip on the back of a back contact battery is deviated, insulating glue is damaged to cause short circuit, a battery piece is seriously warped after welding the welding strip, hidden cracks are caused during lamination, the battery piece is warped to cause stress, failure risks exist in the outdoor use process, and the like, the invention provides a back contact battery which is a screen BC battery, and comprises a silicon wafer, a plurality of rows of auxiliary grids which are arranged on the back of the silicon wafer in a first direction, wherein each row of auxiliary grids is alternately provided with positive auxiliary grids and negative auxiliary grids which are arranged at intervals along the length direction of the auxiliary grids; the positive electrode auxiliary grid comprises a long positive electrode auxiliary grid and a short positive electrode auxiliary grid, and the negative electrode auxiliary grid comprises a long negative electrode auxiliary grid and a short negative electrode auxiliary grid;
The auxiliary grids in the same row consist of a long anode auxiliary grid and a short cathode auxiliary grid, or consist of a long cathode auxiliary grid and a short anode auxiliary grid; a long positive electrode auxiliary grid and a long negative electrode auxiliary grid are respectively arranged on the auxiliary grids of two adjacent rows; all the short negative electrode auxiliary grids are provided with more than one negative electrode main grid region in the length direction of the auxiliary grid and the long negative electrode auxiliary grid at the corresponding position, and a plurality of short negative electrode auxiliary grids on each negative electrode main grid region are distributed along a first direction perpendicular to the length direction of the auxiliary grid; all the short positive electrode auxiliary grids are provided with more than one positive electrode main grid region in the length direction of the auxiliary grid and the long positive electrode auxiliary grids at corresponding positions, and a plurality of short positive electrode auxiliary grids on each positive electrode main grid region are distributed along a first direction; and the negative electrode main gate regions and the positive electrode main gate regions are alternately arranged in the length direction of the auxiliary gate.
Negative electrode main grid PAD points are distributed in the middle of the negative electrode main grid region along the first direction, and positive electrode main grid PAD points are distributed in the middle of the positive electrode main grid region along the first direction.
By the design of the long and short auxiliary grids, a positive main grid region and a negative main grid region are respectively formed at the short positive auxiliary grid and the short negative auxiliary grid, and connecting wires are not printed in the main grid regions, so that silver paste can be saved; meanwhile, due to the arrangement of the short positive electrode auxiliary grid and the short negative electrode auxiliary grid, poor welding short circuit can be prevented.
Preferably, the width of the auxiliary grid is 10-30um, and the height is 10-15um.
Preferably, the number of PAD points is at least 6, wherein the number of the negative electrode main gate PAD points and the positive electrode main gate PAD points is 3, the widths of the negative electrode main gate PAD points and the positive electrode main gate PAD points are 80-120um, the lengths of the negative electrode main gate PAD points and the positive electrode main gate PAD points are 60-80um, and the thicknesses of the negative electrode main gate PAD points and the positive electrode main gate PAD points are 3-10um; the heights of the negative electrode main grid PAD point and the positive electrode main grid PAD point are not lower than the height of the auxiliary grid.
An insulating region is formed between the short negative electrode auxiliary gate and the long positive electrode auxiliary gate at intervals on two sides of the negative electrode main gate region; an insulating region is formed between the short positive electrode auxiliary gate and the long negative electrode auxiliary gate at intervals on two sides of the positive electrode main gate region; and the distance between the PAD point of the negative electrode main gate and the end points of the two ends of the short negative electrode auxiliary gate is 50-100um, and the distance between the PAD point of the positive electrode main gate and the end points of the two ends of the short positive electrode auxiliary gate is 50-100um, so that the short circuit caused by the connection between the positive electrode and the negative electrode auxiliary gate and the connection between the negative electrode and the positive electrode auxiliary gate due to the deviation of welding strips can be avoided, meanwhile, carriers in a breakpoint area can be collected by the short auxiliary gate, and the efficiency loss is reduced.
Preferably, solder paste with the width of 60-100um and the thickness of 5-10um is printed between the PAD point of the negative electrode main gate and the position right below the PAD point of the positive electrode main gate and the surface of the silicon wafer;
Solder paste with the thickness of 3-5um, the width of 10-30um and the length of 80-120um is printed between the PAD point of the negative electrode main grid, the position right below the PAD point of the positive electrode main grid and the auxiliary grid, and the purpose of the solder paste printing is to enhance the welding tension at the fine grid and improve the reliability of the assembly.
Preferably, the cathode main grid region is welded with a welding strip along the length direction thereof, and the anode main grid region is welded with a welding strip along the length direction thereof; and the welding band width is 60-100um and the thickness is 200-270um. The low-temperature conductive welding strip is paved at the middle position of the PAD point, the welding strip mainly comprises tin, lead, bismuth, silver and rare earth elements according to a certain proportion, the local heating uniformity of the laser spot welding is good, the welding is only carried out at the PAD point, the welding strip in the non-welding area has a telescopic space, the warping of a battery piece caused by single-sided welding can be greatly reduced, and the conduction EL imaging can be realized.
Preferably, the negative electrode main gate regions and the positive electrode main gate regions are alternately arranged along a second direction perpendicular to the first direction, and distances from the negative electrode main gate regions to adjacent two positive electrode main gate regions are equal.
The invention also provides a preparation method of the screen BC battery, which comprises the following steps:
step one, printing an auxiliary grid on the back surface of a silicon wafer;
Printing solder paste on a negative electrode main grid PAD point of a negative electrode main grid area of the silicon wafer and on a positive electrode main grid PAD point of a positive electrode main grid area; printing solder paste on all auxiliary grid positions right below the PAD point of the negative electrode main grid and the PAD point of the positive electrode main grid by using a steel mesh;
Step three, after the solder paste is dried, paving a welding strip right above a positive electrode main grid area and a negative electrode main grid area of the silicon wafer, pressing the welding strip by using a pressing net, and carrying out local rapid heating welding on a PAD point area by adopting a laser spot welding technology;
and fourthly, heating by a laminating machine to fuse the welding strip at the non-PAD point with the auxiliary grid to form alloy.
In the second step, the solder paste is dried by an infrared lamp tube heating furnace, wherein the drying temperature is 170-240 ℃ and the drying time is 15-60 seconds;
Preferably, in the third step, the laser spot welding technology is adopted to locally and rapidly heat and weld the PAD point area, the welding temperature is 200-240 ℃, the welding time is 1-3s, and the laser local spot welding can prevent welding warpage and hidden cracking.
Preferably, in the fourth step, the lamination temperature is set to 145-155 ℃, the lamination pressure is divided into three sections, the first section of pressure is 10-20kp and the holding time is 10-30s, the second section of pressure is 40-50kp and the holding time is 10-30s, the third section of pressure is 70-80kp and the holding time is 600-800s, and the lamination temperature and the lamination pressure are utilized in the lamination process to enable the low-temperature conductive welding strip and the auxiliary grid to form an alloy.
The beneficial effects are that:
the technical scheme of the invention has the following beneficial effects:
(1) By the design of the long and short auxiliary grids, a positive main grid region and a negative main grid region are respectively formed at the short positive auxiliary grid and the short negative auxiliary grid, and connecting wires are not printed in the main grid regions, so that silver paste can be saved.
(2) The distance between the PAD point of the negative electrode main gate and the end point of the short negative electrode auxiliary gate is 50-100um, the distance between the PAD point of the positive electrode main gate and the end point of the short positive electrode auxiliary gate is 50-100um, the short circuit caused by the connection between the positive electrode and the negative electrode auxiliary gate and the connection between the negative electrode and the positive electrode auxiliary gate due to the deviation of welding strips can be avoided, meanwhile, the short auxiliary gate can collect carriers in a breakpoint area, and the efficiency loss is reduced.
(3) The low-temperature conductive welding strip is paved at the middle position of the PAD point and is welded only at the PAD point, the welding strip in the non-welding area has a telescopic space, the warping of the battery piece caused by single-sided welding can be greatly reduced, and the conduction EL imaging can be realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art back side structure of a BC battery;
FIG. 2 is a schematic view of the back side structure of a BC battery in accordance with the preferred embodiment of the present invention;
FIG. 3 is a flow chart of a preferred BC battery manufacturing process in accordance with the present invention.
In the figure, 1, a silicon wafer; 2. an auxiliary grid; 21. a positive electrode auxiliary grid; 211. a long positive electrode secondary grid; 212. short positive electrode secondary grid; 22. a negative electrode auxiliary grid; 221. a long negative electrode auxiliary grid; 222. short negative electrode auxiliary grid; 3. a negative electrode main gate region; 31. a negative electrode main grid PAD point; 4. a positive electrode main grid PAD point;
41. positive main gate PAD point.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, based on the embodiments of the invention, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the invention.
According to the invention, through the design of the long and short auxiliary grids, a positive main grid region and a negative main grid region are respectively formed on the short positive auxiliary grid and the short negative auxiliary grid, and no connecting line is printed on the main grid region, so that silver paste can be saved; meanwhile, due to the arrangement of the short positive electrode auxiliary grid and the short negative electrode auxiliary grid, poor welding short circuit can be prevented. The specific technical scheme is as follows:
As shown in fig. 2, a screen BC battery comprises a silicon wafer 1, and a plurality of rows of auxiliary grids 2 arranged on the back surface of the silicon wafer 1 in a first direction, wherein each row of auxiliary grids 2 is alternately provided with positive electrode auxiliary grids 21 and negative electrode auxiliary grids 22 which are arranged at intervals along the length direction; the positive electrode sub-gate 21 includes a long positive electrode sub-gate 211 and a short positive electrode sub-gate 212, and the negative electrode sub-gate 22 includes a long negative electrode sub-gate 221 and a short negative electrode sub-gate 222;
The auxiliary grid 2 in the same row consists of a long positive auxiliary grid 211 and a short negative auxiliary grid 222 or consists of a long negative auxiliary grid 221 and a short positive auxiliary grid 212; a long positive electrode auxiliary grid 211 and a long negative electrode auxiliary grid 221 are respectively arranged on the auxiliary grids 2 of two adjacent rows; all the short negative electrode auxiliary grids 222 are provided with more than one negative electrode main grid region 3 in the length direction of the auxiliary grid 2 and the long negative electrode auxiliary grids 221 at corresponding positions, and a plurality of short negative electrode auxiliary grids 222 on each negative electrode main grid region 3 are arranged along a first direction perpendicular to the length direction of the auxiliary grid 2; all the short positive electrode auxiliary grids 212 are formed with more than one positive electrode main grid region 4 in the length direction of the auxiliary grid 2 and the long positive electrode auxiliary grids 211 at corresponding positions, and a plurality of short positive electrode auxiliary grids 212 on each positive electrode main grid region 4 are arranged along the first direction; and the negative electrode main gate regions 3 and the positive electrode main gate regions 4 are alternately arranged in the length direction of the sub-gate 2.
Negative main gate PAD dots 31 are arranged in the first direction in the middle of the negative main gate region 3, and positive main gate PAD dots 41 are arranged in the first direction in the middle of the positive main gate region 4.
As a preferred embodiment, the width of the auxiliary grid 2 is 10-30um and the height is 10-15um.
The number of PAD points is at least 6, wherein 3 are respectively a negative electrode main grid PAD point 31 and a positive electrode main grid PAD point 41, the widths of the negative electrode main grid PAD point 31 and the positive electrode main grid PAD point 41 are 80-120um, the lengths are 60-80um, and the thicknesses are 3-10um; the heights of the negative electrode main gate PAD point 31 and the positive electrode main gate PAD point 41 are not lower than the height of the sub gate 2.
An insulating region 5 is formed between the short negative electrode auxiliary gate 222 and the long positive electrode auxiliary gate 211 at intervals on two sides of the negative electrode main gate region 3; an insulating region 5 is formed between the short positive electrode auxiliary gate 212 and the long negative electrode auxiliary gate 221 at intervals on two sides of the positive electrode main gate region 4; and the distance between the PAD point 31 of the negative electrode main gate and the PAD point 31 of the negative electrode main gate corresponds to the distance between the end points of the two ends of the short negative electrode auxiliary gate 222 by 50-100um, and the distance between the PAD point 41 of the positive electrode main gate and the PAD point 41 of the positive electrode auxiliary gate 212 by 50-100um, so that the short circuit caused by the connection between the positive electrode and the negative electrode auxiliary gate and the connection between the negative electrode and the positive electrode auxiliary gate due to the deviation of welding strips can be avoided, and meanwhile, the short auxiliary gate can collect carriers in the breakpoint area, thereby reducing the efficiency loss.
As a preferred embodiment, solder paste with a width of 60-100um and a thickness of 5-10um is printed between the PAD point 31 of the negative electrode main gate and the PAD point 41 of the positive electrode main gate and the surface of the silicon wafer 1;
Solder paste with the thickness of 3-5um, the width of 10-30um and the length of 80-120um is printed between the positive electrode main grid PAD point 31, the right lower part of the positive electrode main grid PAD point 41 and the auxiliary grid 2, and the purpose of the solder paste printing is to enhance the welding tension at the fine grid and improve the reliability of the assembly.
As a preferred embodiment, the cathode main gate region 3 is welded with a welding strip (not shown) along its length direction, and the anode main gate region 4 is welded with a welding strip along its length direction; and the welding band width is 60-100um and the thickness is 200-270um. The low-temperature conductive welding strip is paved at the middle position of the PAD point, the welding strip mainly comprises tin, lead, bismuth, silver and rare earth elements according to a certain proportion, the local heating uniformity of the laser spot welding is good, the welding is only carried out at the PAD point, the welding strip in the non-welding area has a telescopic space, the warping of a battery piece caused by single-sided welding can be greatly reduced, and the conduction EL imaging can be realized.
As a preferred embodiment, the negative electrode main gate regions 3 and the positive electrode main gate regions 4 are alternately arranged in a second direction perpendicular to the first direction, and distances from the negative electrode main gate regions 3 to adjacent two of the positive electrode main gate regions 4 are equal.
The embodiment also provides a preparation method of the screen BC battery, which comprises the following steps:
Step S101, printing an auxiliary grid on the back surface of a silicon wafer;
step S102, printing solder paste on a negative electrode main grid PAD point of a negative electrode main grid area and a positive electrode main grid PAD point of a positive electrode main grid area of a silicon wafer; printing solder paste on all auxiliary grid positions right below the PAD point of the negative electrode main grid and the PAD point of the positive electrode main grid by using a steel mesh;
step S103, after the solder paste is dried, paving a welding strip right above a positive electrode main grid area and a negative electrode main grid area of the silicon wafer, pressing the welding strip by using a pressing net, and carrying out local rapid heating welding on a PAD point area by adopting a laser spot welding technology;
And step S104, heating by using a laminating machine to fuse the welding strip at the non-PAD point and the auxiliary grid to form an alloy.
In the step S102, the solder paste is dried by an infrared lamp tube heating furnace, wherein the drying temperature is 170-240 ℃ and the drying time is 15-60S;
Preferably, in step S103, the laser spot welding technology is adopted to perform local rapid heating welding in the PAD point region, the welding temperature is 200-240 ℃, the welding time is 1-3S, and the laser local spot welding can prevent welding warpage and hidden cracking.
Preferably, in step S104, the lamination temperature is set to 145-155 ℃, the lamination pressure is divided into three sections, the first section of pressure is 10-20kp, the holding time is 10-30S, the second section of pressure is 40-50kp, the holding time is 10-30S, the third section of pressure is 70-80kp, and the holding time is 600-800S, and the lamination temperature and the pressure are utilized in the lamination process to enable the low-temperature conductive welding strip and the auxiliary grid to form an alloy.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. The solar cell is characterized by comprising a silicon wafer and a plurality of rows of auxiliary grids arranged in the first direction on the back surface of the silicon wafer, wherein each row of auxiliary grids is alternately provided with positive electrode auxiliary grids and negative electrode auxiliary grids which are arranged at intervals along the length direction of the auxiliary grids; the positive electrode auxiliary grid comprises a long positive electrode auxiliary grid and a short positive electrode auxiliary grid, and the negative electrode auxiliary grid comprises a long negative electrode auxiliary grid and a short negative electrode auxiliary grid;
The auxiliary grids in the same row consist of a long anode auxiliary grid and a short cathode auxiliary grid, or consist of a long cathode auxiliary grid and a short anode auxiliary grid; a long positive electrode auxiliary grid and a long negative electrode auxiliary grid are respectively arranged on the auxiliary grids of two adjacent rows; all the short negative electrode auxiliary grids are provided with more than one negative electrode main grid region in the length direction of the auxiliary grid and the long negative electrode auxiliary grid at the corresponding position, and a plurality of short negative electrode auxiliary grids on each negative electrode main grid region are distributed along a first direction perpendicular to the length direction of the auxiliary grid; all the short positive electrode auxiliary grids are provided with more than one positive electrode main grid region in the length direction of the auxiliary grid and the long positive electrode auxiliary grids at corresponding positions, and a plurality of short positive electrode auxiliary grids on each positive electrode main grid region are distributed along a first direction; the negative electrode main gate regions and the positive electrode main gate regions are alternately arranged in the length direction of the auxiliary gate;
Negative main grid PAD points are distributed in the middle of the negative main grid region along the first direction, and positive main grid PAD points are distributed in the middle of the positive main grid region along the first direction;
The width of the negative electrode main grid PAD point and the positive electrode main grid PAD point is 80-120um, the length is 60-80um, and the thickness is 3-10um; the heights of the negative electrode main grid PAD point and the positive electrode main grid PAD point are not lower than the height of the auxiliary grid;
An insulating region is formed between the short negative electrode auxiliary gate and the long positive electrode auxiliary gate at intervals on two sides of the negative electrode main gate region; an insulating region is formed between the short positive electrode auxiliary gate and the long negative electrode auxiliary gate at intervals on two sides of the positive electrode main gate region; and the distance between the PAD point of the negative electrode main gate and the end point of the short negative electrode auxiliary gate is 50-100um, and the distance between the PAD point of the positive electrode main gate and the end point of the short positive electrode auxiliary gate is 50-100um.
2. A solar cell according to claim 1, wherein the sub-grid has a width of 10-30um and a height of 10-15um.
3. The solar cell according to claim 1, wherein solder paste with the width of 60-100um and the thickness of 5-10um is printed between the PAD point of the negative electrode main gate and the PAD point of the positive electrode main gate and the surface of the silicon wafer;
Solder paste with thickness of 3-5um, width of 10-30um and length of 80-120um is printed between the PAD point of the negative electrode main gate, the PAD point of the positive electrode main gate and the auxiliary gate.
4. The solar cell of claim 1, wherein the negative main grid region is welded with a solder strip along its length direction and the positive main grid region is welded with a solder strip along its length direction; and the welding band width is 60-100um and the thickness is 200-270um.
5. A solar cell according to claim 1, wherein the negative main gate regions and the positive main gate regions are alternately arranged in a second direction perpendicular to the first direction, and the distances from the negative main gate regions to adjacent two of the positive main gate regions are equal.
6. A method of manufacturing a solar cell according to any one of claims 1 to 5, comprising the steps of:
step one, printing an auxiliary grid on the back surface of a silicon wafer;
Printing solder paste on a negative electrode main grid PAD point of a negative electrode main grid area of the silicon wafer and on a positive electrode main grid PAD point of a positive electrode main grid area; printing solder paste on all auxiliary grid positions right below the PAD point of the negative electrode main grid and the PAD point of the positive electrode main grid by using a steel mesh;
Step three, after the solder paste is dried, paving a welding strip right above a positive electrode main grid area and a negative electrode main grid area of the silicon wafer, pressing the welding strip by using a pressing net, and carrying out local rapid heating welding on a PAD point area by adopting a laser spot welding technology;
and fourthly, heating by a laminating machine to fuse the welding strip at the non-PAD point with the auxiliary grid to form alloy.
7. The method of manufacturing a solar cell according to claim 6, wherein in the second step, the solder paste is dried by an infrared lamp tube heating furnace at 170-240 ℃ for 15-60s.
8. The method for manufacturing a solar cell according to claim 6, wherein in the third step, a laser spot welding technology is adopted to perform local rapid heating welding in a PAD point area, the welding temperature is 200-240 ℃, and the welding time is 1-3s.
9. The method according to claim 6, wherein in the fourth step, the lamination temperature is set to 145-155 ℃, the lamination pressure is divided into three steps, the first step is 10-20kp, the holding time is 10-30s, the second step is 40-50kp, the holding time is 10-30s, the third step is 70-80kp, and the holding time is 600-800s.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311167535.3A CN117199152B (en) | 2023-09-11 | 2023-09-11 | Solar cell and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311167535.3A CN117199152B (en) | 2023-09-11 | 2023-09-11 | Solar cell and preparation method thereof |
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| Publication Number | Publication Date |
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| CN117199152A CN117199152A (en) | 2023-12-08 |
| CN117199152B true CN117199152B (en) | 2024-06-04 |
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| CN202311167535.3A Active CN117199152B (en) | 2023-09-11 | 2023-09-11 | Solar cell and preparation method thereof |
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