CN117199145B - High-capacitance-ratio super-abrupt variable-capacitance diode and preparation method thereof - Google Patents
High-capacitance-ratio super-abrupt variable-capacitance diode and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000003247 decreasing effect Effects 0.000 claims abstract description 10
- 238000009826 distribution Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 207
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000011241 protective layer Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 125000004437 phosphorous atom Chemical group 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 5
- -1 boron ions Chemical class 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 230000002441 reversible effect Effects 0.000 abstract description 10
- 239000004065 semiconductor Substances 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 7
- 230000002829 reductive effect Effects 0.000 description 7
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- 230000000694 effects Effects 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
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- 238000005468 ion implantation Methods 0.000 description 1
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
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Abstract
The invention belongs to the technical field of semiconductor devices and provides a high-capacitance-ratio abrupt varactor and a preparation method thereof, wherein the high-capacitance-ratio abrupt varactor comprises an N+ type silicon substrate, an N-type epitaxial layer, an oxide layer, a silicon nitride layer, a front metal layer and a back metal layer, wherein the N-type epitaxial layer is arranged on the N+ type silicon substrate; the N-type epitaxial layer is arranged on the N-type epitaxial layer, the doping concentration of the N-type epitaxial layer is larger than that of the N-type epitaxial layer, and the doping concentration from the N-type epitaxial layer to the N-type epitaxial layer is in gradient decreasing distribution; the oxide layer is arranged on the N-type epitaxial layer, and a window is etched on the oxide layer; forming a plurality of P-type doped regions on the N-type epitaxial layer and the N-type epitaxial layer based on the window; the silicon nitride layer is arranged on the oxide layer; the front metal layer is arranged on the silicon nitride layer; the back metal layer is arranged under the N+ type silicon substrate. The invention ensures that the ultra-abrupt varactor has high variation rate of the width of the depletion layer under the reverse bias, thereby having high capacitance ratio.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a high capacitance ratio hyperabrupt varactor and a preparation method thereof.
Background
The varactor diode generates a transitional capacitance effect under reverse bias voltage by utilizing the depletion layer width between PN junctions, realizes a variable junction capacitance value, and is widely applied to circuits such as high-frequency tuning, communication, radio and the like. With the improvement of the working frequency of the radio frequency semiconductor device, the application of the 2G to 5G network ensures that the input and output signals in the communication circuit have higher frequency matching and wider frequency spectrum range, thereby meeting the requirements of stable, secret and designability of channels between communication. Varactors are widely appreciated in the field of radio frequency communications because they can be integrated directly with other active semiconductor devices to protect other devices in the circuit from voltage surges.
The conventional varactor is manufactured by using single-layer epitaxy, and only using ion implantation to change doping concentration, wherein most regions are in the same resistivity range, so that after reverse bias is applied, the width of a local space charge region is widened too slowly, and the change of capacitance ratio is not obvious enough. Second, the P region is single in structure, usually only a circular or rectangular window is used, and the volume is large, but the specific surface area is small, so that the junction capacitance value is too small under zero bias. These disadvantages severely limit the capacitance ratio of the varactor, which requires greater frequency tuning capability in circuits with broader spectral operating ranges in the 5G era.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a high capacitance ratio variable capacitance diode and a preparation method thereof, so as to solve the problem that the capacitance ratio change is not obvious due to the adoption of single-layer epitaxy of the current diode.
In a first aspect, the present invention provides a high capacitance ratio variable varactor, comprising:
An n+ type silicon substrate;
The N-type epitaxial layer is arranged on the N+ type silicon substrate;
The N-type epitaxial layer is arranged on the N-type epitaxial layer, the doping concentration of the N-type epitaxial layer is larger than that of the N-type epitaxial layer, and the doping concentration from the N-type epitaxial layer to the N-type epitaxial layer is in gradient decreasing distribution;
The oxide layer is arranged on the N-type epitaxial layer, and a window is etched on the oxide layer; forming a plurality of P-type doped regions on the N-type epitaxial layer and the N-type epitaxial layer based on the window;
The silicon nitride layer is arranged on the oxide layer;
The front metal layer is arranged on the silicon nitride layer;
And the back metal layer is arranged below the N+ type silicon substrate.
According to the technical scheme, the high capacitance ratio variable capacitance diode provided by the invention has the advantages that the double-layer doping concentration N-type epitaxial layer and the N-type epitaxial layer form gradient doping, the variation difference of the width of the depletion layers in different PN junction areas is large after back pressure is applied, and the capacitance ratio is improved; the P-type doped region structure of the multiple grooves enables the PN junction to have large specific surface area under zero bias, and the PN junction is equivalent to a circuit with a plurality of capacitors connected in parallel, so that the initial junction capacitance is very high.
Optionally, the thickness of the N-type epitaxial layer is smaller than that of the N-type epitaxial layer, and the resistivity of the N-type epitaxial layer is 1-10The resistivity of the N-type epitaxial layer is 0.1-1/>。
According to the technical scheme, the N-type epitaxial layer controls the withstand voltage of the hyperabrupt varactor; the doping concentration of the N-type epitaxial layer is larger than that of the N-type epitaxial layer, phosphorus atoms can be diffused into the N-type epitaxial layer under high-temperature nitrogen, and the doping concentration is reduced, so that the doping concentration is gradually decreased from the N-type epitaxial layer to the N-type epitaxial layer, the ultra-abrupt varactor is enabled to have high capacitance ratio under reverse bias, and the width change rate of a depletion layer is high.
Optionally, each two of the P-type doped regions are a group, and the first spacing distance of the P-type doped regions in each groupLess than the second spacing distance/>, of two adjacent different sets of P-type doped regions。
According to the technical scheme, the two P-type doped regions are arranged in a group of intermittent mode, so that when the width of the space charge region is increased to a certain range, the two potential barrier regions are combined into one depletion layer, the distance equivalent to the distance of the conductive polar plate is increased, the equivalent is that local capacitance is connected in series, the capacitance is rapidly reduced, and the capacitance ratio is further increased.
Optionally, the thickness of the oxide layer is 1-2um, and the thickness of the silicon nitride layer is 300-500nm.
According to the technical scheme, the thicker passivation layer is arranged, so that the electric field force can be balanced, and the reliability of the device is enhanced.
Optionally, the front metal layer and the P-type doped region form an ohmic contact, and the back metal layer contacts with the n+ type silicon substrate to form a metal electrode.
Optionally, the front metal layer comprises a first barrier layer, a first middle layer and a first protective layer which are sequentially arranged from bottom to top; the back metal layer comprises a second barrier layer, a second middle layer and a second protective layer which are sequentially arranged from top to bottom.
In a second aspect, the present invention provides a method for preparing a variable varactor with high capacitance ratio, which includes:
S1, sequentially preparing an N-type epitaxial layer and an N-type epitaxial layer on an N+ type silicon substrate, wherein the doping concentration of the N-type epitaxial layer is greater than that of the N-type epitaxial layer;
S2, under the high temperature of nitrogen, phosphorus atoms are diffused from the N-type epitaxial layer to the N-type epitaxial layer and are distributed in a gradient decreasing manner;
s3, growing an oxide layer on the N-type epitaxial layer;
S4, photoetching and etching the oxide layer to form a window, and injecting boron ions into the window to form a P-type doped region;
S5, depositing a silicon nitride layer on the oxide layer, and removing the silicon nitride on the P-type doped region by dry etching;
s6, depositing the front metal layer on the silicon nitride layer and the P-type doped region;
S7, sputtering a back metal layer on the bottom of the N+ type silicon substrate.
By adopting the technical scheme, the application has the following technical effects:
The doping concentration from the N-type epitaxial layer to the N-type epitaxial layer is in gradient decreasing distribution, so that gradient phosphorus atom self-doping is realized, the depletion layer width change rate is high under the reverse bias of the high capacitance ratio hyperabrupt varactor, and the varactor has high capacitance ratio;
2. The multiple P-type doped regions are structured, so that the P-type doped regions have high depth-to-width ratio, the specific surface area is increased while the volume is reduced, the area of a depletion layer is increased, the parallel circuit is equivalent to a plurality of capacitors under zero bias, and the initial junction capacitance is far more than that of a conventional varactor;
The 3.P doped regions are distributed intermittently in two groups at equal intervals, when the back pressure is added to a certain value, two adjacent junction capacitances are combined into a space charge region, the distance between the conductive polar plates is increased, and the capacitance ratio of zero bias voltage to high reverse bias voltage is further increased, wherein the serial circuit is equivalent to a local capacitance.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. Like elements or portions are generally identified by like reference numerals throughout the several figures. In the drawings, elements or portions thereof are not necessarily drawn to scale.
Fig. 1 is a schematic diagram of a high capacitance ratio variable varactor according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of a method for manufacturing a high capacitance ratio variable varactor according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram of an article obtained in step S1 according to a second embodiment of the present invention;
FIG. 4 is a schematic diagram of an article obtained in step S3 according to a second embodiment of the present invention;
FIG. 5 is a schematic diagram of an article obtained in step S4 according to a second embodiment of the present invention;
FIG. 6 is a schematic diagram of an article obtained in step S5 according to a second embodiment of the present invention;
FIG. 7 is a schematic view of an article obtained in step S6 according to a second embodiment of the present invention;
FIG. 8 is a graph showing the doping concentration of a high capacitance ratio variable varactor diode according to a first embodiment of the present invention;
fig. 9 is a graph showing the capacitance comparison between a high capacitance ratio variable varactor and a conventional varactor according to a first embodiment of the present invention.
Reference numerals:
A 1-n+ type silicon substrate; a 2-N-type epitaxial layer; a 3-N type epitaxial layer; a 4-oxide layer; a 5-P type doped region; a 6-silicon nitride layer; 7-a front side metal layer; 8-backside metal layer.
Detailed Description
Embodiments of the technical scheme of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and thus are merely examples, and are not intended to limit the scope of the present invention.
It is noted that unless otherwise indicated, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs.
In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "vertical," "horizontal," "top," "bottom," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. In the description of the present invention, the meaning of "plurality" is two or more unless specifically defined otherwise.
In the present application, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
Example 1
As shown in fig. 1, the present embodiment provides a high capacitance ratio variable varactor, which includes an n+ type silicon substrate 1, an N-type epitaxial layer 2, an N-type epitaxial layer 3, an oxide layer 4, a silicon nitride layer 6, a front metal layer 7 and a back metal layer 8, wherein the N-type epitaxial layer 2 is disposed on the n+ type silicon substrate 1; the N-type epitaxial layer 3 is arranged on the N-type epitaxial layer 2, the doping concentration of the N-type epitaxial layer 3 is larger than that of the N-type epitaxial layer 2, and the doping concentrations of the N-type epitaxial layer 3 to the N-type epitaxial layer 2 are distributed in a gradient decreasing manner; the oxide layer 4 is arranged on the N-type epitaxial layer 3, and a window is etched on the oxide layer 4; forming a plurality of P-type doped regions 5 on the N-type epitaxial layer 3 and the N-type epitaxial layer 2 based on the windows; the silicon nitride layer 6 is arranged on the oxide layer 4; the front metal layer 7 is arranged on the silicon nitride layer 6; the back metal layer 8 is provided under the n+ type silicon substrate 1.
Specifically, the double-layer doping concentration N-type epitaxial layer 2 and the N-type epitaxial layer 3 form gradient doping, the variation difference of the width of depletion layers of different PN junction areas is large after back pressure is applied, and the capacitance ratio is improved; the P-type doped region 5 structure of the multiple grooves enables the PN junction to have large specific surface area under zero bias, and the PN junction is equivalent to a circuit with a plurality of capacitors connected in parallel, so that the initial junction capacitance is very high.
Optionally, the thickness of the N-type epitaxial layer 3 is smaller than that of the N-type epitaxial layer 2, and the resistivity of the N-type epitaxial layer 2 is 1-10The resistivity of the N-type epitaxial layer 3 is 0.1-1/>. The N-type epitaxial layer 2 controls the withstand voltage of the hyperabrupt varactor; the doping concentration of the N-type epitaxial layer 3 is larger than that of the N-type epitaxial layer 2, phosphorus atoms can be diffused into the N-type epitaxial layer 2 under high-temperature nitrogen, and the doping concentration is reduced, so that the doping concentration is distributed in a gradient decreasing manner from the N-type epitaxial layer 3 to the N-type epitaxial layer 2, and the depletion layer width of the ultra-abrupt varactor is rapid in change rate under reverse bias, so that the ultra-abrupt varactor has a high capacitance ratio.
Optionally, each two P-type doped regions 5 are formed as a group, and the P-type doped regions 5 in each group are spaced apart by a first distanceLess than the second separation distance/>, of two adjacent different sets of P-type doped regions 5. The P-type doped region 5 extends from the N-type epitaxial layer 3 to the N-type epitaxial layer 2, and multiple layers of N-epitaxy with different concentrations are used to obtain doped epitaxy with linear distribution, parabolic distribution, equi-discrete distribution and gaussian distribution so as to improve the junction capacitance ratio under reverse bias, and the grooves forming the P-type doped region 5 can be cylindrical or rectangular. And a plurality of windows are arranged to increase the number of the P-type doped regions 5, so as to increase the specific surface area of the PN junction and obtain higher zero bias capacitance.
The two P-type doped regions 5 are arranged in a group of intermittent mode, so that when the width of the space charge region is increased to a certain range, two potential barrier regions are combined into a depletion layer, the distance equivalent to the distance of a conductive polar plate is increased, the equivalent is that local capacitors are connected in series, the capacitance is rapidly reduced, and the capacitance ratio is further increased.
Alternatively, the thickness of the oxide layer 4 is 1-2um, the thickness of the silicon nitride layer 6 is 300-500nm, and the electric field force can be balanced and the reliability of the device can be enhanced by arranging a thicker passivation layer.
Optionally, the front metal layer 7 and the P-type doped region 5 form an ohmic contact, and the back metal layer 8 contacts the n+ type silicon substrate 1 to form a metal electrode. In one possible embodiment, the front metal layer 7 includes a first barrier layer, a first intermediate layer, and a first protective layer disposed in order from bottom to top; the back metal layer 8 includes a second barrier layer, a second intermediate layer, and a second protective layer, which are disposed in this order from top to bottom.
Referring to fig. 8 and 9, fig. 8 shows a phosphorus doping concentration comparison graph of the high capacitance ratio variable varactor diode and the conventional varactor diode provided by the present invention, and fig. 9 shows a capacitance ratio comparison graph of the high capacitance ratio variable varactor diode and the conventional varactor diode provided by the present invention; wherein (a) and (c) are schematic curves of the variable capacitance diode with high capacitance ratio, and (b) and (d) are schematic curves of the conventional variable capacitance diode. Under reverse bias, the capacitance ratio of the variable capacitance diode with the high capacitance ratio provided by the embodiment is remarkably improved, and the variable capacitance diode with the high capacitance ratio has higher zero bias capacitance.
The technical scheme in the embodiment of the application at least has the following technical effects:
1. the double-layer doping concentration N-type epitaxial layer 2 and the N-type epitaxial layer 3 form gradient doping, the variation difference of the width of depletion layers of different PN junction areas is large after back pressure is applied, and the capacitance ratio is improved;
the high aspect ratio of the P-doped region 5, the structure of the P-doped region 5 with multiple trenches enables the specific surface area of the PN junction to be large under zero bias, which is equivalent to a circuit with a plurality of capacitors connected in parallel, and enables the initial junction capacitance to be high under zero bias.
3. The arrangement mode of the two grooves is that the grooves in the two grooves are arranged in a group, so that the grooves in the two grooves are close in distance, the capacitors are connected in series under a certain reverse bias voltage, the capacitance value is reduced, the grooves in the two grooves are far away, the capacitors cannot suddenly drop, and a more controllable and freely-adjustable frequency spectrum is achieved.
Example 2
As shown in fig. 2, the present embodiment provides a method for manufacturing a variable varactor with high capacitance ratio, which includes:
S1, as shown in FIG. 3, an N-type epitaxial layer 2 and an N-type epitaxial layer 3 are sequentially prepared on an N+ type silicon substrate 1, and the doping concentration of the N-type epitaxial layer 3 is larger than that of the N-type epitaxial layer 2.
S2, under the high temperature of nitrogen, phosphorus atoms are diffused from the N-type epitaxial layer 3 to the N-type epitaxial layer 2 and are distributed in a gradient decreasing mode.
S3, as shown in FIG. 4, growing an oxide layer 4 on the N-type epitaxial layer 3; the oxide layer 4 is formed by introducing oxygen at 900-1100 ℃ and growing on the N-type epitaxial layer 3 in a dry oxygen oxidation mode, and the thickness of the oxide layer 4 is 1-2 mu m.
S4, as shown in FIG. 5, forming a window on the oxide layer 4 by photoetching, and implanting boron ions into the window to form a P-type doped region 5.
Optionally, a plurality of rectangular windows are formed on the oxide layer 4 by photolithography and etching, and boron ions are implanted to form a P-type doped region 5. And (3) carrying out rapid thermal annealing, wherein silicon atoms fall off to form vacancies, boron atoms enter the crystal lattice to generate covalent bonds, and the interstitial atoms form substitutional atoms which are 3% -5% of the implanted boron ions, and a thin oxygen layer is generated on the surface.
The trench morphology of different P-type doped regions 5 and different doping depth-to-width ratios can greatly influence the junction capacitance value, and the difference of arrangement structures can lead to the series connection of regional junction capacitances, so that the capacitance is effectively reduced, and the capacitance ratio is improved.
Meanwhile, oxygen atoms and silicon atoms react on the P-type doped region 5 and the oxide layer 4 to form a thin oxygen layer, but the growth speed of the thin oxygen layer on the oxide layer 4 is faster than that of the P-type doped region 5 due to the barrier of the oxide layer 4.
S5, as shown in FIG. 6, depositing a silicon nitride layer 6 with the thickness of 300-500nm on the oxide layer 4 in a PECVD mode, and removing the silicon nitride on the P-type doped region 5 by dry etching; and dry etching is carried out again to remove the thin oxygen layer, so that the contact between the subsequent front metal layer 7 and the P-type doped region 5 is facilitated.
The thin oxygen layer removed in step S5 mainly refers to the thin oxygen layer on the P-type doped region 5, and the thickness of the thin oxygen layer grown thereon is very thin due to the blocking of the oxide layer 4.
S6, as shown in FIG. 7, a front metal layer 7 is deposited on the silicon nitride layer 6 and the P-type doped region 5 through an evaporation table, ohmic contact is formed between the front metal layer 7 and the P-type doped region 5, and the front metal layer 7 is sequentially provided with a blocking layer, an intermediate layer and a protective layer from bottom to top.
S7, as shown in FIG. 1, sputtering a back metal layer 8 on the bottom of the N+ type silicon substrate 1 to form electrode communication; the back metal layer 8 is a barrier layer, an intermediate layer and a protective layer in sequence from top to bottom.
In the description of the present invention, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention, and are intended to be included within the scope of the appended claims and description.
Claims (7)
1. A high capacitance ratio hyperabrupt varactor, comprising:
An n+ type silicon substrate;
The N-type epitaxial layer is arranged on the N+ type silicon substrate;
The N-type epitaxial layer is arranged on the N-type epitaxial layer, the doping concentration of the N-type epitaxial layer is larger than that of the N-type epitaxial layer, and the doping concentration from the N-type epitaxial layer to the N-type epitaxial layer is in gradient decreasing distribution;
The oxide layer is arranged on the N-type epitaxial layer, and a window is etched on the oxide layer; forming a plurality of P-type doped regions on the N-type epitaxial layer and the N-type epitaxial layer based on the window; every two P-type doped regions are a group, and the first interval distance of the P-type doped regions in each group Less than the second spacing distance/>, of two adjacent different sets of P-type doped regions；
The silicon nitride layer is arranged on the oxide layer;
The front metal layer is arranged on the silicon nitride layer and the P-type doped region, and ohmic contact is formed between the front metal layer and the P-type doped region;
And the back metal layer is arranged below the N+ type silicon substrate.
2. The high capacitance ratio hyperabrupt varactor of claim 1, wherein the N-type epitaxial layer has a thickness less than the N-type epitaxial layer, the N-type epitaxial layer having a resistivity of 1-10The resistivity of the N-type epitaxial layer is 0.1-1/>。
3. The hyperabrupt varactor of claim 1, wherein the P-doped region has a widthFrom 0.1 to 10 μm, said first separation distance/>From 0.1 to 10 μm, said separation distance/>10-30 Μm.
4. The hyperabrupt varactor of claim 1, wherein the oxide layer has a thickness of 1-2um and the silicon nitride layer has a thickness of 300-500nm.
5. The hyperabrupt varactor of claim 1, wherein the back metal layer contacts an n+ silicon substrate to form a metal electrode.
6. The hyperabrupt varactor of claim 5, wherein the front side metal layer comprises a first barrier layer, a first middle layer, and a first protective layer disposed in sequence from bottom to top; the back metal layer comprises a second barrier layer, a second middle layer and a second protective layer which are sequentially arranged from top to bottom.
7. A method for preparing a high capacitance ratio abrupt varactor, comprising:
S1, sequentially preparing an N-type epitaxial layer and an N-type epitaxial layer on an N+ type silicon substrate, wherein the doping concentration of the N-type epitaxial layer is greater than that of the N-type epitaxial layer;
S2, under the high temperature of nitrogen, phosphorus atoms are diffused from the N-type epitaxial layer to the N-type epitaxial layer and are distributed in a gradient decreasing manner;
s3, growing an oxide layer on the N-type epitaxial layer;
S4, photoetching and etching the oxide layer to form a window, and injecting boron ions into the window to form a P-type doped region;
S5, depositing a silicon nitride layer on the oxide layer, and removing the silicon nitride on the P-type doped region by dry etching;
s6, depositing the front metal layer on the silicon nitride layer and the P-type doped region;
S7, sputtering a back metal layer on the bottom of the N+ type silicon substrate.
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| RU165025U1 (en) * | 2016-02-11 | 2016-09-27 | Акционерное общество "Научно-исследовательский институт полупроводниковых приборов" (АО "НИИПП") | VARICAP WITH AN INCREASED COVERAGE FACTOR |
| CN115483104A (en) * | 2022-10-28 | 2022-12-16 | 西安微电子技术研究所 | Manufacturing method of variable capacitance diode |
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| US7253073B2 (en) * | 2004-01-23 | 2007-08-07 | International Business Machines Corporation | Structure and method for hyper-abrupt junction varactors |
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| KR20010046433A (en) * | 1999-11-12 | 2001-06-15 | 김충환 | Variable capacitance diode and method for fabricating the same |
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| RU165025U1 (en) * | 2016-02-11 | 2016-09-27 | Акционерное общество "Научно-исследовательский институт полупроводниковых приборов" (АО "НИИПП") | VARICAP WITH AN INCREASED COVERAGE FACTOR |
| CN115483104A (en) * | 2022-10-28 | 2022-12-16 | 西安微电子技术研究所 | Manufacturing method of variable capacitance diode |
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