CN117199109A - Insulated gate bipolar transistor and manufacturing method thereof - Google Patents
Insulated gate bipolar transistor and manufacturing method thereof Download PDFInfo
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- CN117199109A CN117199109A CN202210617417.7A CN202210617417A CN117199109A CN 117199109 A CN117199109 A CN 117199109A CN 202210617417 A CN202210617417 A CN 202210617417A CN 117199109 A CN117199109 A CN 117199109A
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Abstract
The application provides an insulated gate bipolar transistor and a manufacturing method thereof. The insulated gate bipolar transistor includes: a collector region having opposed first and second surfaces; at least one doped region, wherein each doped region is contacted with the first surface, and a plurality of doped regions are arranged at intervals; the drift region is positioned at one side of the doped region, which is far away from the collector region, and is provided with a third surface, which is far away from the doped region, and the doping concentration of the doped region is higher than that of the drift region; at least one super junction penetrating into the drift region along the third surface, wherein a part of the drift region is located between the doped region and the super junction, the drift region and the doped region are of a first doping type, and the super junction and the collector region are of a second doping type. By arranging the doped region below the super junction, the current tailing phenomenon in the turn-off process of the transistor is improved, the turn-off energy loss of the transistor is effectively reduced, and the reliability of the device is greatly improved.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to an insulated gate bipolar transistor and a manufacturing method thereof.
Background
The insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) is a compound full-control voltage driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOS), has the advantages of high input impedance of the MOSFET and low conduction voltage drop of the GTR, namely, small driving power and reduced saturation voltage, and is very suitable for being applied to the fields of variable current systems with 600V and above of direct current voltage, such as alternating current motors, frequency converters, switching power supplies, lighting circuits, traction transmission and the like.
When the IGBT is conducted, a large amount of holes are injected into the drift region by the emitting region and the collector region, so that the conductivity of the device is increased, and the conduction loss is reduced. However, when the IGBT is turned off, a large amount of injected holes cannot quickly eliminate carriers, so that a current tailing phenomenon is formed, and a large turn-off energy loss exists in the IGBT.
Disclosure of Invention
The application mainly aims to provide an insulated gate bipolar transistor and a manufacturing method thereof, which are used for solving the problem of larger turn-off energy loss of an IGBT in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided an insulated gate bipolar transistor comprising: a collector region having opposed first and second surfaces; at least one doped region, wherein each doped region is contacted with the first surface, and a plurality of doped regions are arranged at intervals; the drift region is positioned at one side of the doped region, which is far away from the collector region, and is provided with a third surface, which is far away from the doped region, and the doping concentration of the doped region is higher than that of the drift region; at least one super junction penetrating into the drift region along the third surface, wherein a part of the drift region is located between the doped region and the super junction, the drift region and the doped region are of a first doping type, and the super junction and the collector region are of a second doping type.
Further, the doping concentration of the doped region increases along a first direction, wherein the first direction is a direction in which the third surface points to the first surface.
Further, the doped region is at least partially located between the superjunction and the collector region.
Further, the projection of the doped region onto the first surface coincides with the first surface.
Further, the superjunction extends in the first direction.
Further, the method further comprises the following steps: the second doped region is positioned between the collector region and the doped region, and the second doped region is of a second doping type.
According to another aspect of the present application, there is provided a method for manufacturing an insulated gate bipolar transistor, comprising the steps of: providing a substrate; forming at least one doped region on one side of a substrate; forming a drift region on one side of the doped region far away from the substrate, wherein the drift region is provided with a third surface far away from the doped region, and the doping concentration of the doped region is higher than that of the drift region; forming at least one super junction in the drift region, wherein the super junction penetrates into the drift region along the third surface, and part of the drift region is positioned between the doped region and the super junction; and forming a collector region on one side of the substrate far away from the drift region, wherein the collector region is provided with a first surface and a second surface which are opposite, and the doped region is in contact with the first surface, wherein the drift region and the doped region are of a first doping type, and the super junction and the collector region are of a second doping type.
Further, the step of forming the doped region includes: a doped region is formed on one side of the substrate using a vapor phase epitaxy process.
Further, the step of forming the superjunction includes: a patterned mask plate is arranged on the third surface of the drift region, and a super junction is formed in the drift region based on the patterned mask plate; or forming a patterned mask layer on the third surface of the drift region, forming a super junction based on the patterned mask layer, and removing the patterned mask layer.
Further, the method further comprises the following steps: growing an epitaxial layer on the third surface; and forming an emission region in the epitaxial layer, wherein the doping type of the emission region is the same as that of the collector region.
By applying the technical scheme of the application, the insulated gate bipolar transistor comprises a collector region, at least one doped region, a drift region and at least one super junction, wherein the collector region is provided with a first surface and a second surface which are opposite, each doped region is in contact with the first surface, a plurality of doped regions are arranged at intervals, the drift region is positioned at one side of the doped region far away from the collector region, the drift region is provided with a third surface far away from the doped region, the doping concentration of the doped region is higher than that of the drift region, the super junction penetrates into the drift region along the third surface, part of the drift region is positioned between the doped region and the super junction, the drift region and the doped region are of a first doping type, and the super junction and the collector region are of a second doping type. Through setting up the doped region in the below of super junction, can reduce the forward turn-on voltage of transistor to set up this doped region and contact with the collector region, reduced the hole quantity that the collector region gushes into the drift region, and then can reduce the memory space of minority carrier in the drift region, improve the current tailing phenomenon, thereby reduce IGBT device shutoff energy loss.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
fig. 1 shows a schematic structural diagram of an embodiment of an insulated gate bipolar transistor according to an embodiment of the present application;
fig. 2 is a schematic cross-sectional view of a substrate after forming a doped region and a drift region in a method for forming an insulated gate bipolar transistor according to an embodiment of the present application;
FIG. 3 shows a schematic cross-sectional view of the substrate after forming a deep trench in the drift region shown in FIG. 2;
FIG. 4 shows a schematic cross-sectional view of the body after formation of a super junction in the drift region shown in FIG. 3;
fig. 5 shows a schematic cross-sectional view of the substrate after forming an epitaxial layer on the third surface of the drift region shown in fig. 4;
FIG. 6 shows a schematic cross-sectional view of the substrate after forming a gate trench in the epitaxial layer shown in FIG. 5;
FIG. 7 is a schematic cross-sectional view of the substrate after forming a gate oxide and gate electrode in the gate trench shown in FIG. 6;
FIG. 8 shows a schematic cross-sectional view of the substrate after forming a doped well in the epitaxial layer shown in FIG. 7;
FIG. 9 shows a schematic cross-sectional view of the substrate after formation of an emitter region in the epitaxial layer shown in FIG. 8;
fig. 10 shows a schematic cross-sectional view of the substrate after forming a dielectric layer and an emitter metal on the side of the epitaxial layer shown in fig. 9 remote from the drift region;
FIG. 11 shows a schematic cross-sectional view of the substrate of FIG. 10 after forming a collector region on a side of the substrate away from the drift region;
fig. 12 shows a schematic cross-sectional view of the substrate after forming collector metal on the side of the collector region away from the drift region shown in fig. 11.
Wherein the above figures include the following reference numerals:
1. a substrate; 2. a drift region; 3. a super junction; 4. an epitaxial layer; 5. a gate oxide layer; 6. a gate; 7. doping the well; 8. an emission region; 9. a dielectric layer; 10. an emitter metal; 11. a collector region; 12. a collector metal; 13. a doped region; 101. patterning the mask layer; 102. a deep groove; 104. and a gate groove.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As mentioned in the background art, when the IGBT is turned on, the collector region injects a large amount of holes into the drift region to increase the conductivity of the device and reduce the on loss, and, conversely, when the device is turned off, the large amount of holes injected into the drift region cannot be quickly eliminated, thereby causing a current tailing phenomenon, and causing a large turn-off energy loss of the IGBT.
In order to solve the above-mentioned problems, the present inventors propose an insulated gate bipolar transistor, as shown in fig. 1, comprising a collector region 11, at least one doped region 13, a drift region 2 and at least one super junction 3, wherein the collector region 11 has a first surface and a second surface opposite to each other, the doped region 13 is in contact with the first surface of the collector region 11, the doped regions 13 are spaced apart, the drift region 2 is located at a side of the doped region 13 away from the collector region 11, the drift region 2 has a third surface away from the doped region 13, the doping concentration of the doped region 13 is higher than the doping concentration of the drift region 2, the super junction 3 penetrates into the drift region 2 along the third surface, and a portion of the drift region 2 is located between the doped region 13 and the super junction 3, wherein the drift region 2 and the doped region 13 are of a first doping type, and the super junction 3 and the collector region 11 are of a second doping type.
In the transistor, the doped region 13 which is in contact with the collector region 11 is added on the first surface of the collector region 11, so that holes entering the drift region 2 through the collector region 11 in the on process of the device can be blocked, the number of holes entering the drift region 2 is reduced, the minority carrier storage amount in the hole drift region 2 is further reduced, the time for existence of tailing current in the device is shortened, the current tailing phenomenon of the transistor in the off process is improved, and the off energy loss of the transistor can be effectively reduced.
In some alternative embodiments, the doping concentration of the doped region 13 is higher than the doping concentration of the drift region 2, and further alternatively, the doping concentration of the doped region 13 is 1 order to 4 orders of magnitude higher than the doping concentration of the drift region 2, and an exemplary doping concentration of the doped region 13 is 1×10 20 /cm 3 The doping concentration of the drift region 2 is 1×10 16 /cm 3 Up to 1X 10 19 /cm 3 。
In some alternative embodiments, the doping concentration of the doped region 13 increases in a first direction, wherein the first direction is the direction in which the third surface points to the first surface, i.e. the doping concentration of the doped region 13 decreases in a gradient in a direction away from the collector region 11, and the average doping concentration of the doped region 13 is 1×10 16 /cm 3 The doping concentration of the doped region 13 near the collector region 11 is higher than 1×10 16 /cm 3 While the doping concentration of the doped region 13 on the side remote from the collector region 11 is lower than 1×10 16 /cm 3 . By setting the doping concentration gradient of the doping region 13, a part of holes can be blocked from entering the drift region 2 at the side close to the collector region 11, a phenomenon of current tailing in the transistor turn-off process caused by storing a large amount of hole carriers in the drift region 2 is avoided, and the doping concentration at the side far away from the collector region 11 is set relatively low, so that holes can enter the drift region 2 from the collector region 11 through the doping region 13, the turn-on efficiency of the transistor can be improved, and the turn-on loss of the transistor is reduced.
The doped region 13 is at least partially located between the superjunction 3 and the collector region 11, and in some alternative embodiments, the projection of the doped region 13 onto the first surface of the collector region 11 coincides with the first surface. That is, the doped region 13 may be a continuous doped region that completely covers the first surface of the collector region 11, and the width of the doped region 13 in the vertical first direction corresponds to the width of the first surface of the collector region 11. The arrangement mode of completely overlapping the first surface of the collector region 11 can enable holes entering the drift region 2 from the collector region 11 to be blocked in a large area, is beneficial to reducing the number of carriers existing in the drift region 2 of the transistor, further reduces the tailing current and shortens the time of the tailing current, thereby improving the current tailing phenomenon in the switching-off process of the transistor and effectively reducing the switching-off energy loss of the transistor.
In some alternative embodiments, the doped regions 13 are a plurality of doped regions disposed on the first surface of the collector region 11 at intervals, and since the doped regions 13 are doped with high concentration, the doped regions can reduce the resistivity of the transistor in the on state of the transistor, thereby reducing the on loss of the transistor, and correspondingly, the forward on voltage of the transistor can be increased, and by the manner of interval disposition, the forward on voltage of the transistor can be reduced, and the reliability of the transistor device can be improved.
In some alternative embodiments, the super-junction extends in the first direction, such that the drain-to-source on-resistance, gate capacitance, output charge, and die size of the device are reduced at the same time, such that the device has lower on-loss.
In some alternative embodiments, an insulated gate bipolar transistor further comprises a second doped region formed by implanting a second doping type into the substrate 1, the second doped region being located between the collector region and the doped region, the doping concentration of the second doped region being smaller than the doping concentration of the collector region 11, for example, when the doping concentration of the second doped region is 1×10 17 /cm 3 In this case, the doping concentration of the collector region 11 may be 1×10 18 /cm 3 Or 1X 10 19 /cm 3 . Wherein, the second doping region and the collector region 11 are both of the second doping type, and the conduction loss of the device can be reduced by forming the second doping type between the collector region and the doped region, thereby improving the reliability of the device.
In some alternative embodiments, the thickness of the doped region 13 may be adjusted according to actual needs. The thickness of the doped region 13 may be, for example, 1.5 μm to 3 μm. Because the doping concentration of the doped region is heavily doped, and the conductivity of the device can be reduced by the heavy doping, in the embodiment, the conductivity of the device can be ensured and the conduction loss of the device can be reduced by controlling the thickness of the doped region to be 1.5-3 mu m.
In some alternative embodiments, the portion of the drift region 2 in the transistor is located between the doped region 13 and the superjunction 3. Optionally, the distance between the doped region 13 and the super junction 3 is 3 μm to 4 μm. By setting the thickness of the doped region 13 and the distance between the doped region 13 and the super junction 3, the transistor requirements of different parameters required under different scenes can be adapted, and the matching performance of the transistor device is improved.
According to another aspect of the present application, there is provided a method for manufacturing an insulated gate bipolar transistor, the method comprising: providing a substrate, forming at least one doped region on one side of the substrate, forming a drift region on one side of the doped region away from the substrate, wherein the drift region is provided with a third surface away from the doped region, the doping concentration of the doped region is higher than that of the drift region, forming at least one super junction in the drift region, penetrating the super junction into the drift region along the third surface, wherein part of the drift region is positioned between the doped region and the super junction, forming a collector region on one side of the substrate away from the drift region, the collector region is provided with a first surface and a second surface which are opposite, the doped region is in contact with the first surface, the drift region and the doped region are of a first doping type, and the super junction and the collector region are of a second doping type.
First, as shown in fig. 2, in some alternative embodiments, a vapor phase epitaxy process is used to form a doped region 13 on one side of the substrate 1.
In some alternative embodiments, the substrate 1 is a silicon substrate, and further alternatively, the substrate 1 may be of a first doping type or a second doping type, and the transistor device meets various functional requirements by epitaxially growing different structures on the silicon substrate of different doping types.
The doped region 13 may be formed by vapor phase epitaxy, liquid phase epitaxy, or solid phase epitaxy. Alternatively, a silicon source with high volatility is reacted or pyrolyzed with hydrogen gas at high temperature by vapor phase epitaxy to deposit a silicon crystal layer on the substrate 1, wherein the silicon source can be SiH 4 、SiHCl 3 And SiCl 4 By means ofThe vapor phase epitaxy can improve the perfection and high integration of the silicon material, reduce the leakage current in the memory cell, and further improve the reliability of the corresponding device.
In some alternative embodiments, the doping type of the doped region 13 includes phosphorus and arsenic. Further alternatively, in order to obtain silicon crystal layers with different electrical properties, dopants may be added during the formation of the doped region 13 by the vapor phase epitaxy process, i.e., different doped layers are formed by vapor phase doping, for example, PCl is added during the epitaxy process 3 、PH 3 、SbCl 3 AsCl 3 The equal doping agent forms an N-type doping layer, and the P-type doping agent BCl 3 、BBr 3 B, B 2 H 6 And adding the doping agent into an epitaxial growth process to form a P-type doped layer, and controlling the amount of the doping agent forming the doped layer to form doped layers with different resistivity, so that the matching property of the device is improved.
In some alternative embodiments, the doped region 13 is a plurality of doped regions 13 spaced apart on the substrate 1, further alternatively, the doped region 13 may also be only one doped region 13 contacting the substrate 1, where the doped region 13 may be etched at any position on the substrate 1 according to the requirements of matching different devices to form doped regions 13 with different sizes.
In some embodiments, the doped regions 13 are ready-made doped sheets, and the doped regions 13 required in the respective devices are formed by bonding the doped sheets to the substrate 1.
In some alternative embodiments, as shown in fig. 2, after the doped region 13 is formed, an epitaxial growth process is used to form the drift region 2 on the side of the doped region 13 away from the substrate 1, and the drift region 2 has a third surface away from the doped region 13, further alternatively, chemical vapor deposition or physical vapor deposition may be used to form the drift region 2, and after the drift region 2 is formed, a deep trench 102 is formed in the drift region 2, where the deep trench 102 extends along the third surface in a direction pointing to the substrate 1, as shown in fig. 3.
In some alternative embodiments, a patterned mask layer 101 is disposed on the third surface of the drift region 2, that is, a hard mask layer is formed on the third surface of the drift region 2, then a photoresist layer is deposited on the hard mask layer, patterning is performed by exposing and developing, and then a deep trench 102 as shown in fig. 3 is formed in the drift region 2 by etching, and then the remaining mask layer is removed, further alternatively, the patterned mask layer 101 is disposed on the third surface of the drift region 2, and further alternatively, a photoresist layer having an opening with a specific size is formed on the third surface, and then the drift region 2 is etched in the opening of the photoresist layer to form the deep trench 102.
In some alternative embodiments, as shown in fig. 4, the deep trench 102 is filled with polysilicon of a different doping type than the drift region 2 to form the super junction 3.
In some alternative embodiments, as shown in fig. 5, the epitaxial layer 4 is formed on the third surface of the drift region 2 by epitaxial growth, and the doping type of the epitaxial layer 4 is the same as that of the drift region 2, and the doping may be that the epitaxial layer 4 is formed by adding as a dopant in an epitaxial growth process, or further alternatively, after epitaxially growing a silicon layer with a certain thickness, the epitaxial layer 4 may be formed by adopting an ion implantation method.
In some alternative embodiments, as shown in fig. 6, a hard mask layer and photoresist are deposited on a side of the epitaxial layer 4 away from the drift region 2, patterning is performed by photolithography, at least one gate trench 104 is formed by etching, and then the remaining mask layer is removed, where the gate trench 104 may be a plurality of gate trenches 104 disposed at intervals, further optionally, a patterned mask layer 101 may be disposed on a side of the epitaxial layer 4 away from the drift region 2, further optionally, the gate trench 104 may be formed by etching the epitaxial layer 4 by applying a photoresist layer with a specific photoresist opening, and further optionally, the gate trench 104 may be formed by etching the epitaxial layer 4 by dry etching or wet etching.
In some alternative embodiments, as shown in fig. 7, a gate oxide layer 5 is formed on the inner wall and bottom of the gate trench 104 using a chemical vapor deposition or physical vapor deposition method, and then grown silicon dioxide is filled in the gate trench 104 outside the formed gate oxide layer 5 to form the gate electrode 6.
In some alternative embodiments, as shown in fig. 8, a doped well 7 is formed on the side of the epitaxial layer 4 away from the drift region 2 by means of ion implantation, the doped well 7 being of opposite doping type to the epitaxial layer 4, i.e. the doped well 7 may be converted from at least a part of the epitaxial layer 4.
In some alternative embodiments, as shown in fig. 9, at least one emitter region 8 is formed on the side of the doped well 7 away from the epitaxial layer 4, the emitter region 8 is disposed around the end of the gate electrode 6 away from the drift region 2, and further alternatively, at least one or more emitter regions 8 disposed around the gate electrode 6 at intervals may be formed in the doped well 7 by using ion implantation and high-temperature diffusion, and the doping type of the emitter regions 8 is the same as that of the collector region 11.
In some alternative embodiments, as shown in fig. 10, at least one dielectric layer 9 is formed on the side, away from the drift region 2, of the doped well 7 by using a mask plate and performing chemical vapor deposition or physical vapor deposition, the dielectric layer 9 is in one-to-one correspondence with the gate electrode 6, and the surface, away from the drift region 2, of the gate electrode 6 is completely covered by the dielectric layer 9, then an emitter metal 10 is formed on the side, away from the drift region 2, of the doped well 7, and further alternatively, the emitter metal 10 may be formed by using evaporation, atomic layer deposition, magnetron sputtering, or other methods.
In some alternative embodiments, as shown in fig. 11, a collector region 11 is formed on a side of the substrate 1 away from the doped region 13 by means of ion implantation, and the collector region 11 has the same doping type as the substrate 1.
In some alternative embodiments, as shown in fig. 12, collector metal 12 is formed on the side of collector region 11 remote from substrate 1 using evaporation, atomic layer deposition, or magnetron sputtering.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
according to the application, the doped region is arranged on the first surface of the collector region in a contact manner, so that holes entering the drift region from the collector region are blocked by the doped region in a path of the drift region, and as the doped region is opposite to the collector region in doping type, part of holes from the collector region reach the drift region through the doped region, and are composited by ions in the doped region, so that the number of ions entering the drift region from the collector region is reduced, the number of stored charges in the transistor is further reduced, the tailing current of the transistor is reduced, the current tailing phenomenon in the switching-off process of the transistor is improved, the switching-off energy loss of the transistor is effectively reduced, and the reliability of the device is greatly improved.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. An insulated gate bipolar transistor, comprising:
a collector region having opposed first and second surfaces;
at least one doped region, wherein each doped region is in contact with the first surface, and a plurality of doped regions are arranged at intervals;
a drift region located at one side of the doped region away from the collector region, the drift region having a third surface away from the doped region, the doped region having a doping concentration higher than that of the drift region;
and the super junction penetrates into the drift region along the third surface, and part of the drift region is positioned between the doped region and the super junction, wherein the drift region and the doped region are of a first doping type, and the super junction and the collector region are of a second doping type.
2. The insulated gate bipolar transistor of claim 1 wherein the doping concentration of the doped region increases in a first direction, the first direction being a direction in which the third surface points toward the first surface.
3. The insulated gate bipolar transistor of claim 1 wherein the doped region is at least partially between the superjunction and the collector region.
4. An insulated gate bipolar transistor according to any of claims 1-3, wherein the projection of the doped region onto the first surface coincides with the first surface.
5. An insulated gate bipolar transistor according to any of claims 1-3, wherein the super junction extends in a first direction.
6. An insulated gate bipolar transistor according to any one of claims 1 to 3, further comprising:
the second doped region is positioned between the collector region and the doped region, and the second doped region is of a second doping type.
7. A method of manufacturing an insulated gate bipolar transistor according to any one of claims 1 to 6, comprising the steps of:
providing a substrate;
forming at least one doped region on one side of the substrate;
forming a drift region on one side of the doped region far away from the substrate, wherein the drift region is provided with a third surface far away from the doped region, and the doping concentration of the doped region is higher than that of the drift region;
forming at least one super junction in the drift region, the super junction penetrating into the drift region along a third surface, a portion of the drift region being located between the doped region and the super junction;
and forming a collector region on one side of the substrate far away from the drift region, wherein the collector region is provided with a first surface and a second surface which are opposite, and the doped region is in contact with the first surface, wherein the drift region and the doped region are of a first doping type, and the super junction and the collector region are of a second doping type.
8. The method of fabricating an insulated gate bipolar transistor according to claim 7, wherein the step of forming the doped region comprises:
and forming the doped region on one side of the substrate by adopting a vapor phase epitaxy process.
9. The method of fabricating an insulated gate bipolar transistor according to claim 7, wherein the step of forming the super junction comprises:
a patterned mask plate is arranged on the third surface of the drift region, and the super junction is formed in the drift region based on the patterned mask plate; or (b)
And forming a patterned mask layer on the third surface of the drift region, forming a super junction based on the patterned mask layer, and removing the patterned mask layer.
10. The method of manufacturing an insulated gate bipolar transistor according to claim 9, further comprising:
growing an epitaxial layer on the third surface;
and forming an emission region in the epitaxial layer, wherein the doping type of the emission region is the same as that of the collector region.
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