CN117199080A - Array substrate, manufacturing method thereof and display panel - Google Patents

Abstract

The invention discloses an array substrate, a manufacturing method thereof and a display panel, wherein the array substrate comprises: the semiconductor device comprises a substrate base plate, a first conductive layer, a first insulating layer, a semiconductor layer and a second conductive layer. The first conductive layer is positioned on one side of the substrate base plate, and the first conductive layer comprises a data signal line. The first insulating layer is positioned on one side of the first conductive layer, which is away from the substrate base plate. The semiconductor layer is positioned on one side of the first insulating layer, which is away from the first conductive layer, and the semiconductor layer comprises an active layer of the thin film transistor. The second conductive layer is positioned on one side of the semiconductor layer away from the first insulating layer, and the second conductive layer is directly formed on the surface of the semiconductor layer. The second conductive layer includes a source electrode and a drain electrode of the thin film transistor, and the source electrode of the thin film transistor is electrically connected to the data signal line. Is beneficial to improving the poor water ripple.

Description

Array substrate, manufacturing method thereof and display panel

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display panel.

Background

The liquid crystal display (Liquid Crystal Display, LCD) panel has the characteristics of low power consumption, high definition, small volume and the like, and is widely applied to the display fields of mobile phones, tablet computers, notebook computers, displays, monitors, televisions and the like.

The liquid crystal display panel generally includes an array substrate and a counter substrate disposed opposite to each other, and a liquid crystal layer between the array substrate and the counter substrate. Conventional array substrates typically require multiple Mask processes to fabricate thin film transistor (Thin Film Transistor, TFT) structures, requiring a large number of reticles (also known as reticles) to be used, resulting in high cost. In the current 4Mask process, a semi-transparent film Mask (HTM for short) is adopted for one exposure, and simultaneously, the patterns of the data signal lines and the patterns of the Active layer, the source electrode and the drain electrode of the TFT are etched, so that the number of masks is effectively saved, but the problem of Active layer tailing is brought, and the defect similar to 'water ripple' is generated when an image is displayed.

Disclosure of Invention

The invention provides an array substrate, a manufacturing method thereof and a display panel, which are used for simplifying the manufacturing process and improving 'poor water ripple'.

In a first aspect of the present invention, there is provided an array substrate comprising:

a substrate base;

a first conductive layer located at one side of the substrate base plate; the first conductive layer includes a data signal line;

the first insulating layer is positioned on one side of the first conductive layer, which is away from the substrate base plate;

the semiconductor layer is positioned on one side of the first insulating layer, which is away from the first conductive layer; the semiconductor layer includes an active layer of a thin film transistor;

the second conductive layer is positioned on one side of the semiconductor layer, which is away from the first insulating layer; the second conductive layer is directly formed on the surface of the semiconductor layer; the second conductive layer comprises a source electrode and a drain electrode of the thin film transistor; the source electrode of the thin film transistor is electrically connected to the data signal line.

In the array substrate provided by the invention, the first conductive layer further comprises a grid electrode of the thin film transistor; the second conductive layer further comprises a gate scan line;

the gate scan line is electrically connected to a gate electrode of the thin film transistor.

The array substrate provided by the invention further comprises:

the second insulating layer is positioned on one side of the second conductive layer, which is away from the semiconductor layer;

the third conductive layer is positioned on one side of the second insulating layer, which is away from the second conductive layer; the third conductive layer includes a pixel electrode;

the pixel electrode is electrically connected to the drain electrode of the thin film transistor.

The array substrate provided by the invention further comprises a first via hole, a second via hole and a third via hole, wherein the first via hole, the second via hole and the third via hole extend from the surface of the second insulating layer, which is away from the side of the substrate, to the side, which is close to the substrate; the first via hole exposes the data signal line and the source electrode of the thin film transistor; the second via hole exposes the grid electrode and the grid electrode scanning line of the thin film transistor; the third via hole exposes the drain electrode of the thin film transistor;

the third conductive layer further includes:

the first connecting part is positioned in the first via hole and is used for electrically connecting the data signal line and the source electrode of the thin film transistor;

the second connecting part is positioned in the second via hole and is used for electrically connecting the grid scanning line and the grid of the thin film transistor;

and the third connecting part is positioned in the third via hole and is used for electrically connecting the pixel electrode and the drain electrode of the thin film transistor.

In the array substrate provided by the invention, the second conductive layer further comprises a pixel electrode; the pixel electrode is electrically connected to the drain electrode of the thin film transistor.

The array substrate provided by the invention further comprises a fourth via hole extending from the surface of the second insulating layer, which is away from the side of the substrate, to the side, which is close to the substrate; the fourth via hole exposes the data signal line;

the second conductive layer further includes:

and the fourth connecting part is positioned in the fourth through hole and is used for electrically connecting the data signal line and the source electrode of the thin film transistor.

The array substrate provided by the invention further comprises:

a fourth conductive layer located at one side of the first insulating layer away from the semiconductor layer; the fourth conductive layer comprises a grid scanning line and a grid of the thin film transistor; the gate electrode of the thin film transistor is electrically connected to the gate scan line.

The array substrate provided by the invention further comprises: a third insulating layer located between the first conductive layer and the fourth conductive layer;

the fourth conductive layer is positioned between the first conductive layer and the first insulating layer; or,

the fourth conductive layer is positioned on one side of the first conductive layer away from the first insulating layer.

In a second aspect of the present invention, there is provided a display panel comprising the array substrate of any one of the above.

In a third aspect of the present invention, a method for manufacturing an array substrate is provided, including:

forming a first conductive layer on a substrate, and etching the first conductive layer to manufacture a data signal line;

forming a first insulating layer on one side of the first conductive layer away from the substrate;

depositing a semiconductor material on one side of the first insulating layer away from the first conductive layer to form a semiconductor layer;

forming a second conductive layer directly on the surface of one side of the semiconductor layer away from the first insulating layer;

etching the second conductive layer to form a source electrode and a drain electrode of the thin film transistor, so that the source electrode of the thin film transistor is electrically connected with the data signal line.

The invention has the following beneficial effects:

the invention provides an array substrate, a manufacturing method thereof and a display panel, wherein the array substrate comprises: the semiconductor device comprises a substrate base plate, a first conductive layer, a first insulating layer, a semiconductor layer and a second conductive layer. The first conductive layer is positioned on one side of the substrate base plate, and the first conductive layer comprises a data signal line. The first insulating layer is positioned on one side of the first conductive layer, which is away from the substrate base plate. The semiconductor layer is positioned on one side of the first insulating layer, which is away from the first conductive layer, and the semiconductor layer comprises an active layer of the thin film transistor. The second conductive layer is positioned on one side of the semiconductor layer away from the first insulating layer, and the second conductive layer is directly formed on the surface of the semiconductor layer. The second conductive layer includes a source electrode and a drain electrode of the thin film transistor, and the source electrode of the thin film transistor is electrically connected to the data signal line. According to the array substrate provided by the invention, the first insulating layer is arranged between the data signal line and the semiconductor layer at intervals, the source electrode and the drain electrode of the thin film transistor are positioned in the second conductive layer and are arranged on different layers with the data signal line, and the semiconductor layer is not in direct contact with the data line, so that light rays with varying intensity can be prevented from irradiating the semiconductor layer, the influence on data signals transmitted on the data signal line is avoided, and the defect of 'water ripple' is favorably improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic top view of an array substrate according to the related art;

FIG. 2a is a schematic cross-sectional view of an array substrate according to the related art;

FIG. 2b is a schematic diagram of a cross-sectional structure of an array substrate according to the related art;

FIG. 3 is a schematic cross-sectional structure of an array substrate according to an embodiment of the present invention;

FIG. 4 is a schematic top view of an array substrate according to an embodiment of the present invention;

FIG. 5a is a schematic diagram of a cross-sectional structure of an array substrate according to an embodiment of the present invention;

FIG. 5b is a schematic diagram of a third cross-sectional structure of the array substrate according to the embodiment of the present invention;

FIG. 5c is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a manufacturing process of an array substrate according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a top view of an array substrate according to an embodiment of the present invention;

FIG. 8a is a schematic diagram of a cross-sectional structure of an array substrate according to an embodiment of the present invention;

FIG. 8b is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention;

FIG. 9 is a second schematic diagram of a manufacturing process of the array substrate according to the embodiment of the invention;

FIG. 10 is a third schematic top view of an array substrate according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a cross-sectional structure of an array substrate according to an embodiment of the present invention;

fig. 12 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention.

Detailed Description

In order that the above objects, features and advantages of the invention will be readily understood, a further description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted. The words expressing the positions and directions described in the present invention are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present invention. The drawings of the present invention are merely schematic representations of relative positional relationships and are not intended to represent true proportions.

The liquid crystal display (Liquid Crystal Display, LCD) panel has the characteristics of low power consumption, high definition, small volume and the like, and is widely applied to the display fields of mobile phones, tablet computers, notebook computers, displays, monitors, televisions and the like.

The liquid crystal display panel generally includes an array substrate and a counter substrate disposed opposite to each other, and a liquid crystal layer between the array substrate and the counter substrate. Conventional array substrates typically require multiple Mask processes to fabricate thin film transistor (Thin Film Transistor, TFT) structures, requiring a large number of reticles (also known as reticles) to be used, resulting in high cost. In the current 4Mask process, a semi-transparent film Mask (HTM for short) is adopted to perform one exposure, and simultaneously, the patterns of the data signal lines and the patterns of the active layer, the source electrode and the drain electrode of the TFT are etched, so that the number of masks is effectively saved.

FIG. 1 is a schematic top view of an array substrate according to the related art; FIG. 2a is a schematic cross-sectional view of an array substrate according to the related art; FIG. 2b is a schematic diagram of a cross-sectional structure of an array substrate according to the related art.

For example, as shown in fig. 1, the array substrate generally includes a data signal line D and a gate scan line G, and the data signal line D and the gate scan line G intersect in a horizontal direction to define a pixel unit, and the pixel unit generally includes a thin film transistor and a pixel electrode P electrically connected to a drain D of the thin film transistor. The data signal line D is electrically connected to a source electrode s of the thin film transistor for inputting a data signal, and the gate scan line G is electrically connected to a gate electrode G of the thin film transistor for controlling the thin film transistor to be turned on or off, thereby controlling whether the data signal is input to the pixel electrode P.

In some technical routes for manufacturing the array substrate by using the 4mask process, as shown in fig. 1-2B, fig. 2a is a schematic cross-sectional structure along a section line A-A in fig. 1, and fig. 2B is a schematic cross-sectional structure along a section line B-B in fig. 1, in particular, during manufacturing, a gate metal layer is deposited on one side of the substrate 100, and then the gate metal layer is etched by using a mask process to manufacture a pattern of a gate G of the thin film transistor and a pattern of a gate scan line G connected to the gate G. Then, an insulating layer is deposited on one side of the gate metal layer, which is away from the substrate 100, and a semiconductor layer and a source drain metal layer are sequentially deposited on one side of the insulating layer, which is away from the gate metal layer, and then the semiconductor layer and the source drain metal layer are etched through a semi-permeable membrane mask process to form a pattern of a data line number D, a pattern of a source electrode s of a thin film transistor, a pattern of a drain electrode D of the thin film transistor and a pattern of an active layer a of the thin film transistor. Then, an insulating layer is deposited on one side of the source drain metal layer, which is away from the active layer, and is etched through a mask process to manufacture a via hole exposing the drain electrode D of the thin film transistor, then a transparent electrode layer is deposited on one side of the insulating layer, which is away from the source drain metal layer, and is etched through a mask process to manufacture a pixel electrode P, and the pixel electrode P is electrically connected with the drain electrode D of the thin film transistor through the material of the transparent electrode layer filled in the via hole. Finally, a passivation layer is deposited on one side of the transparent electrode layer, which is away from the substrate 100, for protection, and then the fabrication of the array substrate can be completed. Only 4mask plates are needed in the whole manufacturing process, so that the process flow is greatly simplified, the manufacturing cost is reduced, and the manufacturing efficiency is improved.

In the step of etching the source and drain metal layer and the semiconductor layer using the semi-permeable film mask process, since the source and drain metal layer and the semiconductor layer are deposited on the surface of the substrate 100 in the entire surface, a portion of the semiconductor layer remains under the data signal line D when the data signal line D is manufactured, and an Active Tail (Active Tail) is generated due to the difference in etching rate of the source and drain metal layer and the semiconductor layer, as shown in fig. 2a and 2b, the width of the semiconductor layer under the data signal line D is shown to be greater than that of the data signal line D. When the image display is carried out, backlight light irradiates onto the semiconductor layer below the data signal line D, so that the resistance of the semiconductor layer below the data signal line D changes, the resistance of the semiconductor layer changes to further cause the resistance of the data signal line D to change due to the fact that the data signal line D is in direct contact with the semiconductor layer below the data signal line D, parasitic capacitance between the data signal line D and surrounding objects is further affected due to the fact that the width of the semiconductor layer below the data signal line D is wider, the data signal transmitted on the data signal line D is sensitive to the change of the resistance and the capacitance, when the brightness of the light irradiated onto the semiconductor layer below the data signal line D changes, the size of the data signal transmitted on the data signal line D changes accordingly, bright and dark alternate stripes appear in a display image, the phenomenon that the active layer tailing is further deepened is generated.

In view of the above, an embodiment of the present invention provides an array substrate for overcoming the above-mentioned problems.

Fig. 3 is a schematic cross-sectional structure of an array substrate according to an embodiment of the present invention.

In an embodiment of the present invention, as shown in fig. 3, the array substrate includes a substrate 100, a first conductive layer 200, a first insulating layer 300, a semiconductor layer 400, and a second conductive layer 500.

The substrate 100 is located at the bottom of the array substrate, and has functions of supporting and carrying. The shape and size of the substrate 100 are adapted to the array substrate, and the shape may be square, rectangular, etc., and in some embodiments, may be a special shape such as a circle, etc., which is not limited herein. The substrate 100 may be made of a transparent material such as glass or resin, and is not limited thereto. In particular, the substrate 100 may be a single-layer structure, and in some embodiments, the array substrate may also be a stacked structure including a plurality of film layers, which is not limited herein.

The first conductive layer 200 is located at one side of the substrate base plate 100. The first conductive layer 200 includes a data signal line D. The first conductive layer 200 may be made of a metal or the like having a higher conductivity, so that the resistance of the data signal line D is advantageously reduced, and the energy loss is reduced. In particular, the first conductive layer 200 may have a single layer structure or a stacked structure including a plurality of film layers, which is not limited herein. For example, the first conductive layer 200 may have a structure of molybdenum/aluminum/molybdenum (Mo/Al/Mo) stack, molybdenum/copper (Mo/Cu) stack, molybdenum/niobium/copper (Mo/Nb/Cu) stack, molybdenum/niobium/copper/molybdenum/titanium (Mo/Nb/Cu/Mo/Ti) stack, indium tin oxide/copper (ITO/Cu) stack, or the like, which is not limited herein.

A first Insulating Layer (GI) 300 is located on a side of the first conductive Layer 200 facing away from the substrate 100 for Insulating and protecting the first conductive Layer 200. The first insulating layer 300 may be made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the first insulating layer 300 may have a single-layer structure or a stacked-layer structure including a plurality of film layers, which is not limited herein.

The semiconductor layer 400 is located on a side of the first insulating layer 300 facing away from the first conductive layer 200. The semiconductor layer 400 includes an active layer a of a thin film transistor. The semiconductor layer 400 may be formed using a material such as a silicon semiconductor, an organic semiconductor, or an oxide semiconductor, which is not limited herein. In particular, the semiconductor layer 400 may have a single-layer structure or a stacked-layer structure including a plurality of film layers, which is not limited herein. For example, the semiconductor layer 400 may include an amorphous silicon (a-Si) layer and a doped (n) layer stacked in a direction away from the substrate base 100 ⁺ a-Si) layer, wherein the amorphous silicon layer is used to form a conductive channel, and the doped layer is used to reduce the contact resistance between the source s and drain d of the thin film transistor and the active layer a, resulting in good ohmic contact.

The second conductive layer 500 is located at a side of the semiconductor layer 400 facing away from the first insulating layer 300. The second conductive layer 500 is directly formed on the surface of the semiconductor layer 400. The second conductive layer 500 includes a source electrode s and a drain electrode d of the thin film transistor. The source s of the thin film transistor is electrically connected to the data signal line D. In particular, the source s of the thin film transistor may be electrically connected to the data signal line D (not shown) through a via hole penetrating the first insulating layer 300, which is not limited herein.

According to the array substrate provided by the embodiment of the invention, the first insulating layer 300 is arranged between the data signal line D and the semiconductor layer 400 at intervals, the source electrode s and the drain electrode D of the thin film transistor are positioned in the second conductive layer 500 and are arranged on different layers with the data signal line D, the semiconductor layer 400 is not in direct contact with the data signal line D, light with varying intensity can be prevented from irradiating the semiconductor layer 400, the influence on the data signal transmitted on the data signal line D is avoided, and the defect of 'water ripple' is improved.

FIG. 4 is a schematic top view of an array substrate according to an embodiment of the present invention; FIG. 5a is a schematic diagram of a cross-sectional structure of an array substrate according to an embodiment of the present invention; FIG. 5b is a schematic diagram of a third cross-sectional structure of the array substrate according to the embodiment of the present invention; FIG. 5c is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention; fig. 6 is a schematic diagram of a manufacturing process of an array substrate according to an embodiment of the present invention.

In some embodiments, as shown in fig. 4 to 5C, where fig. 5a is a schematic cross-sectional structure along a section line A-A in fig. 4, fig. 5B is a schematic cross-sectional structure along a section line B-B in fig. 4, and fig. 5C is a schematic cross-sectional structure along a section line C-C in fig. 4, the first conductive layer 200 further includes a gate g of a thin film transistor. The second conductive layer 500 further includes a gate scan line G. The gate scan line G located in the second conductive layer 500 is electrically connected to the gate electrode G located in the first conductive layer 200. The material of the second conductive layer 500 may be made of a metal with higher conductivity, so as to reduce the resistance of the data signal line D and reduce energy loss. In particular, the second conductive layer 500 may have a single-layer structure or a stacked-layer structure including a plurality of film layers, which is not limited herein. For example, the first conductive layer 200 may have a structure of molybdenum/aluminum/molybdenum (Mo/Al/Mo) stack, molybdenum/copper (Mo/Cu) stack, molybdenum/niobium/copper (Mo/Nb/Cu) stack, molybdenum/niobium/copper/molybdenum/titanium (Mo/Nb/Cu/Mo/Ti) stack, and the like, which is not limited herein.

In implementation, the source s and the drain d of the thin film transistor share one conductive layer with the gate scan line G, which is beneficial to reducing the number of conductive film layers and reducing the thickness of the array substrate. And the second conductive layer 500 is directly formed on the surface of the semiconductor layer 400, and can be manufactured by a single mask process using a semi-transparent mask when manufacturing the gate scan line G and the active layer a, the source electrode s and the drain electrode d of the thin film transistor, thereby facilitating the simplification of process steps, the reduction of manufacturing cost and the improvement of manufacturing efficiency.

As shown in fig. 4 to 5b, the array substrate further includes a third conductive layer 600 and a second insulating layer 700.

The second insulating layer 700 is located at a side of the second conductive layer 500 facing away from the semiconductor layer 400, for insulating and protecting the second conductive layer 500 and the semiconductor layer 400. The first insulating layer 300 may be made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the first insulating layer 300 may have a single-layer structure or a stacked-layer structure including a plurality of film layers, which is not limited herein.

The third conductive layer 600 is located on a side of the second insulating layer 700 facing away from the second conductive layer 500. The third conductive layer 600 includes a pixel electrode P electrically connected to the drain electrode d of the thin film transistor. The third conductive layer 600 may be made of a transparent conductive material such as Indium Tin Oxide (ITO) to ensure light transmittance of the pixel electrode P and improve light utilization.

In specific implementation, the array substrate further includes a first via H1, a second via H2, and a third via H3 extending from a surface of the second insulating layer 700 on a side facing away from the substrate 100 to a side near the substrate 100; the first via hole H1 exposes the data signal line D and the source s of the thin film transistor; the second via hole H2 exposes the gate electrode G and the gate scan line G of the thin film transistor; the third via H3 exposes the drain d of the thin film transistor. The third conductive layer 600 further includes: a first connection portion 601, a second connection portion 602, and a third connection portion 603. The first connection portion 601 is located in the first via H1 and is used for electrically connecting the data signal line D and the source s of the thin film transistor; the second connection portion 602 is located in the second via H2 and is used for electrically connecting the gate scan line G and the gate G of the thin film transistor; the third connection portion 603 is located in the third via H2 and is used for electrically connecting the pixel electrode P and the drain d of the thin film transistor.

In specific implementation, the array substrate in the embodiment shown in fig. 4 may be manufactured by the following steps:

1. as shown in fig. 6 (a), a first conductive layer 200 is deposited on one side of a substrate 100, and then a mask process is used to pattern a data signal line D and a gate electrode g on the first conductive layer 200 through steps of photoresist coating, exposure, development, etching, stripping, etc.;

2. as shown in fig. 6 (b), a first insulating layer 300, a semiconductor layer 400 and a second conductive layer 500 are sequentially deposited over the entire surface of the first conductive layer 200 on the side facing away from the substrate 100, and then the semiconductor layer 400 and the second conductive layer 500 are patterned into an active layer a, a source s, a drain d and a gate scan line G of the thin film transistor by steps of photoresist coating, exposure, development, etching, stripping, etc. using a semi-transparent mask process. Wherein, when the semi-transparent mask is used for exposure, the regions of the gate scan line G, the source electrode s and the drain electrode d are not exposed, the regions between the source electrode s and the drain electrode d are subjected to semi-exposure and the regions of the first insulating layer 300, which do not need to be provided with the semiconductor layer 400 and the second conductive layer 500, are subjected to full-exposure, the regions of the first insulating layer 300, which do not need to be provided with the semiconductor layer 400 and the second conductive layer 500, can be sequentially etched during etching to form the gate scan line G, then the regions between the source electrode s and the drain electrode d are etched to form the source electrode s and the drain electrode d, and the doping (n) on the surface of the second conductive layer 500 and between the source electrode s and the drain electrode d is etched at the same time ⁺ a-Si) layer forming a conductive layer channel; in particular manufacturing, as shown in fig. 4, 5a and 6 (b), the orthographic projection of the source s of the thin film transistor on the substrate 100 at least partially overlaps with the orthographic projection of the data signal line D on the substrate 100, and the orthographic projection of the gate scan line G on the substrate 100 at least partially overlaps with the orthographic projection of the gate G of the thin film transistor on the substrate 100, so as to facilitate subsequent connection;

3. as shown in fig. 6 (c), a second insulating layer 700 is deposited on the entire surface of the side of the second conductive layer 500 facing away from the active layer 400, and then a mask process is used to form a first via H1, a second via H2, and a third via H3 extending to the side close to the substrate 100 on the side of the second insulating layer 700 facing away from the substrate 100 through steps of photoresist coating, exposure, development, etching, stripping, and the like. The first via H1 is formed in an overlapping area between the orthographic projection of the source s of the thin film transistor on the substrate 100 and the orthographic projection of the data signal line D on the substrate 100, and the first via H1 penetrates through the second insulating layer 700, the second conductive layer 500, the active layer 400 and the first insulating layer 300, so that the bottom of the first via H1 exposes the data signal line D, and the sidewall of the first via H1 exposes the source s of the thin film transistor; the second via hole H2 is formed in an overlapping region of the orthographic projection of the gate scan line G on the substrate 100 and the orthographic projection of the gate electrode G of the thin film transistor on the substrate 100, and the second via hole H2 penetrates through the second insulating layer 700, the second conductive layer 500, the active layer 400 and the first insulating layer 300, so that the bottom of the second via hole H2 exposes the gate electrode G of the thin film transistor, and the sidewall of the second via hole H2 exposes the gate scan line G; the third via hole H3 is formed in the region where the orthographic projection of the drain electrode d of the thin film transistor on the substrate 100 is located, and the side wall of the third via hole H3 exposes the drain electrode d of the thin film transistor;

4. as shown in fig. 6 (d), a third conductive layer 600 is deposited on the entire surface of the side of the second insulating layer 700 facing away from the second conductive layer 500, and then a photoresist coating process, exposing, developing, etching, stripping, etc. are applied to the third conductive layer 600 to form a pixel electrode P, a first connection portion 601, a second connection portion 602, and a third connection portion 603. The first connection portion 601 is located in the first via H1, and the first connection portion 601 electrically connects the data signal line D exposed by the first via H1 and the source s of the thin film transistor; the second connection portion 602 is located in the second via H2, and the second connection portion 602 electrically connects the gate scan line G exposed by the second via H2 with the gate G of the thin film transistor; the third connection portion 603 is located in the third via H3, and the third connection portion 603 electrically connects the pixel electrode P and the drain electrode d of the thin film transistor exposed by the third via H3.

By adopting the above process steps, the array substrate provided by the embodiment shown in fig. 4 can be manufactured by only 4Mask processes, so that the manufacturing process is greatly simplified, the manufacturing cost is reduced, and the manufacturing efficiency is improved. As shown in fig. 2b, only one insulating layer is provided between the data signal line D and the pixel electrode P, and the distance W between the data signal line D and the pixel electrode P is small, so that a large parasitic capacitance is easily generated, and crosstalk is generated on the signal on the data signal line D, thereby causing crosstalk failure. In the array substrate provided in the embodiment shown in fig. 4, at least the first insulating layer 300 and the second insulating layer 700 are spaced between the data signal line D and the pixel electrode P, the distance W between the data signal line D and the pixel electrode P is larger, and the parasitic capacitance is smaller, so that crosstalk defect can be greatly reduced.

In particular, the array substrate provided in the embodiment shown in fig. 4 may be manufactured by other steps, for example, etching the semiconductor layer 400 and the second conductive layer 500 respectively through two Mask processes, which is not limited herein. After the pixel electrode P is fabricated, a passivation layer may be further deposited on a side of the third conductive layer 600 facing away from the second insulating layer 700 to protect the array substrate, which is not limited herein.

FIG. 7 is a schematic diagram of a top view of an array substrate according to an embodiment of the present invention; FIG. 8a is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention; FIG. 8b is a schematic diagram of a cross-sectional structure of an array substrate according to an embodiment of the present invention; FIG. 9 is a second schematic diagram of a manufacturing process of the array substrate according to the embodiment of the invention.

In some embodiments, as shown in fig. 7-8B, where fig. 8a is a schematic cross-sectional structure along the section line A-A of fig. 7, and fig. 8B is a schematic cross-sectional structure along the section line B-B of fig. 7, the second conductive layer 500 further includes a pixel electrode P. The pixel electrode P is electrically connected to the drain electrode d of the thin film transistor. The material of the second conductive layer 500 may be made of transparent conductive material such as Indium Tin Oxide (ITO), so as to ensure light transmittance of the pixel electrode P and improve light utilization rate. In specific implementation, the second conductive layer 500 is directly formed on the surface of the semiconductor layer 400, and the pixel electrode P and the source s and the drain d of the thin film transistor are manufactured simultaneously by using the material of the second conductive layer 500, and the pixel electrode P and the source s and the drain d of the thin film transistor are located in the same film layer. And the number of holes can be reduced, the area of the pixel electrode P is prevented from being reduced due to the hole opening area, and the pixel aperture opening ratio and the light transmittance are improved.

In some embodiments, as shown in fig. 7 and 8a, the array substrate further includes a fourth via H4 extending from a surface of the second insulating layer 300 on a side facing away from the substrate 100 to a side near the substrate 100. The fourth via H4 exposes the data signal line D. In implementation, the second conductive layer 500 further includes a fourth connection portion 501. The fourth connection portion 501 is located in the fourth via H4 and is used for electrically connecting the data signal line D and the source s of the thin film transistor. The fourth connection part 501, the pixel electrode P, and the source s and the drain d of the thin film transistor are simultaneously fabricated in the second conductive layer 500, which can simplify the fabrication process, and is beneficial to reducing the fabrication cost and improving the fabrication efficiency.

In specific implementation, as shown in fig. 7 to 8b, the array substrate further includes a fourth conductive layer 800. The fourth conductive layer 800 is located at a side of the first insulating layer 300 facing away from the semiconductor layer 400. The fourth conductive layer 800 includes a gate scan line G and a gate electrode G of the thin film transistor. The gate electrode G of the thin film transistor is electrically connected to the gate scan line G. The gate scan line G and the data signal line D are disposed in different film layers, so that the difficulty in wiring design can be reduced, and the gate scan line G and the semiconductor layer 400 are disposed separately, so that the influence of the semiconductor layer 400 on the signal of the gate scan line G can be further avoided. The fourth conductive layer 800 may be made of a material having a high conductivity, such as metal, so that the resistance of the gate scan line G is reduced and the energy loss is reduced. In particular, the fourth conductive layer 800 may have a single-layer structure or a stacked-layer structure including a plurality of film layers, which is not limited herein. For example, the fourth conductive layer 800 may have a structure of molybdenum/aluminum/molybdenum (Mo/Al/Mo) stack, molybdenum/copper (Mo/Cu) stack, molybdenum/niobium/copper (Mo/Nb/Cu) stack, molybdenum/niobium/copper/molybdenum/titanium (Mo/Nb/Cu/Mo/Ti) stack, indium tin oxide/copper (ITO/Cu) stack, or the like, which is not limited herein.

In some embodiments, as shown in fig. 7 to 8b, the array substrate further includes a third insulating layer 900. The third insulating layer 900 is located between the first conductive layer 200 and the fourth conductive layer 800. In particular, as shown in fig. 8a, a fourth conductive layer 800 may be disposed between the first conductive layer 200 and the first insulating layer 300, and the data signal line D is disposed on a side of the fourth conductive layer 800 facing away from the first insulating layer 300. Compared with the array substrate shown in fig. 2b, which has the data signal line D and the pixel electrode P separated by at least the first insulating layer 300 and the third insulating layer 900, in the embodiment shown in fig. 7 to 8b, the data signal line D and the pixel electrode P are separated by at least the first insulating layer 300 and the third insulating layer 900, the distance W between the data signal line D and the pixel electrode P is larger, and the parasitic capacitance is smaller, so that crosstalk defect can be greatly reduced. The third insulating layer 900 may be made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the first insulating layer 300 may have a single-layer structure or a stacked-layer structure including a plurality of film layers, which is not limited herein.

In specific implementation, the array substrate in the embodiment shown in fig. 7 may be manufactured by the following steps:

1. as shown in fig. 9 (a), a first conductive layer 200 is deposited on one side of a substrate 100, and then a mask process is used to form a data signal line D pattern on the first conductive layer 200 through steps of photoresist coating, exposure, development, etching, stripping, etc.;

2. as shown in fig. 9 (b), a third insulating layer 900 and a fourth conductive layer 800 are sequentially deposited on the entire surface of the side of the first conductive layer 200 facing away from the substrate 100, and then a film mask process is used to form patterns of a gate electrode G and a gate scanning line G of the thin film transistor on the fourth conductive layer 800 through steps of photoresist coating, exposure, development, etching, stripping, and the like;

3. as shown in fig. 9 (c), the first insulating layer 300 and the semiconductor layer 400 are sequentially deposited on the entire surface of the side of the fourth conductive layer 800 facing away from the third insulating layer 900, and then a semi-transparent film mask process is used to pattern the semiconductor layer 400 by coating photoresist, exposing, developing, etching, stripping, etc., and a fourth via H4 penetrating through the first insulating layer 300 and the third insulating layer 900 is opened in a region corresponding to the orthographic projection of the data signal line D on the substrate 100 to expose the data signal line D. When the semi-permeable mask is used for exposure, the area where the active layer a is located is not exposed, the area corresponding to the fourth via hole H4 is fully exposed, the area which is not provided with the active layer a and is not perforated is semi-exposed, the first insulating layer 300 and the third insulating layer 900 can be sequentially etched to form the fourth via hole during etching, and then the semiconductor layer 400 which is not provided with the active layer a and is not perforated is etched to form the active layer a;

4. as shown in fig. 9 (d), a second conductive layer 500 is deposited on the entire surface of the side of the semiconductor layer 400 facing away from the first insulating layer 300, and then a mask process is used to form a fourth connection portion 501 in the fourth via hole H4 and the source s and drain d of the thin film transistor on the second conductive layer 500 through steps of photoresist coating, exposure, development, etching, stripping, etc. One end of the source electrode s of the thin film transistor is overlapped on the active layer a, and is electrically connected to the active layer a, and the other end is connected to the fourth connection part 501 to be electrically connected to the data signal line D. In particular, dry etching may be used to etch the source s and the drain d of the thin film transistor, and after the source s and the drain d of the thin film transistor are etched, the surface of the active layer a between the source s and the drain d of the thin film transistor may be continuously etched to remove the doped layer (n ⁺ a-Si) layer forming a conductive channel.

By adopting the above process steps, the array substrate provided by the embodiment shown in fig. 7 can be manufactured by only 4Mask processes, so that the manufacturing process is greatly simplified, the manufacturing cost is reduced, and the manufacturing efficiency is improved.

In specific implementation, the array substrate provided in the embodiment shown in fig. 7 may be manufactured by other steps, which is not limited herein. After the pixel electrode P is fabricated, a passivation layer may be deposited on a side of the second conductive layer 500 facing away from the semiconductor layer 400 to protect the array substrate, which is not limited herein.

FIG. 10 is a third schematic top view of an array substrate according to an embodiment of the present invention; FIG. 11 is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention.

In an embodiment, as shown in fig. 10 and 11, fig. 11 is a schematic cross-sectional structure along a section line A-A of fig. 10, which is similar to the structure of the array substrate in the embodiment shown in fig. 7 to 8b, except that the fourth conductive layer 800 is located on a side of the first conductive layer 200 facing away from the first insulating layer 300. In the embodiment shown in fig. 10 and 11, the structure and the manufacturing process of the array substrate may refer to the embodiments shown in fig. 7 to 9, and will not be described herein.

In a second aspect of the embodiments of the present invention, a display panel is provided, where the display panel includes the array substrate provided in any one of the embodiments. The display panel may be a liquid crystal display panel or other types of display panels that need to be used on the array substrate, and will not be described herein. For example, the display panel may be a vertically aligned (Vertical Alignment, VA) lcd panel, which is not limited herein. In specific implementation, the display panel provided by the embodiment of the present invention has the same technical effects as the array substrate provided by any one of the embodiments, and will not be described herein.

Fig. 12 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention.

In a third aspect of the embodiment of the present invention, there is further provided a method for manufacturing a display array substrate, as shown in fig. 12, the method including the steps of:

s121: forming a first conductive layer on the array substrate, and etching the first conductive layer to manufacture a data signal line;

s122: forming a first insulating layer on one side of the first conductive layer away from the substrate;

s123: depositing a semiconductor material on one side of the first insulating layer away from the first conductive layer to form a semiconductor layer;

s124: forming a second conductive layer directly on the surface of one side of the semiconductor layer away from the first insulating layer;

s125: etching the second conductive layer to form a source electrode and a drain electrode of the thin film transistor, so that the source electrode of the thin film transistor is electrically connected with the data signal line.

In the method for manufacturing the array substrate provided by the embodiment of the invention, the first insulating layer 300 is arranged between the data signal line D and the semiconductor layer 400 at intervals, the source electrode s and the drain electrode D of the thin film transistor are positioned in the second conductive layer 500 and are arranged on different layers from the data signal line D, the semiconductor layer 400 is not in direct contact with the data signal line D, the light with the intensity change can be prevented from irradiating the semiconductor layer 400, the influence on the data signal transmitted on the data signal line D is avoided, and the defect of 'water ripple' is improved.

The specific structure of the array substrate and the manufacturing process thereof provided in the embodiment of the present invention are described in detail in the foregoing, and when the specific structure of the array substrate is implemented, the specific manufacturing method of the array substrate provided in the embodiment of the present invention may refer to the content related to the specific structure of the foregoing array substrate, which is not described herein.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (10)

1. An array substrate, characterized by comprising:

a substrate base;

a first conductive layer located on one side of the substrate base plate; the first conductive layer includes a data signal line;

the first insulating layer is positioned on one side of the first conductive layer, which is away from the substrate base plate;

the semiconductor layer is positioned on one side of the first insulating layer, which is away from the first conductive layer; the semiconductor layer includes an active layer of a thin film transistor;

the second conductive layer is positioned on one side of the semiconductor layer, which is away from the first insulating layer; the second conductive layer is directly formed on the surface of the semiconductor layer; the second conductive layer comprises a source electrode and a drain electrode of the thin film transistor; the source electrode of the thin film transistor is electrically connected with the data signal line.

2. The array substrate of claim 1, wherein the first conductive layer further comprises a gate of the thin film transistor; the second conductive layer further comprises a gate scan line;

the gate scan line is electrically connected to a gate electrode of the thin film transistor.

3. The array substrate of claim 2, further comprising:

the second insulating layer is positioned on one side of the second conductive layer, which is away from the semiconductor layer;

the third conductive layer is positioned on one side of the second insulating layer, which is away from the second conductive layer; the third conductive layer includes a pixel electrode;

the pixel electrode is electrically connected with the drain electrode of the thin film transistor.

4. The array substrate of claim 3, further comprising first, second, and third vias extending from a surface of the second insulating layer on a side facing away from the substrate to a side proximate to the substrate; the first via hole exposes the data signal line and the source electrode of the thin film transistor; the second via hole exposes the gate electrode of the thin film transistor and the gate scan line; the third via hole exposes the drain electrode of the thin film transistor;

the third conductive layer further includes:

the first connecting part is positioned in the first via hole and is used for electrically connecting the data signal line and the source electrode of the thin film transistor;

the second connecting part is positioned in the second via hole and is used for electrically connecting the grid scanning line and the grid of the thin film transistor;

and the third connecting part is positioned in the third via hole and is used for electrically connecting the pixel electrode and the drain electrode of the thin film transistor.

5. The array substrate of claim 1, wherein the second conductive layer further comprises a pixel electrode; the pixel electrode is electrically connected with the drain electrode of the thin film transistor.

6. The array substrate of claim 5, further comprising a fourth via extending from a surface of the second insulating layer on a side facing away from the substrate to a side proximate to the substrate; the fourth via hole exposes the data signal line;

the second conductive layer further includes:

and the fourth connecting part is positioned in the fourth through hole and is used for electrically connecting the data signal line and the source electrode of the thin film transistor.

7. The array substrate of claim 6, further comprising:

a fourth conductive layer located at one side of the first insulating layer away from the semiconductor layer; the fourth conductive layer comprises a gate scanning line and a gate of the thin film transistor; the grid electrode of the thin film transistor is electrically connected with the grid electrode scanning line.

8. The array substrate of claim 7, further comprising: a third insulating layer located between the first conductive layer and the fourth conductive layer;

the fourth conductive layer is located between the first conductive layer and the first insulating layer; or,

the fourth conductive layer is positioned on one side of the first conductive layer away from the first insulating layer.

9. A display panel comprising an array substrate according to any one of claims 1 to 8.

10. The manufacturing method of the array substrate is characterized by comprising the following steps of:

forming a first conductive layer on a substrate, and etching the first conductive layer to manufacture a data signal line;

forming a first insulating layer on one side of the first conductive layer away from the substrate base plate;

depositing a semiconductor material on one side of the first insulating layer away from the first conductive layer to form a semiconductor layer;

forming a second conductive layer directly on the surface of one side of the semiconductor layer away from the first insulating layer;

etching the second conductive layer to form a source electrode and a drain electrode of the thin film transistor, and electrically connecting the source electrode of the thin film transistor with the data signal line.