CN117198873A - P-type crystalline silicon film, preparation method thereof and semiconductor device - Google Patents
P-type crystalline silicon film, preparation method thereof and semiconductor device Download PDFInfo
- Publication number
- CN117198873A CN117198873A CN202311268055.6A CN202311268055A CN117198873A CN 117198873 A CN117198873 A CN 117198873A CN 202311268055 A CN202311268055 A CN 202311268055A CN 117198873 A CN117198873 A CN 117198873A
- Authority
- CN
- China
- Prior art keywords
- material layer
- type
- layer
- polycrystalline silicon
- polysilicon material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021419 crystalline silicon Inorganic materials 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 241
- 229920005591 polysilicon Polymers 0.000 claims abstract description 121
- 239000000463 material Substances 0.000 claims abstract description 105
- 239000002210 silicon-based material Substances 0.000 claims abstract description 87
- 238000002425 crystallisation Methods 0.000 claims abstract description 64
- 230000008025 crystallization Effects 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000010438 heat treatment Methods 0.000 claims abstract description 42
- 238000000151 deposition Methods 0.000 claims description 121
- 230000008021 deposition Effects 0.000 claims description 120
- 238000009792 diffusion process Methods 0.000 claims description 93
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 54
- 229910052710 silicon Inorganic materials 0.000 claims description 47
- 239000010703 silicon Substances 0.000 claims description 47
- 239000010408 film Substances 0.000 claims description 32
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000005641 tunneling Effects 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 239000002994 raw material Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 236
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 20
- 239000001301 oxygen Substances 0.000 description 20
- 229910052760 oxygen Inorganic materials 0.000 description 20
- 239000012159 carrier gas Substances 0.000 description 18
- 229910000077 silane Inorganic materials 0.000 description 18
- 239000007789 gas Substances 0.000 description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 16
- 238000000137 annealing Methods 0.000 description 14
- 230000000052 comparative effect Effects 0.000 description 14
- 239000002019 doping agent Substances 0.000 description 13
- 238000001816 cooling Methods 0.000 description 11
- 239000013078 crystal Substances 0.000 description 10
- 229910052810 boron oxide Inorganic materials 0.000 description 9
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 9
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 9
- 229910052757 nitrogen Inorganic materials 0.000 description 8
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910052990 silicon hydride Inorganic materials 0.000 description 4
- 229910000085 borane Inorganic materials 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- -1 silicon hydride compound Chemical class 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical compound BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 238000001069 Raman spectroscopy Methods 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Photovoltaic Devices (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The present disclosure provides a p-type crystalline silicon film, a method for preparing the same, and a semiconductor device. The preparation method of the p-type crystalline silicon film comprises the following steps: preparing a polysilicon material layer with crystallization rate less than or equal to 35% on a substrate; the polycrystalline silicon material layer is an intrinsic polycrystalline silicon material layer, p-type doping elements are doped into the intrinsic polycrystalline silicon material layer, and heat treatment is carried out to form a p-type polycrystalline silicon layer with the crystallization rate of more than 90%; or the polysilicon material layer is a doped polysilicon material layer containing p-type doping elements, and the doped polysilicon material layer is subjected to heat treatment to form the p-type polysilicon layer with the crystallization rate of more than 90%.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a p-type crystalline silicon film, a preparation method thereof and a semiconductor device.
Background
Semiconductors play an important role in current production and life, for example, field effect transistors, solar cells and the like are common semiconductor devices.
Silicon is a common semiconductor material, pure silicon being an intrinsic semiconductor, i.e. a doped semiconductor can be formed when silicon atoms in the silicon lattice are replaced by donor or acceptor impurities. The carrier mobility of a doped semiconductor is directly related to the impurity concentration therein. The carrier mobility of p-type semiconductors is generally low due to solid solubility and conduction mechanisms, and needs to be further improved. In the conventional technology, the carrier mobility of the p-type semiconductor is generally improved by improving the doping concentration of the p-type doping element, but if the doping concentration is too high, an impurity-rich layer is formed on the surface, so that the etching processability of the semiconductor material is affected.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method for producing a p-type crystalline silicon thin film to improve carrier mobility of a p-type semiconductor while ensuring processability of the p-type crystalline silicon thin film.
According to some embodiments of the present disclosure, there is provided a method for preparing a p-type crystalline silicon thin film, including the steps of:
preparing a polysilicon material layer with crystallization rate less than or equal to 35% on a substrate;
the polycrystalline silicon material layer is an intrinsic polycrystalline silicon material layer, p-type doping elements are doped into the intrinsic polycrystalline silicon material layer, and heat treatment is carried out to form a p-type polycrystalline silicon layer with the crystallization rate of more than 90%; or alternatively, the first and second heat exchangers may be,
the polysilicon material layer is a doped polysilicon material layer containing p-type doping elements, and the doped polysilicon material layer is subjected to heat treatment to form the p-type polysilicon layer with the crystallization rate of more than 90%.
In some embodiments of the present disclosure, the layer of polycrystalline silicon material is a layer of intrinsic polycrystalline silicon material, the layer of intrinsic polycrystalline silicon material is prepared by a chemical vapor deposition method, and in the step of preparing the layer of intrinsic polycrystalline silicon material, a reactive material including a silicon source is introduced into a deposition chamber.
In some embodiments of the present disclosure, the intrinsic polycrystalline silicon material layer is prepared by a low pressure chemical vapor deposition method, and in the step of preparing the intrinsic polycrystalline silicon material layer, the gas pressure in the deposition chamber is controlled to be 100mTorr to 500mTorr, the flow rate of the silicon source is controlled to be 100sccm to 1200sccm, and the deposition temperature is controlled to be 490 ℃ to 610 ℃.
In some embodiments of the present disclosure, the step of doping the intrinsic polycrystalline silicon material layer with a p-type doping element and performing a heat treatment includes:
placing the substrate with the intrinsic polycrystalline silicon material layer in a diffusion chamber, introducing a doping source containing the p-type doping element into the diffusion chamber, and forming a diffusion layer containing the p-type doping element on the intrinsic polycrystalline silicon layer;
and heating the intrinsic polycrystalline silicon material layer and the diffusion layer to perform junction pushing treatment, and enabling the p-type doping element to be diffused and doped into the intrinsic polycrystalline silicon material layer in the junction pushing treatment process to form the p-type polycrystalline silicon layer.
In some embodiments of the present disclosure, in forming a diffusion layer containing the p-type doping element on the intrinsic polycrystalline silicon layer, controlling a temperature in the diffusion chamber to be 700 ℃ to 890 ℃;
In the process of pushing and knot treatment, the knot pushing temperature is controlled to be 850-960 ℃.
In some embodiments of the present disclosure, the polysilicon material layer is a doped polysilicon material layer containing a p-type doping element, the doped polysilicon material layer is prepared by a chemical vapor deposition method, and in the step of preparing the doped polysilicon material layer, a reaction raw material including a silicon source and a doping source including the p-type doping element is introduced into a deposition chamber.
In some embodiments of the present disclosure, the doped polysilicon material layer is prepared by a low pressure chemical vapor deposition method in the preparation of the doped polysilicon material layer, and in the preparation of the doped polysilicon material layer, the air pressure in the deposition chamber is controlled to be 100 mTorr-500 mTorr, and the deposition temperature is controlled to be 490 ℃ to 610 ℃.
In some embodiments of the present disclosure, the doped polysilicon material layer is prepared by a plasma enhanced chemical vapor deposition method, and in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 1000 mTorr-5000 mTorr, the deposition temperature is controlled to be 300 ℃ to 550 ℃, and the deposition power is controlled to be 5000W-15000W.
In some embodiments of the present disclosure, the heat treatment temperature is controlled to be 800 ℃ to 1000 ℃ during the heat treatment of the doped polysilicon material layer.
In some embodiments of the present disclosure, the p-type doping element is selected from one or more of boron and gallium.
In some embodiments of the present disclosure, the substrate includes an n-type silicon wafer and a tunneling oxide layer stacked on the n-type silicon wafer, and the polysilicon material layer is prepared on a side of the tunneling oxide layer away from the n-type silicon wafer.
Further, the disclosure also provides a p-type crystalline silicon film, which comprises a p-type polycrystalline silicon layer, wherein the p-type polycrystalline silicon layer contains p-type doping elements, and the crystallization rate of the p-type polycrystalline silicon layer is above 90%.
In some embodiments of the disclosure, the p-type crystalline silicon film is prepared by the method for preparing a p-type crystalline silicon film according to any of the embodiments above.
Further, the present disclosure also provides a semiconductor device including the p-type crystalline silicon film according to any one of the above embodiments.
In some embodiments of the present disclosure, the semiconductor device is a solar cell or a field effect transistor.
The carrier mobility of doped semiconductors is typically improved by increasing the doping concentration in conventional techniques. The present disclosure creates a new approach to increasing the carrier mobility of doped polysilicon by increasing its crystallization rate.
Specifically, in the preparation method of the crystalline silicon film, an intrinsic polycrystalline silicon material layer or a doped polycrystalline silicon material layer with the crystallization rate less than or equal to 35% is prepared on a substrate in advance, and then the intrinsic polycrystalline silicon material layer is subjected to doping treatment and heat treatment or the doped polycrystalline silicon material layer is subjected to heat treatment. The present disclosure has been developed to find that, for a p-type doped polysilicon material layer, the lower the crystallization rate of the polysilicon material layer before heat treatment, the higher the crystallization rate of the polysilicon material layer after heat treatment. With the improvement of the crystallization rate, the continuity of the crystal lattice of the p-type crystal silicon film is also improved, and the crystal boundary and defects are also reduced, so that the scattering of carriers in the crystal lattice can be reduced, and the carrier mobility of the p-type crystal silicon film is improved.
The foregoing description is merely an overview of the present invention and may be practiced according to the teachings of the present invention in order that the present invention may be more clearly understood.
Drawings
FIG. 1 is a schematic diagram showing steps of a method for preparing a p-type crystalline silicon film;
FIG. 2 is a schematic diagram showing steps of another method for preparing a p-type crystalline silicon film.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure is more fully described below. Preferred embodiments of this disclosure are presented herein. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The present disclosure provides a method for preparing a p-type crystalline silicon film, which includes the steps of: and preparing a polysilicon material layer with the crystallization rate less than or equal to 35 percent on the substrate. The polycrystalline silicon material layer is an intrinsic polycrystalline silicon material layer, p-type doping elements are doped into the intrinsic polycrystalline silicon material layer, and heat treatment is carried out to form the p-type polycrystalline silicon layer with the crystallization rate of more than 90%. Or the polysilicon material layer is a doped polysilicon material layer containing p-type doping elements, and the doped polysilicon material layer is subjected to heat treatment to form the p-type polysilicon layer with the crystallization rate of more than 90%.
The carrier mobility of doped semiconductors is typically improved by increasing the doping concentration in conventional techniques. The present disclosure creates a new approach to increasing the carrier mobility of doped polysilicon by increasing its crystallization rate.
Specifically, in the preparation method of the crystalline silicon film, an intrinsic polycrystalline silicon material layer or a doped polycrystalline silicon material layer with the crystallization rate less than or equal to 35% is prepared on a substrate in advance, and then the intrinsic polycrystalline silicon material layer is subjected to doping treatment and heat treatment or the doped polycrystalline silicon material layer is subjected to heat treatment. The present disclosure has been developed to find that, for a p-type doped polysilicon material layer, the lower the crystallization rate of the polysilicon material layer before heat treatment, the higher the crystallization rate of the polysilicon material layer after heat treatment. With the improvement of the crystallization rate, the continuity of the crystal lattice of the p-type crystal silicon film is also improved, and the crystal boundary and defects are also reduced, so that the scattering of carriers in the crystal lattice can be reduced, and the carrier mobility of the p-type crystal silicon film is improved.
The preparation method of the p-type crystalline silicon film can be realized in various modes.
FIG. 1 is a schematic diagram showing steps of a method for preparing a p-type crystalline silicon film. Referring to fig. 1, the p-type crystalline silicon thin film includes steps S1.1 to S1.3.
And S1.1, preparing an intrinsic polycrystalline silicon material layer on the substrate.
In some examples of this embodiment, a substrate is used to carry the layer of intrinsic polysilicon material. The substrate material may include one or more of glass, quartz, sapphire, silicon germanium alloy, gallium nitride, or gallium arsenide. In addition, the substrate can also be an intermediate product of certain devices, and the finally prepared p-type polycrystalline silicon layer can participate in the composition of the devices.
For example, if the device to be fabricated is a solar cell, in some examples of this embodiment, the substrate may comprise an n-type silicon wafer on which the layer of intrinsic polysilicon material may be fabricated directly in order to ultimately form a pn junction. Further, in some examples of this embodiment, the substrate may further include a tunnel oxide layer disposed on the n-type silicon wafer. A layer of intrinsic polysilicon material may also be prepared on the tunnel oxide layer to facilitate the final formation of a passivation contact structure on the n-type silicon wafer.
In some examples of this embodiment, the tunnel oxide layer may be prepared on the n-type silicon wafer by deposition or thermal oxidation. For example, an n-type silicon wafer may be placed in a thermal oxidation chamber, and oxygen is introduced into the thermal oxidation chamber to form a tunneling oxide layer on the surface of the n-type silicon wafer. In this embodiment, the thickness of the tunnel oxide layer may be 1nm to 2nm.
In some examples of this embodiment, in the step of preparing the tunnel oxide layer, the temperature in the thermal oxidation chamber may be controlled to 500-640 ℃, the reaction time may be controlled to 2-60 min, and the oxygen flow may be controlled to 1000-30000 sccm.
In this example, the crystallization rate of the prepared intrinsic polycrystalline silicon material layer is 35% or less. For example, the crystallization rate of the prepared intrinsic polycrystalline silicon material layer is 0.1%, 1%, 3%, 5%, 10%, 15%, 20%, 25%, 35%, or the crystallization rate of the intrinsic polycrystalline silicon material layer may be in a range between any two of the above crystallization rates.
The specific process conditions for preparing the intrinsic polycrystalline silicon material layer can be controlled, so that the crystallization rate of the prepared intrinsic polycrystalline silicon material layer is low. It is understood that the crystallization rate can be characterized by raman testing.
In some examples of this embodiment, the intrinsic polycrystalline silicon material layer may be prepared by a chemical vapor deposition method, and in the step of preparing the intrinsic polycrystalline silicon material layer, a reactive material including a silicon source is introduced into the deposition chamber.
In some examples of this embodiment, the silicon source may be a silicon-containing compound capable of forming elemental silicon upon thermal decomposition. Further, the silicon source may be a silicon hydride compound. The silicon hydride may include, but is not limited to SiH 4 And Si (Si) 2 H 6 One or more of the following. The silicon hydrogen compound can be heatedCan decompose and generate silicon atoms that deposit on the substrate and aggregate to form a layer of intrinsic polycrystalline silicon material.
In some examples of this embodiment, the manner of preparing the intrinsic polycrystalline silicon material layer may be a low pressure chemical vapor deposition process. Further, in the step of preparing the intrinsic polycrystalline silicon material layer, the air pressure in the deposition chamber is controlled to be 100 mTorr-500 mTorr, and the deposition temperature is controlled to be 490-610 ℃. Alternatively, the deposition temperature may be controlled to be 490 ℃ to 590 ℃. Wherein, by controlling the air pressure and the deposition temperature in the deposition chamber at the same time, the crystallization rate of the prepared intrinsic polycrystalline silicon material layer can be lower than 35%.
Further, in some examples of this embodiment, in the step of preparing the intrinsic polysilicon material layer, the gas pressure within the deposition chamber may be controlled to be 100mTorr, 150mTorr, 200mTorr, 250mTorr, 300mTorr, 400mTorr, 500mTorr, or alternatively, the gas pressure within the deposition chamber may be controlled to be within a range between any two of the above. By controlling the gas pressure in the deposition chamber within the above range, the deposition rate of silicon atoms can be increased as much as possible while reducing the crystallization rate of the intrinsic polycrystalline silicon material layer.
Further, in some examples of this embodiment, in the step of preparing the intrinsic polycrystalline silicon material layer, the deposition temperature may be controlled to be 490 ℃, 500 ℃, 510 ℃, 520 ℃, 530 ℃, 540 ℃, 550 ℃, 560 ℃, 570 ℃, 580 ℃, 585 ℃, 590 ℃, or the deposition temperature may also be controlled to be within a range between any two of the above. By controlling the deposition temperature within the above range, the deposition rate of silicon atoms can be increased as much as possible while reducing the crystallization rate of the intrinsic polycrystalline silicon material layer.
In addition, in the step of preparing the intrinsic polycrystalline silicon material layer, the deposition temperature may be selected correspondingly according to the air pressure in the deposition chamber. When the gas pressure in the deposition chamber is high, the deposition temperature may also be set high so as to increase the deposition rate while ensuring a low crystallization rate.
In some examples of this embodiment, the flow rate of the silicon source may be controlled to be 100sccm to 800sccm in the step of preparing the intrinsic polycrystalline silicon material layer. Further, the flow rate of the silicon source may be controlled to be 100sccm, 200sccm, 300sccm, 400sccm, 500sccm, 600sccm, 700sccm, 800sccm, or the flow rate of the silicon source may be controlled to be within a range between any two of the above.
In some examples of this embodiment, the deposition time may be controlled to be 30min to 800min. For example, the deposition time may be controlled to be 30min, 50min, 100min, 200min, 300min, 500min, 700min, 800min, or the deposition time may be controlled to be within a range between any two of the above-described deposition times.
And S1.2, doping p-type doping elements into the intrinsic polycrystalline silicon material layer.
In some examples of this embodiment, the manner of incorporating the p-type doping element into the intrinsic polysilicon material layer may be diffusion, and this step may be performed in a diffusion chamber.
In some examples of this embodiment, the step of incorporating a p-type doping element into the intrinsic polysilicon material layer comprises: and placing the substrate with the intrinsic polycrystalline silicon material layer in a diffusion chamber, introducing a doping source containing p-type doping elements into the diffusion chamber, and forming a diffusion layer containing p-type doping elements on the intrinsic polycrystalline silicon layer.
The doping source may be selected according to the p-type doping element to be doped. In some examples of this embodiment, the p-type doping element may be selected from one or more of boron and gallium. In this embodiment, the p-type doping element may be boron. Accordingly, in this embodiment, the doping source may be one or more of boron trichloride and boron tribromide. The dopant source may be carried into the diffusion chamber by a carrier gas.
In some examples of this embodiment, the temperature in the diffusion chamber may be controlled to 700 ℃ to 890 ℃ during the preparation of the diffusion layer containing the p-type doping element on the intrinsic polycrystalline silicon layer. For example, the temperature in the diffusion chamber may be controlled to be 700 ℃, 710 ℃, 720 ℃, 730 ℃, 740 ℃, 750 ℃, 760 ℃, 770 ℃, 780 ℃, 790 ℃, 800 ℃, 810 ℃, 820 ℃, 830 ℃, 840 ℃, 850 ℃, 860 ℃, 870 ℃, 880 ℃, 890 ℃, or the temperature in the diffusion chamber may be controlled to be in a range between any two of the above. Wherein, by controlling the temperature in the diffusion chamber to be higher, not only is the formation of the diffusion layer on the intrinsic polysilicon material layer facilitated, but more importantly, the intrinsic polysilicon material layer with lower crystallization rate can be converted into the p-type polysilicon layer with higher crystallization rate.
In some examples of this embodiment, the flow rate of the carrier gas carrying the dopant source may be controlled to be 100sccm to 400sccm during the preparation of the diffusion layer containing the p-type dopant element on the intrinsic polycrystalline silicon layer.
In some examples of this embodiment, an oxidizing gas, which may be selected from oxygen, may also be introduced into the diffusion chamber during diffusion. The flow rate of the oxidizing gas may be 400sccm to 1000sccm. It will be appreciated that the oxidizing gas may react with the dopant source to form an oxidized material containing the p-type dopant element, such as boron oxide, which may be a component of the diffusion layer.
In some examples of this embodiment, the gas pressure in the diffusion chamber may be controlled to be between 100mbar and 400mbar during diffusion.
And S1.3, performing heat treatment on the intrinsic polycrystalline silicon material layer and the diffusion layer.
In some examples of this embodiment, the p-type doping element in the diffusion layer is diffused into the intrinsic polysilicon material layer during the heat treatment to form a p-type polysilicon layer.
The heat treatment refers to a treatment mode of heating the intrinsic polycrystalline silicon material layer and then cooling the intrinsic polycrystalline silicon material layer. The silicon atoms in the intrinsic polycrystalline silicon material layer can be rearranged and the crystallization rate thereof can be improved through heat treatment. However, in the conventional technology, the solid solubility of the p-type doping element is low, the presence of the p-type doping element prevents the rearrangement of silicon atoms and limits the improvement of the crystallization rate, so that the crystallization rate of the p-type polysilicon is always difficult to reach more than 90%. Even if the pre-annealing or post-annealing process is performed, it is practically difficult to effectively improve carrier mobility of the doped polysilicon. According to the embodiment, the intrinsic amorphous silicon layer with low crystallization rate is prepared first, and then the diffusion treatment and the heat treatment are carried out correspondingly, so that the crystallization rate of the final p-type polycrystalline silicon layer can be obviously improved.
In some examples of this embodiment, the step of thermally treating the intrinsic polycrystalline silicon material layer and the diffusion layer comprises: the intrinsic polysilicon material layer and the diffusion layer are heated to perform a push-junction process, and the p-type doping element is diffused into the intrinsic polysilicon material layer during the push-junction process to form the p-type polysilicon layer.
In some examples of this embodiment, the push junction temperature may be controlled to be 850-960 ℃ during the push junction process. By controlling the temperature of the diffusion chamber and the junction pushing temperature during the junction pushing process, the crystallization rate of the final p-type polysilicon layer can be ensured while the p-type doping element is diffused into the intrinsic polysilicon material layer.
In some examples of this embodiment, the junction pushing temperature may be controlled to 850 ℃, 860 ℃, 870 ℃, 880 ℃, 890 ℃, 900 ℃, 910 ℃, 920 ℃, 930 ℃, 940 ℃, 950 ℃, 960 ℃, or the junction pushing temperature may be controlled to be within a range between any two of the above temperatures during the junction pushing process.
It will be appreciated that the preparation of the p-type polysilicon layer can be accomplished by steps S1.1-S1.3, in which embodiment an intrinsic polysilicon material layer is prepared that does not contain doping elements, and then the p-type doping elements are incorporated into the intrinsic polysilicon material layer, i.e. in an ex-situ doping. The p-type crystalline silicon film of the present disclosure may include the p-type polycrystalline silicon layer.
FIG. 2 is a schematic diagram showing steps of another method for preparing a p-type crystalline silicon film. Referring to fig. 2, the p-type crystalline silicon thin film includes steps S2.1 to S2.2.
And S2.1, preparing a doped polysilicon material layer on the substrate.
In some examples of this embodiment, a substrate is used to carry the layer of intrinsic polysilicon material. The substrate may be selected with reference to the substrate in step S1.1, which is not described here again.
In this embodiment, the doped polysilicon material layer contains a p-type doping element. In some examples of this embodiment, the p-type doping element may be selected from one or more of boron and gallium.
In this example, the crystallization rate of the prepared doped polysilicon material layer was below 35%. For example, the crystallization rate of the prepared doped polysilicon material layer is 0.1%, 1%, 3%, 5%, 10%, 15%, 20%, 25%, 35%, or the crystallization rate of the doped polysilicon material layer may be in a range between any two of the above crystallization rates.
The specific process conditions for preparing the doped polysilicon material layer can be controlled, so that the crystallization rate of the prepared doped polysilicon material layer is low.
In some examples of this embodiment, the doped polysilicon material layer may be prepared by chemical vapor deposition, and the p-type doping element may be in-situ doped into the doped polysilicon material layer during silicon atomic deposition. In the step of preparing the doped polysilicon material layer, a reactive material comprising a silicon source and a dopant source, the dopant source comprising a p-type dopant element, is introduced into the deposition chamber.
In some examples of this embodiment, the silicon source may be a silicon-containing compound capable of forming elemental silicon upon thermal decomposition. Further, the silicon source may be a silicon hydride compound. The silicon hydride may include, but is not limited to SiH 4 And Si (Si) 2 H 6 One or more of the following.
The doping source can be selected according to the p-type doping element to be doped and a specific preparation process. In this embodiment, the p-type doping element may be boron. Accordingly, in this embodiment, the doping source may comprise a borohydride, for example, the doping source may comprise a borane. The dopant source may be introduced into the deposition chamber along with the silicon source. The dopant source and the silicon source decompose and produce silicon atoms and dopant atoms that are co-deposited on the substrate and aggregate to form a doped polysilicon material layer.
Further, the method for preparing the doped polysilicon material layer can be a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method.
In this embodiment, the doped polysilicon material layer may be prepared by a low pressure chemical vapor deposition method, and in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 100mTorr to 500mTorr, and the deposition temperature is controlled to be 490 ℃ to 580 ℃.
Further, in some examples of this embodiment, in the step of preparing the doped polysilicon material layer, the gas pressure within the deposition chamber may be controlled to be 100mTorr, 150mTorr, 200mTorr, 250mTorr, 300mTorr, 400mTorr, 500mTorr, or alternatively, the gas pressure within the deposition chamber may be controlled to be within a range between any two of the above.
Further, in some examples of this embodiment, in the step of preparing the doped polysilicon material layer, the deposition temperature may be controlled to be preferably 490 ℃, 500 ℃, 510 ℃, 520 ℃, 530 ℃, 540 ℃, 550 ℃, 560 ℃, 570 ℃, 580 ℃, 590 ℃, or the deposition temperature may be controlled to be within a range between any two of the above.
In some examples of this embodiment, in the step of preparing the doped polysilicon material layer, the flow rate of the silicon source may be controlled to be 100sccm to 800sccm and the flow rate of the doping source may be controlled to be 100sccm to 500sccm.
Further, in some examples of this embodiment, the flow rate of the silicon source may be controlled to be 100sccm, 200sccm, 300sccm, 400sccm, 500sccm, 600sccm, 700sccm, 800sccm, or the flow rate of the silicon source may be controlled to be in a range between any two of the above.
Further, in some examples of this embodiment, in the step of preparing the doped polysilicon material layer, the flow rate of the doping source may be controlled to be 100sccm, 150sccm, 200sccm, 300sccm, 350sccm, 400sccm, 450sccm, 500sccm, or the flow rate of the doping source may be controlled to be in a range between any two of the above.
In some examples of this embodiment, the deposition time may be controlled to be 30min to 800min. For example, the deposition time may be controlled to be 30min, 50min, 100min, 200min, 300min, 500min, 700min, 800min, or the deposition time may be controlled to be within a range between any two of the above-described deposition times.
Alternatively, in this embodiment, a doped polysilicon material layer may be prepared by a plasma enhanced chemical vapor deposition method, and in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 1000mTorr to 5000mTorr, the deposition temperature is controlled to be 300 ℃ to 550 ℃, and the deposition power is controlled to be 5000W to 15000W.
Further, in some examples of this embodiment, in the step of preparing the doped polysilicon material layer, the gas pressure within the deposition chamber may be controlled to be 1000mTorr, 1200mTorr, 1500mTorr, 2000mTorr, 2500mTorr, 3000mTorr, 3500mTorr, 4000mTorr, 4500mTorr, 5000mTorr, or alternatively, the gas pressure within the deposition chamber may be controlled to be within a range between any two of the above gas pressures.
Further, in some examples of this embodiment, in the step of preparing the doped polysilicon material layer, the deposition temperature may be controlled to be 300 ℃, 350 ℃, 400 ℃, 450 ℃, 500 ℃, 550 ℃, or the deposition temperature may be controlled to be within a range between any two of the above.
In some examples of this embodiment, the deposition power may be controlled to be 5000W to 15000W. For example, the deposition time may be controlled to be 5000W, 6000W, 7000W, 8000W, 9000W, 10000W, 11000W, 12000W, 13000W, 14000W, 15000W, or the deposition power may be controlled to be within a range between any two of the above. By controlling the deposition power to be lower, the crystallization rate of the prepared polysilicon material layer can be lower.
In some examples of this embodiment, the silicon source is controlled to have a flow rate of 1000sccm to 5000sccm and the dopant source is controlled to have a flow rate of 100sccm to 1000sccm.
Further, in the step of preparing the doped polysilicon material layer, the flow rate of the silicon source may be controlled to be 1000sccm, 2000sccm, 3000sccm, 4000sccm, 5000sccm, or the flow rate of the silicon source may be controlled to be within a range between any two of the above.
Further, in the step of preparing the doped polysilicon material layer, the flow rate of the doping source may be controlled to be 100sccm, 200sccm, 300sccm, 400sccm, 500sccm, 600sccm, 700sccm, 800sccm, 900sccm, 1000sccm, or the flow rate of the doping source may be controlled to be within a range between any two of the above.
It will be appreciated that by either the low pressure chemical vapor deposition method or the plasma deposition method described above, a doped polysilicon material layer having a crystallization rate of less than 35% can be prepared, into which the p-type doping element is in situ doped.
And S2.2, performing heat treatment on the doped polysilicon material layer.
The heat treatment refers to a treatment mode of heating the doped polysilicon material layer and then cooling the doped polysilicon material layer. In some examples of this embodiment, silicon atoms in the doped polysilicon material layer and dopant atoms can be redistributed during the heat treatment process, thereby effectively increasing the crystallization rate of the prepared p-type polysilicon layer.
In some examples of this embodiment, the heat treatment temperature is controlled to be 800 ℃ to 1000 ℃ during the heat treatment of the doped polysilicon material layer. By controlling the heat treatment temperature during the heat treatment, the crystallization rate of the final p-type polysilicon layer can be ensured while doping atoms are embedded in the silicon lattice.
In some examples of this embodiment, during the heat treatment of the doped polysilicon material layer, the heat treatment temperature may be controlled to be 800 ℃, 820 ℃, 850 ℃, 880 ℃, 900 ℃, 920 ℃, 950 ℃, 980 ℃, 1000 ℃, or the annealing temperature may be controlled to be in a range between any two of the above temperatures.
It will be appreciated that the preparation of the p-type polysilicon layer can be accomplished through steps S2.1-S2.2. The p-type crystalline silicon film of the present disclosure may include the p-type polycrystalline silicon layer.
Further, the present disclosure also provides a p-type crystalline silicon film including a p-type polycrystalline silicon layer. The p-type polysilicon layer contains p-type doping elements, and the crystallization rate of the p-type polysilicon layer is more than 90%. Further, the crystallization rate of the p-type polysilicon layer may be 90%, 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, 99%, or the thickness of the p-type polysilicon layer may be in a range between any two of the above thicknesses.
Further, the p-type crystalline silicon film can be prepared by the preparation method of the p-type crystalline silicon film in any embodiment.
Further, the present disclosure also provides a semiconductor device that may include a p-type crystalline silicon film as in any of the embodiments described above. It can be appreciated that the p-type crystalline silicon film can be used as a functional layer in the semiconductor device, which has a higher crystallization rate and a higher carrier mobility, so that the electrical performance of the semiconductor device can be improved.
In some examples of this embodiment, the semiconductor device may be a solar cell or a field effect transistor. Further, the solar cell may be a crystalline silicon solar cell, and the specific structure thereof may be designed with reference to the structure of the existing solar cell, which is not described herein.
In order to facilitate the explanation of the preparation method of the p-type crystalline silicon thin film of the present disclosure and the advantages thereof, the present disclosure also provides the following examples and comparative examples.
Preparing a substrate
Providing an n-type monocrystalline silicon piece, performing damage removal treatment and polishing treatment by using a KOH solution with the mass concentration of 10%, wherein the process time is 2-10 min, the process temperature is 50-80 ℃, and cleaning the n-type monocrystalline silicon piece;
placing the cleaned silicon wafer in a thermal oxidation chamber, introducing oxygen with the flow of 10000sccm, heating the thermal oxidation chamber to 600 ℃, and keeping the reaction for 30min to form a tunneling oxide layer on the surface of the n-type monocrystalline silicon wafer as a substrate.
Example 1
Placing a substrate in a deposition chamber of low-pressure chemical vapor deposition equipment, and introducing silane into the deposition chamber;
controlling the air pressure in the deposition chamber to be 300mTorr, controlling the deposition temperature of the deposition chamber to be 570 ℃, controlling the silane flow to be 500sccm, and controlling the deposition time to be 100min to form an intrinsic polycrystalline silicon material layer;
Transferring the substrate into a diffusion chamber, controlling the temperature of the diffusion chamber to 850 ℃, introducing boron trichloride into the diffusion chamber by taking nitrogen as carrier gas, introducing oxygen, wherein the flow rate of the carrier gas is 200sccm, the flow rate of the oxygen is 800sccm, controlling the pressure of the diffusion chamber to 200mbar, and forming boron oxide as a diffusion layer on the surface of the intrinsic polycrystalline silicon material layer;
and controlling the temperature of the diffusion chamber to be increased to 950 ℃ to perform junction pushing treatment, so that boron atoms are diffused into the intrinsic polycrystalline silicon material layer, naturally cooling the diffusion chamber, and completing annealing treatment to form the p-type polycrystalline silicon layer.
Example 2
Placing a substrate in a deposition chamber of low-pressure chemical vapor deposition equipment, and introducing silane into the deposition chamber;
controlling the air pressure in the deposition chamber to be 200mTorr, controlling the deposition temperature of the deposition chamber to be 540 ℃, controlling the silane flow to be 500sccm, and controlling the deposition time to be 300min to form an intrinsic polycrystalline silicon material layer;
transferring the substrate into a diffusion chamber, controlling the temperature of the diffusion chamber to 850 ℃, introducing boron trichloride into the diffusion chamber by taking nitrogen as carrier gas, introducing oxygen, wherein the flow rate of the carrier gas is 200sccm, the flow rate of the oxygen is 800sccm, controlling the pressure of the diffusion chamber to 200mbar, and forming boron oxide as a diffusion layer on the surface of the intrinsic polycrystalline silicon material layer;
And controlling the temperature of the diffusion chamber to be increased to 950 ℃ to perform junction pushing treatment, so that boron atoms are diffused into the intrinsic polycrystalline silicon material layer, naturally cooling the diffusion chamber, and completing annealing treatment to form the p-type polycrystalline silicon layer.
Example 3
Placing a substrate in a deposition chamber of low-pressure chemical vapor deposition equipment, and introducing silane into the deposition chamber;
controlling the air pressure in the deposition chamber to be 300mTorr, controlling the deposition temperature of the deposition chamber to be 580 ℃, controlling the silane flow to be 500sccm, and controlling the deposition time to be 100min to form an intrinsic polycrystalline silicon material layer;
transferring the substrate into a diffusion chamber, controlling the temperature of the diffusion chamber to 850 ℃, introducing boron trichloride into the diffusion chamber by taking nitrogen as carrier gas, introducing oxygen, wherein the flow rate of the carrier gas is 200sccm, the flow rate of the oxygen is 800sccm, controlling the pressure of the diffusion chamber to 200mbar, and forming boron oxide as a diffusion layer on the surface of the intrinsic polycrystalline silicon material layer;
and controlling the temperature of the diffusion chamber to be increased to 950 ℃ to perform junction pushing treatment, so that boron atoms are diffused into the intrinsic polycrystalline silicon material layer, naturally cooling the diffusion chamber, and completing annealing treatment to form the p-type polycrystalline silicon layer.
Example 4
Placing a substrate in a deposition chamber of low-pressure chemical vapor deposition equipment, and introducing silane and borane into the deposition chamber;
Controlling the air pressure in the deposition chamber to be 300mTorr, controlling the deposition temperature of the deposition chamber to be 570 ℃, controlling the silane flow to be 500sccm, controlling the borane flow to be 300sccm, and controlling the deposition time to be 300min to form a boron doped polysilicon material layer;
transferring the substrate into an annealing furnace tube, controlling the temperature of an annealing furnace tube to be increased to 980 ℃, naturally cooling the diffusion chamber, and completing annealing treatment to form a p-type polycrystalline silicon layer.
Comparative example 1
Placing a substrate in a deposition chamber of low-pressure chemical vapor deposition equipment, and introducing silane into the deposition chamber;
controlling the air pressure in the deposition chamber to be 300mTorr, controlling the deposition temperature of the deposition chamber to be 620 ℃, controlling the silane flow to be 500sccm, and controlling the deposition time to be 100min to form an intrinsic polycrystalline silicon material layer;
transferring the substrate into a diffusion chamber, controlling the temperature of the diffusion chamber to 850 ℃, introducing boron trichloride into the diffusion chamber by taking nitrogen as carrier gas, introducing oxygen, wherein the flow rate of the carrier gas is 200sccm, the flow rate of the oxygen is 800sccm, controlling the pressure of the diffusion chamber to 200mbar, and forming boron oxide as a diffusion layer on the surface of the intrinsic polycrystalline silicon material layer;
and controlling the temperature of the diffusion chamber to be increased to 950 ℃ to perform junction pushing treatment, so that boron atoms are diffused into the intrinsic polycrystalline silicon material layer, naturally cooling the diffusion chamber, and completing annealing treatment to form the p-type polycrystalline silicon layer.
Comparative example 2
Placing a substrate in a deposition chamber of low-pressure chemical vapor deposition equipment, and introducing silane into the deposition chamber;
controlling the air pressure in the deposition chamber to be 300mTorr, controlling the deposition temperature of the deposition chamber to be 630 ℃, controlling the silane flow to be 500sccm, and controlling the deposition time to be 100min to form an intrinsic polycrystalline silicon material layer;
transferring the substrate into a diffusion chamber, controlling the temperature of the diffusion chamber to 850 ℃, introducing boron trichloride into the diffusion chamber by taking nitrogen as carrier gas, introducing oxygen, wherein the flow rate of the carrier gas is 200sccm, the flow rate of the oxygen is 800sccm, controlling the pressure of the diffusion chamber to 200mbar, and forming boron oxide as a diffusion layer on the surface of the intrinsic polycrystalline silicon material layer;
and controlling the temperature of the diffusion chamber to be increased to 950 ℃ to perform junction pushing treatment, so that boron atoms are diffused into the intrinsic polycrystalline silicon material layer, naturally cooling the diffusion chamber, and completing annealing treatment to form the p-type polycrystalline silicon layer.
Comparative example 3
Placing a substrate in a deposition chamber of low-pressure chemical vapor deposition equipment, and introducing silane into the deposition chamber;
controlling the air pressure in the deposition chamber to be 700mTorr, controlling the deposition temperature of the deposition chamber to be 620 ℃, controlling the silane flow to be 500sccm, and controlling the deposition time to be 100min to form an intrinsic polycrystalline silicon material layer;
Transferring the substrate into a diffusion chamber, controlling the temperature of the diffusion chamber to 850 ℃, introducing boron trichloride into the diffusion chamber by taking nitrogen as carrier gas, introducing oxygen, wherein the flow rate of the carrier gas is 200sccm, the flow rate of the oxygen is 800sccm, controlling the pressure of the diffusion chamber to 200mbar, and forming boron oxide as a diffusion layer on the surface of the intrinsic polycrystalline silicon material layer;
and controlling the temperature of the diffusion chamber to be increased to 950 ℃ to perform junction pushing treatment, so that boron atoms are diffused into the intrinsic polycrystalline silicon material layer, naturally cooling the diffusion chamber, and completing annealing treatment to form the p-type polycrystalline silicon layer.
Comparative example 4
Placing a substrate in a deposition chamber of low-pressure chemical vapor deposition equipment, and introducing silane into the deposition chamber;
controlling the air pressure in the deposition chamber to be 700mTorr, controlling the deposition temperature of the deposition chamber to be 620 ℃, controlling the silane flow to be 500sccm, and controlling the deposition time to be 100min to form an intrinsic polycrystalline silicon material layer;
transferring the substrate into a diffusion chamber, controlling the temperature of the diffusion chamber to 850 ℃, introducing boron trichloride into the diffusion chamber by taking nitrogen as carrier gas, introducing oxygen, wherein the flow rate of the carrier gas is 200sccm, the flow rate of the oxygen is 800sccm, controlling the pressure of the diffusion chamber to 200mbar, and forming boron oxide as a diffusion layer on the surface of the intrinsic polycrystalline silicon material layer;
And controlling the temperature of the diffusion chamber to be increased to 950 ℃ to perform junction pushing treatment, so that boron atoms are diffused into the intrinsic polycrystalline silicon material layer, naturally cooling the diffusion chamber, and completing annealing treatment to form the p-type polycrystalline silicon layer.
Comparative example 5
Placing a substrate in a deposition chamber of low-pressure chemical vapor deposition equipment, and introducing silane into the deposition chamber;
controlling the air pressure in the deposition chamber to be 700mTorr, controlling the deposition temperature of the deposition chamber to be 595 ℃, controlling the silane flow to be 500sccm, and controlling the deposition time to be 100min to form an intrinsic polycrystalline silicon material layer;
transferring the substrate into a diffusion chamber, controlling the temperature of the diffusion chamber to 850 ℃, introducing boron trichloride into the diffusion chamber by taking nitrogen as carrier gas, introducing oxygen, wherein the flow rate of the carrier gas is 200sccm, the flow rate of the oxygen is 800sccm, controlling the pressure of the diffusion chamber to 200mbar, and forming boron oxide as a diffusion layer on the surface of the intrinsic polycrystalline silicon material layer;
and controlling the temperature of the diffusion chamber to be increased to 950 ℃ to perform junction pushing treatment, so that boron atoms are diffused into the intrinsic polycrystalline silicon material layer, naturally cooling the diffusion chamber, and completing annealing treatment to form the p-type polycrystalline silicon layer.
And (3) testing: the crystallization rate 1 of the polycrystalline silicon material layer and the crystallization rate 2 of the p-type polycrystalline silicon layer prepared in the above examples and comparative examples were tested, and the carrier mobility of the p-type polycrystalline silicon layer prepared in the above examples and comparative examples was tested, and the results can be seen in table 1.
TABLE 1
| Crystallization Rate 1 | Crystallization Rate 2 | Carrier mobility (cm) 2 ·V -1 ·s -1 ) | |
| Example 1 | 12.8％ | 96.1％ | 28.7 |
| Example 2 | 1.0％ | 98.3％ | 30.5 |
| Example 3 | 20.1％ | 94.1％ | 27.3 |
| Example 4 | 10.5％ | 97.1％ | 29.5 |
| Comparative example 1 | 78.5％ | 80.3％ | 15.7 |
| Comparative example 2 | 81.5％ | 80.7％ | 13.2 |
| Comparative example 3 | 65.2％ | 82.7％ | 17.5 |
| Comparative example 4 | 71.9％ | 81.4％ | 16.1 |
| Comparative example 5 | 45.3％ | 85.8％ | 19.2 |
As shown in table 1, the crystallization rates of the polysilicon material layers prepared in examples 1 to 3 were all controlled to 35% or less, and accordingly, the crystallization rate of the p-type polysilicon layer obtained after the heat treatment could be 90% or more. The crystallization rate of the polysilicon material layers prepared in comparative examples 1 to 5 is significantly higher, but the crystallization rate of the p-type polysilicon layer obtained after heat treatment is limited or substantially cannot be significantly improved. Therefore, by controlling the crystallization rate of the initially prepared polysilicon material layer to be low, the finally prepared p-type polysilicon layer can be made to have a crystallization rate of 90% or more. Note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.
It should be understood that the steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the preparation process may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the sub-steps or stages are performed is not necessarily sequential, and may be performed in turn or alternately with at least a portion of the sub-steps or stages of other steps or steps.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
Claims (14)
1. The preparation method of the p-type crystalline silicon film is characterized by comprising the following steps:
preparing a polysilicon material layer with crystallization rate less than or equal to 35% on a substrate;
the polycrystalline silicon material layer is an intrinsic polycrystalline silicon material layer, p-type doping elements are doped into the intrinsic polycrystalline silicon material layer, and heat treatment is carried out to form a p-type polycrystalline silicon layer with the crystallization rate of more than 90%; or alternatively, the first and second heat exchangers may be,
the polysilicon material layer is a doped polysilicon material layer containing p-type doping elements, and the doped polysilicon material layer is subjected to heat treatment to form the p-type polysilicon layer with the crystallization rate of more than 90%.
2. The method of claim 1, wherein the polysilicon material layer is an intrinsic polysilicon material layer, the intrinsic polysilicon material layer is prepared by chemical vapor deposition, and a reaction raw material including a silicon source is introduced into the deposition chamber in the step of preparing the intrinsic polysilicon material layer.
3. The method of claim 2, wherein the intrinsic polycrystalline silicon material layer is prepared by low-pressure chemical vapor deposition, and wherein in the step of preparing the intrinsic polycrystalline silicon material layer, the gas pressure in the deposition chamber is controlled to be 100mTorr to 500mTorr, and the deposition temperature is controlled to be 490 ℃ to 610 ℃.
4. A method of producing a p-type crystalline silicon thin film according to any one of claims 1 to 3, wherein the step of doping a p-type doping element into the intrinsic polycrystalline silicon material layer and performing a heat treatment comprises:
placing the substrate with the intrinsic polycrystalline silicon material layer in a diffusion chamber, introducing a doping source containing the p-type doping element into the diffusion chamber, and forming a diffusion layer containing the p-type doping element on the intrinsic polycrystalline silicon layer;
and heating the intrinsic polycrystalline silicon material layer and the diffusion layer to perform junction pushing treatment, and enabling the p-type doping element to be diffused and doped into the intrinsic polycrystalline silicon material layer in the junction pushing treatment process to form the p-type polycrystalline silicon layer.
5. The method for producing a p-type crystalline silicon thin film according to claim 4, wherein in forming a diffusion layer containing the p-type doping element on the intrinsic polycrystalline silicon layer, the temperature in the diffusion chamber is controlled to be 700 ℃ to 890 ℃;
In the process of pushing and knot treatment, the knot pushing temperature is controlled to be 850-960 ℃.
6. The method for preparing a p-type crystalline silicon thin film according to claim 1, wherein the polysilicon material layer is a doped polysilicon material layer containing a p-type doping element, the doped polysilicon material layer is prepared by a chemical vapor deposition method, and in the step of preparing the doped polysilicon material layer, a reaction raw material including a silicon source and a doping source including the p-type doping element is introduced into a deposition chamber.
7. The method of claim 6, wherein the doped polysilicon material layer is prepared by low-pressure chemical vapor deposition, and in the step of preparing the doped polysilicon material layer, the air pressure in the deposition chamber is controlled to be 100mTorr to 500mTorr, and the deposition temperature is controlled to be 490 ℃ to 610 ℃; or alternatively, the first and second heat exchangers may be,
and preparing the doped polysilicon material layer by adopting a plasma enhanced chemical vapor deposition method, wherein in the step of preparing the doped polysilicon material layer, the air pressure in the deposition chamber is controlled to be 1000 mTorr-5000 mTorr, the deposition temperature is controlled to be 300-550 ℃, and the deposition power is controlled to be 5000-15000W.
8. The method for producing a p-type crystalline silicon thin film according to any one of claims 1 and 6 to 7, wherein a heat treatment temperature is controlled to be 800 ℃ to 1000 ℃ in the process of heat-treating the doped polysilicon material layer.
9. The method for producing a p-type crystalline silicon thin film according to any one of claims 1 to 3 and 5 to 7, wherein the p-type doping element is one or more selected from boron and gallium.
10. The method for preparing a p-type crystalline silicon film according to any one of claims 1 to 3 and 5 to 7, wherein the substrate comprises an n-type silicon wafer and a tunneling oxide layer laminated on the n-type silicon wafer, and the polysilicon material layer is prepared on a side of the tunneling oxide layer away from the n-type silicon wafer.
11. The p-type crystalline silicon film is characterized by comprising a p-type polycrystalline silicon layer, wherein the p-type polycrystalline silicon layer contains p-type doping elements, and the crystallization rate of the p-type polycrystalline silicon layer is more than 90%.
12. The p-type crystalline silicon film according to claim 11, wherein the p-type crystalline silicon film is produced by the production method of the p-type crystalline silicon film according to any one of claims 1 to 10.
13. A semiconductor device comprising the p-type crystalline silicon film according to claim 11 or 12.
14. The semiconductor device according to claim 13, wherein the semiconductor device is a solar cell or a field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311268055.6A CN117198873A (en) | 2023-09-27 | 2023-09-27 | P-type crystalline silicon film, preparation method thereof and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311268055.6A CN117198873A (en) | 2023-09-27 | 2023-09-27 | P-type crystalline silicon film, preparation method thereof and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117198873A true CN117198873A (en) | 2023-12-08 |
Family
ID=89005298
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311268055.6A Pending CN117198873A (en) | 2023-09-27 | 2023-09-27 | P-type crystalline silicon film, preparation method thereof and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117198873A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117594669A (en) * | 2024-01-19 | 2024-02-23 | 浙江晶科能源有限公司 | Solar cell, preparation method thereof, laminated cell and photovoltaic module |
-
2023
- 2023-09-27 CN CN202311268055.6A patent/CN117198873A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117594669A (en) * | 2024-01-19 | 2024-02-23 | 浙江晶科能源有限公司 | Solar cell, preparation method thereof, laminated cell and photovoltaic module |
| CN117594669B (en) * | 2024-01-19 | 2024-05-17 | 浙江晶科能源有限公司 | Solar cell, preparation method thereof, laminated cell and photovoltaic module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI595537B (en) | Method of semiconductor film stabilization | |
| TWI442448B (en) | Methdos to fabricate mosfet devices using selective deposition processes | |
| TWI741121B (en) | Method and apparatus for selective epitaxy | |
| CN100365766C (en) | Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer | |
| TW200834675A (en) | Formation of epitaxial layers containing silicon and carbon | |
| CN117198873A (en) | P-type crystalline silicon film, preparation method thereof and semiconductor device | |
| US7029995B2 (en) | Methods for depositing amorphous materials and using them as templates for epitaxial films by solid phase epitaxy | |
| CN102206799B (en) | Surface passivation method for germanium-based MOS (Metal Oxide Semiconductor) device substrate | |
| US10665693B2 (en) | Semiconductor structure and manufacturing method thereof | |
| CN101393862A (en) | Manufacturing method for gate lateral wall layer and semi-conductor device | |
| TW201030854A (en) | Semiconductor device manufacturing method, semiconductor device and semiconductor device manufacturing installation | |
| CN113782423B (en) | Impurity diffusion method and solar cell manufacturing method | |
| US8759201B2 (en) | Method of forming high growth rate, low resistivity germanium film on silicon substrate | |
| JP2001085427A (en) | Oxynitride film and forming method therefor | |
| JP2010016298A (en) | Method of forming thin metal oxide film | |
| WO2022158148A1 (en) | Method for manufacturing epitaxial wafer | |
| JP2003209059A (en) | Epitaxial silicon single crystal wafer and method of manufacturing the same | |
| KR20160057522A (en) | Manufacturing Method of SiC Based Semiconductor Devices | |
| JP2001110750A5 (en) | ||
| JP2022125625A (en) | Manufacturing method for epitaxial wafer | |
| JP7247902B2 (en) | Epitaxial wafer manufacturing method | |
| JP2005079134A (en) | Semiconductor substrate and its producing process | |
| US20200283896A1 (en) | Methods for low temperature silicide formation | |
| JP2701793B2 (en) | Method for manufacturing semiconductor device | |
| CN112136203A (en) | Method for manufacturing SiC epitaxial substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |