CN117193467A - Low-dropout voltage stabilizing circuit and control method thereof - Google Patents

Abstract

The present disclosure relates to a low dropout voltage regulator circuit and a control method thereof. The low-dropout voltage stabilizing circuit comprises a reference circuit, an amplifying circuit, a power switch circuit, a feedback circuit and a control circuit. The reference circuit is used for generating a reference voltage. The amplifying circuit is used for generating an amplifying voltage according to the reference voltage and a feedback voltage. The power switch circuit is used for receiving the amplified voltage and generating an output voltage at an output end according to an input voltage. The feedback circuit is used for generating a feedback voltage according to the output voltage. The control circuit is used for controlling the power switch circuit according to the input voltage and a signal from the reference circuit.

Description

Low-dropout voltage stabilizing circuit and control method thereof

Technical Field

The present disclosure relates to a low dropout voltage regulator circuit and a control method thereof. In particular to a low-voltage-drop voltage-stabilizing circuit capable of avoiding large surge current from flowing through a power switch circuit in the initial power-on process and a control method thereof.

Background

With the development of technology, various integrated circuits have been developed. However, the performance of many integrated circuits remains to be improved.

For example, in some prior art, during an initial power-up process (initial ramp-up process of an input voltage) of the low-voltage-drop voltage regulator, a large surge current (inrush current) flows through a power switch circuit in the low-voltage-drop voltage regulator, and the component or the metal wire may be burned out by the large surge current.

Disclosure of Invention

Some embodiments of the present disclosure relate to a low dropout voltage regulator circuit. The low-dropout voltage stabilizing circuit comprises a reference circuit, an amplifying circuit, a power switch circuit, a feedback circuit and a control circuit. The reference circuit is used for generating a reference voltage. The amplifying circuit is used for generating an amplifying voltage according to the reference voltage and a feedback voltage. The power switch circuit is used for receiving the amplified voltage and generating an output voltage at an output end according to an input voltage. The feedback circuit is used for generating a feedback voltage according to the output voltage. The control circuit is used for controlling the power switch circuit according to the input voltage and a signal from the reference circuit.

Some embodiments of the present disclosure relate to a control method of a low dropout voltage regulator circuit. The control method comprises the following operations: generating a reference voltage by a reference circuit; generating an amplified voltage by an amplifying circuit according to the reference voltage and a feedback voltage; receiving the amplified voltage by a power switch circuit and generating an output voltage at an output end according to an input voltage; generating a feedback voltage according to the output voltage by a feedback circuit; the power switch circuit is controlled by a control circuit according to the input voltage and a signal from the reference circuit.

In summary, in the low dropout voltage regulator circuit of the present disclosure, the control circuit may control the power switch circuit according to the input voltage and the signal from the reference circuit, so that the current flowing through the power switch circuit is smaller during the initial power-up process of the low dropout voltage regulator circuit, thereby avoiding a large surge current.

Drawings

The foregoing and other objects, features, advantages and embodiments of the present disclosure will be apparent from the following description of the drawings in which:

FIG. 1 is a schematic diagram of a LDO according to some embodiments of the present disclosure;

FIG. 2 is a circuit diagram of a LDO according to some embodiments of the present disclosure;

FIG. 3 is a circuit diagram of a LDO according to some embodiments of the present disclosure;

FIG. 4 is a circuit diagram of a LDO according to some embodiments of the present disclosure; and

fig. 5 is a flow chart of a control method according to some embodiments of the present disclosure.

Detailed Description

The term "coupled" as used herein may also refer to "electrically coupled" and the term "connected" may also refer to "electrically connected". "coupled" and "connected" may also refer to two or more components cooperating or interacting with each other.

Reference is made to fig. 1. Fig. 1 is a schematic diagram of a low dropout voltage regulator circuit 100 according to some embodiments of the present disclosure.

By way of example, the low dropout regulator 100 includes a reference circuit 102, an amplifier circuit 104, a power switch circuit 106, a feedback circuit 108, and a control circuit 110.

The reference circuit 102 is coupled to the amplifying circuit 104. The amplifying circuit 104 is coupled to the power switch circuit 106 and the feedback circuit 108. The power switch circuit 106 is coupled to the feedback circuit 108 and the control circuit 110. The load L is coupled between the output terminal OUT and the ground terminal GND. The external capacitor CEX may be disposed on a printed circuit board, a first end of the capacitor CEX is coupled to a pin (pin) of the output terminal OUT through a parasitic resistor RS of the component or the metal trace, and a second end of the capacitor CEX may be coupled to the ground terminal GND. The external capacitor CEX is used to stabilize the output voltage VO.

The reference circuit 102 operates according to the input voltage AVDD and is used to generate the reference voltage VBG. In the example of fig. 1, during the power-up process of the low dropout voltage regulator 100, the input voltage AVDD will rise from 0 v to 5 v, but the disclosure is not limited to this voltage value. Other suitable voltage values are also within the scope of the present disclosure.

The amplifying circuit 104 operates according to the input voltage AVDD and includes a positive input terminal and a negative input terminal. The negative input of the amplifying circuit 104 receives the reference voltage VBG from the reference circuit 102 and the positive input of the amplifying circuit 104 receives the feedback voltage VFB from the feedback circuit 108. The amplifying circuit 104 is used for comparing the reference voltage VBG and the feedback voltage VFB to generate an amplified voltage VGATE. In some embodiments, the amplifying circuit 104 may be an analog amplifier.

The power switch circuit 106 is configured to receive the amplified voltage VGATE and generate an output voltage VO at an output terminal OUT according to the input voltage AVDD. The power switch circuit 106 may include at least one power switch, and the amplifying voltage VGATE may turn on the power switch, and the current flowing through the power switch may charge the output terminal OUT to generate the output voltage VO.

The feedback circuit 108 is configured to generate a feedback voltage VFB to the positive input of the amplifying circuit 104 according to the output voltage VO. For the example of fig. 1, the feedback circuit 108 includes a resistor R1, a resistor R2, and a capacitor CFB. The resistor R1 is coupled between the output terminal OUT and the feedback node N1. The resistor R2 is coupled between the feedback node N1 and the ground GND. The capacitor CFB is coupled between the output terminal OUT and the feedback node N1. Based on the ratio of the resistance values of the resistor R1 and the resistor R2, the feedback voltage VFB is generated at the feedback node N1 in response to the output voltage VO and is transmitted to the positive input terminal of the amplifying circuit 104.

The control circuit 110 is used for controlling the power switch circuit 106 according to the input voltage AVDD and the signal SS from the reference circuit 102. Details of how the control circuit 110 controls the power switch circuit 106 according to the input voltage AVDD and the signal SS will be described with reference to fig. 2 to 4.

Reference is made to fig. 2. Fig. 2 is a circuit diagram of a low dropout voltage regulator 200 according to some embodiments of the present disclosure.

In the example of fig. 2, control circuit 210 may be used to implement control circuit 110 of fig. 1. Specifically, the control circuit 210 may control the power switch circuit 206 according to the input voltage AVDD and the reference voltage VBG from the reference circuit 102. That is, in the example of FIG. 2, the reference voltage VBG from the reference circuit 102 is used to implement the signal SS in FIG. 1.

For example, as shown in fig. 2, the control circuit 210 includes a voltage divider 212, a monitor circuit 214, and a counter circuit 216.

The voltage divider 212 is used for generating a divided voltage VX according to the input voltage AVDD. For example, the voltage divider 212 includes a resistor R3, a resistor R4, and a capacitor CX. The first end of the resistor R3 is configured to receive the input voltage AVDD, the second end of the resistor R3 is coupled to the first end of the resistor R4, and the second end of the resistor R4 is coupled to the ground GND. The first end of the capacitor CX is coupled to the connection node N2 between the resistor R3 and the resistor R4, the second end of the capacitor CX is coupled to the ground GND, and the divided voltage VX is generated at the connection node N2. Under this architecture, there is a positive correlation between the divided voltage VX and the input voltage AVDD. That is, as the input voltage AVDD is higher, the divided voltage VX is also higher.

The detection circuit 214 is used for generating a detection signal DS according to the reference voltage VBG and the divided voltage VX. In some embodiments, the detection circuit 214 may be implemented using a comparator. For example, the comparator may compare the reference voltage VBG with the divided voltage VX. When the divided voltage VX is smaller than the reference voltage VBG, the comparator outputs a detection signal DS having a first logic value (e.g., logic value 0). Conversely, when the divided voltage VX is equal to or greater than the reference voltage VBG, the comparator outputs the detection signal DS having a second logic value (e.g., logic value 1). The detection signal DS having a second logic value (e.g., logic value 1) may enable the counting circuit 216 to start counting.

The counting circuit 216 is used for generating a counting signal CN according to the detection signal DS. As described above, when the divided voltage VX is equal to or greater than the reference voltage VBG, the detection signal DS having the second logic value (e.g., logic value 1) can enable the counting circuit 216 to start counting to generate the counting signal CN to control the power switch circuit 206.

For example, in FIG. 2, the power switch circuit 206 includes a power switch MP1 and power switches MP2-MP4. The power switches MP1-MP4 may be implemented using P-type transistors. The power switches MP1-MP4 are coupled in parallel. The first terminals of the power switches MP1-MP4 are used for receiving the input voltage AVDD, and the second terminals of the power switches MP1-MP4 are coupled to the output terminal OUT. The control terminal of the power switch MP1 is used for receiving the amplified voltage VGATE, and the count signal CN is used for controlling the power switches MP2-MP4.

During the initial power-up process of the low dropout voltage regulator 200, the amplified voltage VGATE may be turned on to the power switch MP1 so that the input voltage AVDD may charge the output terminal OUT with a small amplitude. At this time, since the input voltage AVDD is not large enough and the reference circuit 102 is not stable (the divided voltage VX is smaller than the reference voltage VBG), the detection circuit 214 is not yet outputting the detection signal DS with the second logic value and the counting circuit 216 is still in the disabled state. At this time, the power switches MP2-MP4 are still turned off.

After a period of time, when the input voltage AVDD is large enough (the divided voltage VX is equal to or greater than the reference voltage VBG), that is, the output voltage VO is charged to a certain voltage level and is stable. Since the divided voltage VX is equal to or greater than the reference voltage VBG, the detection circuit 214 may output the detection signal DS having the second logic value to enable the counting circuit 216 to start counting. For example, the value of the count signal CN may be increased from 0. In some embodiments, a power switch control circuit (not shown) may be coupled to the counting circuit 216. When the value of the count signal CN increases to the first value (equivalent to the first delay time), the power switch control circuit may output a control signal to turn on the power switch MP2. When the value of the count signal CN increases to the second value (equivalent to the second delay time), the power switch control circuit may output a control signal to turn on the power switch MP3. When the value of the count signal CN increases to the third value (equivalent to the third delay time), the power switch control circuit may output a control signal to turn on the power switch MP4. That is, when the input voltage AVDD is large enough (the output voltage VO is charged to a certain voltage level and is stable), more power switches are turned on, so that the current flowing through the power switch circuit 206 becomes larger gradually and the low dropout regulator 200 is capable of providing a large current to the load L for normal operation. In some other embodiments, the power switches MP2-MP4 may also be turned on at the same time.

In some embodiments, the power switches MP1-MP4 have the same gate length but different gate widths. For example, the ratio of the gate widths of the power switches MP1-MP4 may be 1:2:4:8, but the disclosure is not limited thereto. In the above example, the size of the power switch MP1 is minimized so that the current initially flowing through the power switch circuit 206 is very small. In some other embodiments, the gate widths of the power switches MP1-MP4 may be all the same.

In addition, the number of transistors in the power switch circuit 206 is only for example, and the disclosure is not limited to this number. Other suitable amounts are within the scope of this disclosure.

For example, in fig. 2, in some embodiments, the low dropout voltage regulator 200 further includes an over-current protection circuit OCP1. The first end of the over-current protection circuit OCP1 is configured to receive the input voltage AVDD, and the second end of the over-current protection circuit OCP1 is coupled to the control end of the power switch MP 1. Generally, the control circuit 210 can control the current flowing through the power switch circuit 206 during the initial power-up process of the LDO 200. The over-current protection circuit OCP1 will start to operate normally after the input voltage AVDD reaches the maximum input voltage (e.g., 5 v) to control the current flowing through the power switch circuit 206.

In some prior art, the low dropout voltage regulator circuit is provided with only an over-current protection circuit. However, as described above, the over-current protection circuit needs to start to operate normally after the input voltage exceeds a threshold voltage. If there are several transistors connected in series in the over-current protection circuit, the threshold voltage will be higher. Based on the threshold voltage, the over-current protection circuit may not be operated normally after the power switch circuit in the LDO is turned on. Accordingly, the over-current protection circuit cannot avoid a large surge current flowing through the power switch circuit in an initial power-up process (an initial rising process of an input voltage) of the low-voltage drop voltage stabilizing circuit.

In some other prior art techniques, an additional low-pass filter circuit (e.g., a resistor-capacitor circuit) is coupled to the output of the reference circuit in the LDO circuit. The additional low-pass filter circuit can enable the reference voltage output by the reference circuit to climb more slowly, so that the power switch circuit charges the output end slowly until the output voltage is stable. However, the additional low pass filter circuit may occupy a large circuit area.

In comparison with the above prior art, in the present disclosure, the control circuit 210 can control the current flowing through the power switch circuit 206 to be smaller during the initial power-up process of the low dropout regulator 200. In this way, a large surge current is prevented from flowing through the power switch circuit 206 during the initial power-up process. In addition, the present disclosure does not require an additional low pass filter circuit, and thus does not increase excessive circuit area.

Reference is made to fig. 3. Fig. 3 is a circuit diagram of a low dropout voltage regulator circuit 300 according to some embodiments of the present disclosure.

One of the main differences between the LDO 300 of FIG. 3 and the LDO 200 of FIG. 2 is that the power switch 306 includes a power switch MP5. The power switch MP5 may be implemented with a P-type transistor. The power switch MP5 includes a first terminal, a second terminal, and a control terminal. The first terminal of the power switch MP5 is configured to receive the input voltage AVDD, the second terminal of the power switch MP5 is coupled to the output terminal OUT, and the control terminal of the power switch MP5 is coupled to the output terminal of the amplifying circuit 104.

Another major difference between the low dropout regulator 300 of fig. 3 and the low dropout regulator 200 of fig. 2 is that the control circuit 310 is configured to implement the control circuit 110 of fig. 1. The control circuit 310 includes the control circuit 210, the additional switch SW, and the transistor MD in fig. 2. The switch SW includes a first terminal and a second terminal. The transistor MD includes a first terminal, a second terminal and a control terminal. The first terminal of the switch SW is used for receiving the input voltage AVDD, and the second terminal of the switch SW is coupled to the first terminal of the transistor MD. The control terminal of the transistor MD is coupled to the second terminal of the transistor MD to form a diode connection (diode). The second terminal of the transistor MD is coupled to the control terminal of the power switch MP5.

In some embodiments, the implementation of the control circuit 210 in fig. 3 is the same as the control circuit 210 in fig. 2. In fig. 3, the counting signal CN output by the control circuit 210 is used to control the switch SW.

During initial power-up of the LDO 300, the switch SW may be turned on to limit the gate-source voltage of the power switch MP5 so that the current flowing through the power switch 306 is not too large.

Similar to fig. 2, after a period of time, the input voltage AVDD is sufficiently large (the divided voltage VX is equal to or greater than the reference voltage VBG). That is, the output voltage VO is charged to a certain voltage level and is relatively stable. The detection circuit 214 may output the detection signal DS having the second logic value to enable the counting circuit 216 to start counting. For example, the value of the count signal CN may be increased from 0. In some embodiments, a switch control circuit (not shown) may be coupled to the counting circuit 216. When the value of the count signal CN increases to a specific value (equivalent to a delay time), the switch control circuit may output a control signal to turn off the switch SW. When the switch SW is turned off, the current flowing through the power switch circuit 306 will become larger, so that the low dropout voltage regulator 300 can provide a large current to the load L for normal operation.

For example, in fig. 3, in some embodiments, the low dropout voltage regulator circuit 300 further includes an over-current protection circuit OCP2. The first end of the over-current protection circuit OCP2 is configured to receive the input voltage AVDD, and the second end of the over-current protection circuit OCP2 is coupled to the control end of the power switch MP5. Generally, the control circuit 310 can control the current flowing through the power switch circuit 306 during the initial power-up process of the LDO 300. The over-current protection circuit OCP2 can start to operate normally after the input voltage AVDD reaches the maximum input voltage (e.g., 5 v) to control the current flowing through the power switch circuit 306.

Similarly, during initial power up of the LDO 300, the current flowing through the power switch circuit 306 is small. In this way, a large surge current is prevented from flowing through the power switch circuit 306 during the initial power-up process. In addition, the present disclosure does not require an additional low pass filter circuit, and thus does not increase excessive circuit area.

Refer to fig. 4. Fig. 4 is a circuit diagram of a low dropout voltage regulator circuit 400 according to some embodiments of the present disclosure.

The following description is mainly directed to the differences between the low dropout regulator circuit 400 and the foregoing embodiments. Other portions of the LDO 400 similar to those of the previous embodiments are not described herein.

For the example of fig. 4, the reference circuit 402 includes a current mirror. The current mirror in reference circuit 402 may provide reference current IX. In some embodiments, the reference circuit 402 may also be used to implement the reference circuit 102 of fig. 2 and 3.

In the example of fig. 4, the control circuit 410 is used to implement the control circuit 110 of fig. 1. The control circuit 410 may control the power switch circuit 406 according to the input voltage AVDD and the reference current IX from the reference circuit 402. That is, in the example of fig. 4, reference current IX from reference circuit 402 is used to implement signal SS in fig. 1.

The power switch circuit 406 includes a power switch MP6. The power switch MP6 may be implemented with a P-type transistor. The power switch MP6 includes a first terminal, a second terminal, and a control terminal. The first terminal of the power switch MP6 is configured to receive the input voltage AVDD, the second terminal of the power switch MP6 is coupled to the output terminal OUT, and the control terminal of the power switch MP6 is coupled to the output terminal of the amplifying circuit 104.

The control circuit 410 includes a transistor MR and a capacitor CR. The transistor MR includes a first terminal, a second terminal and a control terminal. The first end of the transistor MR is used for receiving the input voltage AVDD. A second terminal of the transistor MR is coupled to the control terminal of the power switch MP6. The reference circuit 402, the control terminal of the transistor MR and the first terminal of the capacitor CR are coupled to the node N3. The second terminal of the capacitor CR is coupled to the ground GND. Node voltage VR at node N3 initially has a first logic value (e.g., logic value 0) and reference current IX from reference circuit 402 may be used to charge node N3.

During the initial power-up of the LDO 400, the input voltage AVDD may rise from 0 volts to the threshold voltage of the transistor MR. Since the node voltage VR at the node N3 initially has a first logic value (e.g., logic value 0), the transistor MR is turned on. At this point the power switch MP6 will be turned off. When the reference circuit 402 stabilizes, the reference circuit 402 generates a weak reference current IX to slowly charge the node N3. During the charging process, the gate-source voltage of the transistor MR becomes gradually smaller. Accordingly, the equivalent resistance RR of the transistor MR becomes gradually larger. This increases the difference between the input voltage AVDD and the amplified voltage VGATE, and thus increases the turn-on level of the power switch MP6. Accordingly, the input voltage AVDD charges the output terminal OUT. When the node voltage VR at node N3 is charged to a sufficiently high level (e.g., the difference between the input voltage AVDD and the node voltage VR is less than the absolute value of the threshold voltage of transistor MR), the power switch MP6 will be able to supply a large current to the load L.

For example, in fig. 4, in some embodiments, the low dropout voltage regulator circuit 400 further includes an over-current protection circuit OCP3. The first end of the over-current protection circuit OCP3 is configured to receive the input voltage AVDD, and the second end of the over-current protection circuit OCP3 is coupled to the control end of the power switch MP6. Generally, the control circuit 410 can control the current flowing through the power switch circuit 406 during the initial power-up process of the LDO 400. The over-current protection circuit OCP3 may start to operate normally after the input voltage AVDD reaches the maximum input voltage (e.g., 5 v) to control the current flowing through the power switch circuit 406.

Similarly, during initial power up of the LDO 400, the current flowing through the power switch 406 is small. In this way, a large surge current is prevented from flowing through the power switch circuit 406 during the initial power-up process. In addition, the present disclosure does not require an additional low pass filter circuit, and thus does not increase excessive circuit area.

Reference is made to fig. 5. Fig. 5 is a flow chart of a control method 500 according to some embodiments of the present disclosure. Taking the example of fig. 5, the control method 500 includes operations S510, S520, S530, S540, and S550.

In some embodiments, the control method 500 may be applied to the low dropout voltage regulator 100 in fig. 1, but the disclosure is not limited thereto. For ease of understanding, the control method 500 will be described in connection with the LDO 100 of FIG. 1.

In operation S510, the reference voltage VBG is generated by the reference circuit 102. In some embodiments, the reference circuit 102 may be implemented by the reference circuit 402 in fig. 4.

In operation S520, the amplifying circuit 104 generates the amplifying voltage VGATE according to the reference voltage VBG and the feedback voltage VFB. In some embodiments, the negative input of the amplifying circuit 104 receives the reference voltage VBG, and the positive input of the amplifying circuit 104 receives the feedback voltage VFB.

In operation S530, the power switch circuit 106 receives the amplified voltage VGATE and generates the output voltage VO at the output terminal OUT according to the input voltage AVDD. In some embodiments, when the power switch circuit 106 is turned on, the input voltage AVDD may charge the output terminal OUT through the power switch circuit 106.

In operation S540, the feedback circuit 108 generates the feedback voltage VFB according to the output voltage VO. In some embodiments, the relationship between the feedback voltage VFB and the output voltage VO is related to the ratio of the resistance values of the resistors R1 and R2.

In operation S550, the control circuit 110 controls the power switch circuit 106 according to the input voltage AVDD and the signal SS from the reference circuit 102. In some embodiments (e.g., FIG. 2 and FIG. 3), the signal SS is the reference voltage VBG of the reference circuit 102. In some embodiments (e.g., FIG. 4), signal SS is a reference current IX of reference circuit 102.

In summary, in the low dropout voltage regulator circuit of the present disclosure, the control circuit may control the power switch circuit according to the input voltage and the signal from the reference circuit, so that the current flowing through the power switch circuit is smaller during the initial power-up process of the low dropout voltage regulator circuit, thereby avoiding a large surge current.

While the present disclosure has been described with reference to the embodiments, it should be understood that the invention is not limited thereto, but may be embodied with various changes and modifications within the spirit and scope of the present disclosure by those skilled in the art, and accordingly, the scope of the present disclosure is to be determined from the appended claims.

[ symbolic description ]

100,200,300,400 low-dropout voltage regulator circuit

102,402 reference circuits

104 amplifying circuit

106,206,306,406 Power switch circuit

108 feedback circuit

110,210,310,410: control circuit

212 voltage divider circuit

214 detection circuit

216 counter circuit

500 control method

AVDD: input voltage

VBG reference voltage

VFB feedback voltage

VGATE amplifying Voltage

VO: output voltage

OUT: output terminal

R1, R2, RS, R3, R4, RR: resistance

CFB, CEX, CX, CR capacitor

GND ground terminal

N1, N2, N3: nodes

SS: signal signal

L load

VX, divided voltage

DS detection signal

CN counting signal

MP1, MP2, MP3, MP4, MP5, MP6: power switch

MD, MR: transistor

OCP1, OCP2, OCP3 over-current protection circuit

SW switch

IX reference current

VR node voltage

S510, S520, S530, S540, S550.

Claims (10)

1. A low dropout voltage regulator circuit, comprising:

a reference circuit for generating a reference voltage;

an amplifying circuit for generating an amplifying voltage according to the reference voltage and a feedback voltage;

a power switch circuit for receiving the amplified voltage and generating an output voltage at an output terminal according to an input voltage;

a feedback circuit for generating the feedback voltage according to the output voltage; and

and the control circuit is used for controlling the power switch circuit according to the input voltage and a signal from the reference circuit.

2. The LDO circuit of claim 1, wherein said signal from said reference circuit is said reference voltage.

3. The low dropout voltage regulator circuit according to claim 2, wherein said control circuit comprises:

a voltage dividing circuit for generating a divided voltage according to the input voltage;

a detection circuit for generating a detection signal according to the reference voltage and the divided voltage; and

a counting circuit for generating a counting signal according to the detection signal,

the counting signal is used for controlling the power switch circuit.

4. The LDO circuit of claim 3, wherein said power switch circuit comprises a first power switch and a plurality of second power switches, a control terminal of said first power switch is used for receiving said amplified voltage, and said count signal is used for controlling said plurality of second power switches.

5. The low dropout voltage regulator circuit of claim 3, wherein said power switching circuit comprises a first power switch, and said control circuit further comprises:

a switch, including a first end and a second end, wherein the first end of the switch is used for receiving the input voltage, and the counting signal is used for controlling the switch; and

the transistor comprises a first end, a second end and a control end, wherein the first end of the transistor is coupled with the second end of the switch, the control end of the transistor is coupled with the second end of the transistor, and the second end of the transistor is coupled with a control end of the first power switch.

6. The low dropout voltage regulator circuit according to claim 4 or 5, further comprising:

the overcurrent protection circuit comprises a first end and a second end, wherein the first end of the overcurrent protection circuit is used for receiving the input voltage, and the second end of the overcurrent protection circuit is coupled with the control end of the first power switch.

7. The LDO circuit of claim 1, wherein said signal is a reference current from a current mirror in said reference circuit.

8. The low dropout voltage regulator circuit according to claim 7, wherein said power switching circuit comprises a power switch, and said control circuit further comprises:

the reference circuit is coupled with the control end of the transistor and is connected with a node; and

and a capacitor coupled between the node and a ground, wherein the reference current is used for charging the node.

9. The low dropout regulator circuit of claim 8, further comprising:

the overcurrent protection circuit comprises a first end and a second end, wherein the first end of the overcurrent protection circuit is used for receiving the input voltage, and the second end of the overcurrent protection circuit is coupled with the control end of the power switch.

10. A control method of a low dropout voltage regulator circuit, the control method comprising:

generating a reference voltage by a reference circuit;

generating an amplified voltage according to the reference voltage and a feedback voltage by an amplifying circuit;

receiving the amplified voltage by a power switch circuit and generating an output voltage at an output end according to an input voltage;

generating the feedback voltage according to the output voltage by a feedback circuit; and

the power switch circuit is controlled by a control circuit according to the input voltage and a signal from the reference circuit.