CN117178075A - 在沉积室中制造包含气相外延层的半导体晶片的方法 - Google Patents
在沉积室中制造包含气相外延层的半导体晶片的方法 Download PDFInfo
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Abstract
公开了在沉积室中生产具有从气相沉积的外延层的半导体晶片的方法，其包括通过对所述沉积室进行蚀刻，从所述沉积室中去除已经在先前的涂覆操作期间沉积在所述沉积室中的材料；连续进行涂覆操作，并且每个操作都需要在所述沉积室中将外延层沉积在衬底晶片上，包括使第一沉积气体的第一气流在所述衬底晶片上方传递，以形成具有外延层的半导体晶片；在连续进行的每个所述涂覆操作之前、期间或之后，将第二沉积气体的第二气流传递到各衬底晶片或具有外延层的各半导体晶片的边缘区域，其中对至少一个工艺参数作出改变，其效果是，经由所述第二沉积气体的传递，所述边缘区域中的材料沉积作为自从所述沉积室中去除材料以后所进行的涂覆操作的次数的函数而增加。
Description
本发明涉及一种用于在沉积室中生产具有从气相沉积的外延层的半导体晶片的方法，所述半导体晶片，所述方法包括从沉积室中去除已经在先前的涂覆操作期间沉积在沉积室中的材料。
现有技术/问题
为了生产电子组件，需要具有从气相沉积的外延层的半导体晶片。外延层通常以单晶片反应器的形式沉积在沉积室中。将用于涂覆的衬底晶片放置在基座上，并使沉积气体在沉积温度下穿过与基座一起旋转的衬底晶片上方的沉积室。
还已知的是能够建立具有不同于第一气流的方向的第二气流的沉积室，其主要导致外延层的形成。
根据US2014 0 137 801A1，这种沉积室可用于建立第二沉积气流。
US2015 0 368 796A1提出了这种用于使蚀刻气体与沉积气体反应的沉积室。
JP 2019 114 699A描述了一种采用第二气流以影响第一气流的效果的方法。
WO 2017 102 597A1特别致力于改善具有外延层的半导体晶片的边缘几何形状的问题。已经发现，在沉积室中定期进行典型蚀刻(室蚀刻)以去除已经在先前的涂覆操作期间沉积在沉积室中的材料之后，连续的后续涂覆操作导致随后在沉积室中产生的具有外延层的半导体晶片中的边缘滚降增加。所提出的建议是，在沉积外延层之前，在存在待涂覆的相应衬底晶片的情况下进行蚀刻，以便补偿在沉积外延层期间在边缘区域中减少的材料沉积，其结果是边缘滚降增加。影响该建议的缺点是蚀刻可能导致材料的过度侵蚀，可能看到衬底晶片中的晶体缺陷变得暴露，并且可能产生使半导体晶片被外延层污染的颗粒。
本发明的目的是克服在室蚀刻之后增加边缘滚降的现象，而不必接受上述缺点。
本发明的目的是通过一种用于在沉积室中生产具有从气相沉积的外延层的半导体晶片的方法来实现，所述方法包括：
通过对沉积室进行蚀刻来从沉积室中去除已经在先前的涂覆操作期间沉积在沉积室中的材料；
涂覆操作，这些涂覆操作连续进行并且每个操作都需要在沉积室中将外延层沉积在衬底晶片上，包括使第一沉积气体的第一气流在衬底晶片上方通过，以形成具有外延层的半导体晶片；
在连续进行的每个涂覆操作之前、期间或之后，将第二沉积气体的第二气流传递到相应衬底晶片或具有外延层的相应半导体晶片的边缘区域，其中对至少一个工艺参数作出改变，其效果是通过第二沉积气体的传递，边缘区域中的材料沉积作为自从沉积室中去除材料以后所进行的涂覆操作的次数的函数而增加。
根据本发明，建立第二沉积气体的第二气流，其在很大程度上通过增加从一个涂覆操作到下一个涂覆操作的边缘区域中的材料沉积来补偿从一个涂覆操作到下一个涂覆操作的边缘区域中的预期减少的材料沉积。
由第二沉积气体引起的材料沉积可以在衬底晶片上产生外延层的涂覆操作之前、期间或之后进行。由于第一与第二气流可能相互影响，因此优选在衬底晶片上沉积外延层之前通过沉积气体进行材料的沉积。然而，也可以在完成的具有外延层的半导体晶片上(换句话说，在通过第一沉积气体沉积外延层之后)通过第二沉积气体进行材料的沉积。虽然并未排除在外延层的沉积期间通过第二沉积气体进行材料沉积，但是在外延层的沉积之前或之后作为单独的工艺步骤进行这种材料沉积是有利的。在这些情况下，对于产生外延层的涂覆操作和在边缘区域中引起材料沉积的处理步骤，完全且彼此独立地保持工艺控制。下面假设通过第二沉积气体的材料沉积发生在相应的涂覆操作之前，表示应用单独的工艺步骤。在适当的情况下，该单独的工艺步骤还可以包括提供载气(例如，氢气)的第一气流以及第二沉积气体的第二气流，载气的第一气流在衬底晶片上方通过。相应的单独的涂覆操作还可以包括提供载气的第二气流以及第一沉积气体的第一气流，载气的第二气流被传递到衬底晶片的边缘，以便净化供给线。对于这种情况，这种载气的第二气流的体积速度优选小于5slm，更优选小于3slm。
第二沉积气体或载气的第二气流被传递到位于基座上的衬底晶片的边缘区域。因此，第二气流具有垂直于第一沉积气体或载气的第一气流方向的方向分量。
第一和第二沉积气体各自包含前体气体，该前体气体包括被沉积的半导体：例如，诸如三氯硅烷之类的硅烷。此外，第一沉积气体和第二沉积气体还可以包括载气(例如，氢气)，并且可选地包括掺杂气体(例如，乙硼烷)。这些气体分别与沉积气体的第一和第二气流混合。掺杂气体包括与半导体材料一起沉积的掺杂剂。第一和第二沉积气体的组成可以相同或可以不同。
在工艺步骤期间第二沉积气体被传递到衬底晶片的工艺条件彼此不同，具体取决于自最后的室蚀刻以后已经进行的利用第一沉积气体的涂覆操作的次数。该次数越大，通过第二沉积气体在衬底晶片的边缘区域中沉积的材料量越大。调节工艺条件，使得在边缘区域中沉积的材料的厚度很大程度上补偿了在后续涂覆操作之后没有工艺步骤的情况下预期的边缘滚降。
由于预期的边缘滚降从一个涂覆操作到下一个涂覆操作增加，因此对于工艺步骤，对至少一个工艺参数作出改变，其效果是，与前一工艺步骤相比，与边缘滚降的预期增加相对应的更大量的材料沉积在衬底晶片的边缘区域中。合适的工艺参数例如是第二沉积气体被传递到衬底晶片的边缘区域的时间，或第二沉积气体的第二气流被传递到衬底晶片的边缘区域的速度。例如，第二沉积气体被传递到衬底晶片的边缘区域的时间越长，将在那里沉积的材料量越大。其它合适的工艺参数是沉积气体的第二气流中的前体气体与载气的体积比、在混合这些气体以形成沉积气体的第二气流之前的前体气体与载气的体积速度之比、沉积室中的温度、或衬底晶片旋转的速度。在本发明的意义上，工艺参数的最佳协调还取决于所使用的沉积室，并且可能取决于载气的体积速度，如果其在单独的工艺步骤期间被用作除沉积气体的第二气流之外的载气的第一气流的话。这种协调可以通过试验获得。
为了从沉积室中去除已经在先前的涂覆操作期间沉积在沉积室中的材料，使蚀刻气体(例如，氯化氢)通过沉积室。例如，当沉积室的内表面上的材料沉积达到或超过预定厚度时，或者在已经进行预定次数的涂覆操作之后，优选定期进行这种室蚀刻。在室蚀刻之后，可通过使例如三氯硅烷在沉积温度下通过沉积室来进行室涂覆。这也可以在存在位于基座上的衬底晶片的情况下发生，所述晶片用作掩蔽基座的虚设物。
下面参考附图进一步描述本发明。
附图说明
图1示出了适于实施本发明方法的沉积室的组件。
图2以平面图示出了第一和第二气流传递到衬底晶片。
图3和图4示出了在室蚀刻之后作为外延层沉积序列的函数的边缘几何形状的改变。
所用附图标记列表
1 上盖
2 下盖
3 淀积室
4 衬底晶片
5 基座
6 预热环
7 上内衬
8 下内衬
9 第一气体入口孔
10 用于第二气流的气体入口孔
11 第一气体出口
12 下部气体入口孔
13 下部气体出口
14 第一气流
15 第二气流
本发明示例性实施方案的详细描述
图1所示的用于在衬底晶片上沉积外延层的装置包括沉积室3，其具有上盖1和下盖2，以及包围反应空间的上内衬7和下内衬8。沉积室3外部存在的上下灯阵列未示出。灯的辐射能使沉积室达到气相(蒸气)沉积所需的温度。
对于涂覆操作，将衬底晶片4放置在基座5上，基座5由载体的臂从下方可旋转地保持。围绕基座设置的是预热环6。衬底晶片4可以放置在基座5上，并且在涂覆之后通过穿过基座5的提升杆从基座5上提升。
在衬底晶片4的涂覆中，第一沉积气体沿着衬底晶片上方的第一流动方向穿过设置在上内衬7中的第一气体入口孔9进入沉积室3中，到达第一气体出口11。此外，在下内衬中有一个或多个第二气体入口孔，在单独的工艺步骤中或在涂覆操作中，沉积气体沿着第二流动方向穿过所述一个或多个第二气体入口孔到达衬底晶片4或具有外延层的半导体晶片的边缘区域。最后，作为一种选择，可以设置下部气体入口孔12和下部气体出口13，以便使吹扫气体在基座5下面通过到达下部气体出口13。
图2以平面图示出了衬底晶片4上方的第一气流14和第二气流15传递到衬底晶片4的边缘区域。第二气流15具有垂直于第一气流14的流动方向的方向分量。这两个流动方向包括优选为45°至90°的角度α。当沉积气体以单独的工艺步骤的形式经由第二气流15进入时，优选使由载气组成的第一气流14同时在衬底晶片4或具有外延层的半导体晶片上方通过。在单独的工艺步骤之前或之后进行的涂覆操作期间，沉积气体在衬底晶片上方仅经由第一气流14进行传递，并且可选地，载气经由第二气流15被传递到衬底晶片的边缘。在没有单独的工艺步骤的情况下，第一气流14和第二气流15都包含沉积气体。
实施例：
在第一试验中，在由单晶硅制成并具有300mm直径的25个衬底晶片中的每一个上沉积单晶硅外延层。在沉积室的室蚀刻之后，在单晶片反应器的沉积室中进行涂覆操作。单晶片反应器的设计使得第一气流在衬底晶片上方通过并且第二气流被传递到衬底晶片的边缘区域。
对于每个第二衬底晶片，在涂覆操作之前进行单独的工艺步骤，在该单独的工艺步骤期间，载气的第一气流在衬底晶片上方通过并且沉积气体的第二气流被传递到衬底晶片的边缘区域。自室蚀刻以后进行的涂覆操作的次数越多，用于供应沉积气体的第二气流的选定时间越长。在具有偶数序列号的涂覆操作之前，省略涂覆操作之前的单独的工艺步骤。
在以下涂覆操作之后，以ESFQD_AVG_Δ(边缘位置前表面最小平方位置偏差，ESFQD)的形式研究并量化所产生的具有外延层的半导体晶片的边缘几何形状。对72个边缘位置(长度为30mm且边缘除外范围为2mm的扇区，在长度在半径147.5mm与148mm之间的扇区的区域上进行测量)进行ESFQD测量，并且对于这些测量中的每一个，计算每个衬底晶片和每个所得的具有外延层的半导体晶片的平均值(AVG)，并且将成对的这两个平均值彼此相减(Δ)。
图3将作为减法结果的ESFQD_AVG_Δ绘制为自室蚀刻以后执行的涂覆操作的序列N的函数。序列中的奇数被分配给根据本发明涂覆的那些衬底晶片，偶数被分配给在没有单独工艺步骤的情况下(即，在没有沉积气体的第二气流的情况下)涂覆的那些衬底晶片。此外，在根据本发明进行的方法的情况下，沉积气体的第二气流被传递到衬底晶片的边缘区域的时间比之前根据本发明进行的方法期间的对应时间长恒定量。
随偶数序列下降的数据点反映了在没有介入的情况下在室蚀刻之后增加的边缘滚降的效果。随序列中的奇数上升的数据点表明了本发明的介入在某些情况下极大地补偿了边缘滚降并且在边缘区域中沉积了比预期更多的材料。
在进一步的试验中，对于根据本发明以序列中的奇数进行的涂覆操作，省略了单独的工艺步骤；换句话说，在涂覆操作期间，第二沉积气体的第二气流被传递到衬底晶片的边缘区域，前体气体与载气的不同体积速度比是在前体气体与载气混合形成沉积气体的第二气流之前被选定，并且涂覆操作的时间与第一试验中的时间相比被缩短。
图4示出，通过选择的工艺参数的组合，可以实现具有外延层的半导体晶片的比较均匀的边缘几何形状。
Claims (2)
1.在沉积室中生产具有气相沉积的外延层的半导体晶片的方法，其包括：
通过对所述沉积室进行蚀刻，从所述沉积室去除已经在先前的涂覆操作期间沉积在所述沉积室中的材料；
连续进行涂覆操作，并且每个操作都需要在所述沉积室中将外延层沉积在衬底晶片上，包括使第一沉积气体的第一气流在所述衬底晶片上方传递，以形成具有外延层的半导体晶片；
在连续进行的每个所述涂覆操作之前、期间或之后，将第二沉积气体的第二气流传递到各衬底晶片或具有外延层的各半导体晶片的边缘区域，其中对至少一个工艺参数作出改变，其效果是，经由所述第二沉积气体的传递，所述边缘区域中的材料沉积作为自从所述沉积室去除材料以后所进行的涂覆操作的次数的函数而增加。
2.如权利要求1所述的方法，其特征在于，所述至少一个工艺参数选自以下组中：所述第二沉积气体的第二气流传递到所述衬底晶片所经过的时间、所述第二沉积气体传递到所述衬底晶片的边缘区域的速度、所述第二气流中的前体气体与载气的体积比、在所述前体气体与所述载气混合形成所述第二气流之前所述前体气体与所述载气的体积速度之比、所述沉积室中的温度、以及所述衬底晶片旋转的速度。
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