CN117176267A - Phased array antenna channel rapid calibration method based on FPGA software - Google Patents
Phased array antenna channel rapid calibration method based on FPGA software Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The application discloses a phased array antenna channel rapid calibration method based on FPGA software, which belongs to the technical field of antennas and comprises the following steps: step 1, a frame of automatic calibration instruction is sent to a wave control test box internally provided with FPGA software through an upper computer; step 2, the wave control test box automatically generates a calibration instruction sequence of all channels of the antenna based on the automatic calibration instruction, and sequentially transmits the calibration instruction frames to the phased array antenna FPGA according to the channel sequence to complete the receiving calibration or the transmitting calibration of the full array; step 3, after the phase control antenna wave control FPGA receives a calibration instruction issued by the wave control test box, the phase control antenna wave control FPGA finishes: a) Turning off the whole array; b) Writing the maximum attenuation code into all channels in an angle resolving mode, and setting all channels to be in a maximum attenuation state; c) Starting a power-on instruction of the calibrated channel corresponding to the minimum power-on unit; d) The corresponding amplitude and phase values are set for the designated channel. The application can reduce the delivery time of the whole project and has great significance for mass production projects.
Description
Technical Field
The application belongs to the technical field of antennas, and particularly relates to a phased array antenna channel rapid calibration method based on FPGA software.
Background
Channel calibration of a phased array antenna is an indispensable step in phased array antenna testing, and proper completion of channel calibration is the basis for proper implementation of all functions and performances of the phased array antenna. In the prior art, the method is generally realized in the following way: as shown in fig. 1, the current channel calibration of the phased array antenna mainly includes the steps of issuing corresponding instructions to a wave control box through an upper computer, generating designated level signals by the wave control box or transmitting the instructions to the phased array antenna wave control to complete the calibration, and as shown in fig. 1, the steps are as follows: (1) The upper computer sends a SWITCH wave beam switching instruction to the wave control box, generates a SWITCH signal and transmits the SWITCH signal to the phased array antenna wave control FPGA; (2) The phased array antenna sequentially transmits amplitude and phase writing instructions of all channels, the wave control box forwards the amplitude and phase writing instructions to the phased array antenna wave control FPGA, and all channels of the minimum power-up unit of the pre-calibrated channel are set to a maximum attenuation state; (3) The upper computer sends out a power-on instruction to power up the minimum power-on unit where the calibrated channel is located; (4) The upper computer issues an amplitude-phase writing instruction, issues a secondary clock updating instruction at intervals of 1 millisecond, and writes an initial phase into the calibration channel; (5) The upper computer issues an amplitude and phase writing instruction, issues a secondary clock updating instruction at intervals of 1 millisecond, writes an initial phase +180° phase value into a calibration channel, and acquires vector network data to obtain a compensation phase; (6) If the calibration result is not in accordance with the requirements, the number of calibration groups can be increased, the initial value is set to be a required phase value, the step (4) is returned, and if the calibration result is in accordance with the requirements, the step (7) is carried out; (7) The upper computer issues an amplitude-phase writing instruction and a secondary clock updating instruction, and the calibrated channel is set to be in a maximum attenuation state; (8) The upper computer sends an electricity instruction and a power-on enabling signal of the electricity calibration channel; (9) If all channels are calibrated, proceeding to step (10); (10) If the channels are not completely calibrated, returning to the step (2) to calibrate the next channel; if all channels of all frequency points are calibrated, the antenna receiving or transmitting calibration is finished; if the frequency points are not all traversed, returning to the step (9) to calibrate all channels of the next frequency point. In the system, the phased array antenna wave control FPGA is provided with phased array antenna wave control software/FPGA of the system, and the FPGA is a field programmable gate array chip.
However, the current phased array antenna calibration time is longer, more equipment is occupied, and the method has great significance on the whole project if the phased array antenna channel calibration speed can be improved, especially in a mass production project or a project with urgent delivery time.
Disclosure of Invention
The application aims to provide a phased array antenna channel quick calibration method based on FPGA software, which aims to solve the problems that in the prior art, the phased array antenna calibration time is long, and the delivery time is influenced by more occupied equipment.
In order to achieve the above object, the technical scheme of the present application is as follows:
a phased array antenna channel rapid calibration method based on FPGA software comprises the following steps:
step 1, a frame of automatic calibration instruction is sent to a wave control test box internally provided with FPGA software through an upper computer;
step 2, the wave control test box automatically generates a calibration instruction sequence of all channels of the antenna based on the automatic calibration instruction, and sequentially transmits the calibration instruction frames to the phased array antenna FPGA according to the channel sequence to complete the receiving calibration or the transmitting calibration of the full array;
step 3, after the phase control antenna wave control FPGA receives a calibration instruction issued by the wave control test box, the following operations are completed: a) Turning off the whole array; b) Writing the maximum attenuation code into all channels in an angle resolving mode, and setting all channels to be in a maximum attenuation state; c) Starting a power-on instruction of the calibrated channel corresponding to the minimum power-on unit; d) Setting the designated channel as corresponding amplitude and phase values;
and 4, ending the calibration.
In step 1, a frame of automatic calibration instruction includes frequency point information, receiving and transmitting information, vector network LDAC delay time, phase shift group number and phase value of each group phase shift.
In step 2, in the wave control test box, the FPGA software sequentially completes the receiving or transmitting calibration of the full array according to the sequence of the frequency point 0~F and the channels 0 to n.
Further, the FPGA software needs to send k+1 frames of data for completing channel calibration, the previous K frames are amplitude phase control frames, the k+1 frames are power-off frames, the frame instruction interval is determined according to the vector network feedback signal, and the FPGA frame instruction interval can reach 50us, where k=phase shift group number is 2.
After the scheme is adopted, the following beneficial effects are realized: (1) According to the scheme, the FPGA software is used for automatically taking the place of the upper computer to send the instruction, the upper computer only needs to send a small amount of frame instructions to finish the calibration work of the phased array antenna, the instruction transmission time is almost shortened, and the phased array antenna channel calibration time is greatly shortened. Meanwhile, the scheme distributes the instruction in the wave control box FPGA software and the phased array antenna wave control FPGA software, and the minimum interval time between instruction frames is changed from the minimum interval of 1ms of the upper computer to 50 us-100 us, so that the channel calibration time is further shortened.
In addition, the upper computer transmits the command frame in a simplified manner, so that the software and the operation of the channel calibration upper computer are simplified, and the testers are released.
The reduction of the test time can reduce the delivery time of the whole project, and has great significance especially for mass production projects.
(2) Compared with the prior art, the speed of the upper computer for transmitting data to the FPGA is very slow, the minimum frame interval in the upper computer is 1ms, but the transmission speed can reach 100Mbps through a synchronous serial port between the FPGAs, and the frame interval time in FPGA software can reach ns level. The calibration sequence frames are automatically generated through the wave control box FPGA software and the phased array antenna FPGA software, so that the instruction transmission time and the interval time can be reduced.
(3) The operation of an upper computer is simplified, and the calibration time of the phased array antenna is shortened, so that the project delivery time is shortened; and meanwhile, the calibration site and equipment are also released, and the cost is saved.
Drawings
Fig. 1 is a schematic flow chart of the prior art.
Fig. 2 is a flow chart of a method for fast calibration of a phased array antenna channel based on FPGA software according to an embodiment of the application.
Fig. 3 is a schematic diagram of a command sequence generated by the wave control box according to an embodiment of the present application.
Fig. 4 is a flowchart of a phased array antenna wave-controlled FPGA according to an embodiment of the present application.
Detailed Description
The following is a further detailed description of the embodiments:
the application provides a phased array antenna channel rapid calibration method based on FPGA software, which is basically as shown in figure 2,
the method comprises the following steps:
and step 1, the upper computer issues a normally low SWITCH instruction to the wave control test box, and after the wave control test box analyzes, the signal of switching the SWITCH level is sent to the phased array antenna FPGA.
And 2, the upper computer sends a frame of automatic calibration instruction, waits for all frequency points of all channels to finish receiving calibration, and finally turns off the whole array, wherein the frame of automatic calibration instruction sent to the wave control test box FPGA by the upper computer comprises frequency point information, receiving and transmitting information, vector network LDAC delay time, phase shift group number and phase value of each group of phase shifts.
And 3, automatically generating a calibration sequence frame by using the FPGA software of the test box, and sequentially completing the receiving calibration of the full array by using the FPGA according to the sequence of 0-10 frequency points and 0-767 channels (11 frequency points and 768 channels of the calibrated phased array antenna), wherein the sequence instruction of the FPGA of the wave control box is shown in figure 3.
The FPGA finishes the channel calibration and needs to send 3 frames of data, the first 2 frames are amplitude-phase control frames, the 3 rd frames are power-off frames, the frame instruction interval is 50us, the vector network timeout is 5 ms), and the phase shift group number is 1 group.
Step 4, after the phase control antenna wave control FPGA receives the calibration instruction issued by the wave control test box, the following operations are completed through FPGA software, as shown in fig. 4:
a) Turning off the whole array;
b) Writing the maximum attenuation code into all channels in an angle resolving mode, and setting all channels to be in a maximum attenuation state;
c) Starting a power-on instruction of the calibrated channel corresponding to the minimum power-on unit;
and 5, ending the receiving calibration.
And 6, after the connection of the external emission calibration is completed, the upper computer issues a SWITCH instruction with the duty ratio of 20 percent and the frequency of 10KHz to the wave control test box, and after the wave control test box analyzes, the signal of switching the SWITCH level between the receiving and the transmitting is sent to the FPGA.
And 7, executing according to the steps 2-4, and completing emission calibration.
In the embodiment, the upper computer only needs to send a few frames of instructions to finish the calibration work of the phased array antenna by automatically taking the place of the upper computer for issuing instructions through the FPGA software, so that the time for transmitting the instructions is almost shortened, and the calibration time of the phased array antenna channel is greatly shortened. Meanwhile, the scheme distributes the instruction in the wave control box FPGA program and the phased array antenna wave control FPGA program, and the minimum interval time between instruction frames is changed from the interval of 1ms of the upper computer to the interval of 50us, so that the channel calibration time is further shortened. The calibration of the channel can be completed by the fact that the upper computer sends countless instruction frames.
The foregoing is merely exemplary of the present application and the specific structures and/or characteristics of the present application that are well known in the art have not been described in detail herein. It should be noted that modifications and improvements can be made by those skilled in the art without departing from the structure of the present application, and these should also be considered as the scope of the present application, which does not affect the effect of the implementation of the present application and the utility of the patent. The protection scope of the present application is subject to the content of the claims, and the description of the specific embodiments and the like in the specification can be used for explaining the content of the claims.
Claims (4)
1. A phased array antenna channel rapid calibration method based on FPGA software is characterized in that: the method comprises the following steps:
step 1, a frame of automatic calibration instruction is sent to a wave control test box internally provided with FPGA software through an upper computer;
step 2, the wave control test box automatically generates a calibration instruction sequence of all channels of the antenna based on the automatic calibration instruction, and sequentially transmits the calibration instruction frames to the phased array antenna FPGA according to the channel sequence to complete the receiving calibration or the transmitting calibration of the full array;
step 3, after the phase control antenna wave control FPGA receives a calibration instruction issued by the wave control test box, the following operations are completed:
a) Turning off the whole array;
b) Writing the maximum attenuation code into all channels in an angle resolving mode, and setting all channels to be in a maximum attenuation state;
c) Starting a power-on instruction of the calibrated channel corresponding to the minimum power-on unit;
d) Setting the designated channel as corresponding amplitude and phase values;
and 4, ending the calibration.
2. The method for rapid calibration of a phased array antenna path based on FPGA software of claim 1, wherein: in step 1, a frame of automatic calibration instruction includes frequency point information, receiving and transmitting calibration information, vector network LDAC delay time, phase shift group number and phase value of each group phase shift.
3. The method for rapid calibration of a phased array antenna path based on FPGA software of claim 1, wherein: in the step 2, in the wave control test box, FPGA software sequentially completes the receiving calibration or the transmitting calibration of the full array according to the sequence of frequency points 0~F and channels 0-N.
4. A method for rapid calibration of a phased array antenna path based on FPGA software as claimed in claim 3, wherein: the FPGA software finishes the channel calibration and needs to send K+1 frames of data, the front K frames are amplitude phase control frames, the K+1 frames are power-off frames, the frame instruction interval is determined according to the vector network feedback signals, and the FPGA frame instruction interval can reach 50us, wherein K=the phase shift group number is 2.
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| CN117590095A (en) * | 2024-01-18 | 2024-02-23 | 成都华兴大地科技有限公司 | Method for rapidly testing directional diagram of phased array antenna based on FPGA software |
| CN117890689A (en) * | 2024-03-13 | 2024-04-16 | 成都华兴大地科技有限公司 | Calibration method suitable for phased array without amplitude control |
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| CN117890689A (en) * | 2024-03-13 | 2024-04-16 | 成都华兴大地科技有限公司 | Calibration method suitable for phased array without amplitude control |
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