CN117175910A - Three-level inverter driving structure and method, inverter and electronic equipment - Google Patents
Three-level inverter driving structure and method, inverter and electronic equipment Download PDFInfo
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Abstract
The application relates to a three-level inverter driving structure, a three-level inverter driving method, an inverter and electronic equipment, and belongs to the technical field of electronic circuits, wherein the driving structure comprises a first driving circuit, and an output end outputs a conduction signal in a state that the potential difference between a first receiving end and a second receiving end of the first driving circuit exceeds a preset value; the first receiving end of the second driving circuit is connected with the second receiving end of the first driving circuit, and the second receiving end of the second driving circuit is connected with the first receiving end of the first driving circuit; and the output end of the second driving circuit outputs a conduction signal in a state that the potential difference between the first receiving end and the second receiving end of the second driving circuit exceeds a preset value; the signal generating circuit is used for generating a control signal to change the first receiving end potential of the first driving circuit and the second receiving end potential of the first driving circuit. The application has the effect of facilitating the driving of the inverter.
Description
Technical Field
The present application relates to the field of electronic circuits, and in particular, to a three-level inverter driving structure, a three-level inverter driving method, an inverter, and an electronic device.
Background
The conventional three-level inverter types are classified into three types: neutral point clamped, flying capacitor, and cascade. As shown in fig. 1, the neutral point clamped (Neutral Point Clamped, NPC) three-level inverter is a three-phase electric output, and the power components of each phase of the inverter comprise four IGBT switching tubes (Q11-Q14) and two clamping diodes (D11, D12). The switch state combination of the 4 IGBT switch tubes can form different modes to output three levels of Vbus/2, 0 or-Vbus/2, and the inverter can be controlled to output corresponding three-phase electric waveforms through controlling the four IGBT switch tubes of each phase.
In the neutral point clamped three-level inverter, the IGBT switching transistor Q11 and the IGBT switching transistor Q13 are negative level switches, and output a negative level to the load, and the IGBT switching transistor Q12 and the IGBT switching transistor Q14 are positive level switches, and output a positive level to the load. At present, a microcontroller and a programmable gate array are generally adopted to output PWM control signals so as to control the on-off of each IGBT switching tube; however, if the IGBT switching tube Q11 and the IGBT switching tube Q13 are turned on simultaneously, or the IGBT switching tube Q12 and the IGBT switching tube Q14 are turned on simultaneously, a dc bus short circuit is easily caused to damage the inverter, and how to stably drive the inverter reduces the possibility of damage to the inverter.
Disclosure of Invention
In order to facilitate stable driving of an inverter, the application provides a three-level inverter driving structure, a three-level inverter driving method, an inverter and electronic equipment.
In a first aspect, the present application provides a three-level inverter driving structure, which adopts the following technical scheme:
a three-level inverter driving structure comprising:
the first driving circuit comprises a first receiving end, a second receiving end and an output end, and the output end of the first driving circuit outputs a conduction signal in a state that the potential of the first receiving end of the first driving circuit is higher than that of the second receiving end of the first driving circuit by a preset value;
the second driving circuit comprises a first receiving end, a second receiving end and an output end, wherein the first receiving end of the second driving circuit is connected with the second receiving end of the first driving circuit, and the second receiving end of the second driving circuit is connected with the first receiving end of the first driving circuit; and in a state that the potential of the first receiving end of the second driving circuit is higher than the potential of the second receiving end of the second driving circuit by a preset value, the output end of the second driving circuit outputs a conducting signal;
the signal generating circuit is connected with the first driving circuit and the second driving circuit and is used for generating a control signal so as to change the first receiving end potential of the first driving circuit and the second receiving end potential of the first driving circuit.
By adopting the technical scheme, as the first receiving end of the second driving circuit is connected with the second receiving end of the first driving circuit, the second receiving end of the second driving circuit is connected with the first receiving end of the first driving circuit, namely the first receiving end of the second driving circuit and the second receiving end of the first driving circuit are in the same potential, the second receiving end of the second driving circuit and the first receiving end of the first driving circuit are in the same potential, and the first driving circuit and the second driving circuit output a conducting signal when the potential of the first receiving end of the first driving circuit is higher than that of the second receiving end. Therefore, only one of the first driving circuit and the second driving circuit can output a conduction signal in the same time period, and the control signal output by the signal generating circuit changes the potential so as to switch the first driving circuit to output the conduction signal or the second driving circuit to switch the output conduction signal, thereby realizing the effect of being convenient for driving the inverter.
Optionally, the method is applied to an inverter, each phase of the inverter comprises four switching tubes which are sequentially connected in series, the first driving circuit and the second driving circuit are provided with two groups, and the output end of the first driving circuit and the output end of the second driving circuit of each group are respectively connected with grid electrodes of the switching tubes which are alternately arranged.
Through adopting above-mentioned technical scheme, because each phase of dc-to-ac converter contains four switching tubes, contain two sets of alternate switching tubes promptly, based on the theory of operation of dc-to-ac converter three-level topological structure can know, the switching tube of alternate switching tube of a set of is the positive level switch, then the switching tube of another set of alternate is the negative level switch, by first drive circuit and second drive circuit drive two sets of alternate switching tubes, first drive circuit and second drive circuit can not export the turn-on signal simultaneously, thereby make the switching tube of alternate switching tube of every group can not switch on simultaneously, avoid the direct current busbar short circuit that alternate switching tube switched on simultaneously to a certain extent caused.
Optionally, the first driving circuit and the second driving circuit each include a light emitting diode D1 sub-circuit, a first photosensitive sub-circuit, and a second photosensitive sub-circuit;
the light emitting diode D1 sub-circuit is optically coupled with the first photosensitive sub-circuit and the second photosensitive sub-circuit; the anode of the light emitting diode D1 sub-circuit is connected with the first receiving end of the first driving circuit, the cathode is connected with the second receiving end of the first driving circuit, or the anode of the light emitting diode D1 sub-circuit is connected with the first receiving end of the second driving circuit, and the cathode is connected with the second receiving end of the second driving circuit;
the first photosensitive sub-circuit is connected with a second photosensitive sub-circuit, the first photosensitive sub-circuit is also connected with a power supply Vcc, the second photosensitive sub-circuit is grounded, and a driving port is arranged between the first photosensitive sub-circuit and the second photosensitive sub-circuit;
the first photosensitive sub-circuit reduces the equivalent resistance between the power supply Vcc and the driving port along with the increase of the illumination intensity, and the second photosensitive sub-circuit increases the equivalent resistance between the signal output port and the ground along with the increase of the illumination intensity.
By adopting the technical scheme, when the potential difference between the first receiving end of the first driving circuit and the second receiving end of the first driving circuit exceeds a preset value, or when the potential difference between the first receiving end of the second driving circuit and the second receiving end of the second driving circuit exceeds a preset value, the light emitting diode D1 sub-circuit is conducted and emits light, so that the equivalent resistance of the first photosensitive sub-circuit is reduced, the equivalent resistance of the second photosensitive sub-circuit is increased, the partial pressure at the driving port is improved, and the driving port outputs a conducting signal.
Optionally, the light emitting diode D1 sub-circuit includes one or a plurality of light emitting diodes D1 connected in series in sequence.
By adopting the technical scheme, one or a plurality of light emitting diodes D1 which are sequentially connected in series are utilized so as to adjust the preset value of the potential difference.
Optionally, the first photo-sub circuit includes a photo-NPN triode Q1, a base electrode of the photo-NPN triode Q1 is optically coupled to the light emitting diode D1 sub circuit, a collector electrode is connected to the power supply Vcc, and an emitter electrode is connected to the driving port and the second photo-sub circuit.
By adopting the technical scheme, when the base electrode of the photosensitive NPN triode Q1 receives illumination, the equivalent resistance between the emitter electrode and the collector electrode of the photosensitive NPN triode Q1 is reduced until the photosensitive NPN triode Q1 is saturated and conducted, so that the effect of reducing the equivalent resistance between the power supply Vcc and the driving port along with the increase of illumination intensity is realized.
Optionally, the second photosensitive subcircuit includes a photosensitive PNP transistor Q2, where a base of the photosensitive PNP transistor Q2 is optically coupled to the light emitting diode D1 subcircuit, an emitter is connected to the drive port and the first photosensitive subcircuit, and a collector is grounded to the signal ground Vee.
By adopting the technical scheme, when the base electrode of the photosensitive PNP triode receives illumination, the equivalent resistance between the emitter electrode and the collector electrode of the photosensitive PNP triode is increased until the photosensitive PNP triode is turned off, so that the effect of reducing the equivalent resistance between the driving port and the ground along with the increase of illumination intensity is realized.
Optionally, buffers are serially arranged between the first driving circuit and the signal generating circuit and between the second driving circuit and the signal generating signal.
By adopting the technical scheme, the stability of the input to the first driving circuit and the second driving circuit is improved by utilizing the buffering property.
In a second aspect, the present application provides a driving method of a three-level inverter, which adopts the following technical scheme:
a three-level inverter driving method is applied to the three-level inverter driving structure, and comprises the following steps:
the signal generation circuit generates two groups of control signals, and each group of control signals comprises a first control signal and a second control signal;
each first driving circuit receives a set of control signals;
each second driving circuit receives a group of control signals received by the first driving circuit connected with the second driving circuit;
the first driving circuit outputs a conducting signal in a state that the potential of a first control signal in each group of control signals is higher than that of a second control signal by more than a preset value;
in a state that the potential of the second control signal in each group of control signals is higher than that of the first control signal by more than a preset value, the second driving circuit outputs a conducting signal so that the first driving circuit and the second driving circuit do not output the conducting signal at the same time.
In a third aspect, the present application provides an inverter, which adopts the following technical scheme:
an inverter comprising a three-level inverter driving structure as described above.
In a fourth aspect, the present application provides an electronic device, which adopts the following technical scheme:
an electronic device comprising an inverter as described above.
Drawings
Fig. 1 is a schematic diagram of an NPC type three-level inverter in the related art.
Fig. 2 is a block diagram of a driving structure according to an embodiment of the present application.
Fig. 3 is a schematic circuit diagram of a driving structure according to an embodiment of the application.
Fig. 4 is a schematic diagram of a connection structure of a driving structure and an inverter according to an embodiment of the present application.
Fig. 5 is a waveform diagram of a turn-on signal output by the driving structure according to an embodiment of the present application.
FIG. 6 is a truth table of driving structure inputs and outputs according to one embodiment of the present application.
FIG. 7 is a flow chart of a driving method according to an embodiment of the application.
Reference numerals illustrate: 1. a first driving circuit; 2. a second driving circuit; 3. a signal generating circuit; 4. a light emitting diode D1 sub-circuit; 5. a first photo-sub-circuit; 6. a second photo-sub-circuit.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The embodiment of the application discloses a three-level inverter driving structure. Referring to fig. 1, a three-level inverter driving structure includes:
the first driving circuit 1 includes a first receiving end, a second receiving end and an output end, and the output end of the first driving circuit 1 outputs a conducting signal in a state that the potential of the first receiving end of the first driving circuit 1 is higher than the potential of the second receiving end of the first driving circuit 1 by a preset value.
The second driving circuit 2 comprises a first receiving end, a second receiving end and an output end, wherein the first receiving end of the second driving circuit 2 is connected with the second receiving end of the first driving circuit 1, and the second receiving end of the second driving circuit 2 is connected with the first receiving end of the first driving circuit 1; and the output terminal of the second driving circuit 2 outputs a turn-on signal in a state where the first receiving terminal potential of the second driving circuit 2 is higher than the second receiving terminal potential of the second driving circuit 2 by a preset value.
It should be noted that the preset value may be set according to actual situations.
The signal generating circuit 3 is connected to the first driving circuit 1 and the second driving circuit 2, and generates a control signal to change the first receiving terminal potential of the first driving circuit 1 and the second receiving terminal potential of the first driving circuit 1.
It should be understood that, since the first receiving end of the second driving circuit 2 is connected to the second receiving end of the first driving circuit 1, the first receiving end of the second driving circuit 2 and the second receiving end of the first driving circuit 1 are equipotential points, and the second receiving end of the second driving circuit 2 and the first receiving end of the first driving circuit 1 are also equipotential points. Therefore, when the signal generating circuit 3 changes the potential of the first receiving terminal of the first driving circuit 1, the potential of the second receiving terminal of the second driving circuit 2 is changed in synchronization; when the signal generating circuit 3 changes the potential of the second receiving terminal of the first driving circuit 1, the potential of the first receiving terminal of the second driving circuit 2 also changes synchronously.
In the above embodiment, since the first receiving end of the second driving circuit 2 is connected to the second receiving end of the first driving circuit 1, the second receiving end of the second driving circuit 2 is connected to the first receiving end of the first driving circuit 1, that is, the first receiving end of the second driving circuit 2 and the second receiving end of the first driving circuit 1 are at the same potential, the second receiving end of the second driving circuit 2 and the first receiving end of the first driving circuit 1 are at the same potential, and the first driving circuit 1 and the second driving circuit 2 both output the on signal when the potential of the first receiving end is higher than the potential of the second receiving end. Therefore, only one of the first driving circuit 1 and the second driving circuit 2 can output a conduction signal in the same time period, and the control signal output by the signal generating circuit 3 changes the electric potential to switch the first driving circuit 1 to output the conduction signal or the second driving circuit 2 to switch the second driving circuit 2 to output the conduction signal, thereby realizing the effect of being convenient for driving the inverter.
Referring to fig. 3, as an embodiment of the first driving circuit 1 and the second driving circuit 2, each of the first driving circuit 1 and the second driving circuit 2 includes a light emitting diode D1 sub-circuit 4, a first photo-sub-circuit 5, and a second photo-sub-circuit 6.
Specifically, the light emitting diode D1 sub-circuit 4 includes one or a plurality of light emitting diodes D1 having cathodes and anodes sequentially connected in series. One or a plurality of light emitting diodes D1 connected in series in order to adjust the preset value of the potential difference. It should be understood that when the led D1 sub-circuit 4 includes one led D1, the preset value is the turn-on voltage of the led D1. When the led D1 circuit includes a plurality of diodes, the preset value is an overlapping value of the turn-on voltages of each led D1.
The light emitting diode D1 sub-circuit 4 is optically coupled to the first light sensitive sub-circuit 5 and the second light sensitive sub-circuit 6; the anode of the light emitting diode D1 sub-circuit 4 is connected to the first receiving end of the first driving circuit 1, and the cathode is connected to the second receiving end of the first driving circuit 1, or the anode of the light emitting diode D1 sub-circuit 4 is connected to the first receiving end of the second driving circuit 2, and the cathode is connected to the second receiving end of the second driving circuit 2.
Further, the anode of the light emitting diode D1 of the first driving circuit 1 is connected to the first receiving end of the first driving circuit 1, and the cathode is connected to the second receiving end of the first driving circuit 1; the anode of the light emitting diode D1 of the second driving circuit 2 is connected to the first receiving terminal of the second driving circuit 2, and the cathode is connected to the second receiving terminal of the second driving circuit 2. Based on this, it should be understood that in a state where the first receiving-end potential of the first driving circuit 1 is higher than the second receiving-end potential of the first driving circuit 1 by a preset value, that is, a forward voltage difference exists between the anode and the cathode of the light emitting diode D1 of the first driving circuit 1, the light emitting diode D1 of the first driving circuit 1 is in a forward biased state, so that the light emitting diode D1 of the first driving circuit 1 is turned on to output an illumination signal. And at this time, the cathode potential of the light emitting diode D1 of the second driving circuit 2 is higher than the anode potential thereof, so that the light emitting diode D1 of the second driving circuit 2 is in a reverse biased state to turn off the light emitting diode D1 of the second driving circuit 2 to stop light emission. Conversely, if the second receiving end potential of the first driving circuit 1 is higher than the first receiving end potential of the first driving circuit 1 by a preset value, the light emitting diode D1 of the first driving circuit 1 is reverse biased to stop emitting light, and the light emitting diode D1 of the second driving circuit 2 is forward biased to be turned on to output an illumination signal.
It should be noted that, in a state where the potential difference between the first receiving terminal of the first driving circuit 1 and the second receiving terminal of the first driving circuit 1 is smaller than the preset value, neither the light emitting diode D1 of the first driving circuit 1 nor the light emitting diode D1 of the second driving circuit 2 reaches the forward bias condition, so that neither the first driving circuit 1 nor the second driving circuit 2 outputs the illumination signal at this time. In this case, even if the control signal output from the signal generating circuit 3 receives external interference to raise the potential of both the first receiving terminal of the first driving circuit 1 and the second receiving terminal of the first driving circuit 1, the abnormal conduction of the light emitting diode D1 of the first driving circuit 1 or the second driving circuit 2 is not caused due to the unchanged voltage difference, that is, external noise is eliminated, and malfunction is not easily caused. In addition, by flowing currents in opposite directions to each other, the high-frequency magnetic flux in the control signal outputted from the signal generating circuit 3 is canceled, and thereby EMI noise generated by signal harmonics is reduced.
The first photosensitive sub-circuit 5 is connected with the second photosensitive sub-circuit 6, the first photosensitive sub-circuit 5 is also connected with a power supply Vcc, the second photosensitive sub-circuit 6 is grounded, and a driving port is arranged between the first photosensitive sub-circuit 5 and the second photosensitive sub-circuit 6.
Wherein, the first photosensitive sub-circuit 5 reduces the equivalent resistance between the power supply Vcc and the driving port along with the increase of the illumination intensity, and the second photosensitive sub-circuit 6 increases the equivalent resistance between the signal output port and the ground along with the increase of the illumination intensity.
It should be understood that the illumination intensity is the illumination intensity of the illumination signal output by the light emitting diode D1 sub-circuit 4, the first photosensitive sub-circuit 5 and the second photosensitive sub-circuit 6 together form a voltage division structure, and the voltage division relationship of the first photosensitive sub-circuit 5 and the second photosensitive sub-circuit 6 is changed by the illumination intensity of the illumination signal to change the potential of the driving port disposed between the first photosensitive sub-circuit 5 and the second photosensitive sub-circuit 6.
In the above embodiment, when the potential difference between the first receiving end of the first driving circuit 1 and the second receiving end of the first driving circuit 1 exceeds the preset value, or when the potential difference between the first receiving end of the second driving circuit 2 and the second receiving end of the second driving circuit 2 exceeds the preset value, the light emitting diode D1 sub-circuit 4 is turned on and emits light, so that the equivalent resistance of the first photosensitive sub-circuit 5 is reduced, and the equivalent resistance of the second photosensitive sub-circuit 6 is increased, thereby increasing the voltage division at the driving port and realizing that the driving port outputs the on signal.
As an embodiment of the first photo-sub-circuit 5, the first photo-sub-circuit 5 comprises a photo-NPN triode Q1, the base of the photo-NPN triode Q1 is optically coupled to the light emitting diode D1 sub-circuit 4, the collector is connected to the power supply Vcc, the emitter is connected to the drive port and the second photo-sub-circuit 6.
In the above embodiment, when the base electrode of the NPN transistor Q1 receives the light, the equivalent resistance between the emitter electrode and the collector electrode of the NPN transistor Q1 decreases until the NPN transistor Q1 is saturated and turned on, thereby achieving the effect of decreasing the equivalent resistance between the power supply Vcc and the driving port with the increase of the light intensity.
As an embodiment of the second photo-sub-circuit 6, the second photo-sub-circuit 6 comprises a photo-sensitive PNP transistor Q2, the base of the photo-sensitive PNP transistor Q2 is optically coupled to the light emitting diode D1 sub-circuit 4, the emitter is connected to the drive port and the first photo-sub-circuit 5, and the collector is connected to the signal ground Vee.
According to the embodiment, when the base electrode of the photosensitive PNP triode receives illumination, the equivalent resistance between the emitter electrode and the collector electrode of the photosensitive PNP triode is increased until the photosensitive PNP triode is turned off, so that the effect of reducing the equivalent resistance between the driving port and the ground along with the increase of illumination intensity is achieved.
Referring to fig. 4, as a further embodiment of the inverter driving circuit, the driving circuit is applied to an inverter, each phase of the inverter includes four switching tubes connected in series in sequence, the first driving circuit 1 and the second driving circuit 2 are provided with two groups, and the output end of the first driving circuit 1 and the output end of the second driving circuit 2 of each group are respectively connected with gates of the switching tubes that are alternately arranged.
It should be understood that, among the four switching tubes of each phase of the inverter, the first switching tube and the third switching tube are negative level switches, and the second switching tube and the fourth switching tube are positive level switches, so that the first switching tube and the third switching tube cannot be simultaneously turned on, and the second switching tube and the fourth switching tube cannot be simultaneously turned on.
Specifically, the inverter includes two groups of inter-phase switching tubes, i.e., two switching tubes that have no direct connection relationship, and in this embodiment, the inter-phase switching tubes refer to a first switching tube and a third switching tube in each phase of the inverter, and also refer to a second switching tube and a fourth switching tube in each phase of the inverter.
Referring to fig. 5, fig. 5 shows the conduction signals received by the gates of the four switching tubes of each phase of the inverter according to the present embodiment, the conduction conditions of the first switching tube and the third switching tube are always opposite, and similarly, the conduction conditions of the second switching tube and the fourth switching tube are always opposite.
Referring to fig. 6, fig. 6 is a truth table of inputs and outputs of the first driving circuit 1 and the second driving circuit 2. The signals PWM1-PWM4 are control signals generated by the signal generating circuit 3, that is, the signal generating circuit 3 generates four paths of control signals. V1-V4 represent the on signals input to the switching tube. When the signal PWM1 is at a high level and the signal PWM3 is at a low level, the first driving circuit 1 outputs a high level signal, i.e. a conducting signal, to control the first switching tube to be conducted, and at the same time the second driving circuit 2 outputs a low level to control the third switching tube to be turned off. On the contrary, when the signal PWM3 is at a high level and the signal PWM1 is at a low level, the first driving circuit 1 outputs a low level signal to control the first switching tube to be turned off, and at the same time, the second driving circuit 2 outputs a high level, i.e. a conducting signal, to control the third switching tube to be turned on. When the signal PWM1 and the signal PWM3 are both high or both low, the first switching transistor and the third switching transistor are both turned off at this time since there is no potential difference at this time. It can be found that no matter which high-low level signal combination signal PWM1 and signal PWM3 is, the condition that the first switching tube and the third switching tube are conducted simultaneously is impossible, so that the condition that the direct current bus is short-circuited caused by the fact that the first switching tube and the third switching tube are conducted simultaneously is avoided. Similarly, the principle of the signals PWM2 and PWM4 controlling the second switching tube and the fourth switching tube together is similar to the principle of the signals PWM1 and PWM3 controlling the first switching tube and the third switching tube together, and will not be described herein.
In the above embodiment, since each phase of the inverter includes four switching tubes, that is, two groups of inter-phase switching tubes, based on the working principle of the three-level topology structure of the inverter, it is known that one group of inter-phase switching tubes is a positive level switch, and the other group of inter-phase switching tubes is a negative level switch, the first driving circuit 1 and the second driving circuit 2 drive the two groups of inter-phase switching tubes, and the first driving circuit 1 and the second driving circuit 2 do not output conduction signals at the same time, so that the inter-phase switching tubes of each group cannot be conducted at the same time, and a direct current bus short circuit caused by the simultaneous conduction of the inter-phase switching tubes is avoided to a certain extent.
As a further embodiment of the inverter driving structure, buffers are provided in series between the first driving circuit 1 and the signal generating circuit 3 and between the second driving circuit 2 and the signal generating signal.
In the above embodiment, the stability of the input to the first driving circuit 1 and the second driving circuit 2 is improved by the buffering property.
The application also discloses a three-level inverter driving method which is applied to the three-level inverter driving structure, and comprises the following steps:
the signal generating circuit 3 generates two sets of control signals, and each set of control signals includes a first control signal and a second control signal;
each first driving circuit 1 receives a set of control signals;
each second driving circuit 2 receives a set of control signals received by the first driving circuit 1 connected thereto;
the first driving circuit 1 outputs a turn-on signal in a state in which the first control signal potential in each set of control signals is higher than the second control signal potential by more than a preset value;
in a state in which the second control signal potential in each set of control signals is higher than the first control signal potential by more than a preset value, the second drive circuit 2 outputs the on signal so that the first drive circuit 1 and the second drive circuit 2 do not output the on signal at the same time.
It should be noted that, the electronic device provided by the present application can implement the three-level inverter driving structure, and a specific working process of an electronic device may refer to a corresponding process in the above method embodiment.
The application also provides an inverter which comprises the three-level inverter driving structure.
The application provides an electronic device comprising an inverter as described above.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The foregoing description of the preferred embodiments of the application is not intended to limit the scope of the application in any way, including the abstract and drawings, in which case any feature disclosed in this specification (including abstract and drawings) may be replaced by alternative features serving the same, equivalent purpose, unless expressly stated otherwise. That is, each feature is one example only of a generic series of equivalent or similar features, unless expressly stated otherwise.
Claims (10)
1. A three-level inverter driving structure, comprising:
the first driving circuit (1) comprises a first receiving end, a second receiving end and an output end, and the output end of the first driving circuit (1) outputs a conduction signal in a state that the potential of the first receiving end of the first driving circuit (1) is higher than that of the second receiving end of the first driving circuit (1) by a preset value;
the second driving circuit (2) comprises a first receiving end, a second receiving end and an output end, wherein the first receiving end of the second driving circuit (2) is connected with the second receiving end of the first driving circuit (1), and the second receiving end of the second driving circuit (2) is connected with the first receiving end of the first driving circuit (1); and in a state that the potential of the first receiving end of the second driving circuit (2) is higher than the potential of the second receiving end of the second driving circuit (2) by a preset value, the output end of the second driving circuit (2) outputs a conducting signal;
and a signal generating circuit (3) connected to the first driving circuit (1) and the second driving circuit (2) for generating a control signal to change the first receiving terminal potential of the first driving circuit (1) and the second receiving terminal potential of the first driving circuit (1).
2. The three-level inverter driving structure according to claim 1, applied to an inverter, wherein each phase of the inverter comprises four switching tubes connected in series in turn, and the three-level inverter driving structure is characterized in that:
the first driving circuit (1) and the second driving circuit (2) are provided with two groups, and the output end of the first driving circuit (1) and the output end of the second driving circuit (2) of each group are respectively connected with the grid electrodes of the alternate switching tubes.
3. A three-level inverter driving structure according to claim 1, wherein the first driving circuit (1) and the second driving circuit (2) each comprise a light emitting diode D1 sub-circuit (4), a first light sensitive sub-circuit (5) and a second light sensitive sub-circuit (6);
the light emitting diode D1 sub-circuit (4) is optically coupled with the first photosensitive sub-circuit (5) and the second photosensitive sub-circuit (6); the anode of the light emitting diode D1 sub-circuit (4) is connected with the first receiving end of the first driving circuit (1), the cathode is connected with the second receiving end of the first driving circuit (1), or the anode of the light emitting diode D1 sub-circuit (4) is connected with the first receiving end of the second driving circuit (2), and the cathode is connected with the second receiving end of the second driving circuit (2);
the first photosensitive sub-circuit (5) is connected with the second photosensitive sub-circuit (6), the first photosensitive sub-circuit (5) is also connected with a power supply Vcc, the second photosensitive sub-circuit (6) is grounded, and a driving port is arranged between the first photosensitive sub-circuit (5) and the second photosensitive sub-circuit (6);
the first photosensitive sub-circuit (5) reduces the equivalent resistance between the power supply Vcc and the driving port along with the increase of the illumination intensity, and the second photosensitive sub-circuit (6) increases the equivalent resistance between the signal output port and the ground along with the increase of the illumination intensity.
4. The three-level inverter driving structure according to claim 1, wherein: the light emitting diode D1 sub-circuit (4) comprises one or a plurality of light emitting diodes D1 which are sequentially connected in series.
5. The three-level inverter driving structure according to claim 1, wherein: the first photosensitive sub-circuit (5) comprises a photosensitive NPN triode Q1, wherein the base electrode of the photosensitive NPN triode Q1 is optically coupled with the light emitting diode D1 sub-circuit (4), the collector electrode is connected with a power supply Vcc, and the emitter electrode is connected with the driving port and the second photosensitive sub-circuit (6).
6. The three-level inverter driving structure according to claim 1, wherein: the second photosensitive subcircuit (6) comprises a photosensitive PNP transistor Q2, wherein the base electrode of the photosensitive PNP transistor Q2 is optically coupled with the light emitting diode D1 subcircuit (4), the emitting electrode is connected with the driving port and the first photosensitive subcircuit (5), and the collecting electrode is grounded with a signal ground Vee.
7. A three-level inverter driving structure according to claim 1, wherein buffers are provided in series between the first driving circuit (1) and the signal generating circuit (3) and between the second driving circuit (2) and the signal generating signal.
8. A three-level inverter driving method applied to the three-level inverter driving structure as claimed in any one of claims 1 to 7, comprising:
the signal generation circuit (3) generates two groups of control signals, and each group of control signals comprises a first control signal and a second control signal;
each first drive circuit (1) receives a set of control signals; each second driving circuit (2) receives a set of control signals received by the first driving circuit (1) connected thereto;
the first driving circuit (1) outputs a conducting signal in a state that the potential of a first control signal in each group of control signals is higher than that of a second control signal by more than a preset value;
in a state that the potential of the second control signal in each group of control signals is higher than that of the first control signal by more than a preset value, the second driving circuit (2) outputs a conducting signal so that the first driving circuit (1) and the second driving circuit (2) do not output the conducting signal at the same time.
9. An inverter, characterized in that: a three-level inverter drive structure comprising the structure as claimed in any one of claims 1-7.
10. An electronic device, characterized in that: comprising an inverter as claimed in claim 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311130293.0A CN117175910A (en) | 2023-08-31 | 2023-08-31 | Three-level inverter driving structure and method, inverter and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311130293.0A CN117175910A (en) | 2023-08-31 | 2023-08-31 | Three-level inverter driving structure and method, inverter and electronic equipment |
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| CN117175910A true CN117175910A (en) | 2023-12-05 |
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| CN202311130293.0A Pending CN117175910A (en) | 2023-08-31 | 2023-08-31 | Three-level inverter driving structure and method, inverter and electronic equipment |
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| Country | Link |
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| CN (1) | CN117175910A (en) |
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