CN117174149A

CN117174149A - Memory control method, memory storage device and memory control circuit unit

Info

Publication number: CN117174149A
Application number: CN202311263457.7A
Authority: CN
Inventors: 曾彦錞; 刘世华
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2023-09-27
Filing date: 2023-09-27
Publication date: 2023-12-05

Abstract

The invention provides a memory control method, a memory storage device and a memory control circuit unit. The method comprises the following steps: detecting a state of a memory storage device; and adjusting an operation mode of the memory storage device according to the state of the memory storage device, wherein in the first operation mode, a first waiting time before the memory storage device enters the power saving mode is longer than a second waiting time before the memory storage device enters the power saving mode in the second operation mode. Therefore, the power consumption of the memory storage device can be further reduced under the premise of not affecting the performance of the memory storage device as much as possible.

Description

Memory control method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory control technology, and more particularly, to a memory control method, a memory storage device, and a memory control circuit unit.

Background

Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable electronic devices.

The memory storage device of partial type can automatically enter the power saving mode after being idle for more than a preset time length. Thus, the power consumption of the memory storage device in the idle state can be reduced. Generally, the predetermined time period is set to an optimal value before the memory storage device is shipped, so as to balance the performance and the power consumption of the memory storage device as much as possible after the memory storage device is shipped. However, in practice, no matter how the preset time period is optimized before the memory storage device leaves the factory, once the working state of the memory storage device changes, the balance between the performance and the power consumption of the memory storage device is easily broken (for example, the performance of the memory storage device is greatly reduced or the power consumption of the memory storage device is greatly increased), thereby affecting the user experience.

Disclosure of Invention

The present invention provides a memory control method, a memory storage device and a memory control circuit unit, which can improve the above problems.

Exemplary embodiments of the present invention provide a memory control method for a memory storage device. The memory control method includes: detecting a state of the memory storage device; and adjusting an operation mode of the memory storage device according to the state of the memory storage device, wherein the operation mode comprises a first operation mode and a second operation mode, a first waiting time before the memory storage device enters a power saving mode is longer than a second waiting time before the memory storage device enters the power saving mode in the second operation mode.

In an example embodiment of the invention, the second latency is zero.

In an example embodiment of the present invention, the step of adjusting the operation mode of the memory storage device according to the state of the memory storage device comprises: updating a reference value according to the state of the memory storage device, wherein the reference value relates to the performance of the memory storage device within a target time range; and adjusting the operation mode of the memory storage device according to the reference value.

In an example embodiment of the present invention, the step of updating the reference value according to the state of the memory storage device includes: and updating the reference value according to at least one of the written data quantity, the read data quantity and the interface transmission data quantity of the memory storage device in the target time range.

In an example embodiment of the present invention, the step of updating the reference value according to the at least one of the write data amount, the read data amount, and the interface transmission data amount of the memory storage device within the target time range includes: obtaining at least one performance evaluation parameter according to the at least one of the write data amount, the read data amount and the interface transmission data amount of the memory storage device in the target time range; in response to a first performance evaluation parameter of the at least one performance evaluation parameter meeting a first update condition, adding a first adjustment value to the reference value; and subtracting a second adjustment value from the reference value in response to the first performance assessment parameter meeting a second update condition, wherein the first update condition is different from the second update condition.

In an example embodiment of the present invention, the step of adjusting the operation mode of the memory storage device according to the reference value comprises: in response to the reference value meeting a first trigger condition, setting the operating mode of the memory storage device to the first operating mode; and in response to the reference value meeting a second trigger condition, setting the operating mode of the memory storage device to the second operating mode, wherein the first trigger condition is different from the second trigger condition.

In an example embodiment of the present invention, in the power saving mode, the memory storage device has the capability to hold data stored in a buffer memory.

In an example embodiment of the invention, the power saving mode entered in the first operation mode is the same as the power saving mode entered in the second operation mode.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: detecting a state of the memory storage device; and adjusting an operation mode of the memory storage device according to the state of the memory storage device, wherein the operation mode comprises a first operation mode and a second operation mode, a first waiting time before the memory storage device enters a power saving mode is longer than a second waiting time before the memory storage device enters the power saving mode in the second operation mode.

In an example embodiment of the present invention, the operation of the memory control circuit unit to adjust the operation mode of the memory storage device according to the state of the memory storage device includes: updating a reference value according to the state of the memory storage device, wherein the reference value relates to the performance of the memory storage device within a target time range; and adjusting the operation mode of the memory storage device according to the reference value.

In an example embodiment of the present invention, the operation of the memory control circuit unit to update the reference value according to the state of the memory storage device includes: and updating the reference value according to at least one of the written data quantity, the read data quantity and the interface transmission data quantity of the memory storage device in the target time range.

In an example embodiment of the present invention, the operation of the memory control circuit unit updating the reference value according to the at least one of the write data amount, the read data amount, and the interface transmission data amount of the memory storage device within the target time range includes: obtaining at least one performance evaluation parameter according to the at least one of the write data amount, the read data amount and the interface transmission data amount of the memory storage device in the target time range; in response to a first performance evaluation parameter of the at least one performance evaluation parameter meeting a first update condition, adding a first adjustment value to the reference value; and subtracting a second adjustment value from the reference value in response to the first performance assessment parameter meeting a second update condition, wherein the first update condition is different from the second update condition.

In an example embodiment of the present invention, the operation of the memory control circuit unit to adjust the operation mode of the memory storage device according to the reference value includes: in response to the reference value meeting a first trigger condition, setting the operating mode of the memory storage device to the first operating mode; and in response to the reference value meeting a second trigger condition, setting the operating mode of the memory storage device to the second operating mode, wherein the first trigger condition is different from the second trigger condition.

The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is to: detecting a state of the memory storage device; and adjusting an operation mode of the memory storage device according to the state of the memory storage device, wherein the operation mode comprises a first operation mode and a second operation mode, a first waiting time before the memory storage device enters a power saving mode is longer than a second waiting time before the memory storage device enters the power saving mode in the second operation mode.

In an example embodiment of the present invention, the operation of the memory management circuit to adjust the operation mode of the memory storage device according to the state of the memory storage device comprises: updating a reference value according to the state of the memory storage device, wherein the reference value relates to the performance of the memory storage device within a target time range; and adjusting the operation mode of the memory storage device according to the reference value.

In an example embodiment of the present invention, the operation of the memory management circuit to update the reference value according to the state of the memory storage device comprises: and updating the reference value according to at least one of the written data quantity, the read data quantity and the interface transmission data quantity of the memory storage device in the target time range.

In an example embodiment of the present invention, the operation of the memory management circuit to update the reference value according to the at least one of the write data amount, the read data amount, and the interface transmission data amount of the memory storage device within the target time range includes: obtaining at least one performance evaluation parameter according to the at least one of the write data amount, the read data amount and the interface transmission data amount of the memory storage device in the target time range; in response to a first performance evaluation parameter of the at least one performance evaluation parameter meeting a first update condition, adding a first adjustment value to the reference value; and subtracting a second adjustment value from the reference value in response to the first performance assessment parameter meeting a second update condition, wherein the first update condition is different from the second update condition.

In an example embodiment of the present invention, the operation of the memory management circuit to adjust the operation mode of the memory storage device according to the reference value comprises: in response to the reference value meeting a first trigger condition, setting the operating mode of the memory storage device to the first operating mode; and in response to the reference value meeting a second trigger condition, setting the operating mode of the memory storage device to the second operating mode, wherein the first trigger condition is different from the second trigger condition.

Based on the above, by dynamically determining whether to operate the memory storage device in the first operation mode or the second operation mode, the waiting time of the memory storage device before entering the power saving mode can be dynamically adjusted. Therefore, the power consumption of the memory storage device can be further reduced under the premise of not affecting the performance of the memory storage device as much as possible.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention;

FIG. 5 is a schematic diagram of a memory control circuit unit shown according to an example embodiment of the invention;

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating controlling a memory storage device to operate in a first mode of operation or a second mode of operation at different points in time according to an example embodiment of the invention;

FIG. 8 is a schematic diagram illustrating controlling a memory storage device to enter a power saving mode in a first mode of operation according to an example embodiment of the invention;

FIG. 9 is a schematic diagram illustrating controlling a memory storage device to enter a power saving mode in a second mode of operation according to an example embodiment of the present invention;

FIG. 10 is a flowchart of a memory control method according to an example embodiment of the invention;

FIG. 11 is a flowchart of a memory control method according to an example embodiment of the invention;

fig. 12 is a flowchart of a memory control method according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.

In an example embodiment, host system 11 may be coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, host system 11 may be connected to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 via a wired or wireless connection via the data transmission interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a wide variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to a substrate of the host system.

Fig. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the peripheral component interconnect Express (Peripheral Component Interconnect Express, PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may be a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) compliant standard, a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware and performing operations of writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a second-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states. By applying a read voltage, it is possible to determine which memory state a memory cell belongs to, and thereby obtain one or more bits stored in the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical program units, and the physical program units may constitute a plurality of physical erase units. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and a physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

Fig. 5 is a schematic diagram of a memory control circuit unit according to an example embodiment of the invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53.

The memory management circuit 51 is used for controlling the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and when the memory storage device 10 is operated, the control commands are executed to perform operations such as writing, reading and erasing data. The operation of the memory management circuit 51 is explained as follows, which is equivalent to the explanation of the operation of the memory control circuit unit 42.

In an example embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit unit 42 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the ram of the memory management circuit 51. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells of the rewritable nonvolatile memory module 43. The memory write circuit is used for issuing a write instruction sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory read circuit is used for issuing a read instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erase circuit is used for issuing an erase command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 43 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 52 is connected to the memory management circuit 51. Memory management circuitry 51 may communicate with host system 11 through host interface 52. The host interface 52 is used to receive and identify the commands and data transmitted by the host system 11. For example, instructions and data transmitted by host system 11 may be transmitted to memory management circuit 51 via host interface 52. In addition, the memory management circuitry 51 may communicate data to the host system 11 through the host interface 52. In the present example embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format acceptable to the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 is to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection (Garbage Collection, GC) operations, etc.). These sequences of instructions are, for example, generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 obtains the write command from the host system 11, the error checking and correcting circuit 54 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 54 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.

The buffer memory 55 is connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of fig. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of fig. 5 may include a flash memory management circuit.

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a memory area 601 and a spare (spare) area 602.

In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also be referred to as a Virtual Block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In an exemplary embodiment, a dummy block may also include one or more physical erase units.

The entity units 610 (0) -610 (a) in the storage area 601 are used to store user data (e.g., user data from the host system 11 of fig. 1). For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle area 602. In addition, the physical cells in the free area 602 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool (free pool).

The memory management circuit 51 may configure the logic units 612 (0) through 612 (C) to map the physical units 610 (0) through 610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic programming unit or be composed of a plurality of consecutive or non-consecutive logic addresses.

It should be noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is currently mapped by a certain logic unit, the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not mapped by any logic unit, the data stored in the entity unit is invalid.

The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

In an example embodiment, memory storage device 10 may be in a busy state to process instructions from host system 11. For example, in accordance with instructions from the host system 11, the memory management circuit 51 may instruct the rewritable nonvolatile memory module 43 to perform operations such as reading, writing, or erasing. During the read, write or erase operations performed by the rewritable nonvolatile memory module 43, the memory storage device 10 is busy. After completing the instructions from the host system 11, the memory storage device 10 may be in an idle state during the period when the rewritable nonvolatile memory module 43 is not performing operations such as reading, writing or erasing.

In an example embodiment, the memory storage device 10 may operate in a power saving mode and a normal mode to balance performance and power consumption of the memory storage device 10. For example, the power consumption (e.g., power consumption per unit time) of the memory storage device 10 in the power saving mode may be lower than the power consumption of the memory storage device 10 in the normal mode. In addition, the performance of the memory storage device 10 in the normal mode may be higher than the performance of the memory storage device 10 in the power saving mode.

In an example embodiment, in a power saving mode, power to at least some of the circuit modules in the memory storage device 10 may be turned off. For example, in a power saving mode, power to the rewritable nonvolatile memory module 43 may be cut off to reduce power consumption of the memory storage device 10.

In an example embodiment, in a power saving mode, power to at least one buffer memory (e.g., buffer memory 55) in memory storage device 10 may be maintained (i.e., not turned off). Thus, in the power saving mode, the memory storage device 10 still has the ability to hold data stored in the buffer memory.

In an exemplary embodiment, in the power saving mode, the power supply to both the rewritable nonvolatile memory module 43 and the buffer memory (e.g., the buffer memory 55) can be cut off to reduce the power consumption of the memory storage device 10. It should be noted that once power to a buffer memory (e.g., buffer memory 55) is cut off, data stored in the buffer memory may be lost.

In an example embodiment, the amount of read data per unit time, the amount of write data per unit time, the amount of interface transfer data per unit time, and/or the system clock (clock) of the memory storage device 10 may also be reduced in the power saving mode compared to the normal mode to reduce the power consumption of the memory storage device 10. However, since the amount of data read per unit time, the amount of data written per unit time, the amount of data transferred per unit time, and/or the system clock of the memory storage device 10 are reduced, the performance of the memory storage device 10 is correspondingly reduced in the power saving mode. In addition, many more types of parameters or system configurations may be adjusted depending on whether the memory storage device 10 is currently operating in a normal mode or a power saving mode, and the invention is not limited.

In an example embodiment, the memory storage device 10 may perform switching between the normal mode and the power saving mode based on a plurality of operation modes. For example, the plurality of operating modes includes a first operating mode and a second operating mode. In particular, in the first operation mode, the latency (also referred to as the first latency) before the memory storage device 10 enters the power saving mode may be longer than the latency (also referred to as the second latency) before the memory storage device 10 enters the power saving mode in the second operation mode. For example, assuming that the first latency is N milliseconds (ms) and the second latency is M ms, N may be greater than M.

In an example embodiment, it is assumed that the memory storage device 10 operates in a first mode of operation. In the first mode of operation, the memory management circuit 51 may count the length of time (also referred to as the first length of time) that the memory storage device 10 is in an idle state. The memory management circuit 51 may determine whether the first time period exceeds a first waiting time (e.g., N milliseconds). In response to the first length of time exceeding the first latency, the memory management circuit 51 may control the memory storage device 10 to enter a power saving mode. However, if the first period of time does not exceed the first waiting time, the memory management circuit 51 may not control the memory storage device 10 to enter the power saving mode. For example, if the first time period does not exceed the first waiting time, the memory storage device 10 may be maintained in the normal mode.

In an example embodiment, it is assumed that the memory storage device 10 operates in the second mode of operation. In the second mode of operation, the memory management circuit 51 may count the length of time the memory storage device 10 is in an idle state (also referred to as a second length of time). The memory management circuit 51 may determine whether the second length of time exceeds a second latency (e.g., M milliseconds, and M is less than N). In response to the second length of time exceeding the second latency, the memory management circuit 51 may control the memory storage device 10 to enter a power saving mode. However, if the second length of time does not exceed the second waiting time, the memory management circuit 51 may not control the memory storage device 10 to enter the power saving mode. For example, if the second length of time does not exceed the second waiting time, the memory storage device 10 may remain in the normal mode.

In other words, the memory storage device 10 needs to be maintained in the idle state for a longer time in the first operation mode than in the second operation mode, and then can enter the idle mode. However, in the second operation mode, the memory storage device 10 can quickly enter the power saving mode as long as it can maintain the idle state for a short time (even without any waiting time).

In an example embodiment, the second waiting time may also be zero. In the case where the second latency is zero (i.e., m=0), in the second operation mode, in response to the memory storage device 10 being in or entering an idle state (e.g., switching from a normal operation state to an idle state), the memory management circuit 51 may directly control the memory storage device 10 to enter a power saving mode without any latency.

In an exemplary embodiment, the memory management circuit 51 may dynamically determine whether to operate the memory storage device 10 in the first operation mode or the second operation mode according to the current requirements. Thus, the power consumption of the memory storage device 10 can be effectively reduced without affecting the performance of the memory storage device 10 as much as possible. From another perspective, by dynamically adjusting (e.g., increasing or decreasing) the latency of the memory storage device 10 to enter the power saving mode, the power consumption of the memory storage device 10 can be effectively reduced without affecting the user experience as much as possible.

In an example embodiment, the memory management circuit 51 may detect a state (also referred to as a performance state) of the memory storage device 10. This performance state relates to the performance of the memory storage device 10 over a time frame (also referred to as a target time frame). For example, the target time range may be 250 milliseconds, and the target time range may be adjusted according to the actual needs.

In an example embodiment, the memory management circuit 51 may dynamically adjust the operating mode of the memory storage device 10 according to the performance state. For example, the memory management circuit 51 may switch the operating mode of the memory storage device 10 from the first operating mode to the second operating mode or from the second operating mode to the first operating mode depending on the detected performance state. Alternatively, the memory management circuit 51 may also temporarily not change the operating mode of the memory storage device 10 based on the detected performance state.

In an example embodiment, the memory management circuit 51 may update a reference value according to the performance status of the memory storage device 10. This reference value relates to the performance of the memory storage device 10 over a target time frame. For example, the reference value may reflect the performance and/or the trend of performance of the memory storage device 10 over a target time frame. The memory management circuit 51 can adjust the operation mode of the memory storage device 10 according to the reference value.

In an exemplary embodiment, the memory management circuit 51 may update the reference value according to at least one of the write data amount, the read data amount, and the interface transmission data amount of the memory storage device 10 within the target time range. For example, this amount of write data may include an amount of write data per unit time of the memory storage device 10 within a target time range. This amount of read data may include an amount of read data per unit time of the memory storage device 10 within a target time range. This amount of interface transfer data may include the amount of interface transfer data per unit time of memory storage device 10 within a target time range. Thus, the updated reference value may also reflect the performance and/or the performance trend of the memory storage device 10 within the target time range, for example, the write data amount per unit time, the read data amount per unit time, and/or the transmission data amount per unit time of the interface of the memory storage device 10 within the target time range.

In an example embodiment, the amount of write data of the memory storage device 10 within the target time range may include an amount of write data per unit time of the memory storage device 10 detected at one or more points in time within the target time range. For example, this amount of write data may be positively correlated to the total number of write instructions that memory storage device 10 retrieves from host system 11 over a target time frame.

In an example embodiment, the amount of read data of the memory storage device 10 within the target time range may include an amount of read data per unit time of the memory storage device 10 detected at one or more points in time within the target time range. For example, this amount of read data may be positively correlated to the total number of read instructions that memory storage device 10 retrieves from host system 11 over a target time frame.

In an example embodiment, the amount of interface transfer data of the memory storage device 10 within the target time range may include an amount of interface transfer data per unit time between the memory storage device 10 and the host system 11 detected at one or more points in time within the target time range. For example, this amount of interface transfer data may be positively correlated to the total number of instructions fetched by memory storage device 10 from host system 11 over a target time frame and/or the total amount of data transferred between memory storage device 10 and host system 11 over the target time frame.

In an exemplary embodiment, the memory management circuit 51 may obtain at least one performance evaluation parameter according to at least one of the write data amount, the read data amount, and the interface transmission data amount of the memory storage device 10 within the target time range. For example, one performance evaluation parameter may reflect or be related to the amount of write data, the amount of read data, and/or the amount of interface transfer data of the memory storage device 10 at a point in time (also referred to as a sampling point) within a target time frame. Alternatively, the performance evaluation parameters may reflect the trend of the write data amount, the read data amount, and/or the interface transmission data amount of the memory storage device 10 within the target time range.

In an example embodiment, the memory management circuit 51 may determine whether one of the performance evaluation parameters (also referred to as a first performance evaluation parameter) meets an update condition (also referred to as a first update condition). In response to the first performance evaluation parameter meeting the first update condition, the memory management circuit 51 may add an adjustment value (also referred to as a first adjustment value) to the reference value to update the reference value. For example, the first adjustment value may be any value greater than zero.

In an example embodiment, the memory management circuit 51 may determine whether the first performance evaluation parameter meets another refresh condition (also referred to as a second refresh condition). In response to the first performance evaluation parameter meeting the second update condition, the memory management circuit 51 may subtract an adjustment value (also referred to as a second adjustment value) from the reference value to update the reference value. For example, the second adjustment value may be any value greater than zero, and the first adjustment value may be the same or different from the second adjustment value.

In an exemplary embodiment, the memory management circuit 51 may determine whether the first performance evaluation parameter is smaller than a predetermined value (also referred to as a first predetermined value). In response to the first performance-assessment parameter being less than the first preset value, the memory management circuit 51 may determine that the first performance-assessment parameter meets a first update condition and update the reference value (e.g., add the reference value to the first adjustment value). However, if the first performance evaluation parameter is not less than the first preset value, the memory management circuit 51 may determine that the first performance evaluation parameter does not meet the first update condition and does not update the reference value.

In an exemplary embodiment, the memory management circuit 51 may determine whether the first performance evaluation parameter is greater than a predetermined value (also referred to as a second predetermined value). In response to the first performance-assessment parameter being greater than a second preset value, the memory management circuit 51 may determine that the second performance-assessment parameter meets a second update condition and update the reference value (e.g., subtract a second adjustment value from the reference value). However, if the first performance evaluation parameter is not greater than the second preset value, the memory management circuit 51 may determine that the first performance evaluation parameter does not meet the second update condition and does not update the reference value.

In an exemplary embodiment, assume that the first preset value is P1, the second preset value is P2, the first adjustment value is S1, the second adjustment value is S2, and P1 is smaller than P2. In an example embodiment, in response to the first performance evaluation parameter being less than P1, the memory management circuit 51 may determine that the first performance evaluation parameter meets a first update condition and add S1 to the reference value to obtain an updated reference value. Alternatively, in an example embodiment, in response to the first performance level parameter being greater than P2, the memory management circuit 51 may determine that the first performance level parameter meets the second update condition and subtract S2 from the reference value to obtain an updated reference value.

In an exemplary embodiment, more update conditions may be used to update the reference value, and the adjustment value corresponding to each update condition may be set according to the actual requirement. Then, in response to a performance evaluation parameter meeting an update condition, the memory management circuit 51 may update the reference value according to an adjustment value corresponding to the update condition.

In an example embodiment, the memory management circuit 51 may determine whether the reference value (e.g., the updated reference value) meets a trigger condition (also referred to as a first trigger condition). In an example embodiment, in response to the reference value meeting a first trigger condition, the memory management circuit 51 may set the operation mode of the memory storage device 10 to a first operation mode. However, if the reference value does not meet the first trigger condition, the memory management circuit 51 may not change the operation mode of the memory storage device 10 (e.g., maintain the operation mode of the memory storage device 10 in the second operation mode).

In an example embodiment, the memory management circuit 51 may determine whether the reference value (e.g., the updated reference value) meets another trigger condition (also referred to as a second trigger condition). In an example embodiment, in response to the reference value meeting a second trigger condition, the memory management circuit 51 may set the operation mode of the memory storage device 10 to a second operation mode. However, if the reference value does not meet the second trigger condition, the memory management circuit 51 may not change the operation mode of the memory storage device 10 (e.g., maintain the operation mode of the memory storage device 10 in the first operation mode).

In an exemplary embodiment, the memory management circuit 51 may determine whether the reference value is less than a threshold value (also referred to as a first threshold value). In an exemplary embodiment, if the reference value is smaller than the first threshold value, the trend of the performance of the memory storage device 10 in the target time range is: the performance of the memory storage device 10 does not significantly decrease (and may even gradually increase) over the target time frame. Accordingly, in response to the reference value being less than the first threshold, the memory management circuit 51 may determine that the reference value meets the first trigger condition and set the operating mode of the memory storage device 10 to the first operating mode. However, if the reference value is not less than the first threshold value, the memory management circuit 51 may determine that the reference value does not meet the first trigger condition and does not adjust the operation mode of the memory storage device 10.

In an exemplary embodiment, in the case that the performance of the memory storage device 10 in the target time range is not significantly reduced (may even gradually increase), the operation mode of the memory storage device 10 is set to the first operation mode, and the time point when the memory storage device 10 enters the power saving mode may be delayed and/or the frequency of the memory storage device 10 entering the power saving mode may be reduced. Thus, unnecessary power consumption of the memory storage device 10 due to frequent power-saving mode entry and exit of the memory storage device 10 under the condition that the performance of the memory storage device 10 is not significantly reduced (even possibly gradually increased) can be avoided.

In an exemplary embodiment, the memory management circuit 51 may determine whether the reference value is greater than a threshold value (also referred to as a second threshold value). In an exemplary embodiment, if the reference value is greater than the second threshold value, the trend of the performance of the memory storage device 10 in the target time range is: the performance of the memory storage device 10 has significantly degraded over the target time frame. Accordingly, in response to the reference value being greater than the second threshold, the memory management circuit 51 may determine that the reference value meets the second trigger condition and set the operating mode of the memory storage device 10 to the second operating mode. However, if the reference value is not greater than the second threshold value, the memory management circuit 51 may determine that the reference value does not meet the second trigger condition and does not adjust the operation mode of the memory storage device 10.

In an exemplary embodiment, when the performance of the memory storage device 10 has significantly decreased within the target time range, the operation mode of the memory storage device 10 is set to the second operation mode, so that the time point when the memory storage device 10 enters the power saving mode can be advanced and/or the frequency of the memory storage device 10 entering the power saving mode can be increased. Thus, the power consumption of the memory storage device 10 can be effectively reduced in the case where the performance of the memory storage device 10 has been significantly reduced.

Fig. 7 is a schematic diagram illustrating controlling the memory storage device to operate in a first operation mode or a second operation mode at different points in time according to an exemplary embodiment of the present invention. Referring to fig. 7, assume that the first threshold is THR (1), the second threshold is THR (2), and THR (1) is smaller than THR (2). In an exemplary embodiment, between the time points T (0) to T (1) and the time points T (2) to T (3), in response to the reference value RV being smaller than THR (1), the memory management circuit 51 may determine that the reference value RV meets the first trigger condition and set the operation mode of the memory storage device 10 to the first mode (i.e. the first operation mode). Thus, between the time points T (0) to T (1) and the time points T (2) to T (3), the memory storage device 10 can perform switching between the normal mode and the power saving mode based on the first operation mode, as shown in fig. 8.

Fig. 8 is a schematic diagram illustrating controlling a memory storage device to enter a power saving mode in a first operation mode according to an exemplary embodiment of the present invention. Referring to fig. 8, in the first operation mode, it is assumed that the memory storage device 10 is in or enters the idle state from the time point T (4). The memory management circuit 51 may maintain the memory storage device 10 in the normal mode before the length of time Δt (1) for which the memory storage device 10 is in the idle state (i.e., the first length of time) exceeds the waiting time WT (1) (i.e., the first waiting time). It should be noted that after the time point T (5), the memory management circuit 51 may control the memory storage device 10 to enter the power saving mode in response to the time length Δt (1) exceeding the waiting time WT (1) (i.e., Δt (1) > WT (1)).

Referring back to fig. 7, between the time points T (1) to T (2), in response to the reference value RV being greater than THR (2), the memory management circuit 51 may determine that the reference value RV meets the second trigger condition and set the operation mode of the memory storage device 10 to the second mode (i.e. the second operation mode). Thus, between the time points T (1) to T (2), the memory storage device 10 can perform switching between the normal mode and the power saving mode based on the second operation mode, as shown in fig. 9.

Fig. 9 is a schematic diagram illustrating controlling a memory storage device to enter a power saving mode in a second operation mode according to an exemplary embodiment of the present invention. Referring to fig. 9, in the second operation mode, it is assumed that the memory storage device 10 is in or enters the idle state from the time point T (6). The memory management circuit 51 maintains the memory storage device 10 in the normal mode until the length of time Δt (2) for which the memory storage device 10 is in the idle state (i.e., the second length of time) exceeds the waiting time WT (2) (i.e., the second waiting time). It should be noted that, at the time point T (7), the memory management circuit 51 may control the memory storage device 10 to enter the power saving mode in response to the time period Δt (2) exceeding the waiting time WT (2) (i.e., Δt (2) > WT (2)). Note that the waiting time WT (2) in fig. 9 is less than the waiting time WT (1) in fig. 8 (i.e., WT (2) < WT (1)).

In an example embodiment, the latency WT (2) may also be zero. In the case where the waiting time WT (2) is zero (i.e., WT (2) =0), at the time point T (6), in response to the memory storage device 10 entering the idle state, the memory management circuit 51 may directly control the memory storage device 10 to enter the power saving mode without any waiting time.

In an example embodiment, the power saving mode entered in the first operation mode is the same as the power saving mode entered in the second operation mode. That is, regardless of whether the memory storage device 10 supports several power saving modes (e.g., power saving modes in different power states or preset sleep, or standby modes, etc.), the power saving mode entered in the first operation mode and the power saving mode entered in the second operation mode refer to the same power saving mode among the one or more power saving modes, and are not different (types of) power saving modes.

In an exemplary embodiment, the difference between entering the power saving mode in the first operation mode and entering the power saving mode in the second operation mode is only that the waiting time before entering the power saving mode is different, and after the corresponding waiting time, the entering power saving modes are not different from each other. Alternatively, in an exemplary embodiment, the power saving mode entered in the first operation mode may be different from the power saving mode entered in the second operation mode, depending on the practical requirements.

Fig. 10 is a flowchart of a memory control method according to an exemplary embodiment of the present invention. Referring to fig. 10, in step S1001, a state of a memory storage device is detected. In step S1002, an operation mode of the memory storage device is adjusted according to a state of the memory storage device, wherein the operation mode includes a first operation mode and a second operation mode. In particular, in the first mode of operation, the first latency of the memory storage device before entering the power saving mode is longer than the second latency of the memory storage device before entering the power saving mode in the second mode of operation.

Fig. 11 is a flowchart of a memory control method according to an exemplary embodiment of the present invention. Referring to fig. 11, in step S1101, a state of a memory storage device is detected. In step S1102, the reference value is updated according to the state of the memory storage device. In step S1103, it is determined whether the reference value meets the first trigger condition. If the reference value meets the first trigger condition, in step S1104, the operation mode of the memory storage device is set to the first operation mode. If the reference value does not meet the first trigger condition, in step S1105, it is determined whether the reference value meets the second trigger condition. If the reference value meets the second trigger condition, in step S1106, the operation mode of the memory storage device is set to the second operation mode. If the reference value does not meet the first trigger condition and the second trigger condition, the process returns to step S1101 and maintains the current operation mode. In addition, after steps S1104 and S1106, the process may also return to step S1101.

Fig. 12 is a flowchart of a memory control method according to an exemplary embodiment of the present invention. Referring to fig. 12, in step S1201, performance evaluation parameters are obtained according to at least one of the write data amount, the read data amount and the interface transmission data amount of the memory storage device within the target time range. In step S1202, it is determined whether the performance evaluation parameter meets the first update condition. If the performance evaluation parameter meets the first update condition, in step S1203, the reference value is increased (e.g. the reference value is added with the first adjustment value). If the performance evaluation parameter does not meet the first update condition, in step S1204, it is determined whether the performance evaluation parameter meets the second update condition. If the performance evaluation parameter meets the second update condition, in step S1205, the reference value is reduced (e.g., the reference value is subtracted by the second adjustment value). If the performance evaluation parameter does not meet the first update condition and the second update condition, the process returns to step S1201. In addition, after steps S1203 and S1205, the process may also return to step S1201.

However, the steps in fig. 10 to 12 are described in detail above, and will not be described here again. It should be noted that each step in fig. 10 to 12 may be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the methods of fig. 10 to 12 may be used with the above exemplary embodiments, or may be used alone, and the present invention is not limited thereto.

In summary, the memory control method, the memory storage device and the memory control circuit unit provided by the invention can dynamically adjust the operation mode of the memory storage device according to the performance state of the memory storage device, thereby changing the waiting time of the memory storage device before entering the power saving mode. Therefore, the power consumption of the memory storage device can be further reduced on the premise that the efficiency of the memory storage device is not affected as much as possible, and therefore the user experience is improved.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A memory control method for a memory storage device, the memory control method comprising:

Detecting a state of the memory storage device; and

adjusting an operating mode of the memory storage device according to the state of the memory storage device,

wherein the modes of operation include a first mode of operation and a second mode of operation,

in the first mode of operation, a first latency time before the memory storage device enters a power saving mode is longer than a second latency time before the memory storage device enters the power saving mode in the second mode of operation.

2. The memory control method of claim 1, wherein the second latency is zero.

3. The memory control method according to claim 1, wherein the step of adjusting the operation mode of the memory storage device according to the state of the memory storage device comprises:

updating a reference value according to the state of the memory storage device, wherein the reference value relates to the performance of the memory storage device within a target time range; and

the operating mode of the memory storage device is adjusted according to the reference value.

4. The memory control method according to claim 3, wherein the step of updating the reference value according to the state of the memory storage device comprises:

And updating the reference value according to at least one of the written data quantity, the read data quantity and the interface transmission data quantity of the memory storage device in the target time range.

5. The memory control method according to claim 4, wherein the step of updating the reference value in accordance with the at least one of the write data amount, the read data amount, and the interface transmission data amount of the memory storage device within the target time range includes:

obtaining at least one performance evaluation parameter according to the at least one of the write data amount, the read data amount and the interface transmission data amount of the memory storage device in the target time range;

in response to a first performance evaluation parameter of the at least one performance evaluation parameter meeting a first update condition, adding a first adjustment value to the reference value; and

in response to the first performance evaluation parameter meeting a second update condition, subtracting a second adjustment value from the reference value,

wherein the first update condition is different from the second update condition.

6. The memory control method according to claim 3, wherein the step of adjusting the operation mode of the memory storage device according to the reference value comprises:

In response to the reference value meeting a first trigger condition, setting the operating mode of the memory storage device to the first operating mode; and

in response to the reference value meeting a second trigger condition, setting the operating mode of the memory storage device to the second operating mode,

wherein the first trigger condition is different from the second trigger condition.

7. The memory control method according to claim 1, wherein in the power saving mode, the memory storage device has a capability to hold data stored in a buffer memory.

8. The memory control method according to claim 1, wherein the power saving mode entered in the first operation mode is the same as the power saving mode entered in the second operation mode.

9. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable nonvolatile memory module; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to:

Detecting a state of the memory storage device; and

10. The memory storage device of claim 9, wherein the second latency is zero.

11. The memory storage device of claim 9, wherein the operation of the memory control circuit unit to adjust the operating mode of the memory storage device according to the state of the memory storage device comprises:

12. The memory storage device of claim 11, wherein the operation of the memory control circuit unit to update the reference value according to the state of the memory storage device comprises:

13. The memory storage device of claim 12, wherein the operation of the memory control circuit unit to update the reference value according to the at least one of the amount of write data, the amount of read data, and the amount of interface transfer data of the memory storage device within the target time range comprises:

14. The memory storage device of claim 11, wherein the operation of the memory control circuit unit to adjust the operating mode of the memory storage device according to the reference value comprises:

15. The memory storage device of claim 9, wherein in the power saving mode, the memory storage device has the ability to hold data stored in a buffer memory.

16. The memory storage device of claim 9, wherein the power saving mode entered in the first mode of operation is the same as the power saving mode entered in the second mode of operation.

17. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:

a host interface for connecting to a host system;

a memory interface to connect to the rewritable non-volatile memory module; and

a memory management circuit coupled to the host interface and the memory interface,

Wherein the memory management circuit is to:

detecting a state of the memory storage device; and

18. The memory control circuit unit of claim 17, wherein the second latency is zero.

19. The memory control circuit unit of claim 17, wherein the operation of the memory management circuit to adjust the operating mode of the memory storage device according to the state of the memory storage device comprises:

20. The memory control circuit unit of claim 19, wherein the operation of the memory management circuit to update the reference value according to the state of the memory storage device comprises:

21. The memory control circuit unit of claim 20, wherein the operation of the memory management circuit to update the reference value according to the at least one of the amount of write data, the amount of read data, and the amount of interface transfer data of the memory storage device within the target time range comprises:

22. The memory control circuit unit of claim 19, wherein the operation of the memory management circuit to adjust the operating mode of the memory storage device according to the reference value comprises:

23. The memory control circuit unit of claim 17, wherein in the power saving mode, the memory storage device has the ability to hold data stored in a buffer memory.

24. The memory control circuit unit of claim 17, wherein the power saving mode entered in the first mode of operation is the same as the power saving mode entered in the second mode of operation.