CN117172208A

CN117172208A - Isolation method and device for verification environment, electronic equipment and storage medium

Info

Publication number: CN117172208A
Application number: CN202311451502.1A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2023-11-02
Filing date: 2023-11-02
Publication date: 2023-12-05
Anticipated expiration: 2043-11-02
Also published as: CN117172208B

Abstract

The disclosure relates to the technical field of integrated circuits, and provides an isolation method, an isolation device, electronic equipment and a storage medium for a verification environment, wherein the method comprises the following steps: respectively constructing macro files corresponding to the subsystems aiming at each subsystem, wherein the macro files comprise connection components of verification IP (Internet protocol) associated with the subsystems and do not comprise connection components of verification IP not associated with the subsystems; closing a verification IP irrelevant to a connection component included in the macro file in the system; and executing macro files corresponding to the Y subsystems in parallel when executing the simulation command to obtain Y execution results respectively corresponding to the Y subsystems, wherein the execution results indicate the correctness of the bus interconnection mode of the corresponding subsystems. According to the isolation method for the verification environment, the subsystems are used as granularity to isolate the verification environment, so that verification of interconnection of a plurality of subsystem buses can be independently carried out in parallel, influences among different subsystems are shielded, labor cost is saved, and verification efficiency is improved.

Description

Isolation method and device for verification environment, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to an isolation method and apparatus for a verification environment, an electronic device, and a storage medium.

Background

In the design process of large-scale integrated circuits, the design and verification of the bus interconnection of the system on a chip is a very important link. Through verifying the system bus interconnection, the error of the bus interconnection configuration can be cleared quickly, and meanwhile, the bandwidth and delay data of the bus in the current interconnection mode can be obtained quickly, so that the bus interconnection mode can be adjusted conveniently.

After the functional complexity of the system on the new generation integrated circuit chip is improved, the system comprises more subsystems, and the system bus interconnection is generally composed of sub-bus interconnection and system main bus interconnection of a plurality of subsystems, so that the bus interconnection mode is more complicated, paths with huge orders of magnitude exist, and all the hosts and slaves must be integrated into one bus interconnection verification environment for verifying all the data paths. The verification environment is similar to a complex network structure, the number of data paths and the complexity of the data paths required to simulate verification can seriously slow down the simulation speed, and the verification labor and the verification progress are also extremely challenging.

Disclosure of Invention

In view of this, the disclosure provides an isolation method, an apparatus, an electronic device, and a storage medium for an authentication environment, where the isolation method for an authentication environment in the embodiments of the disclosure uses a subsystem as a granularity to isolate the authentication environment, so that the authentication of a plurality of subsystems bus interconnection can be independently performed in parallel, thereby shielding the influence between different subsystems, saving labor cost, and improving the authentication efficiency.

According to an aspect of the present disclosure, there is provided an isolation method of a verification environment for isolating the verification environment, the verification environment being an environment for verifying correctness of a bus interconnection manner of a system, the system including X subsystems, X being an integer greater than 1, each subsystem including at least one master and/or at least one slave, each master/slave corresponding to one verification IP, the method comprising: respectively constructing a macro file corresponding to each subsystem, wherein the macro file comprises a connection component of the verification IP associated with the subsystem and does not comprise a connection component of the verification IP not associated with the subsystem; closing a verification IP irrelevant to a connection component included in the macro file in the system; adding macro files corresponding to Y subsystems in a simulation command, wherein Y is more than 1 and less than or equal to X, and Y is an integer; and executing macro files corresponding to the Y subsystems in parallel when executing the simulation command to obtain Y execution results respectively corresponding to the Y subsystems, wherein the execution results indicate the correctness of the bus interconnection mode of the corresponding subsystems.

In one possible implementation manner, before the step of closing the verification IP in the system, which is independent of the connection component included in the macro file, the method further includes: importing information of all the hosts and all the slaves included in the system into a global database; the closing of the verification IP in the system, which is independent of the connection component included in the macro file, includes: and calling a plurality of method objects in the global database, and closing the verification IP irrelevant to the connection components included in the macro file in the system.

In one possible implementation manner, the switch state of the verification IP is preset to be an on state, the calling the plurality of method objects in the global database, and closing the verification IP irrelevant to the connection component included in the macro file in the system includes: invoking a first method object according to a first name which is irrelevant to a connection component included in the macro file and provided with a regular matching identifier, and setting the switch states of all verification IPs associated with the first name to be closed; invoking a second method object, and updating the switch state of the verification IP associated with the first name in the global database; invoking a third method object, traversing and inquiring the switch states of all the verification IPs in the global database according to the verification IP names, and establishing the verification IP with the switch states set as the on state; the first name comprises at least one of a name of the subsystem, a name of the host, a name of the slave, a bus protocol type supported by the host and a bus protocol type supported by the slave.

In one possible implementation manner, the switch state of the verification IP is preset to be an on state, the calling the plurality of method objects in the global database, and closing the verification IP irrelevant to the connection component included in the macro file in the system includes: invoking a first method object according to a second name which is irrelevant to a connection component included in the macro file and does not have a regular matching identification, and setting the switch states of all verification IPs associated with the second name to be closed; invoking a third method object, traversing and inquiring the switch states of all the verification IPs in the global database according to the verification IP names, and establishing the verification IP with the switch states set as the on state; the second name comprises at least one of the name of the host and the name of the slave.

In one possible implementation, the information of all the hosts and all the slaves includes the bus protocol type supported by the host, the bus protocol type supported by the slave, the bit width, the burst type, the switch state of the authentication IP of the host, and the switch state of the authentication IP of the slave.

In one possible implementation, the connection component of the authentication IP associated with the subsystem includes: a connection component associated with each host included in the subsystem and a bus protocol type supported by the host; and a connection component associated with each slave accessible to a master included in the subsystem and a bus protocol type supported by the slave.

In one possible implementation, the bus protocol types include an advanced extensible interface AXI type, an advanced peripheral bus APB type, an advanced high-performance bus AHB type.

According to another aspect of the present disclosure, there is provided an isolation device of a verification environment for isolating the verification environment, the verification environment being an environment for verifying correctness of a bus interconnection manner of a system, the system including X subsystems, X being an integer greater than 1, each subsystem including at least one master and/or at least one slave, each master/slave corresponding to one verification IP, the device comprising: a definition module, configured to separately construct, for each subsystem, a macro file corresponding to the subsystem, where the macro file includes a connection component of an authentication IP associated with the subsystem and does not include a connection component of an authentication IP not associated with the subsystem; the closing module is used for closing the verification IP which is irrelevant to the connection assembly included in the macro file in the system; the adding module is used for adding macro files corresponding to Y subsystems in the simulation command, wherein Y is more than 1 and less than or equal to X, and Y is an integer; and executing macro files corresponding to the Y subsystems in parallel when executing the simulation command to obtain Y execution results respectively corresponding to the Y subsystems, wherein the execution results indicate the correctness of the bus interconnection mode of the corresponding subsystems.

In one possible implementation, the apparatus further includes: the importing module is used for importing information of all the hosts and all the slaves included in the system into a global database; the closing module is specifically configured to: and calling a plurality of method objects in the global database, and closing the verification IP irrelevant to the connection components included in the macro file in the system.

According to another aspect of the present disclosure, there is provided an electronic device including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing the instructions stored by the memory.

According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement the above-described method.

According to another aspect of the present disclosure, there is provided a computer program product comprising a computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above method.

According to the isolation method of the verification environment, when a system comprises X subsystems (X is an integer greater than 1) and each subsystem comprises at least one host computer and/or at least one slave computer, a macro file corresponding to each subsystem is respectively built for each subsystem, so that the macro file comprises a connection component of a verification IP (Internet protocol) associated with the subsystem and does not comprise a connection component of the verification IP not associated with the subsystem, and simulation isolation is realized; the data isolation is realized by closing the verification IP irrelevant to the connection assembly included in the macro file in the system; and adding macro files corresponding to Y subsystems in the simulation command (Y is more than 1 and less than or equal to X, and Y is an integer), so that when the simulation command is executed, the macro files corresponding to the Y subsystems are executed in parallel to obtain Y execution results respectively corresponding to the Y subsystems, and the execution results indicate the correctness of the bus interconnection mode of the corresponding subsystems. According to the isolation method of the verification environments, the subsystems are used as granularity, verification environments of Y subsystems are isolated respectively through simulation isolation and data isolation, verification of a plurality of subsystem bus interconnection can be independently conducted in parallel, influences among different subsystems are shielded, labor cost is saved, and verification efficiency is improved.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a verification environment set in the prior art when performing system bus interconnection verification.

Fig. 2 illustrates an exemplary application scenario of an isolation method of a verification environment according to an embodiment of the present disclosure.

Fig. 3 illustrates an exemplary application scenario of an isolation method of a verification environment according to an embodiment of the present disclosure.

Fig. 4 illustrates an exemplary structure of a global database according to an embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of a flow of an isolation method of a verification environment according to an embodiment of the disclosure.

FIG. 6 illustrates an example of the effects of embodiments of the present disclosure employing emulation isolation and data isolation.

FIG. 7 illustrates an example of the effects of embodiments of the present disclosure employing emulation isolation and data isolation.

Fig. 8 shows a schematic diagram of a flow of an isolation method of a verification environment according to an embodiment of the disclosure.

Fig. 9 shows a schematic diagram of a connection assembly according to an embodiment of the present disclosure.

Fig. 10 shows a schematic diagram of the structure of an isolation device of a verification environment according to an embodiment of the present disclosure.

Fig. 11 shows a block diagram of an apparatus 1900 according to an embodiment of the disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

This prior art sets up authentication IP (Verification Intellectual Property, VIP) on the host and slave upstream and downstream of the bus, through which random incentives of various combinations within the standard protocol are issued. What is needed to be authenticated at this time may be a data path (connection component) between the authentication IP of the master and the authentication IP of the slave.

As shown in fig. 1, the system includes subsystems ss_noc_1, ss_noc_2, ss_noc_n, ss_noc_m, the authentication environment including authentication IP mst_1 of host 1 and authentication IP slv_1 of slave 1 belonging to subsystem ss_noc_1, authentication IP mst_2 of host 2 and authentication IP slv_2 of slave 2 belonging to subsystem ss_noc_2, authentication IP mst_n of host n and authentication IP slv_n of slave n belonging to subsystem ss_noc_n, authentication IP mst_m of host m and authentication IP slv_m of slave m belonging to subsystem ss_noc_m. A data path exists between the authentication IP of each host and the authentication IP of the slave in the subsystem where the host resides, and a data path also exists between the authentication IP of each host and the authentication IP of the slave in the other subsystem (via the master bus main_noc), thus forming an authentication environment of a fully interconnected mesh structure as shown in fig. 1.

This verification environment has the following drawbacks:

(1) During verification, the verification IP of all hosts and the verification IP of all slaves need to be compiled, so that the verification speed is low;

(2) Bus interconnect verification of a single subsystem may be affected by verification IP in other subsystems. For example, in fig. 1, for the authentication IP mst_1 of the host, it is not related to the authentication IP mst_2/mst_m/mst_n of other hosts, but if the authentication IP mst_2/mst_m/mst_n of other hosts is wrong, the authentication environment reports the error, so that the authentication IP mst_1 itself cannot continue.

(2) When multiple users verify based on one verification environment at the same time, the same environment component is inevitably modified, and the correct setting is possible for a certain user, and the correct setting is possible for other users, so that the situation of (2) occurs.

Fig. 2 and 3 illustrate exemplary application scenarios of the isolation method of the verification environment according to the embodiments of the present disclosure.

As shown in fig. 2, in this application scenario, the system includes a bus, and a plurality of masters (masters) and a plurality of slaves (slave) connected to the bus.

The buses may include a main bus and a sub-bus. The system may include a plurality of subsystems connected to the main bus by a sub-bus. A number of masters and/or a number of slaves may be included in each subsystem. The host may be a hardware device or a software module, such as a central processing unit (central processing unit, CPU), a module using a peripheral component interconnect express (peripheral component interconnect express, PCIE) protocol, a module using a universal serial bus (universal serial bus, USB) protocol, and the like. The slave may be a hardware device or a software module, such as a Double Data Rate (DDR) synchronous dynamic random access memory (SRAM), a static random-access memory (SRAM), and the like.

Each master has access to at least one slave. Each slave can access at least one address space of the system.

Referring to fig. 2, the system may include a host 1, a host 2, a host n, a host m, a slave 1, a slave 2, a slave n, a slave m. The master 1 and the slave 1 belong to the subsystem ss_noc_1, the master 2 and the slave 2 belong to the subsystem ss_noc_2, the master n and the slave n belong to the subsystem ss_noc_n, and the master m and the slave m belong to the subsystem ss_noc_m. Wherein each master has access to slave 1, slave 2, slave n, slave m, respectively. For this subsystem, as the verification environment is generated in a prior art manner, an example of the generated verification environment may be seen in fig. 1.

As shown in fig. 3, the user's requirement may be to verify that the bus interconnect is configured in a manner that allows a host to successfully access an address space, and store a completed file (not shown) associated with system bus interconnect verification in memory.

The processor may retrieve the user filled file from memory. The user may fill in a plurality of files, and the formats of the different files may not be uniform or recognized by the verification environment. In this regard, the processor may convert the retrieved file into a predefined data format such that the format of the format-converted file is uniform and recognizable by the verification environment.

The processor may then generate a connection component to verify the IP and a global database based on the format converted file. The connection component of the verification IP of the host computer comprises an interface for connecting the host computer with a bus, and the connection component of the verification IP of the slave computer comprises an interface for connecting the slave computer with the bus. The connection component may connect the master/slave authentication IP to the bus such that the master and slave authentication IPs are communicable through the connection component and the bus. The global database comprises a plurality of resource pools and at least one method object, and different resource pools are isolated from each other. Fig. 4 illustrates an exemplary structure of a global database according to an embodiment of the present disclosure. Referring to fig. 4, the resource pool is used to store data related to system bus interconnection verification based on file parsing after format conversion. The method object defines a method of querying a resource pool.

The processor may generate test cases and verification environments from the connection components and the global database. The isolation method of the verification environment of the embodiment of the disclosure is used when generating the test case and the verification environment. By executing the isolation method of the verification environment in the embodiment of the disclosure, the verification environment can be isolated by taking the subsystem as granularity, and the closing step of verification IP irrelevant to the subsystem is added in the test case, and when the test case is executed, an excitation signal is input into the verification environment of the corresponding subsystem, so that bus interconnection verification aiming at each subsystem can be performed in parallel, and according to the comparison result of the execution result output by the verification environment, the data path under the system bus interconnection of the subsystem can be determined for verification, and the correctness of the subsystem bus setting mode is further determined. The correctness of the overall bus setting mode of the system can be further determined through the comparison result of the execution results output by the verification environments corresponding to all the subsystems.

As shown in fig. 5, the method is used for isolating a verification environment, wherein the verification environment is used for verifying correctness of a bus interconnection mode of a system, the system comprises X subsystems, X is an integer greater than 1, each subsystem comprises at least one host and/or at least one slave, and each host/slave corresponds to one verification IP, and the method comprises:

Step S51, respectively constructing macro files corresponding to the subsystems aiming at each subsystem, wherein the macro files comprise connection components of verification IP (Internet protocol) associated with the subsystems and do not comprise connection components of verification IP not associated with the subsystems;

step S52, closing the verification IP irrelevant to the connection components included in the macro file in the system;

step S53, adding macro files corresponding to Y subsystems in the simulation command, wherein Y is more than 1 and less than or equal to X, and Y is an integer;

and executing macro files corresponding to the Y subsystems in parallel when executing the simulation command to obtain Y execution results respectively corresponding to the Y subsystems, wherein the execution results indicate the correctness of the bus interconnection mode of the corresponding subsystems.

For example, an exemplary structure of the system may be seen in fig. 2 and related description. The verification environment is isolated, and can comprise two parts, namely simulation isolation and data isolation.

Wherein, the simulation isolation can be realized through step S51. For each subsystem, a macro file corresponding to the subsystem is respectively constructed, and the macro file only comprises connection components of the verification IP associated with the subsystem and does not comprise connection components of the verification IP not associated with the subsystem. In this case, the macro file, when executed, will only invoke the connection components of the authentication IP associated with the subsystem, shielding the connection components of other unrelated authentication IPs.

For example, for a peripheral component interconnect express (Peripheral Component Interconnect Express, PCIE) subsystem, where the host A1 includes a slave A2 and accesses a slave B2 of a graphics processor (Graphics Processing Unit, GPU) subsystem, when a macro file corresponding to the subsystem is constructed, the macro file corresponding to the PCIE subsystem may include a connection component of an authentication IP of the host A1, a connection component of an authentication IP of the slave A2, and a connection component of an authentication IP of the slave B2 associated with the PCIE subsystem, and the host B1 of the GPU subsystem may be a host not associated with the PCIE subsystem, so that the macro file corresponding to the PCIE subsystem may not include a connection component of an authentication IP of the host B1.

Data isolation may be achieved by step S52, the purpose of which is to shut down the authentication IP in the system independent of the connection components comprised by the macro file. Fig. 6 and 7 illustrate examples of effects after embodiments of the present disclosure employ emulation and data isolation.

When the configuration and access relationship of the subsystems are as shown in fig. 2, in the example of fig. 6, the subsystem ss_noc_1 is authenticated, and the authentication IP mst_1 of the host 1 and the authentication IPs (slv_1, slv_2, slv_n, slv_m) of the slaves accessible to the host 1 are related to the macro file corresponding to the subsystem ss_noc_1, and the authentication IP mst_2 of the host 2, the authentication IP mst_n of the host n, and the authentication IP mst_m of the host m are not related to the macro file corresponding to the subsystem ss_noc_1.

After isolating the authentication environment, only the data paths (connection components) between the authentication IP mst_1 of the host 1 and the authentication IPs (slv_1, slv_2, slv_n, slv_m) of the slaves accessible to the host 1 are valid, and the other data paths (connection components) are invalid; only the authentication IP mst_1 of the host 1 and the authentication IP (slv_1, slv_2, slv_n, slv_m) of the slave accessible to the host 1 are established, and the authentication IP mst_2 of the other host 2, the authentication IP mst_n of the host n, and the authentication IP mst_m of the host m are all closed.

When the configuration and access relationship of the subsystems are as shown in fig. 2, in the example of fig. 7, the subsystem ss_noc_2 is authenticated, and the authentication IP mst_2 of the host 2 and the authentication IPs (slv_1, slv_2, slv_n, slv_m) of the slaves accessible to the host 2 are related to the macro file corresponding to the subsystem ss_noc_2, and the authentication IP mst_2 of the host 1, the authentication IP mst_n of the host n, and the authentication IP mst_m of the host m are not related to the macro file corresponding to the subsystem ss_noc_2.

After isolating the authentication environment, only the data paths (connection components) between the authentication IP mst_2 of the host 2 and the authentication IPs (slv_1, slv_2, slv_n, slv_m) of the slaves accessible to the host 2 are valid, and the other data paths (connection components) are not valid; only the authentication IP mst_2 of the host 2 and the authentication IP (slv_1, slv_2, slv_n, slv_m) of the slave accessible to the host 2 are established, and the authentication IP mst_1 of the other host 1, the authentication IP mst_n of the host n, and the authentication IP mst_m of the host m are all closed.

After the simulation and data isolation are completed, step S53 may be performed, where macro files corresponding to Y subsystems are added in the simulation command, where 1 < y+.x, Y is an integer, that is, macro files corresponding to some or all of the subsystems are added. The Y subsystems may be selected from the X subsystems according to a user instruction. And then, when the simulation command is executed, macro files corresponding to the Y subsystems can be executed in parallel, and Y execution results respectively corresponding to the Y subsystems are finally obtained, wherein each execution result can indicate the correctness of the bus interconnection mode of the corresponding subsystem. For example, the execution result may include an execution result of the master side and an execution result of the slave side, and the comparison result may be obtained by comparing the execution result of the master side and the execution result of the slave side, where the comparison result may indicate the correctness of the bus interconnection manner of the subsystem.

After the correctness of the bus interconnection mode of all the subsystems passes the verification, the switch state of all the verification IPs can be set to be in an on state, and the macro file corresponding to the system is executed, so that the macro file comprises the connection components with all the verification IPs, and the verification of all the hosts and the slaves included in the whole system is realized.

As shown in fig. 8, in a possible implementation manner, before step S52, the method further includes:

step S54, importing information of all the hosts and all the slaves included in the system into a global database;

step S52 includes:

invoking a plurality of method objects in the global database, and closing the verification IP irrelevant to the connection components included in the macro file in the system.

For example, before step S52, step S54 may be performed to first import information of all the masters and all the slaves involved in the verification into the resource pool of the global database. The global database may be a preset database with a custom data format, the data format of which can be seen in fig. 4, and the manner of importing information into the global database can be seen in fig. 3 and related descriptions. Referring to fig. 4, the global database may further include preset method objects, and when step S52 is performed, a plurality of method objects in the global database may be called, and the verification IP in the system, which is independent of the connection component included in the macro file, is closed. Exemplary closing means may be found in the further description below.

And storing information of all the hosts and the slaves through a global database, and closing the verification IP through a method object, so that verification can be automatically completed. Those skilled in the art will appreciate that verification of the system bus interconnect may be accomplished even without the global database being set, and that embodiments of the present disclosure are not limited as to whether a global database is set.

In one possible implementation, the information of all the hosts and all the slaves includes the bus protocol type supported by the host, the bus protocol type supported by the slave, the bandwidth, the burst type, the switch state of the authentication IP of the host, and the switch state of the authentication IP of the slave.

For example, each master/slave may support one bus protocol type, and different hosts, different slaves may support different bus protocol types. In one possible implementation, the bus protocol types include advanced extensible interface (advanced extensible interface, AXI) type, advanced peripheral bus (advanced peripheral bus, APB) type, advanced high-performance bus (AHB) type. The AXI types may further include a plurality of types of ace_lite, AXI4, AXI3, and the like. The AHB types may further include a plurality of types of AHB5, ahb5_lite, and the like. The APB type may further include various types of APB2, APB3, APB4, etc.

Each host/slave includes a variety of bit widths including an interface address bit width, an interface data bit width, an interface read/write signal bit width, and the like. Each master/slave may support at least one burst type, such as narrowband bursts, loopback bursts, etc. The master/slave authentication IP has a switch state in which it is allowed to be authenticated when in an on state and is not allowed to be authenticated when in an off state. The information of all the hosts and all the slaves entered into the global database may include the bus protocol type supported by the host, the bus protocol type supported by the slave, the bandwidth, the burst type, the on-off state of the authentication IP of the host, and the on-off state of the authentication IP of the slave, which are described above.

It will be appreciated that the information of all the hosts and all the slaves may also include more information, such as the interface activation status of the host/slave, the interface maximum burst length, etc. may also be entered into the global database, as long as the information about the hosts and the slaves is concerned, and the embodiments of the present disclosure are not limited with respect to the specific type of information that may be entered into the global data.

It will be appreciated by those skilled in the art that the above-described bus protocol types are merely examples, and that in practical applications the bus protocol types may include more types, as long as the bus can support a protocol type, which is not limited by the present disclosure.

In one possible implementation, a connection component of an authentication IP associated with a subsystem, comprises:

a connection component associated with each host and bus protocol type supported by the host included in the subsystem;

and a connection component associated with each slave and the bus protocol types supported by the slave that are accessible to the master included in the subsystem.

For example, each master/slave may support one of the above-mentioned possible bus protocol types, and the connection component makes the authentication IP of the master/slave connectable to the bus, and performs route conversion through the bus, so that a data path can be established between the master and the slave of different bus protocol types. Therefore, when a connection component of the authentication IP (hereinafter referred to as connection component) is set, a connection component associated with each of the host and the bus protocol type supported by the host may be set for each of the slaves, and a connection component associated with each of the slaves and the bus protocol type supported by the slaves may be set for each of the slaves.

As shown in fig. 9, assuming that for the subsystem ss_noc_1, the bus protocol type supported by the host 1 included therein is an AHB type, and the bus protocol type supported by the slave 1 included therein is an APB type, the connection component associated with both the bus protocol types supported by the host 1 and the host 1 may be the connection component ss1_mst1_ahb. The connection component associated with both the slave 1 and the bus protocol types supported by the slave 1 may be a connection component ss1_slv1_apb.

Similarly, assuming that for subsystem ss_noc_2, the bus protocol type supported by host 2 included therein is AXI type and the bus protocol type supported by slave 2 included therein is APB type, the connection component associated with both the bus protocol types supported by host 2 and host 2 may be connection component ss2_mst2_axi. The connection component associated with both the slave 2 and the bus protocol types supported by the slave 2 may be connection component ss2_slv2_apb.

The connection elements associated with other subsystems are arranged in the same manner as the connection elements associated with the subsystems ss_noc_1/ss_noc_2, and are not illustrated herein.

For ease of management, the connection components may be stored in classes according to the subsystem to which their associated master/slave belongs and the associated bus protocol type. For example, if a subsystem includes multiple hosts supporting the same bus protocol type, the connection components associated with that portion of the hosts may be stored as a class, an identification may be set for the class to indicate the name of the subsystem, a connection component indicating that the class includes a connection component that is an authentication IP of the host, a bus protocol type associated with the class. Similarly, if a subsystem includes a plurality of slaves supporting the same bus protocol type, the connection components associated with the slaves may be stored as a class, and an identifier may be set for the class to indicate the name of the subsystem, indicate that the connection components included in the class are connection components of the slave that verify IP, and indicate the bus protocol type associated with the class, so as to facilitate searching according to the identifier when constructing a macro file.

Those skilled in the art will appreciate that the storage of the connection components should not be limited to the above examples, as long as the required connection components can be found accurately.

When executing step S51, the corresponding connection component classification is found according to the name of the subsystem, the names of the host and the slave associated with the subsystem, and the bus protocol types supported by the host and the slave associated with the subsystem, and the required connection component is obtained therefrom. For example, when the macro file corresponding to the subsystem ss_noc_1 is constructed, each of the connection components (including the connection component of the authentication IP of the host 1 and the connection component of the authentication IP of the slave 1) associated with each of the hosts and each of the slaves of the subsystem ss_noc_1 may be found first and added to the macro file corresponding to the subsystem ss_noc_1. And then finding out the connection component of the verification IP of the slave machine 2 from the connection components associated with the subsystem SS_NOC_2, finding out the connection component of the verification IP of the slave machine n from the connection components associated with the subsystem SS_NOC_n, finding out the connection component of the verification IP of the slave machine m from the connection components associated with the subsystem SS_NOC_m, and adding the connection components to macro files corresponding to the subsystem SS_NOC_1 respectively. The authentication environment at this time may be as shown in fig. 6, such that the authentication environment supports a comprehensive authentication of the data path associated with the host 1.

There are many method objects preset in the global database. In performing step S52, there may be various combinations of the plurality of method objects invoked. Two possible combinations of the plurality of method objects invoked are presented below.

In one possible implementation, the switch state of the authentication IP is preset to an on state,

invoking a plurality of method objects in a global database, closing a verification IP irrelevant to a connection component included in a macro file in a system, including:

invoking a first method object according to a first name which is irrelevant to a connection component included in the macro file and provided with a regular matching identifier, and setting the switch states of all verification IPs associated with the first name to be closed;

invoking a second method object, and updating the switch state of the verification IP associated with the first name in the global database;

invoking a third method object, traversing and inquiring the switch states of all the verification IPs in the global database according to the verification IP names, and establishing the verification IP with the switch states set as the on state;

the first name comprises at least one of a name of a subsystem, a name of a host, a name of a slave, a bus protocol type supported by the host and a bus protocol type supported by the slave.

For example, the switch state of the authentication IP of all the masters and all the slaves may be preset as the on state. If the correctness of the bus interconnection mode of a certain subsystem needs to be verified, in order to avoid the influence of other irrelevant hosts/slaves, the switch state of the verification IP irrelevant to the connection component included in the macro file corresponding to the subsystem can be set to be in a closed state.

For example, a first name with a regularly matched identification that is independent of the connection components included in the macro file may be predetermined. The first name may be at least one of a name of the subsystem, a name of the host, a name of the slave, a bus protocol type supported by the host, a bus protocol type supported by the slave, and the identification of the canonical match may be, for example, ". The first method object is then invoked during the set-up phase of the test case, and may include a method object set_master_power_st for setting the on-off state of the authentication IP of the master, and a method object set_slave_power_st for setting the on-off state of the authentication IP of the slave, setting the on-off states of all authentication IPs associated with the first name to the off state. For example, for subsystem ss_noc_1, when the first name is ss_noc_1, all authentication IPs associated with the first name may include authentication IP mst_1 of master 1, authentication IP slv_1 of slave 1. The first method object is invoked to set the switch states of all authentication IPs associated with the first name to the off state.

Because the first name with the regular matching identification cannot be matched with the information of the host/slave in the global database, the second method object can be called in the establishment stage of the environment, the name of the host and/or the slave associated with the first name is acquired, and the on-off state of the verification IP of the host and/or the slave associated with the first name in the global database is updated. The second method object may include a method object update_master_power_st for acquiring a name of the first name-associated host, updating a switching state of the authentication IP of the first name-associated host in the global database, and a method object update_slave_power_st for acquiring a name of the first name-associated slave, updating a switching state of the authentication IP of the first name-associated slave in the global database. Taking ss_noc_1 as an example, the second method object is called, and the name MST1 of the host 1 and the name SLV1 of the slave 1 associated with the first name can be obtained. Based on the acquired name MST1 of the master 1 and the acquired name SLV1 of the slave 1, the authentication IP mst_1 of the master 1 and the authentication IP slv_1 of the slave 1 may be updated to the off state.

Finally, a third method object can be called in the establishment stage of the environment, and the on-off states of all verification IPs in the global database can be traversed and queried according to the verification IP names, wherein the third method object can comprise a method object get_all_work_master_name of the verification IPs of the hosts in all on-states in the global database and a method object get_all_work_slave_name of the verification IPs of the slaves in all on-states in the global database. And then establishes a verification IP with the switch state set to the on state. The verification IP irrelevant to the connection components included in the macro file in the system is updated to be in a closed state, and the third method object is not established when the third method object is called, so that the closing of the verification IP irrelevant to the connection components included in the macro file in the system is realized.

It should be understood by those skilled in the art that the first method object, the second method object, and the third method object may be set in other forms, so long as the first method object, the second method object, and the third method object are called to implement the above functions, and the specific setting manner of the first method object, the second method object, and the third method object is not limited in the embodiments of the present disclosure.

In this way, the authentication IP that is not related to the bus interconnect authentication process of a particular subsystem can be turned off in the isolated authentication environment, and the labor cost required for the isolation process is low.

invoking the first method object according to a second name which is irrelevant to a connection component included in the macro file and does not have a regular matching identification, and setting the switch states of all verification IPs associated with the second name to be closed;

invoking a third method object, traversing and inquiring the switch states of all verification IPs in the global database according to the verification IP names, and establishing the verification IP with the switch states set as the on state;

The second name comprises at least one of the name of the host and the name of the slave.

For example, a second name may also be predetermined that is independent of the connection components included in the macro file and does not have an identification of a regular match. The second name may include at least one of a name of the master and a name of the slave. The first method object is then invoked during the build phase of the test case, setting the switch states of all validation IPs associated with the second name to an off state. For example, if the name of host 1 is MST1, when the second name is MST1, all authentication IPs associated with the second name may include authentication IP MST_2 of host 2. Invoking the first method object to set the switch states of all authentication IPs associated with the second name to the off state.

Because the second name can be accurately matched with the information of the master machine/slave machine in the global database, the information of the master machine/slave machine matched with the second name in the global database can be directly updated without calling the second method object to further develop the second name. And then, the third method object can be directly called in the establishment stage of the environment, the switch states of all the verification IPs in the global database are traversed and inquired according to the verification IP names, and the verification IPs with the switch states set as the on states are established. The verification IP irrelevant to the connection components included in the macro file in the system is updated to be in a closed state, and the third method object is not established when the third method object is called, so that the closing of the verification IP irrelevant to the connection components included in the macro file in the system is realized.

Examples of the first method object, the second method object, and the third method object are described above and are not described here.

In this way, the authentication IP that is independent of the bus interconnect authentication process for a particular subsystem can be turned off in the isolated authentication environment, and the data processing costs required for the isolation process are low.

Those skilled in the art will appreciate that there may be many more options for the regular matching identifier, and the embodiments of the present disclosure are not limited to the specific arrangement of the regular matching identifier.

It will be appreciated by those skilled in the art that there are more types of method objects preset in the global database, such as a method object get_ uvc _info_by_name, for obtaining all general authentication information of a master or a slave according to the name of the master or the slave; and a method object get_region_by_name for obtaining all address block information accessible to the host or the slave according to the name of the host or the slave, and so on. More combinations of the method objects may be possible, as long as the method object can close the verification IP in the system, which is irrelevant to the connection component included in the macro file, and the embodiment of the disclosure does not limit what method object is specifically called.

The present disclosure also provides an isolation device of a verification environment, and fig. 10 is a schematic diagram showing a structure of the isolation device of the verification environment according to an embodiment of the present disclosure.

As shown in fig. 10, in one possible implementation, the apparatus is configured to isolate a verification environment, where the verification environment is an environment for verifying correctness of a bus interconnection manner of a system, where the system includes X subsystems, where X is an integer greater than 1, and each subsystem includes at least one master and/or at least one slave, and each master/slave corresponds to a verification IP, and the apparatus includes:

a definition module 101, configured to separately construct, for each subsystem, a macro file corresponding to the subsystem, where the macro file includes a connection component of an authentication IP associated with the subsystem and does not include a connection component of an authentication IP not associated with the subsystem;

a closing module 102, configured to close an authentication IP in the system, where the authentication IP is unrelated to a connection component included in the macro file;

the adding module 103 is used for adding macro files corresponding to Y subsystems in the simulation command, wherein Y is more than 1 and less than or equal to X, and Y is an integer;

In one possible implementation, the apparatus further includes:

the importing module is used for importing information of all the hosts and all the slaves included in the system into a global database;

the closing module is specifically configured to: and calling a plurality of method objects in the global database, and closing the verification IP irrelevant to the connection components included in the macro file in the system.

the method for calling the plurality of method objects in the global database, closing the verification IP irrelevant to the connection components included in the macro file in the system, comprises the following steps:

The first name comprises at least one of a name of the subsystem, a name of the host, a name of the slave, a bus protocol type supported by the host and a bus protocol type supported by the slave.

invoking a first method object according to a second name which is irrelevant to a connection component included in the macro file and does not have a regular matching identification, and setting the switch states of all verification IPs associated with the second name to be closed;

In one possible implementation, the connection component of the authentication IP associated with the subsystem includes:

In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.

The disclosed embodiments also provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method. The computer readable storage medium may be a volatile or nonvolatile computer readable storage medium.

The embodiment of the disclosure also provides an electronic device, which comprises: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing the instructions stored by the memory.

Embodiments of the present disclosure also provide a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above method.

Fig. 11 shows a block diagram of an apparatus 1900 according to an embodiment of the disclosure. For example, the apparatus 1900 may be provided as an electronic device. Referring to FIG. 11, the apparatus 1900 includes a processing component 1922 that further includes one or more processors and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions. Further, processing component 1922 is configured to execute instructions to perform the methods described above.

The apparatus 1900 may further comprise a power component 1926 configured to perform power management of the apparatus 1900, a wired or wireless network interface 1950 configured to connect the apparatus 1900 to a network, and an input/output interface 1958 (I/O interface). The apparatus 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server ^TM ，Mac OS X ^TM ，Unix ^TM , Linux ^TM ，FreeBSD ^TM Or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 1932, including computer program instructions executable by processing component 1922 of apparatus 1900 to perform the above-described methods.

The present disclosure may be a system, method, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for causing a processor to implement aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.

Computer program instructions for performing the operations of the present disclosure can be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, c++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information of computer readable program instructions, which can execute the computer readable program instructions.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for isolating a verification environment, the method being used for isolating the verification environment, the verification environment being used for verifying the correctness of a bus interconnection mode of a system, the system comprising X subsystems, X being an integer greater than 1, each subsystem comprising at least one host and/or at least one slave, each host/slave corresponding to a verification IP, the method comprising:

respectively constructing a macro file corresponding to each subsystem, wherein the macro file comprises a connection component of the verification IP associated with the subsystem and does not comprise a connection component of the verification IP not associated with the subsystem;

Closing a verification IP irrelevant to a connection component included in the macro file in the system;

adding macro files corresponding to Y subsystems in a simulation command, wherein Y is more than 1 and less than or equal to X, and Y is an integer;

2. The method of claim 1, wherein prior to said shutting down an authentication IP in the system that is independent of a connection component included in the macro file, the method further comprises:

importing information of all the hosts and all the slaves included in the system into a global database;

the closing of the verification IP in the system, which is independent of the connection component included in the macro file, includes:

and calling a plurality of method objects in the global database, and closing the verification IP irrelevant to the connection components included in the macro file in the system.

3. The method of claim 2, wherein the switch state of the authentication IP is preset to an on state,

4. The method of claim 2, wherein the switch state of the authentication IP is preset to an on state,

5. The method of claim 2, wherein the information of all hosts and all slaves includes a bus protocol type supported by the host, a bus protocol type supported by the slave, a bit width, a burst type, a switching state of a validation IP of the host, a switching state of a validation IP of the slave.

6. The method of claim 5, wherein the connection component of the authentication IP associated with the subsystem comprises:

a connection component associated with each host included in the subsystem and a bus protocol type supported by the host;

and a connection component associated with each slave accessible to a master included in the subsystem and a bus protocol type supported by the slave.

7. The method of claim 5, wherein the bus protocol type comprises an advanced extensible interface AXI type, an advanced peripheral bus APB type, an advanced high-performance bus AHB type.

8. An isolation device for a verification environment, wherein the device is configured to isolate the verification environment, the verification environment is configured to verify correctness of a bus interconnection manner of a system, the system includes X subsystems, X is an integer greater than 1, each subsystem includes at least one host and/or at least one slave, and each host/slave corresponds to a verification IP, the device includes:

a definition module, configured to separately construct, for each subsystem, a macro file corresponding to the subsystem, where the macro file includes a connection component of an authentication IP associated with the subsystem and does not include a connection component of an authentication IP not associated with the subsystem;

the closing module is used for closing the verification IP which is irrelevant to the connection assembly included in the macro file in the system;

the adding module is used for adding macro files corresponding to Y subsystems in the simulation command, wherein Y is more than 1 and less than or equal to X, and Y is an integer;

9. An electronic device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to implement the method of any one of claims 1 to 7 when executing the instructions stored by the memory.

10. A non-transitory computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the method of any of claims 1 to 7.