CN117156863A - Ferroelectric memory structure, method of manufacturing the same, ferroelectric memory device, and method of controlling the same - Google Patents

Ferroelectric memory structure, method of manufacturing the same, ferroelectric memory device, and method of controlling the same Download PDF

Info

Publication number
CN117156863A
CN117156863A CN202311431186.1A CN202311431186A CN117156863A CN 117156863 A CN117156863 A CN 117156863A CN 202311431186 A CN202311431186 A CN 202311431186A CN 117156863 A CN117156863 A CN 117156863A
Authority
CN
China
Prior art keywords
electrode
ferroelectric
channel layer
ferroelectric memory
modulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202311431186.1A
Other languages
Chinese (zh)
Other versions
CN117156863B (en
Inventor
薛飞
王丁
王宝玉
杨伟伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZJU Hangzhou Global Scientific and Technological Innovation Center
Original Assignee
ZJU Hangzhou Global Scientific and Technological Innovation Center
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ZJU Hangzhou Global Scientific and Technological Innovation Center filed Critical ZJU Hangzhou Global Scientific and Technological Innovation Center
Priority to CN202311431186.1A priority Critical patent/CN117156863B/en
Publication of CN117156863A publication Critical patent/CN117156863A/en
Application granted granted Critical
Publication of CN117156863B publication Critical patent/CN117156863B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present disclosure relates to ferroelectric memory structures, methods of fabricating ferroelectric memory structures, ferroelectric memory devices, and methods of tuning. Embodiments of the present disclosure provide a method for fabricating a ferroelectric memory structure, the method comprising: forming a ferroelectric channel layer laminated on a substrate; forming a first electrode and a second electrode which are arranged at intervals along the extending direction of the ferroelectric channel layer and are respectively connected with the ferroelectric channel layer; and forming a modulating electrode, wherein the modulating electrode is positioned between the first electrode and the second electrode, and the modulating electrode is contacted with the ferroelectric channel layer. According to the method for manufacturing the ferroelectric memory structure, the first electrode, the second electrode and the modulation electrode are formed according to the ferroelectric channel layer, the ferroelectric memory structure with adjustable channel resistance is obtained, and the influence on product stability caused by factors such as quality defects of materials, uneven material thickness, micro-nano processing technology and the like is reduced.

Description

Ferroelectric memory structure, method of manufacturing the same, ferroelectric memory device, and method of controlling the same
Technical Field
The present disclosure relates to the field of semiconductor technology, and in particular, to a ferroelectric memory structure and a method of manufacturing the same, a ferroelectric memory device, and a method of controlling the same.
Background
With the advent of artificial intelligence, the internet of things and the large data age, massive data needs to be processed and stored in a very short time. In a conventional von neumann architecture computer, these data are constantly shuttled to the compute and memory units, thus posing significant speed and energy challenges. To break through the bottlenecks and constraints of von neumann structures in terms of speed delay and energy consumption, new calculation paradigms have been created. For example, a novel artificial neural network chip based on a memristor can simulate the working mode of human brain, and perfect fusion of calculation and storage is realized in the same device, so that the operation power consumption is expected to be reduced, the calculation speed is expected to be improved, and the novel artificial neural network chip based on the memristor has important theoretical and practical significance for developing a chip technology of 'perception-storage-calculation integration'.
The emerging two-dimensional layered material has excellent semiconductor and ferroelectric properties, and can be directly used as a channel material to prepare a ferroelectric memristor, so that the functions of calculation and storage are fused.
Although a single memristor has excellent electrical properties, the performance stability of the array memristor is insufficient due to the influence of factors such as quality defects of materials, uneven thicknesses of the materials, micro-nano processing technology and the like. When a plurality of memristors are manufactured and formed, the device-to-device variability is large, and the cycle-to-cycle variability is large in implementation, so that the working performance of a 'sense-in-sense' integrated chip based on a two-dimensional ferroelectric memristor array is seriously affected.
Disclosure of Invention
Based on the above, it is necessary to provide a ferroelectric memory structure and a manufacturing method thereof, a ferroelectric memory device and a regulating method thereof, aiming at the problem of insufficient performance stability of array memristors.
Embodiments of the present disclosure provide a method for fabricating a ferroelectric memory structure, the method comprising: forming a ferroelectric channel layer laminated on a substrate; forming a first electrode and a second electrode which are arranged at intervals along the extending direction of the ferroelectric channel layer and are respectively connected with the ferroelectric channel layer; and forming a modulating electrode, wherein the modulating electrode is positioned between the first electrode and the second electrode, and the modulating electrode is contacted with the ferroelectric channel layer.
According to the method for manufacturing the ferroelectric memory structure, the first electrode, the second electrode and the modulation electrode are formed according to the ferroelectric channel layer, the ferroelectric memory structure with adjustable channel resistance is realized, the resistance change performance of the ferroelectric memory structure can be modulated and stabilized by changing the external voltage and adding the modulation voltage, and the influence of factors such as quality defects of materials, uneven thickness of the materials and micro-nano processing technology on the stability of product performance is reduced.
In some embodiments, the method for fabricating a ferroelectric memory structure further comprises: and forming a dielectric layer laminated on the substrate, wherein the ferroelectric channel layer is positioned on one side of the dielectric layer, which is opposite to the substrate.
In the method, the dielectric layer is formed to serve as an insulating protective layer, so that electric leakage of the ferroelectric channel layer is reduced, and polarization and domain structure retention of the ferroelectric channel layer are improved.
In some embodiments, the step of forming the first electrode includes: the first electrode is in Schottky contact with the ferroelectric channel layer; the step of forming the second electrode includes: the second electrode is in Schottky contact with the ferroelectric channel layer; the step of forming the modulating electrode includes: the modulating electrode is in ohmic contact or Schottky contact with the ferroelectric channel layer.
The method can influence the barrier heights of the source electrode and the drain electrode by forming a Schottky barrier, so that the forward voltage drop is lower, the reverse recovery time is extremely short, the switching is extremely rapid, and the stability of the ferroelectric storage structure is ensured.
In some embodiments, the first electrode, the second electrode, and the modulating electrode are located on the same side of the ferroelectric channel layer in the stacking direction.
The first electrode, the second electrode and the modulation electrode are positioned on the same side of the ferroelectric channel layer along the stacking direction in the method, so that the method is easy to implement. Furthermore, it is convenient to form a flat ferroelectric channel layer.
The embodiment of the disclosure provides a ferroelectric memory structure, which comprises a substrate, a ferroelectric channel layer, a first electrode, a second electrode and a modulating electrode, wherein the ferroelectric channel layer is laminated on the substrate; the first electrode is connected to the ferroelectric channel layer; the second electrode is connected with the ferroelectric channel layer, and the second electrode and the first electrode are arranged at intervals along the extending direction of the ferroelectric channel layer; the modulating electrode is positioned between the first electrode and the second electrode, and the modulating electrode is contacted with the ferroelectric channel layer.
According to the ferroelectric storage structure provided by the embodiment of the disclosure, the polarization direction of the channel ferroelectric domain can be turned to be consistent with the external electric field through the voltage applied by the first electrode and the second electrode, and the modulation voltage is applied by the modulation electrode, so that the polarization direction of the channel ferroelectric domain is subjected to local fine tuning, and the stability of the ferroelectric storage structure is improved.
In some embodiments, the ferroelectric memory structure further comprises a dielectric layer located between the substrate and the ferroelectric channel layer.
According to the ferroelectric storage structure provided by the embodiment of the disclosure, the dielectric layer can serve as an insulating protective layer, so that electric leakage of the ferroelectric channel layer is reduced, and polarization and domain structure retention of the ferroelectric channel layer are improved.
In some embodiments, the first electrode is in schottky contact with the ferroelectric channel layer and the second electrode is in schottky contact with the ferroelectric channel layer; the modulating electrode is in ohmic contact or Schottky contact with the ferroelectric channel layer.
According to the ferroelectric storage structure provided by the embodiment of the disclosure, the Schottky contact formed by the electrode and the ferroelectric channel layer can form a Schottky barrier when external voltage is applied, so that the barrier heights of the source electrode and the drain electrode are influenced, the forward voltage drop is low, the reverse recovery time is extremely short, the switching is very rapid, and the stability of the ferroelectric storage structure is ensured.
In some embodiments, the first electrode, the second electrode, and the modulating electrode are located on the same side of the ferroelectric channel layer in the stacking direction.
According to the ferroelectric memory structure provided by the embodiment of the disclosure, the first electrode, the second electrode and the modulation electrode are positioned on the same side of the ferroelectric channel layer along the stacking direction, so that the top gate structure can be protected.
A ferroelectric memory device provided in an embodiment of the present disclosure includes: a plurality of ferroelectric memory structures and circuit structures as described above arranged in an array. The circuit structure is electrically connected to the first electrode, the second electrode and the modulating electrode of each ferroelectric memory structure.
The ferroelectric memory structure and the circuit structure are arranged in the array, so that the stability and the cycle consistency of the ferroelectric memory device are improved.
The method for regulating and controlling the ferroelectric memory device provided by the embodiment of the disclosure comprises the following steps: applying a forward voltage or a reverse voltage to the first electrode and the second electrode to adjust the ferroelectric casting polarization direction of the ferroelectric channel layer; a modulating voltage is applied to the modulating electrode.
According to the method for regulating and controlling the ferroelectric memory device, the polarization direction of the channel ferroelectric domain is enabled to be turned to be consistent with the external electric field through the voltage applied by the first electrode and the second electrode, and the modulation voltage is applied through the modulation electrode, so that the polarization direction of the channel ferroelectric domain is subjected to local fine adjustment, and the working performance of the ferroelectric memory device is improved.
Drawings
FIG. 1 is a flow diagram of a method for fabricating a ferroelectric memory structure provided by embodiments of the present disclosure;
fig. 2 is a top view of a ferroelectric memory structure arranged in an array in a ferroelectric memory device provided in accordance with an embodiment of the present disclosure;
FIG. 3 is a cross-sectional view taken at A-A' of FIG. 2;
FIG. 4 is a scatter plot of a cyclic uniformity test of a ferroelectric memory device provided by an embodiment of the present disclosure;
fig. 5 is a flow chart diagram of a method of modulating a ferroelectric memory structure provided in an embodiment of the present disclosure.
Reference numerals illustrate: 100. a ferroelectric memory device; 10. a ferroelectric memory structure; 1. a substrate; 2. a dielectric layer; 3. a ferroelectric channel layer; 4. a first electrode; 5. a second electrode; 6. modulating the electrode; 20. and a circuit structure.
Detailed Description
In order to make the above objects, features and advantages of the embodiments of the present disclosure more comprehensible, a detailed description of specific embodiments of the present disclosure is provided below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. The disclosed embodiments may be embodied in many other forms other than described herein and similar modifications may be made by those skilled in the art without departing from the spirit of the disclosed embodiments, so that the disclosed embodiments are not limited to the specific examples of embodiments described below.
In the description of the embodiments of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the embodiments of the present disclosure and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the embodiments of the present disclosure.
In the presently disclosed embodiments, unless expressly stated and limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intermediary. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. For example, the first electrode may also be referred to as a second electrode, and the second electrode may also be referred to as a first electrode. In the description of the embodiments of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly specified otherwise.
In the presently disclosed embodiments, the terms "connected," "connected," and the like are to be construed broadly and, unless otherwise specifically indicated and defined, as being either fixedly connected, detachably connected, or integrally formed, for example; can be flexible connection or rigid connection along at least one direction; can be mechanically or electrically connected; either directly, indirectly, through intermediaries, or both, or in which case the intermediaries are present, or in which case the two elements are in communication or in which case they interact, unless explicitly stated otherwise. The terms "mounted," "disposed," "secured," and the like may be construed broadly as connected. The specific meaning of the above terms in the embodiments of the present disclosure may be understood by those of ordinary skill in the art according to specific circumstances.
As used herein, the terms "layer," "region" and "regions" refer to portions of material that include regions having a certain thickness. The layers can extend horizontally, vertically and/or along a tapered surface. The layer can be a region of uniform or non-uniform continuous structure, whose thickness perpendicular to the direction of extension may be no greater than the thickness of the continuous structure. The layers can include multiple layers, either stacked or discretely extending. The various regions in the figures, the shapes of the layers and their relative sizes and positional relationships are exemplary only, as may be subject to variations due to manufacturing tolerances or technical limitations, and may be adjusted to actual requirements.
The working process of the two-dimensional ferroelectric memristor is determined by three independent variables of ferroelectric polarization, schottky barrier height change and initial barrier height, and the two-dimensional ferroelectric memristor belongs to interface behaviors and has high cycle consistency. In the device manufacturing process, the initial barrier height is easily affected by the micro-nano processing technology to cause differences, thereby affecting the performance of the whole device and the consistency of the device array. Therefore, the size and the direction of the local ferroelectric domain are regulated and controlled by introducing a third terminal modulation electrode to apply voltage; the change of the local electric domain can influence the barrier heights of the source electrode and the drain electrode, so that the device performance of the memristor is further influenced, and finally the device consistency of the memristor array is regulated and controlled.
Referring to fig. 1, fig. 1 shows a flow diagram of a method for fabricating a ferroelectric memory structure in an embodiment of the present disclosure. Referring to fig. 2 and 3, a method 1000 for fabricating a ferroelectric memory structure provided by embodiments of the present disclosure may be used to fabricate a ferroelectric memory structure 10, and may also be used to fabricate a plurality of ferroelectric memory structures 10 simultaneously. The method 1000 may be used to fabricate a plurality of ferroelectric memory structures 10 of an array.
The method 1000 for fabricating a ferroelectric memory structure provided by the embodiments of the present disclosure includes the following steps S102 to S104.
In some embodiments, the method 1000 further includes step S101, forming a dielectric layer 2 laminated to the substrate 1. The dielectric layer 2 may be formed by an epitaxial growth process. The dielectric layer 2 is laminated on the substrate 1 along the Z-axis direction, which may be referred to herein as the first direction.
In step S102, the ferroelectric channel layer 3 is formed. A two-dimensional ferroelectric semiconductor material may be employed as the ferroelectric channel layer 3. The ferroelectric channel layer 3 is laminated on the substrate 1 in the Z-axis direction, and the ferroelectric channel layer 3 is illustratively located on the side of the dielectric layer 2 facing away from the substrate 1.
In step S103, the first electrode 4 and the second electrode 5 are formed. The first electrode 4 and the second electrode 5 can be formed simultaneously; the first electrode 4 and the second electrode 5 may be formed separately. The first electrode 4 and the second electrode 5 may be formed by an epitaxial growth process. The first electrode 4 and the second electrode 5 are arranged at intervals along the extension direction of the ferroelectric channel layer 3. The first electrode 4 and the second electrode 5 are connected to the ferroelectric channel layer 3, respectively.
Illustratively, the first electrode 4 and the second electrode 5 are disposed at intervals along the X-axis direction. The first electrode 4 and the second electrode 5 are both located on the side of the ferroelectric channel layer 3 facing away from the dielectric layer 2 in the stacking direction. The first electrode 4 is illustratively a source and the second electrode 5 is a drain.
In step S104, the modulating electrode 6 is formed. The modulation electrode 6 may be formed on the ferroelectric channel layer 3 in the first direction and the second direction by an epitaxial growth process. The first direction is perpendicular to the second direction. The modulating electrode 6 is located between the first electrode 4 and the second electrode 5. The modulation electrode 6 is in contact with the ferroelectric channel layer 3.
The method 1000 for manufacturing a ferroelectric memory structure according to the embodiments of the present disclosure forms the first electrode 4, the second electrode 5, and the modulation electrode 6 according to the ferroelectric channel layer 3, and can realize the ferroelectric memory structure 10 with high stability by changing the applied voltage and adding the modulation voltage.
The method 1000 has the advantages of low cost and easy implementation, and can reduce the influence of factors such as quality defects of the material, uneven thickness of the material, micro-nano processing technology and the like on the performance of the ferroelectric memory structure 10; is compatible with current semiconductor processing.
In the method 1000 for manufacturing a ferroelectric memory structure provided in the embodiment of the present disclosure, step S102 and step S103 may be performed first, and then step S104 may be performed. In other embodiments, step S102 may be performed after step S104 is performed.
In some embodiments, the step of forming the first electrode 4 comprises: forming a first electrode 4 in schottky contact with the ferroelectric channel layer 3; the step of forming the second electrode 5 includes: a second electrode 5 is formed in schottky contact with the ferroelectric channel layer 3.
The method can influence the barrier heights of the source electrode and the drain electrode by forming a Schottky barrier, so that the forward voltage drop is low, the reverse recovery time is short, and the switching is very quick, thereby helping to ensure the stability of the ferroelectric memory structure 10.
In some embodiments, the step of forming the modulating electrode 6 comprises: a modulating electrode 6 is formed in ohmic or schottky contact with the ferroelectric channel layer 3. This results in a ferroelectric memory structure 10 of simple construction and ensures a good modulation effect.
Illustratively, the step of forming the modulating electrode 6 includes: a modulating electrode 6 is formed in schottky contact with the ferroelectric channel layer 3. In other embodiments, the step of forming the modulating electrode 6 comprises: a modulating electrode 6 is formed in ohmic contact with the ferroelectric channel layer 3.
In one embodiment, ferroelectric memory structure 10 is comprised of substrate 1, dielectric layer 2, ferroelectric channel layer 3, first electrode 4, second electrode 5, and modulating electrode 6.
It is understood that the substrate 1 can be a layer, can include one or more layers therein, can have one or more layers thereon and/or thereunder. The substrate 1 and the dielectric layer 2 may be regarded as a composite layer.
Illustratively, the material of the substrate 1 may include at least one of silicon carbide, silicon germanium, III-V compounds such as gallium nitride and gallium arsenide. The material of the dielectric layer 2 is illustratively an insulating material. The material of the dielectric layer 2 may be an oxide. Optionally, the dielectric layer 2 is, for example, one of silicon dioxide, hafnium oxide and aluminum oxide.
Illustratively, the material of the ferroelectric channel layer 3 is a ferroelectric material, which may be, for example, indium diselenide, indium trisulfide or indium trisulfide. The material of the ferroelectric channel layer 3 may be sulfide, selenide, telluride, or the like.
Illustratively, each of the first electrode 4, the second electrode 5, and the modulating electrode 6 may be an elemental structure or a multi-layer structure. The material of the first electrode 4, the material of the second electrode 5 and the material of the modulating electrode 6 are respectively inert metal materials, and can be selected from gold, nickel, tungsten, titanium, platinum, molybdenum and chromium.
Referring to fig. 2 and 3, fig. 2 illustrates an array arrangement of ferroelectric memory structures 10 in an embodiment of the present disclosure, and fig. 3 illustrates a ferroelectric memory device 100 in an embodiment of the present disclosure. The ferroelectric memory device 100 comprises a ferroelectric memory structure 10 and a circuit structure 20. The plurality of ferroelectric memory structures 10 may be formed as a unitary structure with the circuit structure 20 electrically connected to each ferroelectric memory structure 10.
The ferroelectric memory structure 10 provided in the embodiments of the present disclosure includes a substrate 1, a ferroelectric channel layer 3, a first electrode 4, a second electrode 5, and a modulating electrode 6.
The ferroelectric channel layer 3 is laminated on the substrate 1. Illustratively, the ferroelectric memory structure 10 further includes a dielectric layer 2, the substrate 1, the dielectric layer 2, and the ferroelectric channel layer 3 are sequentially stacked, and the first electrode 4, the second electrode 5, and the modulation electrode 6 are located on the upper side of the ferroelectric channel layer 3. The first electrode 4 is connected to the ferroelectric channel layer 3; the second electrode 5 is connected to the ferroelectric channel layer 3. The second electrode 5 and the first electrode 4 are arranged at intervals along the extension direction of the ferroelectric channel layer 3, and the modulating electrode 6 is located between the first electrode 4 and the second electrode 5. The modulation electrode 6 is in contact with the ferroelectric channel layer 3.
The first electrode 4 is illustratively a source and the second electrode 5 is a drain. The operation of the ferroelectric memory structure 10 may include the following steps.
On the one hand, a source-drain positive voltage may be applied to the first electrode 4 and the second electrode 5, and an electric field in the source-drain positive voltage direction is formed in the ferroelectric channel layer 3. As the voltage increases and the electric field strength increases, eventually the polarization direction of the ferroelectric channel layer 3 coincides with the electric field along the source-drain positive voltage direction.
On the other hand, a source-drain negative voltage may be applied to the first electrode 4 and the second electrode 5, and an electric field in the source-drain negative voltage direction may be formed in the ferroelectric channel layer 3. As the voltage increases, the electric field strength increases, eventually causing the polarization direction of the ferroelectric channel layer 3 to be reversed and consistent with the electric field along the negative voltage direction of the source drain.
In addition, a modulating voltage is added at the modulating electrode 6 to generate an additional electric field to the local area of the ferroelectric channel layer 3, so that the local polarization direction of the ferroelectric channel layer 3 is adjusted, the performance difference caused by materials and processes is eliminated, and the ferroelectric memory structure 10 with high stability is realized.
According to the ferroelectric memory structure 10 provided by the embodiment of the disclosure, the polarization direction of the ferroelectric channel layer 3 is turned to be consistent with the external electric field through the voltage applied by the first electrode 4 and the second electrode 5, and the modulation voltage is applied by the modulation electrode 6 to locally finely adjust the polarization direction of the channel ferroelectric domain, so that the stability of the ferroelectric memory structure 10 is improved.
The dielectric layer 2 can serve as an insulating protective layer to reduce electric leakage of the ferroelectric channel layer 3 and improve polarization and domain structure retention of the ferroelectric channel layer 3. The first electrode 4 is in schottky contact with the ferroelectric channel layer 3, the second electrode 5 is in schottky contact with the ferroelectric channel layer 3, and the modulating electrode 6 is in schottky contact with the ferroelectric channel layer 3. The schottky contact formed by the electrode and the ferroelectric channel layer 3 can form a schottky barrier when external voltage is applied, and the barrier heights of the source electrode and the drain electrode are affected, so that the forward voltage drop is low, the reverse recovery time is extremely short, the switching is extremely rapid, and the stability of the ferroelectric memory structure 10 is ensured.
The embodiment of the present disclosure provides a ferroelectric memory device 100, including: a plurality of the above ferroelectric memory structures 10 and circuit structures arranged in an array. The circuit structure 20 is electrically connected to the first electrode 4, the second electrode 5 and the modulating electrode 6 of each ferroelectric memory structure 10.
By arranging the ferroelectric memory structure 10 provided by the embodiments of the present disclosure in an array, stability and cycle uniformity of the ferroelectric memory device 100 are improved.
Illustratively, nine ferroelectric memory structures 10 form a 3×3 array in the XY plane. The array may be implemented by other numbers of ferroelectric memory structures 10, and may be an array with identical rows and columns.
The circuit structure 20 may include an interconnect layer and conductive contacts. The interconnect layer can include one or more conductor layers and contact layers in which interconnect lines and/or via contacts are formed, as well as one or more dielectric layers. Illustratively, the first electrodes 4 of the plurality of ferroelectric memory structures 10 are interconnected, the second electrodes 5 of the plurality of ferroelectric memory structures 10 are interconnected, and the modulating electrodes 6 of the plurality of ferroelectric memory structures 10 are interconnected.
Referring to fig. 5, an embodiment of the present disclosure provides a method 2000 of tuning a ferroelectric memory device, comprising: step S201 and/or step S202, and step S203.
Step S201 includes a step of applying a forward voltage to the first electrode 4 and the second electrode 5 to adjust the ferroelectric cast polarization direction of the ferroelectric channel layer 3. Step S203 may be performed simultaneously to apply a modulation voltage to the modulation electrode 6.
Step S202 includes a step of applying reverse voltages to the first electrode 4 and the second electrode 5 to adjust the ferroelectric cast polarization direction of the ferroelectric channel layer 3. Step S203 may be performed simultaneously to apply a modulation voltage to the modulation electrode 6.
According to the method 2000 for regulating and controlling the ferroelectric memory device 100 provided by the embodiment of the present disclosure, the polarization direction of the channel ferroelectric domain is turned to be consistent with the applied electric field by the voltage applied by the first electrode 4 and the second electrode 5, and the modulation voltage is applied by the modulation electrode 6, so that the polarization direction of the channel ferroelectric domain is locally finely tuned, thereby improving the working performance of the ferroelectric memory device 100.
Illustratively, a forward voltage is first applied between the first electrode 4 and the second electrode 5, so that the ferroelectric domain polarization direction of the entire ferroelectric memory device 100 is consistent and stable with the forward voltage direction, and the ferroelectric memory device 100 is in a high resistance state; then, a reverse voltage is applied between the first electrode 4 and the second electrode 5, so that the polarization direction of the ferroelectric domain of the entire ferroelectric memory device 100 is consistent and stable with the reverse voltage direction, and the ferroelectric memory device 100 is in a low resistance state; finally, modulating voltage is externally connected to the interconnected modulating electrodes 6 to locally fine tune the polarization direction of the ferroelectric memory structure 10 in the ferroelectric memory device 100, thereby eliminating performance differences among the ferroelectric memory devices 100 and completing the regulation and control of the consistency of the ferroelectric memory devices 100.
Referring to fig. 4, fig. 4 shows the results of performing a plurality of read/write cycle tests under different resistance values (resistance value range 6mΩ to 1000mΩ) of the ferroelectric memory device 100. Test results show that under different resistance values, the ferroelectric memory device 100 can obtain good cycle consistency, and the nine cycle relative deviation is controlled within 5%, which indicates that the ferroelectric memory device 100 has good resistance state consistency.
The technical features of the embodiments disclosed above may be combined in any way, and for brevity, all of the possible combinations of the technical features of the embodiments described above are not described, however, they should be considered as the scope of the description provided in this specification as long as there is no contradiction between the combinations of the technical features.
In the embodiments disclosed above, the order of execution of the steps is not limited, and may be performed in parallel, or performed in a different order, unless explicitly stated and defined otherwise. The sub-steps of the steps may also be performed in an interleaved manner. Various forms of procedures described above may be used, and steps may be reordered, added, or deleted as long as the desired results of the technical solutions provided by the embodiments of the present disclosure are achieved, which are not limited herein.
The above disclosed examples represent only a few embodiments of the invention, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that modifications and improvements can be made by those skilled in the art without departing from the inventive concept, which falls within the scope of the invention as claimed. The scope of the invention should, therefore, be determined with reference to the appended claims.

Claims (10)

1. A method for fabricating a ferroelectric memory structure, comprising:
forming a ferroelectric channel layer laminated on a substrate;
forming a first electrode and a second electrode, wherein the first electrode and the second electrode are arranged at intervals along the extending direction of the ferroelectric channel layer and are respectively connected with the ferroelectric channel layer; and
wherein a modulating electrode is formed between the first electrode and the second electrode, the modulating electrode being in contact with the ferroelectric channel layer.
2. The method of fabricating a ferroelectric memory structure according to claim 1, further comprising: and forming a dielectric layer laminated on the substrate, wherein the ferroelectric channel layer is positioned on one side of the dielectric layer, which is away from the substrate.
3. The method for fabricating a ferroelectric memory structure as claimed in claim 1, wherein,
the step of forming the first electrode includes: the first electrode is in Schottky contact with the ferroelectric channel layer;
the step of forming the second electrode includes: the second electrode is in Schottky contact with the ferroelectric channel layer;
the step of forming the modulating electrode comprises: the modulating electrode is in ohmic contact or Schottky contact with the ferroelectric channel layer.
4. The method for manufacturing a ferroelectric memory structure according to any one of claims 1 to 3, wherein the first electrode, the second electrode, and the modulation electrode are located on the same side of the ferroelectric channel layer in a stacking direction.
5. A ferroelectric memory structure comprising:
a substrate;
a ferroelectric channel layer laminated on the substrate;
a first electrode connected to the ferroelectric channel layer;
a second electrode connected to the ferroelectric channel layer, the second electrode and the first electrode being arranged at intervals along the extension direction of the ferroelectric channel layer; and
the ferroelectric memory device is characterized by comprising a modulating electrode, wherein the modulating electrode is positioned between the first electrode and the second electrode, and the modulating electrode is contacted with the ferroelectric channel layer.
6. The ferroelectric memory structure of claim 5, further comprising a dielectric layer between the substrate and the ferroelectric channel layer.
7. The ferroelectric memory structure of claim 5, wherein the first electrode is in schottky contact with the ferroelectric channel layer and the second electrode is in schottky contact with the ferroelectric channel layer; the modulating electrode is in ohmic contact or Schottky contact with the ferroelectric channel layer.
8. The ferroelectric memory structure according to any one of claims 5 to 7, wherein the first electrode, the second electrode, and the modulation electrode are located on the same side of the ferroelectric channel layer in a stacking direction.
9. A ferroelectric memory device, comprising:
a plurality of ferroelectric memory structures as claimed in any one of claims 5 to 8 arranged in an array; a kind of electronic device with high-pressure air-conditioning system
And a circuit structure electrically connected to the first electrode, the second electrode and the modulating electrode of each ferroelectric memory structure.
10. A method of tuning a ferroelectric memory device as in claim 9, comprising:
applying a forward voltage or a reverse voltage to the first electrode and the second electrode to adjust a ferroelectric cast polarization direction of the ferroelectric channel layer; a kind of electronic device with high-pressure air-conditioning system
A modulating voltage is applied to the modulating electrode.
CN202311431186.1A 2023-10-31 2023-10-31 Ferroelectric memory structure, method of manufacturing the same, ferroelectric memory device, and method of controlling the same Active CN117156863B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311431186.1A CN117156863B (en) 2023-10-31 2023-10-31 Ferroelectric memory structure, method of manufacturing the same, ferroelectric memory device, and method of controlling the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311431186.1A CN117156863B (en) 2023-10-31 2023-10-31 Ferroelectric memory structure, method of manufacturing the same, ferroelectric memory device, and method of controlling the same

Publications (2)

Publication Number Publication Date
CN117156863A true CN117156863A (en) 2023-12-01
CN117156863B CN117156863B (en) 2024-02-06

Family

ID=88903181

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311431186.1A Active CN117156863B (en) 2023-10-31 2023-10-31 Ferroelectric memory structure, method of manufacturing the same, ferroelectric memory device, and method of controlling the same

Country Status (1)

Country Link
CN (1) CN117156863B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1056088A (en) * 1996-08-09 1998-02-24 Hitachi Ltd Ferroelectric memory element and ferroelectric memory device equipped with it
KR20050038302A (en) * 2003-10-21 2005-04-27 이재춘 A metal-semiconductor fet for based on ferroelectric a semiconductor
CN110246891A (en) * 2019-06-28 2019-09-17 北京大学 A kind of synapse transistor, device and its manufacturing method, operation array
CN115084360A (en) * 2022-05-31 2022-09-20 复旦大学 Ferroelectric multivalued memory with local regulation and control characteristics and preparation method thereof
CN116940226A (en) * 2023-09-19 2023-10-24 浙江大学杭州国际科创中心 Ferroelectric semiconductor device, touch sense memory, and touch data read/write method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1056088A (en) * 1996-08-09 1998-02-24 Hitachi Ltd Ferroelectric memory element and ferroelectric memory device equipped with it
KR20050038302A (en) * 2003-10-21 2005-04-27 이재춘 A metal-semiconductor fet for based on ferroelectric a semiconductor
CN110246891A (en) * 2019-06-28 2019-09-17 北京大学 A kind of synapse transistor, device and its manufacturing method, operation array
CN115084360A (en) * 2022-05-31 2022-09-20 复旦大学 Ferroelectric multivalued memory with local regulation and control characteristics and preparation method thereof
CN116940226A (en) * 2023-09-19 2023-10-24 浙江大学杭州国际科创中心 Ferroelectric semiconductor device, touch sense memory, and touch data read/write method

Also Published As

Publication number Publication date
CN117156863B (en) 2024-02-06

Similar Documents

Publication Publication Date Title
US10727348B2 (en) Semiconductor device with adjacent source/drain regions connected by a semiconductor bridge, and method for fabricating the same
US20220077171A1 (en) Three-dimensional memory device with source structure and methods for forming the same
US10714535B2 (en) Resistive memory array and fabricating method thereof
US11488979B2 (en) Semiconductor device of three-dimensional structure including ferroelectric layer
WO2006121828A2 (en) One time programmable memory cell
US9070694B2 (en) Manufacturing of electronic devices in a wafer of semiconductor material having trenches with different directions
US11127757B2 (en) Three-dimensional memory device with source structure and methods for forming the same
US7964867B2 (en) Switching element, switching element fabriction method, reconfigurable logic integrated circuit, and memory element
CN110622310A (en) Three-dimensional memory device having source structure and method for forming the same
US20220102377A1 (en) Three-dimensional memory device with source structure and methods for forming the same
CN117156863B (en) Ferroelectric memory structure, method of manufacturing the same, ferroelectric memory device, and method of controlling the same
US11417707B2 (en) Nonvolatile memory device of three-dimensional structure including resistance change element
US20150325580A1 (en) Semiconductor devices and methods of manufacturing the same
CN110867464B (en) Memristor based on 1T1R structure, preparation method thereof and integrated structure
KR102652757B1 (en) Variable low resistance line non-volatile memory device and operating method thereof
JP2019165124A (en) Semiconductor storage device
CN111883531A (en) DRAM memory cell and manufacturing method thereof, memory cell array and chip
KR102280823B1 (en) Variable low resistance area based memory device and controlling thereof
CN116113313B (en) Phase change memory device and method of manufacturing the same
CN217444400U (en) Integrated circuit
KR102370745B1 (en) Variable low resistance area based memory device and controlling thereof
US20240090230A1 (en) Memory array and operation method thereof
KR102059485B1 (en) Variable low resistance area based memory device and controlling thereof
JPS63166A (en) Nonvolatile semiconductor memory
KR20220030985A (en) Variable low resistance area based memory device and controlling thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant