CN117154874A

CN117154874A - Electronic equipment and system

Info

Publication number: CN117154874A
Application number: CN202311013220.3A
Authority: CN
Inventors: 雷奋星; 刘文成; 张桐恺; 梁峰
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2023-03-30
Filing date: 2023-03-30
Publication date: 2023-12-01
Also published as: CN116054357B; CN116054357A

Abstract

The application provides an electronic device and a system, wherein the electronic device comprises: the interface chip, the first power line and the first switch circuit; the first switch circuit comprises a first switch port, a second switch port and a third switch port, the second switch port is used for receiving an instruction to control the connection state of the first switch port and the second switch port, and the third switch port is used for being grounded; under the condition that the voltage of a second chip port corresponding to the signal line in the interface chip is larger than the preset voltage, the first switch circuit receives a conduction instruction through the second switch port, and the first switch port and the third switch port are conducted in response to the conduction instruction, so that the first voltage is released in a mode of being grounded through the first power port. The problem that pins at two ends of a signal wire are in an over-current and over-voltage state for a long time due to the short circuit phenomenon of the power wire and the signal wire in a charger in the charging process is solved, and the risk of burning devices is reduced.

Description

Electronic equipment and system

Technical Field

The present application relates to the field of charging devices, and in particular, to an electronic device and a system.

Background

In order to realize quick charging and improve user experience, high-voltage charging is becoming more and more popular in electronic products such as mobile phones and tablets, and charging safety is becoming more and more important.

In general, the charger and the terminal device to be charged are connected through a universal serial bus interface (universal serial bus, USB interface), where the charger and the terminal device may negotiate information such as a charging voltage by using a signal line in the USB interface, and the charger may output the charging voltage to the terminal device based on a power line in the USB interface.

In the charging process, an abnormal short circuit may occur between the power line and the signal line, and since the power line is used for outputting a higher charging voltage, for example, a high voltage charging voltage of 9 volts (V), 10V, or 20V, and the working voltage of the signal line is generally very low, for example, 3V, after the power line and the signal line are shorted, an overvoltage and overcurrent phenomenon occurs in the signal line, which may cause damage to pin devices related to the signal line and devices on the signal line, so that the signal line cannot be charged, which not only affects the use of users, but also even causes a fire hazard, and how to provide a charging protection circuit to improve the charging safety problem caused by such a situation becomes a big research topic in the field of rapid charging.

Disclosure of Invention

The application provides electronic equipment and a system, which are used for solving the problem that pins at two ends of a signal wire are in an over-current and over-voltage state for a long time due to the short circuit phenomenon of a power wire and the signal wire in a charger in a charging process, and reducing the risk of burning devices.

In a first aspect, the present application provides a charge protection circuit comprising: the interface chip, the first power line, the first signal line and the first switch circuit; the interface chip comprises a first chip port and a second chip port; the first power line comprises a first power port and a second power port, the first power port is used for inputting a first voltage, and the second power port is used for being connected with the first chip port; the first signal line comprises a first signal port and a second signal port, the first signal port is used for inputting a second voltage, the second signal port is used for being connected with the second chip port, and the second voltage is smaller than the first voltage; the first switch circuit comprises a first switch port, a second switch port and a third switch port, wherein the first switch port is used for being connected with the first power supply port, the second switch port is used for receiving an instruction to control the connection state of the first switch port and the second switch port, and the third switch port is used for being grounded; when the voltage of the first chip port is equal to the first voltage and the voltage of the second chip port is equal to the second voltage, the first switch port and the third switch port are disconnected, the interface chip performs negotiation about the value change of the first voltage through the second voltage and an external voltage output device, and the interface chip charges the terminal device through the first voltage; and under the condition that the voltage of the second chip port is larger than a preset voltage, the first switch circuit receives a conduction instruction through the second switch port, and the first switch port and the third switch port are conducted in response to the conduction instruction, so that the first voltage is released in a mode that the first power port is grounded, and the preset voltage is larger than or equal to the second voltage and smaller than the first voltage.

In the present application, the first voltage refers to a voltage transmitted from the voltage output device to the first end of the USB power line, and the second end of the USB power line is used to connect with the first power port. The second voltage refers to an operating voltage of the first signal line. Illustratively, before the terminal device charges the terminal device based on the first voltage, the terminal device negotiates a charging protocol (e.g., a magnitude of the charging voltage, a current carrying capability of the terminal device, etc.) with the voltage output device based on the second voltage, and after the negotiation is completed, the voltage output device transmits the first voltage to the first power supply port based on the charging voltage, so that the terminal device is charged based on the first voltage.

Generally, during charging, if there is data transmission (e.g., file transmission, image transmission, etc.) between the terminal device and the voltage output device, data communication is performed between the voltage output device and the terminal device based on the relevant signal lines (first signal line, second signal line) and the above-mentioned second voltage. In the charging process, if there is no data transmission between the terminal device and the voltage output device, the first signal port may or may not input the second voltage, which is specifically determined according to design, for example, if the voltage output device is a computer including a USB socket, the terminal device will generally input the second voltage in the charging process based on the first voltage, regardless of whether there is data transmission between the terminal device and the voltage output device. If the voltage output device is an adapter, the terminal device does not input the second voltage when there is no data transmission between the terminal device and the voltage output device during the process of charging based on the first voltage.

By adopting the charging protection circuit provided by the application, under the condition that the voltage of the second chip port is larger than the preset voltage, the terminal equipment turns on the grounding switch of the first power port, on one hand, the first voltage is rapidly released through the ground wire by the first switching circuit, so that the duration that the first voltage is transmitted to the second chip port to enable the voltage of the second chip port to be larger than the preset voltage can be reduced; on the other hand, most of the current in the circuit can be released through the ground wire, so that the current flowing to the first signal wire and the second chip port is greatly reduced; the purpose of reducing the duration of overvoltage and overcurrent of the signal port (the second chip end) related to the signal wire and reducing the risk of burning related devices is achieved.

In one possible implementation manner, the charging protection circuit further includes a second power line and a second signal line, a first end of the second power line is used for inputting the first voltage, and a second end of the second power line is used for being connected with the first power port; the first end of the second signal line is used for inputting the second voltage, and the second end of the second signal line is used for being connected with the first signal port; in the case where abnormal conduction does not occur between the second power supply line and the second signal line, the voltage of the first chip port is equal to the first voltage (and the voltage of the second chip port is equal to the second voltage or the voltage of the second chip port is equal to 0); and under the condition that the second power line and the second signal line are abnormally conducted, the first voltage is transmitted to the second chip port, and the voltage of the second chip port is larger than the preset voltage.

The second power line and the second signal line are illustratively power lines and signal lines in a universal serial bus (universal serial bus, USB).

In the present application, the first voltage refers to a voltage transmitted from the voltage output device to the first end of the second power line, and the first voltage varies according to whether the second power line and the second signal line are abnormally turned on. Illustratively, in one possible implementation, the first end of the second power line is used to connect to a voltage output device, and the second power line is further connected to a capacitive circuit (which is also referred to as a second capacitive circuit in other descriptions herein), where the second power line is not abnormally conducted with the second signal line, or where the second power line is abnormally conducted with the second signal line and the voltage output device still outputs a voltage to the first end of the second power line based on a charging voltage, the first voltage being a voltage that the capacitive circuit outputs after storing and filtering based on the charging voltage; in the case where abnormal conduction occurs between the second power line and the second signal line and the voltage output device no longer outputs a voltage to the first end of the second power line based on the charging voltage, the first voltage is a capacitance voltage generated by the capacitor circuit releasing the stored electric energy.

In the present application, the voltage output device may be an adapter or other device (such as a computer, a home socket, etc.) including a USB socket, which is not limited herein.

The voltage output device still outputting the voltage to the first end of the second power line based on the charging voltage can also be understood as a source of the charging voltage which is not turned off by the voltage output device, and the voltage output device no longer outputting the voltage to the first end of the second power line based on the charging voltage can also be understood as a source of the charging voltage which is turned off by the voltage output device.

In one possible implementation manner, in a case where abnormal conduction occurs between the second power line and the second signal line, the voltage output device outputs a voltage to the first end of the second power line no longer based on a charging voltage, and the first switch port is disconnected from the third switch port, the capacitor circuit continuously releases the capacitor voltage through the second chip port, the voltage and current of the second chip port decrease to 0 in a first period, the current of the second chip port has a phenomenon that is greater than a normal operation current of the second chip port in the first period, and the current of a device on the second signal line has a phenomenon that is greater than a normal operation current in the first period; under the conditions that the second power line and the second signal line are abnormally conducted, the voltage output device does not output voltage to the first end of the second power line based on charging voltage any more, and the first switch port and the third switch port are conducted, the capacitor circuit is grounded through the second power line and the first power line to release voltage stored in the capacitor circuit, in the capacitor voltage release process, the voltage of the second chip port is equal to discharging voltage, the current flowing into the second chip port is far smaller than the current flowing into the first switch port, the voltage of the second chip port is rapidly reduced to 0 in a second duration, and the second duration is smaller than the first duration.

It is understood that the first duration and the second duration refer to durations taken from abnormal conduction of the second power line and the second signal line until the voltage of the second chip port is reduced to 0.

In a possible implementation manner, the interface chip further includes a third chip port, and the third chip port is used for being connected with the second switch port; and under the condition that the voltage transmitted to the second chip port is larger than the preset voltage, the interface chip is used for transmitting the conducting instruction to the second switch port through the third chip port.

In one possible implementation, the charging protection circuit further includes a system-on-chip connected to the interface chip; the interface chip is used for sending first overvoltage information to the system-in-chip when the voltage transmitted to the second chip port is larger than the preset voltage, wherein the first overvoltage information is used for indicating that the voltage of the second chip port is larger than the preset voltage; the system-on-chip is used for responding to the first overvoltage information and sending the conducting instruction to the second switch port.

In one possible implementation manner, in a case that the first switch port is turned on with the third switch port and the voltage of the first power supply port is 0, the first switch circuit is further configured to receive a disconnection instruction sent by a system-in-chip or the interface chip, and disconnect the first switch port from the third switch port in response to the disconnection instruction, where the system-in-chip is connected to the interface chip.

The voltage output device turns off the output of the charging voltage after the second power line is turned on with the second signal line, and the terminal device turns on the first switch port and the third switch port, the capacitor voltage of the capacitor circuit is released through the first switch circuit, and under the condition that the voltage of the first power line drops to 0, the system-level chip or the interface chip in the terminal device sends the off instruction to the second switch port, so that the first switch port is disconnected from the second switch port, and the problem that the terminal device cannot be charged again through other normally-turned-on USB charging lines due to the fact that the first switch port is always in a connection state with the second switch port is avoided.

In one possible implementation manner, the charging protection circuit further includes a system-on-chip, where the system-on-chip is connected to the interface chip, and is further configured to record an overvoltage event based on first overvoltage information, where the first overvoltage information is used to indicate that a voltage of the second chip port is greater than the preset voltage, and the first overvoltage information is sent by the interface chip to the system-on-chip.

In one possible implementation, the first signal line is a USB data positive signal line d+, a USB data negative signal line D-, an ac charging confirmation signal line CC, or an auxiliary signal line SBU.

In a second aspect, the present application provides a system of a charge protection circuit, the system comprising: the interface chip, the first power line, the first signal line, the first switch circuit, the protocol chip, the second switch circuit, the third power line and the third signal line; the interface chip comprises a first chip port and a second chip port; the protocol chip comprises a fourth chip port and a fifth chip port; the first power line comprises a first power port and a second power port; the third power line comprises a fourth power port and a fifth power port; the first signal line comprises a first signal port and a second signal port, and the second signal port is connected with the second chip port; the third signal line comprises a third signal port and a fourth signal port; the first switch circuit comprises a first switch port, a second switch port and a third switch port, the first switch port is connected with the first power port, the second switch port is used for receiving an instruction to control the connection state of the first switch port and the second switch port, and the third switch port is grounded; the second switch circuit comprises a fourth switch port, a fifth switch end and a sixth switch Guan Duankou, wherein the fifth switch port is used for receiving an instruction to change the connection state between the fourth switch port and the sixth switch port; the fourth switch port is used for inputting a charging voltage, the fifth switch port is connected with the fourth chip port, the sixth switch port is connected with the fourth power port, the fifth power port is used for being connected with the first power port, the fifth power port is used for outputting a first voltage, and the first voltage is obtained based on the charging voltage and a related capacitance circuit; the third signal port is connected with the fifth chip port, the fourth signal port is used for being connected with the second signal port, the third signal port is used for inputting a second voltage, and the second voltage is smaller than the first voltage; under the condition that the voltage of the first chip port is equal to the first voltage and the voltage of the second chip port is equal to the second voltage, the first switch port and the third switch port are disconnected, the interface chip performs negotiation work about the value of the first voltage through the second voltage and an external voltage output device, and the interface chip charges the terminal device through the first voltage; in the case that the voltage of the fifth chip port is greater than a preset voltage or in the case that the current of the fourth power port is greater than a preset current, the second switching circuit receives a disconnection instruction based on the fifth switching disconnection port, and the fourth switching port and the sixth switching port are disconnected in response to the disconnection instruction so as to shut off the output of the charging voltage; and under the condition that the voltage of the second chip port is larger than a preset voltage, the first switch circuit receives a conduction instruction through the second switch port, and the first switch port and the third switch port are conducted in response to the conduction instruction, so that the first voltage is released in a mode that the first power port is grounded, and the preset voltage is larger than or equal to the second voltage and smaller than the first voltage.

In the system adopting the charging protection circuit provided by the application, in the charging process, the second power line and the second signal line are in short circuit, the first voltage flows to the second chip port and the fifth chip port at the two ends of the signal line through the short circuit part of the power line, so that the protocol chip at the adapter side can monitor that the voltage of the fifth chip port is larger than the preset voltage under the condition that the second chip port and the fifth chip port are in an overcurrent and overvoltage state, and the fourth switch Guan Duankou in the second switch circuit is disconnected from the sixth switch port, and the output of the first voltage is turned off. The interface chip at the terminal equipment side can also monitor that the voltage of the second chip port is larger than the preset voltage, the first switch port and the third switch port in the first switch circuit are conducted, the second power line is grounded, the first voltage remained on the second power line and the voltage stored in the capacitor branch are rapidly released through the ground wire, and therefore the aims of reducing the overvoltage and overcurrent duration of the second chip port and the fifth chip port and reducing the risk of burning related devices are achieved.

In one possible implementation manner, the charging protection system further includes a second power line and a second signal line, a first end of the second power line is connected to the fifth power port, and a second end of the second power line is connected to the first power port; the first end of the second signal line is used for being connected with the fourth signal port, and the second end of the second signal line is used for being connected with the first signal port; in the case that the second power line and the second signal line are not abnormally conducted, the voltage of the first chip port is equal to the first voltage, and the voltage of the second chip port and the voltage of the fifth chip port are equal to the second voltage; transmitting the first voltage to the second chip port and the fifth chip port under the condition that the second power line and the second signal line are abnormally conducted, wherein the voltage of the second chip port and the voltage of the fifth chip port are larger than the preset voltage; and under the conditions that the second power line and the second signal line are abnormally conducted, the fourth switch port and the sixth switch Guan Duankou are conducted, and the first switch port and the third switch port are conducted, the current of the fourth power port is larger than the preset current.

In one possible implementation manner, the protocol chip is configured to send the disconnection instruction to the fifth switch port through the fourth chip port when the voltage of the fifth chip port is greater than the preset voltage.

In one possible implementation manner, the protocol chip is configured to send the disconnection instruction to the fifth switch port through the fourth chip port when the current of the fourth power port is greater than the preset current.

In one possible implementation manner, the interface chip is configured to send the on instruction to the second switch port through the third chip port when the voltage transmitted to the second chip port is greater than the preset voltage.

In one possible implementation, the system of the charging protection circuit further includes a system-on-chip connected with the interface chip; the interface chip is used for sending first overvoltage information to the system-in-chip under the condition that the voltage transmitted to the second chip port is larger than the preset voltage, wherein the first overvoltage information is used for indicating that the voltage of the second chip port is larger than the preset voltage; the system-in-chip is used for responding to the first overvoltage information, sending the conducting instruction to the second switch port and recording an overvoltage event based on the first overvoltage information.

Drawings

Fig. 1 is a schematic diagram of another charge protection circuit according to an embodiment of the present application;

fig. 2 is a voltage change graph of other charging protection circuits after a power line and a d+ signal line in a charger are short-circuited in a charging process according to an embodiment of the present application;

fig. 3 is a schematic diagram of a current flow in a circuit after a power line and a d+ signal line in a charger are shorted in a charging process of another charging protection circuit according to an embodiment of the present application;

fig. 4 is a schematic diagram of a current flow in a circuit after a power line and a d+ signal line in a charger are shorted in a charging process of another charge protection circuit according to an embodiment of the present application;

fig. 5 is a schematic diagram of a charge protection circuit according to an embodiment of the present application;

fig. 6 is a graph of voltage change after a power line and a d+ signal line in a charger are short-circuited in a charging process by using the charge protection circuit according to the embodiment of the present application;

fig. 7 is a schematic diagram of a system of a charge protection circuit according to an embodiment of the present application;

fig. 8 is a schematic diagram of a system of a charge protection circuit according to an embodiment of the present application, in which after a short circuit occurs between a second power line and a second signal line, a current flows in the circuit;

Fig. 9 is a graph showing a change in current of a fourth power port after a short circuit occurs between a second power line and a second signal line in a charging process in a system using one of the charging protection circuits according to the embodiments of the present application;

FIG. 10 is a schematic diagram of a simplified overview of four possible charge protection methods provided by a charge protection circuit according to an embodiment of the present application;

fig. 11 is a schematic diagram of a charging protection method according to an embodiment of the present application;

fig. 12 is a schematic diagram of another charge protection method according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described with reference to the accompanying drawings.

The terms first and second and the like in the description, the claims and the drawings of the present application are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprising," "including," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion. Such as a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to the list of steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

In the present application, "at least one (item)" means one or more, "a plurality" means two or more, "at least two (items)" means two or three and more, "and/or" for describing an association relationship of an association object, and three kinds of relationships may exist, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of (a) or a similar expression thereof means any combination of these items. For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c".

The following describes the pain point problem solved by the charge protection circuit provided by the present application with reference to the charge circuit system shown in fig. 1.

Illustratively, as shown in FIG. 1 below, the charging circuitry includes a terminal device, an adapter, a power line, a D+ signal line, and a D-signal line.

The terminal device comprises an interface chip and a first capacitance circuit, and the adapter comprises a protocol chip (protocol IC chip), an output mos switch circuit and a second capacitance circuit.

The interface chip comprises a first Vbus pin, a first D+ signal pin and a first D-signal pin; wherein the first Vbus pin is an input of a voltage; the first D+ signal pin is a pin corresponding to a universal serial bus (universal serial bus, USB) data positive signal line on the interface chip, and the first D-signal pin is a pin corresponding to a USB data negative signal line on the interface chip.

The protocol chip comprises a voltage input pin, a second D+ signal pin and a second D-signal pin, wherein the second D+ signal pin is a pin corresponding to a USB data positive signal line on the protocol chip, and the second D-signal pin is a pin corresponding to a USB data negative signal line on the protocol chip.

The connection relationship between the adapter and the terminal device comprises:

The first end of the output mos switch circuit is used for connecting charging voltage, the second end of the output mos switch circuit is connected with the first end of the second capacitor circuit, the first end of the second capacitor circuit is also connected with the second end of the power line, and the second end of the second capacitor circuit is grounded; the first end of the power line is connected with the first end of a first capacitance circuit, the first end of the first capacitance circuit is also connected with a first Vbus pin, and the second end of the first capacitance circuit is grounded;

the second d+ signal pin is used for connecting with the first d+ signal pin through the d+ signal line;

the second D-signal pin is used for being connected with the first D-signal pin through the D-signal line.

The first capacitor circuit and the second capacitor circuit are used for storing and filtering the input voltage so that the voltage transmitted to the first Vbus pin is a direct current voltage.

When the charging voltage is input through the first end of the output mos switch circuit and the output mos switch circuit is in a conducting state, the interface chip is configured to receive a first voltage through the second capacitor circuit, the first capacitor circuit and the first Vbus pin, where the first voltage is a voltage obtained by energy storage filtering of the charging voltage through the capacitor circuit.

Under the condition that the second voltage is input to the voltage input pin, the protocol chip is in a working state. The protocol chip is used for carrying out data interaction on negotiation of initial charging voltage and/or rising and falling of charging voltage in the charging process and the like with the terminal equipment based on the D+ signal line and/or the D-signal line.

In general, the default state of the output mos switch circuit may be an on state or an off state. For example, if the default state of the output mos switch circuit is an off state, the adapter may negotiate an initial charging voltage with the interface chip through the d+ signal line and/or the D-signal line, and then set the state of the output mos switch circuit to an on state. Or, for example, the default state of the output mos switch circuit is a conducting state, and after the adapter inputs the power voltage through the charging plug, the output mos switch circuit outputs a charging voltage (for example, 5V) with a lower voltage value to the power line, and the interface chip charges the terminal device based on the charging voltage. The protocol chip is used for dynamically negotiating the rising or reducing of the charging voltage with the interface chip through the d+ signal line and/or the D-signal line after the charging process, for example, if the interface chip sends the charging voltage supported by the terminal device to the protocol chip through the d+ signal line and/or the D-signal line to be 10V, the adapter rises the output charging voltage, for example, the electric quantity of the terminal device is almost full, and then the adapter reduces the charging voltage.

It can be understood that the functions of the protocol chip, the d+ signal line, and the D-signal line in the charging scenario when the default state of the output mos switch circuit is an on state or an off state are conventional in the art, and will not be described in detail.

Generally, the operating voltages (for example, simply referred to as the second voltage) of the above-mentioned d+ signal line and D-signal line are low, and the operating voltage (first voltage) of the power supply line is high, that is, the first voltage is greater than the second voltage. Particularly in a fast charge scenario, for example, the first voltage is 20V and the second voltage is 3V.

The following describes the problems with the circuit shown in fig. 1 described above:

when the second power line is short-circuited to the d+ signal line and/or the D-signal line and is turned on, for example, when a short-circuit phenomenon occurs between the power line and the d+ signal line, the charging voltage output from the output mos switch circuit to the power line flows through the power line and the d+ signal line and through pins at two ends corresponding to the d+ signal line, and after the short-circuit, the charging voltage is greater than the second voltage (for example, the second voltage is 3V and the charging voltage is 20V), so that the devices on the d+ signal line, the first d+ signal pin and the second d+ signal pin are in an overcurrent and overvoltage state, and the devices are burnt.

In other charging protection schemes, the protocol chip in the adapter can monitor the voltages of the second d+ signal pin and the second D-signal pin in the charging process, and when the voltage of the second d+ signal pin or the second D-signal pin is detected to be higher than the preset voltage, the working state of the output mos switch circuit is switched to the off state, that is, the output of the charging voltage is turned off.

According to the scheme, after the output of the charging voltage is turned off, the capacitors in the first capacitor circuit and the second capacitor circuit are discharged, the discharging voltage of the capacitors flows through the devices on the D+ signal line and the pins at the two ends corresponding to the D+ signal line, so that the devices on the first D+ signal pin, the second D+ signal pin and the D+ signal line are still in an over-voltage state for a long time, and the risk of burning the devices is still high.

Illustratively, the voltage of the first D+ signal line after the short circuit is shown in the graph of FIG. 2. Specifically, a short circuit occurs at time t1, the output of the charging voltage of the output mos switch circuit is turned off at time t2, and after time t2, the voltages at the first d+ signal pin, the second d+ signal pin, and the short circuit portion of the power supply line are equal based on the principle that the voltages of the respective branches of the parallel circuit are equal. The direction of the discharge current of the capacitor in the capacitor circuit from time t2 to time t3 is shown in fig. 3, wherein the discharge current in the second capacitor circuit flows to the power line and shunts at the short circuit to the first Vbus pin and the d+ signal line to the first d+ signal pin and the second d+ signal pin, so that the voltage of the second capacitor circuit is released, resulting in the first d+ signal pin and the second d+ signal pin being in an over-current and over-voltage state. At time t3, the voltage output by the capacitor circuit is smaller than the working voltage of the interface chip for stopping charging, after time t3, the charging function of the interface chip stops working, which is equivalent to that the direction from the short circuit position to the first Vbus on the power line belongs to an open circuit state, the discharging current direction of the capacitor in the capacitor circuit is shown in fig. 4, and the second capacitor circuit and the first capacitor circuit slowly release the capacitor voltage to the first D+ signal pin and the second D+ signal pin through the D+ signal line, so that the first D+ signal pin and the second D+ signal pin are in an overcurrent and overvoltage state. Until time t4, the voltages of the first D+ signal pin and the second D+ signal pin drop to 0. Illustratively, the time difference between t1 and t4 is about 180 milliseconds (ms), that is, the first and second D+ signal pins remain in an over-voltage and over-current state for a long period of time during t1 to t 4.

Based on the above, the application provides a charge protection circuit, a system of the charge protection circuit and a charge protection method corresponding to the charge protection circuit, so as to improve the problem that pins at two ends of a signal line and devices on the signal line are in an over-current and over-voltage state for a long time when a short circuit phenomenon occurs between the power line and the signal line (D+ signal line and/or D-signal line), and reduce the risk of burning the devices.

The specific implementation and beneficial effects of the charging protection circuit, the charging protection system and the charging protection method corresponding to the charging protection circuit provided by the application are respectively described below.

First, the charging protection circuit provided by the present application is described in detail below with reference to the circuit diagram shown in fig. 5.

As shown in fig. 5, the charge protection circuit includes an interface chip, a first power line, a first signal line, and a first switch circuit.

The interface chip comprises a first chip port and a second chip port; in the embodiment of the present application, the interface chip may be a back-end chip related to charging, for example, the interface chip may be a charge IC in the terminal device, which is responsible for managing external power supply and charging and discharging of the battery, or the interface chip may be a back-end chip such as a power management unit (power management unit, PMU) that integrates power management and charging control, which is not limited herein.

The first power line comprises a first power port and a second power port, wherein the first power port is used for inputting a first voltage, and the second power port is used for being connected with the first chip port. The first signal line comprises a first signal port and a second signal port, the first signal port is used for inputting a second voltage, the second signal port is used for being connected with the second chip port, and the second voltage is smaller than the first voltage;

the first switch circuit comprises a first switch port, a second switch port and a third switch port, wherein the first switch port is used for being connected with the first power port, the second switch port is used for receiving an instruction to control the working states of the first switch port and the third switch port in the first switch circuit, and the third switch port is used for being grounded; in some possible implementations, the first power line may further include a third power port, where the third power port is configured to be connected to the first switch port, and the third power port may be any one of ports located between the first power port and the second power port (including that the third power port is the same port as the second power port). In the application, whether the second power line and the second signal line are abnormally conducted or not, the voltage of the third power port is consistent with the voltage of the first power port, so that the first switch port is connected with the first power port to describe the connection of the first switch port and the third power port.

The interface chip negotiates information related to a charging protocol, such as a maximum current carrying capacity of a terminal device, a value regarding a charging voltage, etc., with an output device (such as an adapter or a USB socket) of the charging voltage through the first signal line and the second chip interface.

After the negotiation of the charging protocol related information is completed, the first power port may receive a first voltage, and at this time, the first switch circuit is in a first connection state, and the interface chip is further configured to receive the first voltage through the first power line and the first chip port to perform charging, where the first connection state refers to disconnection between the first switch port and the third switch port.

The interface chip is also used for monitoring the voltage of the second chip interface and enabling the first switch circuit to receive the conduction instruction through the second switch port under the condition that the voltage of the second chip port is larger than the preset voltage. The first switch circuit is configured to switch the first connection state to a second connection state in response to the on command, where the second connection state refers to that the first switch port and the third switch port are turned on, and the preset voltage is greater than or equal to the second voltage and less than the first voltage.

The interface chip is further used for enabling the first switch circuit to receive an opening instruction through the second switch port under the condition that the first switch circuit is in a first connection state and the voltage of the second chip port is equal to 0; the first switch circuit is used for switching the second connection state to the first connection state in response to the disconnection instruction. In the embodiment of the application, in the initial state, the first switch circuit is in a first connection state; after receiving the on command, the first switch circuit sets the connection state as a second connection state; the first switch circuit sets the connection state to a first connection state after receiving the disconnection instruction.

In a possible implementation manner, the interface chip further includes a third chip port, and the third chip port is used for being connected with the second switch port. Optionally, the interface chip may send the on command to the second switch port when the interface chip detects that the voltage of the second chip port is greater than the preset voltage.

In one possible implementation, the charge protection circuit further includes a system-on-chip. Optionally, the interface chip may enable the first switch circuit to receive the on command through the second switch port, or the interface chip may send first overvoltage information to the system-level chip when detecting that the voltage of the second chip port is greater than a preset voltage, where the first overvoltage information is used to indicate that the voltage of the second chip port is greater than the preset voltage. The system-in-chip is used for responding to the first overvoltage information and sending the conducting instruction to the second switch port.

Illustratively, the interface chip further includes a seventh chip port, the system on chip includes an eighth chip port and a ninth chip port, and the relationship between the system on chip and the interface chip includes: the eighth chip port is used for being connected with the seventh chip port, and the ninth chip port is used for being connected with the second switch port; the interface chip is specifically configured to send, when it is detected that the voltage of the second chip port is greater than a preset voltage, first overvoltage information to the eighth chip port through the seventh chip port, where the first overvoltage information is used to indicate that the voltage of the second chip port is greater than the preset voltage; the system-in-chip is specifically configured to send the on command to the second switch port through a ninth chip port in response to the first overvoltage information.

In other possible implementations, the system-on-chip is further configured to record an overpressure event based on the first overpressure information in case that the first overpressure information is received, and provide a reference for performing troubleshooting and problem backtracking afterwards.

In the normal charging process of the terminal device, the terminal device obtains the first voltage and the second voltage through the voltage output device and the USB charging wire, hereinafter, for convenience of distinction, a power wire in the USB charging wire is referred to as a second power wire, and a signal wire in the USB charging wire is referred to as a second signal wire. Specifically, the first voltage is a voltage transmitted to the first power port by the voltage output device through a second power line in the USB charging line, and the second voltage is a voltage transmitted to the first signal port by the voltage output device through a second signal line in the USB charging line.

If the second power line and the second signal line are short-circuited during charging and the voltage output device does not stop actively outputting the voltage, the first voltage is still the voltage transmitted to the first power port by the voltage output device through the second power line, but at this time, the second voltage is the voltage transmitted to the first signal port by the voltage output device through the second power line, that is, the second voltage is equal to the first voltage, and at this time, the second voltage is greater than the preset voltage.

If the second power line and the second signal line are short-circuited during charging and the voltage output device stops actively outputting voltage, the first voltage is a voltage transmitted to the first power port through the second power line by a capacitor connected with the second power line in the voltage output device and used for storing and filtering, and the second voltage is a voltage transmitted to the first signal end through the second power line by the capacitor, and at this time, the second voltage is still greater than the preset voltage within a period of time.

However, when the charging protection circuit provided by the application detects that the second voltage is greater than the preset voltage (namely, the second power line and the second signal line are in short circuit), the first power port of the first power line is grounded, so that the voltage output by the capacitor through the second power line is quickly released through the first switch circuit through grounding, most of the current output by the second power line flows to the ground line, the current flowing from the second power line to the second chip port is greatly reduced, the duration of overvoltage and overcurrent of the first signal line is reduced, and the risk of burning related devices is reduced.

The first signal port is an port corresponding to the d+ signal line, the second power line is shorted with the d+ signal line in the USB, the voltage output device actively turns off the output of the charging voltage before the terminal device grounds the first power line (or the second power line), then the voltage of the second chip port (or the first signal port) after the short circuit is shown in the graph of fig. 6, where the d+ signal line is shorted with the power line at time t1, the voltage output device turns off the output of the charging voltage at time t2, the terminal device grounds the first power line at time t5, the voltage in the capacitor in the voltage output device is rapidly released through the second power line and the ground line, and the time difference between t1 and t6 is about 10ms after the detection, so that the risk of burning out of the relevant devices can be reduced.

The charging protection system provided by the application is described in detail below with reference to the circuit diagram shown in fig. 7.

As shown in fig. 7, the charge protection system includes: the interface chip, the first power line, the first signal line, the first switch circuit, the protocol chip, the second switch circuit, the third power line, the third signal line, the second power line and the second signal line;

The interface chip, the first power line, the first signal line, and the first switch circuit are devices related to charging in the terminal device side; the protocol chip, the second switch circuit, the third power line and the third signal line are devices related to charging in the adapter or the USB plug equipment; the second power line and the second signal line are respectively a power line and a signal line in the USB charging line.

The interface chip comprises a first chip port and a second chip port;

the protocol chip comprises a fourth chip port, a fifth chip port and a sixth chip port, wherein the sixth chip port is used for inputting a second voltage; in the embodiment of the present application, the interface chip may be a post-stage chip related to charging, for example, the interface chip may be a charge IC in the terminal device, which is responsible for managing external power supply and charging and discharging of the battery, or the interface chip may be a post-stage chip such as a PMU, which integrates power management and charging control, which is not limited herein. Protocol chips are chips that communicate with the internal components of the adapter and with the external consumer using a communication protocol supported by the adapter.

The first power line comprises a first power port and a second power port, and the second power port is connected with the first chip port;

the third power line comprises a fourth power port and a fifth power port;

the first signal line comprises a first signal port and a second signal port, and the second signal port is connected with the second chip port;

the third signal line comprises a third signal port and a fourth signal port;

the first switch circuit comprises a first switch port, a second switch port and a third switch port, wherein the first switch port is connected with the first power supply port, the second switch port is used for receiving a conduction instruction, and the third switch port is grounded; more specifically, the first power line includes a third power port, and the voltage of the third power port is consistent with the voltage of the first power port, and the third power port is used for being connected with the first switch port.

The second switch circuit comprises a fourth switch port, a fifth switch end and a sixth switch Guan Duankou, and the fifth switch port is used for inputting control instructions;

the fourth switch port is used for inputting charging voltage, the fifth switch port is connected with the fourth chip port, the sixth switch Guan Duankou is connected with the fourth power port, the fifth power port is used for outputting first voltage based on the charging voltage, the fifth power port is used for being connected with the first power port through a second power line, and the second power line is a power line in the USB charging line; in general, in the protocol chip-side device, a second capacitance circuit for storing energy based on the charging voltage and rectifying and filtering the charging voltage is also connected between the fourth power supply port and the fifth power supply port. The first end of the second capacitor circuit is connected with a sixth power port, the sixth power port is any one port between the fourth power port and the fifth power port, and the second end of the second capacitor circuit is grounded. The first voltage is obtained after the charging voltage is rectified and filtered by the capacitor circuit. And, generally, a first capacitor circuit for performing secondary energy storage filtering on the input first voltage is further connected between the first power port and the third power port, a first end of the first capacitor circuit is communicated with the first power port and the second power port through a first power line, a second end of the first capacitor circuit is grounded, the third power port can be any one end point between a capacitor end point and the second power port, and the capacitor end point refers to an end point connected with the first end of the first capacitor circuit on the first power line.

The third signal port is connected with the fifth chip port, and the fourth signal port is used for being connected with the second signal port through a second signal wire, and the second signal wire is a signal wire in the USB charging wire.

The protocol chip is configured to receive the second voltage, and negotiate a charging voltage based on the second voltage, the first signal line, the second signal line, the third signal line, and the second chip interface and the interface chip, where the negotiation content includes but is not limited to: the initial charge voltage and/or data related to the rise and fall of the charge voltage during charging.

For example, in the second switch circuit, the fourth switch Guan Duankou and the sixth switch Guan Duankou default to the off state, and in the charging scenario, the charging process performed by the terminal device based on the circuit diagram shown in fig. 7 includes: before the fourth switch Guan Duankou is turned on with the sixth switch port, the protocol chip negotiates information related to the charging protocol with the interface chip based on the second voltage, the first signal line, the second signal line, the third signal line, and the second chip interface, and after the negotiation of the information related to the charging protocol is completed, the magnitude of the initial charging voltage and the maximum current carrying capacity of the terminal device can be obtained. After the negotiation of the charging protocol related information is completed, the protocol chip sends an on command to the second switch circuit through the fifth switch port, so that the fourth switch Guan Duankou is turned on with the sixth switch Guan Duankou, the charging voltage is short-circuited through the first switch and transmitted to the fifth switch port through the third power line, the first power port outputs a first voltage based on the charging voltage, and the first voltage is transmitted to the first chip port through the second switch port and the first power line, and at this time, the connection state of the first switch circuit is a first connection state, and the first connection state refers to disconnection between the first switch port and the third switch port. Correspondingly, the interface chip receives the first voltage through the first chip port to charge the terminal equipment.

The protocol chip is further used for monitoring the voltage of a fifth chip port, and sending an opening instruction to the fifth switch port through a fourth chip port when the voltage of the fifth chip port is larger than a preset voltage; the second switching circuit disconnects the fourth switch Guan Duankou from the sixth switch port in response to the disconnection instruction.

In some other charging protection circuits, when the power line and the signal line are in a short circuit, the adapter turns off the output of the charging voltage through the second switch circuit after detecting that the voltage of the pin of the signal line is greater than the preset voltage, and the terminal equipment side does not take other protection measures. According to the charging protection circuit, after the adapter turns off the output of the charging voltage, the charging voltage remained on the power line still flows to pins at two ends of the signal line through the signal line short-circuited with the power line according to the rule of transferring the high potential to the low potential; the voltage in the capacitor of the capacitor circuit connected to the power supply line flows to the pins at both ends of the signal line through the power supply line and the signal line short-circuited to the power supply line, and the capacitor voltage is slowly dissipated. That is, although the adapter turns off the output of the charging voltage, the signal line is still in an overvoltage/overcurrent state for a long time, and the charging protection circuit is still to be improved.

However, in the system adopting the charging protection circuit provided by the application, in the charging process, the second power line and the second signal line are in short circuit, the first voltage flows to the second chip port and the fifth chip port at two ends of the signal line through the short circuit part of the power line, so that the protocol chip at the adapter side can monitor that the voltage of the fifth chip port is greater than the preset voltage under the condition that the second chip port and the fifth chip port are in an overcurrent and overvoltage state, and the fourth switch Guan Duankou in the second switch circuit is disconnected from the sixth switch port, and the output of the first voltage is turned off. The interface chip at the terminal equipment side can also monitor that the voltage of the second chip port is larger than the preset voltage, the first switch port and the third switch port in the first switch circuit are conducted, the second power line is grounded, the first voltage remained on the second power line and the voltage stored in the capacitor branch are rapidly released through the ground wire, and therefore the aims of reducing the overvoltage and overcurrent duration of the second chip port and the fifth chip port and reducing the risk of burning related devices are achieved.

For example, after the second power line and the second signal line are shorted, the adapter turns off the output of the charging voltage based on the voltage of the fifth chip port being greater than the preset voltage, and then the terminal device switches the first switch circuit to the second connection state based on the voltage of the second chip port being greater than the preset voltage, so that the voltage of the second chip port or the fifth chip port after the short circuit can be represented by the graph shown in fig. 5.

After the terminal device grounds the first power line at time t5, the direction of the discharge current of the capacitor in the capacitor circuit is shown in fig. 8, and as can be seen from fig. 8, based on the principle that the voltages of the branches in the parallel circuit are equal, the voltage at the short-circuited position of the second power line, the voltage at the short-circuited position of the second signal line, the voltage at the fifth chip port, and the voltage at the second chip port are all equal, but the discharge currents of the first capacitor circuit and the second capacitor circuit are basically discharged from the ground line in the first switch circuit, and the discharge current does not basically flow to the fifth chip port and the second chip port. It is understood that the device burnout is mostly caused by excessive heat of excessive current or excessive voltage exceeding the voltage withstand capability of the device, and the method provided by the application is adopted. And in a short circuit state, the capacitor voltage is released based on the grounding wire, so that the overvoltage and overcurrent time of the second chip port and the fifth chip port is reduced, and the risk of burning the device is reduced.

In one possible implementation manner, the interface chip further includes a third chip interface, and is specifically configured to send the on command to the second switch port through the third chip interface when the voltage of the second chip port is greater than the preset voltage.

In other possible implementations, the device on the interface chip side in the system of the charging protection circuit further includes a system-in-chip, where a communication path exists between the system-in-chip and the interface chip. The interface chip is specifically configured to report first overvoltage information to the system-on-chip when it is determined that the voltage of the second chip port is greater than the preset voltage, where the first overvoltage information may include, for example, but not limited to, an identifier of the overvoltage port and a voltage value of an overvoltage pin. The system-on-chip is configured to send the on command to the first switch circuit in response to the first overvoltage information.

In some terminal devices, there may be the first switch circuit connected to the first power port, where the first switch circuit is configured to turn on the first switch port and the third switch port in response to an on instruction sent by the system-on-chip, for example, when the interface chip detects that the temperature of the first chip port (the second power port) is higher than a preset temperature, the interface chip reports over-temperature information to the system-on-chip, and the system-on-chip sends an on instruction to the first switch circuit after responding to the over-temperature information.

Under the premise, if the interface chip sends a conducting instruction to the first switch circuit after detecting that the voltage of the second chip port is larger than the preset voltage, the interface chip not only needs to write a control logic' which sends the conducting instruction to the first switch circuit when detecting that the voltage of the second chip port is larger than the preset voltage in the interface chip, but also needs to add the third chip port and a wire from the third chip port to the second switch port in the interface chip.

On the premise that the interface chip sends first overvoltage information to the system-level chip under the condition that the voltage of the second chip port is detected to be larger than the preset voltage, the system-level chip responds to the first overvoltage information and sends the conduction instruction to the first switch circuit, control logic for sending the first overvoltage information to the system-level chip when the voltage of the second chip port is detected to be larger than the preset voltage is only needed to be written in the interface chip, and control logic for sending the conduction instruction to the first switch circuit after the first overvoltage information is received is written in the system-level chip.

In another possible implementation manner, the protocol chip is further configured to monitor a current of a fourth power supply port, and in a case where the current of the fourth power supply port is greater than a preset current, the protocol chip sends an off command to a fifth switch port through the fourth chip port, where the fifth switch port is configured to disconnect the fourth switch Guan Duankou from the sixth switch port in response to the off command.

The interface chip at the terminal device side firstly sets the first switch circuit to a second connection state after the second power line and the second signal line are shorted, at this time, the protocol chip does not send an off command to the second switch circuit yet, the charging voltage is released through the second power line and the first power line, the current of the fourth power port is rapidly increased, thereby triggering an overcurrent protection mechanism in the protocol chip. The preset current is determined according to the working current of the power line, the preset current is greater than the working current of the power line, and the working current of the power line is determined according to specific charging voltage, device impedance and specific value conditions of line impedance, which are not limited herein. As shown in fig. 9, after the short circuit, the current of the fourth power port is short-circuited at time t1, and after the short circuit, the charging voltage is released through the first chip port, the second chip port and the fourth chip port, the parallel resistance increases, the total line resistance decreases, and the current of the fourth power port increases. At time t5, the first switch circuit turns on the first switch port and the third switch port, the charging voltage is released through the first switch circuit in a grounding way, and after t5, the current of the fourth power supply port is rapidly increased, so that the output of the charging voltage is obtained by triggering the protocol chip to turn off at time t 7. After t7, the capacitor voltage is rapidly released through the first switch circuit to ground, the current of the fourth power port rapidly drops, and the time difference between t1, t5, t7 and t8 is much less than 180ms.

It should be noted that, in the short-circuit scenario, in the system of such a charge protection circuit in which the voltage of the first chip port is greater than the preset voltage, the on command is sent to the second switch port of the first switch circuit based on the interface chip or the system-level chip, and in the case that the first switch port and the third switch port in the first switch circuit are turned on and the current of the fourth power port is greater than the preset current, the protocol chip sends the off command to the second switch circuit, the current on the power line may occur in a short time before the second switch circuit turns off the output of the charge voltage (for example, during the period of t5 to t7 described above), and such a charge protection scheme requires that the instantaneous current that the first switch circuit can withstand is high and relatively high temperature.

In the system of the charging protection circuit provided by the application, the protocol chip is used for sending an off instruction to the fifth switch port in the second switch circuit under the condition that the voltage of the fifth chip port is monitored to be larger than the preset voltage; and the protocol chip is used for sending a disconnection instruction to the fifth switch port in the second switch circuit when the current of the fourth power port is detected to be larger than the preset current, or the protocol chip can have both the functions, or one of the two functions, which is not limited herein.

In connection with the above description of the system of the charge protection circuit, the present application may also be understood as providing some charge protection schemes that mainly comprise two parts, one part being: after the short circuit phenomenon occurs between the power line and the signal line, the terminal device side can ground the power line, and the power line conducts the charging voltage and the discharging voltage in the capacitor circuit through the ground. The other part is: after the power line and the signal line are short-circuited, the adapter side can shut off the output of the charging voltage. Based on this, as shown in fig. 10, four charging protection schemes that can be implemented by using the charging protection circuit provided by the embodiment of the present application may be provided in the following modes 1 to 4.

Wherein, mode 1 is: the ground switch of the power supply line is enabled by the interface chip on the terminal device side so that the power supply line (Vbus) is grounded and the adapter actively turns off the output of the charging voltage. Specific means for enabling the ground switch of the power line and the output of the charging voltage to be actively turned off by the adapter with respect to the interface chip on the terminal device side can be referred to the system circuit diagram shown in fig. 7 and the related description in the charging protection method shown in fig. 11, and will not be described in detail herein.

Mode 2 is: the interface chip at the terminal device side enables the ground switch of the power line so that the power line is grounded and the adapter passively turns off the output of the charging voltage. Specific means for passively turning off the output of the charging voltage by the adapter may refer to the system circuit diagram shown in fig. 7 and the related description of the charging protection method shown in fig. 11, and will not be described in detail herein.

The mode 3 is as follows: the ground switch of the power line is enabled by the terminal device side system-in-chip so that the power line is grounded and the adapter actively turns off the output of the charging voltage. The specific means for enabling the ground switch of the power line by the system on the terminal device side can be referred to the circuit diagram shown in fig. 7 and the related description in the charge protection method shown in fig. 12, and will not be described in detail herein.

Mode 4 is: the ground switch of the power line is enabled by the terminal device side system on chip so that the power line is grounded and the adapter passively turns off the output of the charging voltage.

The charge protection method of the above-described modes 1 and 3 will be described below with reference to a circuit diagram of a system in which the charge protection circuit shown in fig. 7 is multiplexed and the charge protection method shown in fig. 11. As shown in fig. 11, the method includes:

S1101, the terminal device is in a charged state based on the adapter and the USB charging line.

Specifically, as shown in fig. 7, after the fourth switch Guan Duankou and the sixth switch Guan Duankou in the second switch circuit are turned on, the charging voltage is transmitted to the fourth power supply port of the third power supply line in the adapter, and after the first voltage is stored and filtered by the first capacitor circuit, the first voltage is output from the fourth power supply port of the third power supply line, and the first voltage is transmitted to the terminal device through the third power supply line, the second power supply line, and the second capacitor circuit, so that the terminal device is charged based on the first voltage.

S1102, the power supply line and the signal line in the USB charging line are shorted.

In fig. 7, the occurrence of a short circuit between the power line and the signal line in the USB charging line is represented by the second power line being connected to the second signal line.

In the embodiment of the present application, the signal line may refer to a USB data positive signal line d+, a USB data negative signal line D-, an ac charging confirmation signal line CC (including CC1 and CC 2), or an auxiliary signal line SBU (including SBU1 and SBU 2), which is not limited herein.

S1103, the protocol chip of the adapter monitors that the voltage of the chip port corresponding to the signal line on the protocol chip is larger than the preset voltage.

The chip port on the protocol chip corresponding to the signal line is the fifth chip port in fig. 7. For example, the protocol chip monitors the voltage of the second chip port in real time, e.g., periodically obtains the voltage of the second chip port, if it is determined that the adapter is in a charged state (e.g., the protocol chip determines that the first end of the second switch circuit receives an input of the charging voltage). Generally, the protocol chip has a function of detecting the voltage of the fifth chip port by default.

The second power line is connected to the second signal line, and the first voltage output from the fifth power port is transmitted to the fifth chip port and the second chip port through the second power line and the second signal line, so that the voltage of the fifth chip port is greater than the preset voltage. For example, reference may be made to the flow direction of the current related to the first voltage after the second power line is shorted with the second signal line as shown in fig. 3 or fig. 4.

The description of the preset voltage may be referred to the related description of other embodiments herein and will not be described in detail herein.

S1104, the protocol chip turns off the output of the charging voltage.

Wherein the output of the adapter off charging voltage is embodied in fig. 7 as disconnecting the fourth switch Guan Duankou in the second switching circuit from the sixth switching port. Specifically, the protocol chip sends a disconnection instruction to the fifth switch port in the second switch circuit when it is determined that the voltage at which the fifth chip is disconnected is greater than the preset voltage, and the second switch circuit disconnects the connection between the fourth switch Guan Duankou and the sixth switch port in response to the disconnection instruction.

It can be appreciated that after the output of the charging voltage is turned off, the voltage of the second power line is rapidly reduced to the working voltage of the first chip port, so that the on state between the first power line and the first chip port is changed to the open state, and if the following step S1106 is not performed, the voltage stored in the capacitor circuit in the adapter is slowly dissipated, and the voltages of the fourth chip port and the second chip port are continuously in the overvoltage and overcurrent state for a long period of time.

For example, referring to fig. 2, after the adapter turns off the output of the charging voltage at time t2, the voltage of the first power port drops rapidly to the working voltage of the interface chip to stop charging in the period of t2-t3, and the voltage in the capacitor circuit slowly dissipates in the period of t3-t4, and the voltage of the first power port, the second chip port, or the fourth chip port drops slowly to 0.

In step S1104, the output of the protocol chip off charging voltage refers to the output of the protocol chip active off charging voltage in the adapter, the 'active off' refers to the control logic that sends the off command to the second switch circuit when the voltage of the fourth chip port acquired in the charging process is greater than the preset voltage written in the protocol chip, based on which the output of the charging voltage is turned off directly based on the voltage of the fourth chip port corresponding to the signal line being greater than the preset voltage in the short circuit scenario, and the 'passive off' refers to the ground switch connected with the power line in step S1106 or S1108 being turned on (i.e. the first switch port and the third switch port in the first switch circuit are turned on), and the current of the power line is rapidly raised to trigger the original overcurrent protection mechanism in the protocol chip to turn off the output of the charging voltage.

S1105, an interface chip in the terminal equipment monitors that the voltage of a chip port corresponding to the signal line on the interface chip is larger than a preset voltage.

The chip port on the interface chip corresponding to the signal line is the second chip port in fig. 7. The interface chip may monitor the voltage of the second chip port in real time, e.g., periodically obtain the voltage of the second chip port, if it is determined that the terminal device is in a charged state (e.g., the interface chip determines that the first chip port receives the input of the first voltage). Generally, the interface chip has a function of detecting the voltage of the second chip port by default.

The second power line is connected to the second signal line, and the first voltage output from the fifth power port is transmitted to the fifth chip port and the second chip port through the second power line and the second signal line, so that the voltage of the second chip port is greater than the preset voltage.

S1106, the interface chip enables the ground switch in communication with the USB power line to conduct.

The interface chip enables the grounding switch communicated with the USB power line to be conducted, wherein the connection of the grounding switch in the interface chip enables the first switch port and the third switch port in the first switch circuit to be conducted. Specifically, the interface chip sends a conduction instruction to the second switch port in the first switch circuit through the third chip port under the condition that the voltage of the second chip port is larger than the preset voltage, and the first switch circuit responds to the conduction instruction to conduct the first switch port and the third switch port.

In the present application, the above S1103 and S1105 may be executed simultaneously or sequentially, which is not limited herein.

In another possible implementation manner, the conduction between the first switch port and the third switch port in the first switch circuit may be controlled by a system-on-chip, which is not limited herein. Illustratively, following step S1105, the following steps S1107-S1108 are performed.

It can be understood that based on the charging protection methods of S1103-S1104 and S1105-S1106 (i.e., mode 1), the interface chip immediately sends a turn-on instruction to the second switch port after detecting that the voltage of the second chip port is greater than the preset voltage, instead of sending the turn-on instruction to the second switch port from the system-in-chip through reporting the system-in-chip, so as to reduce the program response time to a certain extent; the protocol chip immediately turns off the output of the charging voltage after detecting that the voltage of the fifth chip port is larger than the preset voltage, but does not wait for the first switch port to be conducted with the third switch port, and then triggers the overcurrent protection to passively turn off the output of the charging voltage, so that the response time of the program is further reduced. Therefore, the duration of overvoltage and overcurrent of chip interfaces at two ends of the signal line after short circuit can be further reduced, and the risk of burning out the device is further reduced.

S1107, the interface chip sends first overvoltage information to the system-in-chip.

The first overvoltage information is used for indicating that the voltage of the second chip port is larger than a preset voltage, and can be also understood as that the second power line and the second signal line are in short circuit.

S1108, the system-in-chip controls the connection of a grounding switch communicated with the USB power line.

The interface chip controls the connection of a grounding switch communicated with the USB power line to connect the first switch port and the third switch port in the first switch circuit. Specifically, after the system-in-chip receives the first overvoltage phenomenon, a conduction instruction is sent to a second switch port in the first switch circuit through a sixth chip port, and the first switch circuit responds to the conduction instruction to conduct the first switch port and the third switch port.

It can be understood that, when the system-in-chip at the terminal device side originally supports sending the on command to the second switch port, based on the charging protection method (i.e. mode 3) of S1103-S1104 and S1107-S1108, the system-in-chip sends the on command to the second switch port based on the first overvoltage information instead of sending the on command to the second switch port by the interface chip, and no additional hardware module related to sending the on command from the interface chip to the second switch port is required, so that the problem of long-time over-current overvoltage on the signal line short-circuited with the power line is improved, and meanwhile, the hardware cost can be further saved.

S1109, the system-on-chip records an overpressure event based on the first overpressure information.

S1110, the voltage of the USB power line and the chip ports correspondingly connected with the two ends of the USB power line is reduced to 0.

Specifically, after step S1106 or after step S1108, the voltages at the second and fourth chip ports may be reduced to 0.

For example, referring to fig. 6, after the adapter turns off the output of the charging voltage at time t2, the interface chip connects the USB power line to ground at time t5, and the voltage in the capacitor circuit is rapidly released in the period of time t5-t6, and the voltage of the first power port, the second chip port, or the fourth chip port is rapidly reduced to 0. Wherein t5 may be earlier, later, or equal to t3 in fig. 2, which is not limited herein.

The charge protection method of modes 2 and 4 described above will be described below with reference to the circuit diagram of the charge protection system shown in fig. 7 and the charge protection method shown in fig. 12. As shown in fig. 12, the method includes:

s1201, the terminal device is in a charged state based on the adapter and the USB charging line.

S1202, the power supply line and the signal line in the USB charging line are short-circuited.

S1203, an interface chip in the terminal device monitors that the voltage of the chip port corresponding to the signal line on the interface chip is greater than a preset voltage.

In fig. 7, the voltage of the chip port corresponding to the signal line on the interface chip is greater than the preset voltage, which is shown in fig. 7 as that the voltage of the second chip port is greater than the preset voltage.

S1204, the interface chip enables a grounding switch communicated with the USB power line to be conducted.

The interface chip enables the grounding switch communicated with the USB power line to be conducted, wherein the connection of the grounding switch in the interface chip enables the first switch port and the third switch port in the first switch circuit to be conducted.

In another possible implementation manner, the conduction between the first switch port and the third switch port in the first switch circuit may be controlled by a system-on-chip, which is not limited herein. Illustratively, following step S1203, the following steps S1204-S1206 are performed.

In the application, after the interface chip detects that the voltage of the second chip port is greater than the preset voltage, the interface chip directly sends the on instruction to the second switch port, so that the program response time can be reduced to a certain extent, the time of overvoltage and overcurrent of the chip interfaces at two ends of the signal line after short circuit can be further reduced, and the risk of burning devices is further reduced.

S1205, the interface chip sends the first overpressure information to the system-in-chip.

S1206, the system-in-chip controls the conduction of a grounding switch communicated with the USB power line.

The interface chip controls the connection of a grounding switch communicated with the USB power line to connect the first switch port and the third switch port in the first switch circuit.

In the application, the system-level chip sends the conducting instruction to the second switch port based on the first overvoltage information, and the related hardware module for sending the conducting instruction to the second switch port from the interface chip is not required to be additionally added, so that the problem of long-time overcurrent and overvoltage on the signal line short-circuited with the power line can be solved, and the hardware cost can be further saved.

S1207, the system on chip records an overvoltage event based on the first overvoltage information.

After S1204 or S1206, the system on chip performs step S1208.

S1208, after the protocol chip in the adapter monitors that the current of the power line in the USB charging line is greater than the preset current, the output of the charging voltage is turned off.

After the second power line and the second signal line are shorted, the interface chip at the terminal device side firstly sets the first switch circuit to be in a second connection state, the charging voltage is released through the second power line and the first power line in a grounding way, and the current of the fourth power port is rapidly increased, so that an overcurrent protection mechanism in the protocol chip is triggered, and the output of the charging voltage is turned off.

In the application, after the first switch port and the third switch port are conducted, the current of the fourth power port is rapidly increased, and the adapter is triggered to passively turn off the output of the charging voltage. In this charging protection method, the current on the first switch circuit may generate a phenomenon that the current is larger in a shorter time (specifically, in a period of time after the first switch port and the third switch port are turned on and the adapter does not turn off the output of the charging voltage), which requires that the instantaneous current that the first switch circuit can withstand is higher and relatively higher temperature.

S1209, the voltage of the USB power line and the chip ports correspondingly connected with the two ends of the USB power line is reduced to 0.

For example, multiplexing fig. 9, a short circuit occurs at time t1, the first switch circuit turns on the first switch port and the third switch port at time t5, the charging voltage is released through the first switch circuit to ground, and after t5, the current of the fourth power supply port increases sharply, so that the output of the charging voltage is turned off by the trigger protocol chip at time t 7. After t7, the capacitor voltage is rapidly released through the first switch circuit to ground, the current of the fourth power port rapidly drops, and the time difference between t1, t5, t7 and t8 is much less than 180ms. The t5 may be earlier, later, or equal to t3 in fig. 2, which is not limited herein.

In other possible implementations, in the charging protection methods corresponding to the foregoing implementations 1 to 4, the adapter may also support both active shutdown and passive shutdown of the output of the charging voltage, and select whether to shut down the output of the charging voltage by active shutdown or passive shutdown according to the timing of triggering the active shutdown and passive shutdown of the adapter in the actual scenario.

As used in the above embodiments, the term "when …" may be interpreted to mean "if …" or "after …" or "in response to determination …" or "in response to detection …" depending on the context. Similarly, the phrase "at the time of determination …" or "if detected (a stated condition or event)" may be interpreted to mean "if determined …" or "in response to determination …" or "at the time of detection (a stated condition or event)" or "in response to detection (a stated condition or event)" depending on the context.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk), etc.

Those of ordinary skill in the art will appreciate that implementing all or part of the above-described method embodiments may be accomplished by a computer program to instruct related hardware, the program may be stored in a computer readable storage medium, and the program may include the above-described method embodiments when executed. And the aforementioned storage medium includes: ROM or random access memory RAM, magnetic or optical disk, etc.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. An electronic device, the electronic device comprising:

the interface chip, the first power line, the first signal line and the first switch circuit;

the interface chip comprises a first chip port and a second chip port; the first power line comprises a first power port and a second power port, the electronic equipment is used for receiving a first voltage input by external equipment through the first power port, and the second power port is used for being connected with the first chip port;

The first signal line comprises a first signal port and a second signal port, the electronic device is used for receiving a second voltage input by external equipment through the first signal port, the second signal port is used for being connected with the second chip port, and the second voltage is smaller than the first voltage;

the first switch circuit comprises a first switch port, a second switch port and a third switch port, the first switch port is used for being connected with the first power supply port, the electronic equipment is used for controlling the first switch circuit to receive an on instruction or an off instruction through the second switch port so as to change the connection state of the first switch port and the third switch port, and the third switch port is used for being grounded;

when the voltage of the first chip port is equal to the first voltage and the voltage of the second chip port is equal to the second voltage, the electronic device is used for controlling the first switch circuit to disconnect the connection between the first switch port and the third switch port, controlling the interface chip to carry out negotiation work about the value change of the first voltage through the second voltage and an external voltage output device, and charging the electronic device through the first voltage;

And under the condition that the voltage of the second chip port is larger than a preset voltage, the electronic equipment is used for controlling the first switch circuit to receive a conduction instruction through the second switch port, and is also used for controlling the first switch circuit to conduct the first switch port and the third switch port in response to the conduction instruction so as to release the first voltage in a mode that the first power port is grounded, and the preset voltage is larger than or equal to the second voltage and smaller than the first voltage.

2. The electronic device of claim 1, wherein the charge protection circuit further comprises a second power line and a second signal line,

the first end of the second power line is used for inputting the first voltage, and the second end of the second power line is used for being connected with the first power port;

the first end of the second signal line is used for inputting the second voltage, and the second end of the second signal line is used for being connected with the first signal port;

under the condition that abnormal conduction does not occur between the second power line and the second signal line, the voltage of the first chip port is equal to the first voltage;

And under the condition that the second power line and the second signal line are abnormally conducted, the first voltage is transmitted to the second chip port, and the voltage of the second chip port is larger than the preset voltage.

3. The electronic device of claim 2, wherein the first end of the second power line is adapted to be connected to a voltage output device, the second power line is further adapted to be connected to a capacitive circuit,

under the condition that the second power line and the second signal line are not abnormally conducted, or under the condition that the second power line and the second signal line are abnormally conducted and the voltage output equipment still outputs the first voltage to the first end of the second power line based on the charging voltage, the first voltage is output by the capacitor circuit after energy storage and filtering based on the charging voltage;

and under the condition that the second power line and the second signal line are abnormally conducted, and the voltage output equipment does not output the first voltage to the first end of the second power line based on the charging voltage, the first voltage is a capacitor voltage generated by releasing stored electric energy by the capacitor circuit.

4. The electronic device of claim 3, wherein the electronic device comprises a memory,

in the case where abnormal conduction occurs between the second power supply line and the second signal line, the voltage output device no longer outputs the first voltage to the first end of the second power supply line based on the charging voltage, and the first switch port is disconnected from the third switch port, the capacitance circuit continuously releases the capacitance voltage through the second chip port, and the voltage and current of the second chip port decrease to 0 in a first period;

under the condition that the second power line and the second signal line are abnormally conducted, the voltage output device does not output the first voltage to the first end of the second power line based on the charging voltage, and the first switch port and the third switch port are conducted, the capacitor circuit discharges the voltage stored in the capacitor circuit through the second power line and the first power line in a grounding manner, in the capacitor voltage discharging process, the voltage of the second chip port is equal to the discharging voltage, the current flowing into the second chip port is smaller than the current flowing into the first switch port, the voltage and the current of the second chip port are rapidly reduced to 0 in a second duration, and the second duration is smaller than the first duration.

5. The electronic device of any of claims 1-4, wherein the interface chip further comprises a third chip port for connecting with the second switch port;

and under the condition that the voltage transmitted to the second chip port is larger than the preset voltage, the electronic equipment is specifically used for controlling the interface chip to send the conduction instruction to the second switch port through the third chip port.

6. The electronic device of any of claims 1-4, wherein the electronic device further comprises a system-on-chip connected with the interface chip;

the electronic device is specifically configured to control the interface chip to send first overvoltage information to the system-in-chip when the voltage transmitted to the second chip port is greater than the preset voltage, where the first overvoltage information is used to indicate that the voltage of the second chip port is greater than the preset voltage;

the electronic device is further used for controlling the system-on-chip to send the conducting instruction to the second switch port in response to the first overvoltage information.

7. The electronic device of any of claims 1-4, wherein the electronic device further comprises a system-on-chip connected with the interface chip;

And under the condition that the first switch port is conducted with the third switch port and the voltage of the first power supply port is 0, the electronic equipment is further used for controlling the system-in-chip or the interface chip to send an opening instruction to the first switch circuit, and the electronic equipment is further used for controlling the first switch circuit to respond to the opening instruction and disconnect the connection between the first switch port and the third switch port.

8. The electronic device of any of claims 1-4, further comprising a system-on-chip connected to the interface chip,

the electronic equipment is used for controlling the system-level chip to record an overvoltage event based on first overvoltage information, the first overvoltage information is used for indicating that the voltage of the second chip port is larger than the preset voltage, and the first overvoltage information is used for controlling the electronic equipment to control the interface chip to send the interface chip to the system-level chip.

9. The electronic device of any of claims 1-4, wherein the first signal line is a USB data positive signal line d+, a USB data negative signal line D-, an ac charge confirmation signal line CC, or an auxiliary signal line SBU.

10. A system of a charging protection circuit is characterized in that the system of the charging protection circuit comprises an electronic device and an adapter,

the electronic device includes: the interface chip, the first power line, the first signal line and the first switch circuit;

the interface chip comprises a first chip port and a second chip port;

the first power line comprises a first power port and a second power port, the electronic equipment is used for receiving the input of a first voltage through the first power port, and the second power port is used for being connected with the first chip port;

the first signal line comprises a first signal port and a second signal port, the electronic equipment is used for receiving the input of a second voltage through the first signal port, the second signal port is connected with the second chip port, and the second voltage is smaller than the first voltage;

the first switch circuit comprises a first switch port, a second switch port and a third switch port, the first switch port is connected with the first power port, the electronic equipment is used for controlling the first switch circuit to receive an on instruction or an off instruction through the second switch port so as to change the connection state of the first switch port and the third switch port, and the third switch port is used for being grounded;

The adapter includes: the protocol chip, the second switch circuit, the third power line and the third signal line;

the protocol chip comprises a fourth chip port and a fifth chip port;

the third power line comprises a fourth power port and a fifth power port;

the third signal line comprises a third signal port and a fourth signal port;

the second switch circuit comprises a fourth switch port, a fifth switch port and a sixth switch Guan Duankou, and the adapter is used for controlling the second switch circuit to receive an on instruction or an off instruction through the fifth switch port so as to change the connection state between the fourth switch port and the sixth switch port;

the adapter is used for receiving the input of charging voltage through the fourth switch port, the fifth switch port is connected with the fourth chip port, the sixth switch port is connected with the fourth power port, the fifth power port is used for being connected with the first power port, the adapter is also used for outputting the first voltage through the fifth power port, and the first voltage is obtained based on the charging voltage and a related capacitance circuit;

The adapter is used for receiving the input of the second voltage through the third signal port, the third signal port is connected with the fifth chip port, the fourth signal port is used for being connected with the second signal port, the adapter is also used for outputting the second voltage through the fourth signal port, and the second voltage is smaller than the first voltage;

when the voltage of the first chip port is equal to the first voltage and the voltage of the second chip port is equal to the second voltage, the electronic device is used for controlling the first switch circuit to disconnect the connection between the first switch port and the third switch port, controlling the interface chip to carry out negotiation work about the value of the first voltage through the second voltage and an external voltage output device, and charging the electronic device through the first voltage;

the adapter is used for controlling the second switching circuit to receive an opening instruction based on the fifth switching port and controlling the second switching circuit to disconnect the connection between the fourth switching port and the sixth switching port in response to the opening instruction so as to cut off the output of the charging voltage under the condition that the voltage of the fifth chip port is larger than a preset voltage or the current of the fourth power port is larger than a preset current;

11. The system of claim 10, further comprising a second power line and a second signal line,

the first end of the second power line is connected with the fifth power port, and the second end of the second power line is connected with the first power port;

the first end of the second signal line is used for being connected with the fourth signal port, and the second end of the second signal line is used for being connected with the first signal port;

in the case that the second power line and the second signal line are not abnormally conducted, the voltage of the first chip port is equal to the first voltage, and the voltage of the second chip port and the voltage of the fifth chip port are equal to the second voltage;

Transmitting the first voltage to the second chip port and the fifth chip port under the condition that the second power line and the second signal line are abnormally conducted, wherein the voltage of the second chip port and the voltage of the fifth chip port are larger than the preset voltage;

and under the conditions that the second power line and the second signal line are abnormally conducted, the fourth switch port and the sixth switch Guan Duankou are conducted, and the first switch port and the third switch port are conducted, the current of the fourth power port is larger than the preset current.

12. The system according to claim 10 or 11, wherein the adapter is specifically configured to control the protocol chip to send the disconnection instruction to the fifth switch port through the fourth chip port if the voltage of the fifth chip port is greater than the preset voltage.

13. The system according to claim 10 or 11, wherein the adapter is specifically configured to control the protocol chip to send the disconnection instruction to the fifth switch port through the fourth chip port when the current of the fourth power port is greater than the preset current.

14. The system of any of claims 10-13, wherein the interface chip further comprises a third chip port for connection with the second switch port,

the electronic device is specifically configured to control the interface chip to send the on instruction to the second switch port through the third chip port when the voltage transmitted to the second chip port is greater than the preset voltage.

15. The system of any of claims 10-13, wherein the electronic device further comprises a system-on-chip connected with the interface chip;

the electronic device is further used for controlling the system-on-chip to respond to the first overvoltage information and send the conducting instruction to the second switch port, and recording an overvoltage event based on the first overvoltage information.