CN117149680A - Main control board for uploading sub-module log of chip mounter and uploading method - Google Patents
Main control board for uploading sub-module log of chip mounter and uploading method Download PDFInfo
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- CN117149680A CN117149680A CN202311402311.6A CN202311402311A CN117149680A CN 117149680 A CN117149680 A CN 117149680A CN 202311402311 A CN202311402311 A CN 202311402311A CN 117149680 A CN117149680 A CN 117149680A
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- 238000004891 communication Methods 0.000 claims abstract description 32
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- 238000009825 accumulation Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
- H05K13/08—Monitoring manufacture of assemblages
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
- G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The invention relates to the technical field of communication, and particularly discloses a main control board and an uploading method for uploading logs of a sub-module of a chip mounter, wherein the main control board is used for actively transmitting the logs to a host computer through DMA (direct memory access) communication and comprises the following steps: the log data caching module is used for receiving and caching log data from the chip mounter sub-module; and the DMA data transmitting module is used for uploading the log data of the log data caching module to the upper computer. The method adopts a DMA communication mode, can actively carry out DMA communication by the FPGA on the main control board, stores the log data of the submodule in an address space agreed with the host computer, automatically generates the log data by the internal of the main control board FPGA, carries out DMA communication by the internal DMA controller, does not need the participation of the host computer, can reduce the utilization rate of the CPU, simultaneously uploads the log data in real time, and saves the logic resources of the main control board FPGA.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a main control board and an uploading method for uploading sub-module logs of a chip mounter.
Background
The SMT chip mounter is high-precision automatic equipment integrating light, electricity, gas and machinery. The control system usually adopts a two-stage control system, wherein the upper computer system mainly adopts a PC to realize programming and man-machine interface, and the lower computer system usually adopts a special industrial control computer system and an FPGA control card to control mechanical movement. The main control board is a core component of the lower computer system and is used for transmitting the motion command and other control commands issued by the upper computer to all the chip mounter sub-modules, and uploading the motion state information of the chip mounter sub-modules, the state information of each sensor and the execution condition of the commands issued by the upper computer.
The state information of each sub-module of the chip mounter needs to be uploaded to the sub-module of the upper computer, the issuing and executing conditions of the upper computer instruction and the like are fed back, the information is collectively called a sub-module log, and the existing communication mode between the upper computer and the main control board is that a PCIe bar register is read and written, namely, the upper computer actively reads and writes the bar register in the main control board. The main control board is a PCIe slave machine and cannot actively communicate with the upper computer. The upper computer reads the log used for accessing the sub-module in a fixed time interval in a polling mode, and the higher the polling rate of the upper computer is, the higher the CPU utilization rate is. And because the log information can not be uploaded in real time, the data caching logic is also required to cache the log information on the main control board. The slower the polling rate of the upper computer is, the larger the data size of the log information which needs to be cached by the main control board is. The more master control board logic resources that the data caching logic needs to consume. Therefore, the existing log uploading mode has fundamental contradiction: the higher the polling speed of the upper computer is, the higher the utilization rate of the CPU is, and the lower the polling speed of the upper computer is, the more logic resources are consumed by the FPGA on the main control board. Along with the continuous richness of chip mounter function, the performance improves, and the log information data volume that each submodule produced also becomes larger and larger, and the drawback of original log uploading mode also shows increasingly.
Disclosure of Invention
The invention aims to overcome the problems in the prior art, and provides a main control board and an uploading method for uploading sub-module logs of a chip mounter, which can solve the contradiction that CPU (central processing unit) utilization rate is reduced and FPGA (field programmable gate array) logic resources are saved, and log data is transmitted to an active upper computer in a mode of controlling DMA (direct memory access) communication by the main control board, so that the purposes of reducing the upper computer CPU utilization rate and reducing logic resources consumed by passcodes on the main control board logs are achieved.
In order to achieve the above object, a first aspect of the present invention provides a main control board for uploading logs of a sub-module of a chip mounter, where the main control board is configured to actively transmit the logs to a host computer through DMA communication, and the main control board includes:
the log data caching module is used for receiving and caching log data from the chip mounter sub-module;
and the DMA data transmitting module is used for uploading the log data of the log data caching module to the upper computer.
Preferably, the method further comprises:
the descriptor generating module is used for determining the target address and the cache capacity of the upper computer, which are used for sending the log data to the log data caching module, and sending filling information to the log data caching module after the cache capacity is fully written;
and the interrupt generating module is used for sending an interrupt signal to inform the upper computer to read the cached log data after receiving the filling information from the log data caching module.
Preferably, the log data are ordered according to the priority order, and the log data with high priority are written into the memory of the log data cache module; writing the log data with low priority into a log buffer area of the log data buffer module, and writing the log data with high priority into the memory after the log data with high priority is written.
Preferably, the descriptor generating module is configured to determine that the sending, by the log data caching module, the log data to the target cache address of the upper computer is specifically:
after the memory is fully written, the log data buffer module sends a fifo full flag bit to the descriptor generating module, the descriptor generating module determines a target address of the log data received by the upper computer each time, and the log data buffer module sends the log data to the target address through the DMA data sending module.
Preferably, the target address= (log uploading frequency-1) ×n+ is the first address of the upper computer buffer, where N is the number of bytes of log data buffered in the memory, and the first address of the upper computer buffer is issued to the descriptor generating module by the upper computer.
Preferably, the method is also used for checking whether the upper computer finishes log reading before uploading the log data to the upper computer every time, and if not, reporting errors.
Preferably, the log data caching module is communicated with the chip mounter sub-module through the 485 module to receive log data.
The second aspect of the present invention provides a method for uploading a sub-module log of a chip mounter, comprising the steps of:
the main control board of the chip mounter receives and caches log data of the sub-modules;
and the main control board uploads the log data to the upper computer through DMA communication.
Preferably, the main control board uploads the log data to the upper computer through DMA communication comprises the following steps:
writing the log data with high priority into a memory, writing the log data with low priority into a log buffer area, and writing the log data with high priority into the memory after the log data with high priority are written;
after the memory is fully written, determining a target address of log data received by the upper computer each time, and transmitting the log data to the target address through the DMA communication, wherein the target address= (log uploading frequency-1) x N+ is the first address of a cache area of the upper computer, N is the byte number of the log data cached by the memory, and the first address of the cache area of the upper computer is issued to the descriptor generating module by the upper computer;
after the cache capacity of the upper computer is determined to be full, an interrupt signal is sent to inform the upper computer to read the cached log data.
Preferably, the method further comprises checking whether the upper computer finishes log reading before uploading the log data to the upper computer every time, and if not, reporting an error.
Through the technical scheme, the FPGA on the main control board can actively carry out DMA communication in a DMA communication mode, sub-module log data are stored in an address space appointed by the host computer, the process is automatically generated inside the main control board FPGA, the DMA communication is carried out through an internal DMA controller, participation of the host computer is not needed, the utilization rate of a CPU can be reduced, meanwhile, log data are uploaded in real time, and logic resources of the main control board FPGA are saved.
Drawings
FIG. 1 is a logic diagram of log uploading function of a main control board of the present invention;
FIG. 2 is a sub-module log packet content of an embodiment of the present invention;
FIG. 3 is a functional schematic diagram of a log data caching module according to an embodiment of the present invention;
FIG. 4 is a functional schematic diagram of a descriptor generating module according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a DMA data transmission module according to an embodiment of the present invention.
Detailed Description
The following describes the detailed implementation of the embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
The embodiment of the invention provides a main control board for uploading logs of a sub-module of a chip mounter, which is used for actively transmitting the logs to a host computer through DMA communication, and is exemplarily based on XDMA IP provided by an Xilinx K7 series FPGA and used for performing DMA communication with a PCIe host. The IP includes a descriptor control module, which supports the assembly and active loading of descriptors in the FPGA, and can implement more flexible DMA control, as shown in fig. 1, including:
the log data caching module is used for receiving and caching log data from the chip mounter sub-module;
and the DMA data transmitting module is used for uploading the log data of the log data caching module to the upper computer.
Further, the log data caching module is communicated with the chip mounter sub-module through the 485 module to receive log data; the main control board is communicated with the upper computer through PCIe TX/RX.
The sub-module is communicated with the main control board through a 485 interface. And (3) summarizing log data of all sub-modules of the chip mounter to a log data caching module, and performing data splicing and caching. The log data format is shown in fig. 2 as follows: the log data is 496 bits, both ends of the log data are respectively provided with a packet header and a packet tail, the packet header length is 8 bits of a byte and is used for representing the number of the sub-module, and the number range of the sub-module is 0-255. The packet tail is a data check bit, and an 8-bit CRC check code is adopted for checking whether the log data are correct or not by the upper computer.
In another embodiment of the present invention, as shown in fig. 1, the main control board further includes:
the descriptor generating module is used for determining the target address and the cache capacity of the upper computer, which are used for sending the log data to the log data caching module, and sending filling information to the log data caching module after the cache capacity is fully written;
and the interrupt generating module is used for sending an interrupt signal to inform the upper computer to read the cached log data after receiving the filling information from the log data caching module.
By adopting a DMA communication mode, the FPGA on the main control board can actively carry out DMA communication, and the sub-module log is stored in an address space agreed with the upper computer. In the process, descriptors are automatically generated in the main control board FPGA, and DMA communication is carried out through the DMA controller, so that the participation of an upper computer is not needed, and the utilization rate of a CPU can be reduced. The log data can be uploaded in real time, and logic resources of a main control board FPGA are saved.
Further, the descriptor generating module is configured to determine that the sending, by the log data caching module, the log data to the target cache address of the upper computer is specifically: after the memory is fully written, the log data caching module sends a fifo full flag bit to the descriptor generating module, the descriptor generating module determines a target address of the log data received by the upper computer each time, and the log data caching module sends the log data to the target address through the DMA data sending module; and the target address= (log uploading frequency-1) multiplied by N+ is the first address of the upper computer buffer zone, wherein N is the byte number of the log data buffered by the memory, and the first address of the upper computer buffer zone is issued to the descriptor generating module by the upper computer.
As shown in fig. 1, after fifo is full, the log data buffer module sends fifo full flag bits to the descriptor generating module. As shown in fig. 3, the descriptor generating module stores the first address of the target buffer area and the address capacity parameter of the target buffer area issued by the host computer, where the buffer area is a memory area of the host computer, and the capacity of the buffer area must be a multiple of the number of bytes of log data buffered by the storage, and the unit of the capacity of the buffer area is that the bytes of log data buffered by Fifo is 4Kb, that is, 512 bytes. After receiving the fifo full flag bit, the descriptor generating module generates a descriptor, and loads the descriptor into the XDMA IP, wherein the descriptor comprises a data length and a data transmission target address, the data length of single data transmission is fixed to 64 bytes, the first target address is the first address of a target cache address, and the following target address calculating mode is as follows:
target address= (log uploading frequency-1) ×512+ upper computer buffer area head address
And meanwhile, the log data caching module sends the log data to the XDMA IP according to an AXI-Stream protocol, and finally the log data is uploaded to an upper computer through a PCIe interface. The journal data of Fifo buffer is 4Kb, i.e. 512 bytes, so the target address in the descriptor generating module will be increased 512 from the target buffer head address after each uploading of journal data. The number of writable times of the target cache area is as follows:
writable times = buffer size/512
When the target cache address allocated by the upper computer is full, the descriptor generating module sends a full flag bit to the log data caching module, the log data caching module forwards the message to the interrupt generating module, the interrupt generating module generates an interrupt, the upper computer is informed to read the data in the target cache address, and the upper computer is informed to the main control board in a bar register writing mode after finishing data reading. Before the next time the log data is uploaded by the main control board, checking the flag bit of the log buffer zone read by the upper computer, if the upper computer does not complete the log data reading at the moment, reporting errors by the main control board, if the upper computer completes the log data reading, clearing 0 log uploading times, re-counting the log uploading times when the log data is uploaded, and restarting the target address accumulation process when the target address is the target buffer head address of the log.
In another embodiment of the present invention, log data is ordered according to a priority order, and the log data is written into the memory of the log data cache module with high priority; writing the log data with low priority into a log buffer area of the log data buffer module, and writing the log data with high priority into the memory after the log data with high priority is written.
As shown in fig. 4, log data is stored in a memory after entering the log data buffer module, and the memory is illustratively fifo with a width of 512 bits and a depth of 8 bits. Considering that log data of different sub-modules can arrive at the same time, the priority of storing the log data of each sub-module into fifo must be ordered, meanwhile, data with low priority must be cached, and after writing the data with high priority into fifo is completed, the data with low priority is written into fifo. The specific logic implementation is as follows: after log data is received, the log data is firstly cached in a log cache area of a log data cache module, the log cache area function is realized based on a cache register, and each sub-module is provided with a corresponding cache register. If there is data in the register, then flag position 1, after the data is read, flag position 0. The data select logic writes the data into fifo in the register with flag bit 1 and stores its data into flag bit 0. If a plurality of data are stored in the flag position 1 at the same time, log data with high priority are selected to be stored in fifo, and the data are stored in the flag position 0, and the data of other registers are temporarily read out. The above process is repeated. When fifo is full, stopping reading the register data, and if the register has unread log data, waiting for uploading the data in fifo and continuing reading. Because the uploading speed of the sub-module log data is far slower than that of the main control board for uploading the log to the upper computer, when fifo data is not considered to be uploaded, new sub-module log data comes, so that the original data of the cache register is covered.
Further, as shown in fig. 5, the DMA data transmission module functions, since the data bit width of the journal cache fifo is 512, and the PCIe DMA communication adopts the 64-bit axistream bus protocol, it is also necessary to perform data bit width conversion on the data read out from the fifo, and transmit the converted data to the XDMA IP Core in the form of the axistream bus protocol. The log data buffer module sends the full flag bit of the log buffer area to the DMA data sending module, after receiving the flag bit, the DMA data sending module pulls up fifo read enable to read one frame of data, then firstly sends the high 64 bits of the log, namely 448-511 bits of the data, then sends 384-447 bits of the data, and the like until the low 64 bits (0-63 bits) of the log are sent completely, then the DMA data sending module pulls up fifo read enable again to read one frame of data, and the process is repeated until the log buffer fifo is read empty.
The technical scheme of the invention has the following beneficial effects: the log data transmission between the main control board and the upper computer adopts PCIe DMA communication, the main control board FPGA automatically generates descriptors according to the requirements, the upper computer CPU is not required to participate, and the use efficiency of the CPU is improved; the sub-module log information can be uploaded in real time, a large amount of log information does not need to be cached in the FPGA, the system design difficulty of the main control board is reduced, and the FPGA logic resources are saved.
Based on the same inventive concept, a second aspect of the embodiment of the present invention provides a method for uploading a sub-module log of a chip mounter, which comprises the following steps based on the above main control board:
the main control board of the chip mounter receives and caches log data of the sub-modules;
and the main control board uploads the log data to the upper computer through DMA communication.
Further, the main control board uploads the log data to the upper computer through DMA communication comprises the following specific processes:
writing the log data with high priority into a memory, writing the log data with low priority into a log buffer area, and writing the log data with high priority into the memory after the log data with high priority are written;
after the memory is fully written, determining a target address of log data received by the upper computer each time, and transmitting the log data to the target address through the DMA communication, wherein the target address= (log uploading frequency-1) x N+ is the first address of a cache area of the upper computer, N is the byte number of the log data cached by the memory, and the first address of the cache area of the upper computer is issued to the descriptor generating module by the upper computer;
after the cache capacity of the upper computer is determined to be full, an interrupt signal is sent to inform the upper computer to read the cached log data.
Further, before uploading the log data to the upper computer each time, checking whether the upper computer finishes log reading, and if not, reporting an error.
In summary, by adopting the DMA communication mode, the FPGA on the main control board can actively perform DMA communication, the log data of the submodule is stored in the address space agreed with the host computer, the process is automatically generated inside the main control board FPGA, and the DMA communication is performed through the internal DMA controller, so that the participation of the host computer is not needed, the utilization rate of the CPU can be reduced, the log data can be uploaded in real time, and the logic resource of the main control board FPGA is saved.
The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited thereto. Within the scope of the technical idea of the invention, a number of simple variants of the technical solution of the invention are possible, including the combination of the individual specific technical features in any suitable way. The various possible combinations of the invention are not described in detail in order to avoid unnecessary repetition. Such simple variations and combinations are likewise to be regarded as being within the scope of the present disclosure.
Claims (10)
1. A main control board for chip mounter submodule log uploading, its characterized in that, the main control board is used for initiatively transmitting the log to the host computer through DMA communication, includes:
the log data caching module is used for receiving and caching log data from the chip mounter sub-module;
and the DMA data transmitting module is used for uploading the log data of the log data caching module to the upper computer.
2. The master control board of claim 1, further comprising:
the descriptor generating module is used for determining the target address and the cache capacity of the upper computer, which are used for sending the log data to the log data caching module, and sending filling information to the log data caching module after the cache capacity is fully written;
and the interrupt generating module is used for sending an interrupt signal to inform the upper computer to read the cached log data after receiving the filling information from the log data caching module.
3. The main control board according to claim 2, wherein log data is ordered according to a priority order, and is written into the memory of the log data cache module with high priority; writing the log data with low priority into a log buffer area of the log data buffer module, and writing the log data with high priority into the memory after the log data with high priority is written.
4. The main control board according to claim 3, wherein the descriptor generating module is configured to determine that the log data buffer module sends log data to a target buffer address of an upper computer specifically is:
after the memory is fully written, the log data buffer module sends a fifo full flag bit to the descriptor generating module, the descriptor generating module determines a target address of the log data received by the upper computer each time, and the log data buffer module sends the log data to the target address through the DMA data sending module.
5. The main control board according to claim 4, wherein the target address= (log uploading number-1) ×n+ is a host buffer area head address, where N is a number of bytes of log data buffered in the memory, and the host buffer area head address is issued to the descriptor generating module by the host.
6. The main control board according to any one of claims 1-5, further comprising checking whether the upper computer has completed log reading before uploading the log data to the upper computer each time, and if not, reporting an error.
7. The main control board of claim 6, wherein the log data buffer module communicates with the chip mounter sub-module via 485 module to receive log data.
8. A method for uploading a sub-module log of a chip mounter, comprising the steps of:
the main control board of the chip mounter receives and caches log data of the sub-modules;
and the main control board uploads the log data to the upper computer through DMA communication.
9. The method of claim 8, wherein the main control board uploads log data to the host computer by DMA communication comprises:
writing the log data with high priority into a memory, writing the log data with low priority into a log buffer area, and writing the log data with high priority into the memory after the log data with high priority are written;
after the memory is fully written, determining a target address of log data received by the upper computer each time, and transmitting the log data to the target address through the DMA communication, wherein the target address= (log uploading frequency-1) x N+ is the first address of a cache area of the upper computer, N is the byte number of the log data cached by the memory, and the first address of the cache area of the upper computer is issued to the descriptor generating module by the upper computer;
after the cache capacity of the upper computer is determined to be full, an interrupt signal is sent to inform the upper computer to read the cached log data.
10. The method of claim 8 or 9, further comprising checking whether the host computer has completed log reading each time before uploading the log data to the host computer, and if not, reporting an error.
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| US7620791B1 (en) * | 2006-04-14 | 2009-11-17 | Tilera Corporation | Mapping memory in a parallel processing environment |
| JP2008227975A (en) * | 2007-03-13 | 2008-09-25 | Ricoh Co Ltd | Image forming device, control method of image forming device, and data transfer device |
| JP2015185586A (en) * | 2014-03-20 | 2015-10-22 | 富士機械製造株式会社 | Controller of component mounter |
| US20180317354A1 (en) * | 2015-10-28 | 2018-11-01 | Fuji Corporation | Feeder trace log saving system |
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