CN117133724B

CN117133724B - Packaged chip structure, processing method thereof and electronic equipment

Info

Publication number: CN117133724B
Application number: CN202310305012.4A
Authority: CN
Inventors: 张智诚; 曹元�
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2023-03-20
Filing date: 2023-03-20
Publication date: 2024-10-01
Anticipated expiration: 2043-03-20
Also published as: CN117133724A

Abstract

The application provides a packaged chip structure, a processing method thereof and electronic equipment, and relates to the technical field of electronic equipment. The packaging chip structure has the magnetic conduction layer and the plastic packaging shielding layer, has the capability of multilayer anti-magnetic interference, is favorable for improving the working reliability of the chip, and has small volume.

Description

Packaged chip structure, processing method thereof and electronic equipment

Technical Field

The present application relates to the field of electronic devices, and in particular, to a packaged chip structure, a processing method thereof, and an electronic device.

Background

In order to realize the functions of an electronic device such as a watch, various chips such as a nonvolatile magnetic random access memory (Magnetic Random Access Memory, MRAM), a radio frequency chip and the like are generally integrated on a circuit board inside the electronic device. The magnetic interference between the chips and the interference of the magnetic field in the external environment where the electronic equipment is located on the chips can all affect the normal operation of the chips. Therefore, how to optimize the anti-magnetic interference structure of the chip becomes more and more important.

Disclosure of Invention

The embodiment of the application provides a packaged chip structure, a processing method thereof and electronic equipment, wherein the packaged chip structure is provided with a magnetic conduction layer and a plastic package shielding layer, has the capability of multilayer anti-magnetic interference, is beneficial to improving the working reliability of a chip, and has small volume.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:

In a first aspect, the present application provides a packaged chip structure, including: the device comprises a substrate, a chip, an insulating layer, a magnetic conduction layer and a plastic package shielding body. The base plate has a first surface, and the chip sets up in the first surface, and the insulating layer sets up in the first surface, and covers the chip, and magnetic conduction layer covers the insulating layer, and the plastic envelope shield covers the first surface to cover magnetic conduction layer, the plastic envelope shield includes resin base member and magnetic shielding filler, and magnetic shielding filler distributes in the resin base member.

In the packaged chip structure provided by the embodiment of the application, the chips can be packaged on the substrate by using the plastic package shielding body, so that the purposes of water resistance and dust resistance are achieved, and the magnetic field shielding effect can be realized. The plastic package shielding layer also encapsulates the magnetic conduction layer, so that on the premise of not increasing the thickness of the packaged chip structure, the magnetic shielding filler in the plastic package shielding body can be used for shielding the magnetic field in the external environment where the chip is positioned, thereby weakening the magnetic field strength of the magnetic field entering the magnetic conduction layer, and then the magnetic field is further shielded by the magnetic conduction layer, so that the magnetic field strength of the magnetic field entering the chip is further reduced. That is, the magnetic field in the external environment where the packaged chip structure is located is shielded by adopting the multi-layer shielding layer, which is favorable for improving the magnetic shielding effect on the chip, so that the chip can still work normally even in the environment with higher magnetic field.

And, based on the multilayer shielding effect that encapsulation chip structure self had, thereby need not to set up in addition on the circuit board and be used for covering the metal shield cover of establishing encapsulation chip structure, need not to consider the metal shield cover among the correlation technique and with this metal shield cover adjacent other encapsulation chip between dodge the problem, saved the space that the metal shield cover took on the circuit board, be favorable to reducing the overall size and the weight of circuit board subassembly, save the overall dimension on the circuit board, then be favorable to realizing miniaturized design and the lightweight design of electronic equipment, still be favorable to integrating more electronic components on the circuit board simultaneously.

In addition, based on the good shielding effect of the packaging chip structure, more possibilities are provided for the layout of the chips on the circuit board, the situation that the two chips are required to be set far due to serious mutual interference between the two chips is avoided to a certain extent, and the situation that the chips are required to be set close to the center of the electronic equipment due to the fact that the two chips are required to be kept at a certain distance from a magnetic field in the external environment where the electronic equipment is located is also avoided to a certain extent. In addition, doping of the magnetic shielding filler in the plastic package shielding body is beneficial to improving the structural strength and toughness of the plastic package shielding body.

In some embodiments of the first aspect of the application, the saturation induction of the plastic package shield is different from the saturation induction of the magnetically permeable layer, and the permeability of the plastic package shield is different from the permeability of the magnetically permeable layer. Therefore, the multilayer shielding layer is favorable for integrally having the characteristics of high magnetic permeability and difficult magnetic saturation, and the magnetic shielding effect of the packaged chip structure is further optimized.

In some embodiments of the first aspect of the present application, the saturation induction of the plastic package shield is greater than the saturation induction of the magnetically permeable layer, and the permeability of the plastic package shield is less than the permeability of the magnetically permeable layer. Specifically, because of the shielding layer with high magnetic permeability, magnetic saturation is often easier to generate, and the magnetic permeability of the plastic package shielding body is smaller than that of the magnetic conductive layer by enabling the saturation magnetic induction intensity of the plastic package shielding body to be larger than that of the magnetic conductive layer. Therefore, the plastic package shielding body which is not easy to be saturated in magnetism can be adopted to initially weaken the intensity of the external magnetic field. Because the plastic package shielding body primarily weakens the magnetic field, the magnetic conduction layer inside is not easy to achieve magnetic saturation, the possibility of the magnetic saturation of the magnetic conduction layer is reduced, the magnetic conduction layer with high magnetic conductivity can weaken the magnetic field greatly, and the shielding effect is improved greatly.

In some embodiments of the first aspect of the present application, the magnetic shielding filler may be in particulate form. Therefore, the granular magnetic shielding filler is easier to uniformly distribute in the resin matrix, so that the uniformity of the magnetic permeability and the magnetic saturation strength of the plastic package shielding body is improved.

In some embodiments of the first aspect of the application, the equivalent diameter of the magnetic shielding filler is in the nanometer scale. That is, the equivalent diameter of the magnetic shielding filler is 1 nanometer (nm) or more and less than 1000nm. Therefore, on one hand, the distribution uniformity of the magnetic shielding filler in the resin matrix is facilitated, on the other hand, the distribution density of the magnetic shielding filler in the resin matrix is facilitated to be improved, the magnetic induction intensity and the magnetic permeability of the plastic package shielding body can be improved through the two aspects, and the shielding effect of the plastic package shielding body is improved. In addition, the structural strength of the plastic package shielding body is further improved.

In some embodiments of the first aspect of the application, the equivalent diameter of the magnetic shielding filler may also be in the order of micrometers. That is, the equivalent diameter of the magnetic shielding filler is greater than or equal to 1 micrometer (um) and less than 1000um. Therefore, the processing cost of the magnetic shielding filler is low, and the whole manufacturing cost of the packaged chip structure is reduced.

In some embodiments of the first aspect of the present application, in order to achieve both the shielding effect of the plastic package shielding body and the processing and manufacturing cost of the magnetic shielding filler, the equivalent diameter of the magnetic shielding filler is in the range of 500nm to 50um, that is, 500nm to 50000nm.

In some embodiments of the first aspect of the present application, the magnetically permeable layer is made of a soft magnetic material. Because the magnetic permeability of the soft magnetic material is higher, when the material of the magnetic conduction layer is the soft magnetic material, the magnetic conduction layer has higher magnetic permeability, which is beneficial to improving the shielding effect.

In some embodiments of the first aspect of the present application, the soft magnetic material is a soft magnetic alloy material and/or ferrite; wherein the soft magnetic alloy material is at least one of nickel-iron alloy, silicon-iron alloy, iron-silicon-chromium alloy and cobalt-iron alloy. Therefore, the shielding effect is improved, the material price is low, and the processing and manufacturing cost of the packaged chip structure is reduced.

In some embodiments of the first aspect of the present application, the material of the magnetic shielding filler is pure iron, and/or silicon steel. Pure iron and silicon steel have higher saturation induction intensity, so that the plastic package shielding body is favorable to have higher saturation induction intensity, the plastic package shielding body is not easy to generate magnetic saturation in a strong magnetic environment, and the pure iron and silicon steel are low in price, so that the processing and manufacturing cost of the packaged chip structure is reduced.

In some embodiments of the first aspect of the application, the thickness of the plastic encapsulated shield is greater than the thickness of the magnetically permeable layer. Therefore, the plastic package shielding body is beneficial to ensuring that the plastic package shielding body has relatively thicker thickness, increasing the weight of the magnetic shielding filler, and further improving the magnetic permeability and the saturation magnetic induction intensity of the plastic package shielding body and the shielding effect.

In some embodiments, the magnetic shielding filler is present in an amount of 30 parts to 90 parts by weight in 100 parts by weight of the plastic molded shield. Therefore, on one hand, the packaging effect of the plastic package shielding body is guaranteed, and on the other hand, the shielding effect of the plastic package shielding body is improved.

In some embodiments of the first aspect of the present application, the magnetically permeable layer is attached to the surface of the insulating layer by a spraying process or a printing process. The plastic package shielding body is formed through an injection molding process, so that the processing process of the magnetic conduction layer is different from that of the plastic package shielding body, and the difference of the processing process is beneficial to the existence of the difference between the magnetic conduction and saturation magnetic induction intensity between the plastic package shielding body and the magnetic conduction layer. Furthermore, the spraying process or the printing process is simple and the cost is low.

In some embodiments of the first aspect of the application, the magnetically permeable layer may also be bonded to the insulating layer by a glue layer. Therefore, the connecting process is simple, the cost is low, and the processing efficiency is improved.

In some embodiments of the first aspect of the present application, the insulating layer is attached to the first surface and the chip by an injection molding process. The insulating layer thus produced may be attached to the first surface and the chip. Thus, the protection effect of the insulating layer on the chip is improved.

Exemplary materials for the insulating layer include, but are not limited to, epoxy and polyimide.

In some embodiments of the first aspect of the present application, the insulating layer is a double-sided tape, and the insulating layer is adhered to the first surface and the magnetic conductive layer, respectively. In this way, the insulating layer is arranged to be the double-sided tape, so that the connecting process between the insulating layer and the first surface and between the insulating layer and the magnetic conductive layer is simplified, and the cost is reduced.

In some embodiments of the first aspect of the present application, the packaged chip structure further includes a first bottom shielding layer disposed between the first surface and the chip, an orthographic projection of the chip on the first bottom shielding layer is located within a peripheral outline of the first bottom shielding layer, and the insulating layer covers the first bottom shielding layer. Therefore, the first bottom shielding layer, the plastic package shielding body and the magnetic conduction layer can be used for forming a magnetic shielding structure surrounding the chip, and the magnetic shielding effect on the chip can be further improved.

Illustratively, the first bottom shield layer is adhered to the first surface with a first insulating adhesive. Therefore, on one hand, the relative fixation between the first bottom shielding layer and the first surface can be realized, and on the other hand, the first insulating glue can be used for playing an insulating role, so that the short circuit between the substrate and the first bottom shielding layer is prevented, and the working reliability of the packaged chip structure is improved.

The chip is illustratively bonded to the first bottom shield layer with a second insulating adhesive. Therefore, on one hand, the relative fixation between the first bottom shielding layer and the chip can be realized, and on the other hand, the second insulating adhesive can be utilized to play an insulating role, so that the short circuit between the chip and the first bottom shielding layer is prevented, and the working reliability of the packaged chip structure is improved.

In some embodiments, the first bottom shielding layer is made of soft magnetic material. Because the magnetic permeability of soft magnetic material is higher, when the material of first bottom shielding layer is soft magnetic material, first bottom shielding layer has higher magnetic permeability, improves shielding effect.

Illustratively, the soft magnetic material is a soft magnetic alloy material and/or ferrite; wherein the soft magnetic alloy material is at least one of nickel-iron alloy, silicon-iron alloy, iron-silicon-chromium alloy and cobalt-iron alloy. Therefore, the shielding effect is improved, the material price is low, and the processing and manufacturing cost of the packaged chip structure is reduced.

Specifically, the first bottom shielding layer is made of nickel-iron alloy, so that the magnetic permeability of the first bottom shielding layer is improved, and the forming of the first bottom shielding layer is facilitated.

In some embodiments of the first aspect of the present application, the packaged chip structure further includes a second bottom shielding layer stacked between the first bottom shielding layer and the first surface. In this way, the first bottom shielding layer, the second bottom shielding layer, the plastic package shielding body and the magnetic conduction layer can be integrally and generally formed into a multi-layer magnetic shielding structure surrounding the chip, so that the magnetic shielding effect on the chip can be further improved. Illustratively, the second bottom shield layer is adhered to the first watch using a third insulating glue. Therefore, on one hand, the relative fixation between the second bottom shielding layer and the first surface can be realized, and on the other hand, the third insulating glue can be used for playing an insulating role, so that the short circuit between the substrate and the second bottom shielding layer is prevented, and the working reliability of the packaged chip structure is improved.

In some embodiments of the first aspect of the application, the saturation induction of the second bottom shielding layer is different from the saturation induction of the first bottom shielding layer, and the permeability of the second bottom shielding layer is different from the permeability of the first bottom shielding layer. In this way, the first bottom shielding layer and the second bottom shielding layer are beneficial to integrally have the characteristics of high magnetic permeability and difficult magnetic saturation, so that the shielding effect is beneficial to further optimization.

In some embodiments, the second bottom shielding layer is made of pure iron and/or silicon steel. Pure iron and silicon steel all have higher saturation induction intensity to be favorable to the second bottom shielding layer to have higher saturation induction intensity, make the second bottom shielding layer be difficult to produce the magnetic saturation more in strong magnetic environment, pure iron and silicon steel low price is favorable to reducing the manufacturing cost of encapsulation chip structure moreover.

In some embodiments of the first aspect of the present application, the saturation induction of the second bottom shielding layer is greater than the saturation induction of the first bottom shielding layer, and the permeability of the second bottom shielding layer is less than the permeability of the first bottom shielding layer, and the insulating layer covers the second bottom shielding layer. Specifically, magnetic saturation tends to occur more easily due to the shielding layer having high magnetic permeability, by making the saturation magnetic induction intensity of the second bottom shielding layer larger than that of the first bottom shielding layer, and the magnetic permeability of the second bottom shielding layer smaller than that of the first bottom shielding layer. Therefore, the second bottom shielding layer which is not easy to be saturated in magnetism can be adopted to weaken the external magnetic field intensity preliminarily, and the second bottom shielding layer weakens the magnetic field preliminarily, so that the first bottom shielding layer inside is not easy to be saturated in magnetism, the possibility of the first bottom shielding layer being saturated in magnetism is reduced, the first bottom shielding layer with high magnetic conductivity can weaken the magnetic field greatly, and the shielding effect is improved greatly.

In some embodiments of the first aspect of the application, the orthographic projection of the first bottom shielding layer on the first surface is located within the orthographic projection of the second bottom shielding layer on the first surface; or the orthographic projection of the first bottom shielding layer on the first surface coincides with the orthographic projection of the second bottom shielding layer on the first surface. Thereby, the magnetic shielding effect is favorably improved.

In some embodiments of the first aspect of the application, the chip has a circuit face, the circuit face facing away from the substrate; the first surface is provided with a bonding pad, and the bonding pad is positioned at the periphery of the first bottom shielding layer; the packaging chip structure also comprises a bonding wire, one end of the bonding wire is fixed on the circuit surface and is electrically connected with the chip, and the other end of the bonding wire is fixed on the bonding pad and is electrically connected with the substrate; the insulating layer covers the bonding wire. Therefore, the connecting process is simple, the cost is low, and the efficiency is high. Moreover, when the packaged chip structure further comprises a first bottom shielding layer, the connection mode does not interfere with the arrangement of the first bottom shielding layer. The bonding lead is covered by the insulating layer, so that the bonding lead cannot penetrate through the plastic package shielding body and the magnetic conduction layer, and the problem of magnetic leakage is prevented. The length of the bonding wires, i.e., the signal and power paths, is advantageously shortened, thereby advantageously increasing the operating speed of the chip. For example, for MRAM, it is advantageous to secure the speed of data reading, writing, and erasing.

In some embodiments of the first aspect of the application, the chip is a bare chip.

In some embodiments of the first aspect of the application, the chip is an MRAM.

In a second aspect, the present application provides a method for processing a packaged chip structure, including the steps of:

Disposing a chip on a first surface of a substrate;

Covering an insulating layer and a magnetic conductive layer on the surface of the chip; the insulating layer is also connected with the first surface and covers the chip, and the insulating layer is positioned between the magnetically permeable layer and the chip;

Fully mixing the first packaging material and the magnetic shielding filler to prepare plastic packaging slurry;

and setting the plastic package slurry on the first surface through an injection molding process, and enabling the plastic package slurry to cover the magnetic conduction layer so as to form the plastic package shielding body.

In the processing method of the packaged chip structure, disclosed by the embodiment of the application, the chips can be packaged on the substrate by utilizing the plastic package shielding body, so that the purposes of water resistance and dust resistance are achieved, and the magnetic field shielding effect can be realized. The plastic package shielding layer also encapsulates the magnetic conduction layer, so that on the premise of not increasing the thickness of the packaged chip structure, the magnetic shielding filler in the plastic package shielding body can be used for shielding the magnetic field in the external environment where the chip is positioned, thereby weakening the magnetic field strength of the magnetic field entering the magnetic conduction layer, and then the magnetic field is further shielded by the magnetic conduction layer, so that the magnetic field strength of the magnetic field entering the chip is further reduced. That is, the magnetic field in the external environment where the packaged chip structure is located is shielded by adopting the multi-layer shielding layer, which is favorable for improving the magnetic shielding effect on the chip, so that the chip can still work normally even in the environment with higher magnetic field.

Illustratively, the first encapsulant material and the magnetically shielding filler are thoroughly mixed using a blender to obtain a molding compound. Thus, the mixing uniformity can be improved. Among them, the mixers include, but are not limited to, propeller type mixers, turbine type mixers, paddle type mixers, anchor type mixers, ribbon type mixers, magnetic heating mixers, hinge type mixers, variable frequency double layer mixers, and side entry type mixers.

In some embodiments of the second aspect of the present application, covering the surface of the chip with the insulating layer and the magnetically permeable layer includes:

disposing a second encapsulation material on the first surface through an injection molding process, and enabling the second encapsulation material to cover the chip so as to form an insulating layer;

the magnetic conductive layer is arranged on the surface of the insulating layer.

Thus, the insulating layer is formed by adopting an injection molding process, so that the insulating layer can be attached to the first surface and the chip. Thus, the protection effect of the insulating layer on the chip is improved.

The second encapsulation material is illustratively the same as the first encapsulation material. Therefore, one packaging material is selected, two different packaging materials are not needed, the material selecting time is saved, and the production process is simplified.

Exemplary second encapsulation materials include, but are not limited to, epoxy and polyimide.

In some embodiments of the second aspect of the present application, disposing the magnetically permeable layer on the surface of the insulating layer comprises:

Thoroughly mixing a solvent and magnetic shielding particles to prepare a shielding slurry;

covering the surface of the insulating layer with shielding slurry through a spraying process or a printing process;

And drying the shielding slurry on the surface of the insulating layer to volatilize the solvent in the shielding slurry so as to form the magnetically conductive layer.

Therefore, the magnetically conductive layer is formed by adopting a spraying process or a printing process, so that the processing process is simplified, and the processing cost is reduced.

Specifically, the solvent includes at least one of water and an organic solvent. That is, the solvent may be water, or an organic solvent, or may include both water and an organic solvent. The organic solvent includes at least one of ethanol, toluene, xylene, pentane, hexane, octane, cyclohexane, cyclohexanone, toluene cyclohexanone, chlorobenzene, dichlorobenzene, dichloromethane, methanol, isopropanol, diethyl ether, propylene oxide, methyl acetate, ethyl acetate, propyl acetate, ethyl propionate, acetone, methyl butanone, methyl isobutyl ketone, ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, ethylene glycol monobutyl ether, acetonitrile, pyridine, and phenol.

In some embodiments of the second aspect of the application, the saturation magnetic induction of the magnetic shielding filler is greater than the saturation magnetic induction of the magnetic shielding particles, and the magnetic permeability of the magnetic shielding filler is less than the magnetic permeability of the magnetic shielding particles.

Specifically, the magnetic shielding particles are made of soft magnetic materials. Because the magnetic permeability of the soft magnetic material is higher, when the material of the magnetic shielding particles is the soft magnetic material, the magnetic conductive layer can have higher magnetic permeability, and the shielding effect is improved.

Illustratively, the soft magnetic material is a soft magnetic alloy material and/or ferrite. Wherein the soft magnetic alloy material is at least one of nickel-iron alloy, silicon-iron alloy, iron-silicon-chromium alloy and cobalt-iron alloy. That is, the soft magnetic alloy material is nickel-iron alloy, silicon-iron alloy, iron-silicon-chromium alloy or cobalt-iron alloy; the soft magnetic alloy material may also be two, three or all of nickel-iron alloy, silicon-iron alloy, iron-silicon-chromium alloy and cobalt-iron alloy. Thereby, the shielding effect is advantageously improved.

In some embodiments, the equivalent diameter of the magnetic shielding particles is on the order of nanometers. That is, the equivalent diameter of the magnetic shielding particles is 1 nanometer (nm) or more and less than 1000nm. Thus, the compact magnetically permeable layer is formed, so that the saturation induction intensity and the magnetic permeability of the magnetically permeable layer are improved, and the shielding effect of the magnetically permeable layer is improved.

In other examples, the equivalent diameter of the magnetic shielding particles may also be on the order of microns. That is, the equivalent diameter of the magnetic shielding particles is greater than or equal to 1 micrometer (um) and less than 1000um. In this way, the processing cost of the magnetic shielding particles is low, which is beneficial to reducing the overall manufacturing cost of the packaged chip structure.

In some embodiments, in order to achieve both the shielding effect of the magnetically permeable layer and the manufacturing cost of the magnetic shielding particles, the equivalent diameter of the magnetic shielding particles ranges from 100nm to 10um, i.e., from 100nm to 10000nm. Illustratively, the equivalent diameter of the magnetic shielding particles ranges from 200nm to 5um.

In some embodiments of the second aspect of the present application, before disposing the chip on the first surface of the substrate, the method further comprises:

Disposing a first bottom shielding layer on a first surface of a substrate;

disposing the chip on the first surface of the substrate includes:

disposing a chip on a side surface of the first bottom shielding layer away from the first surface; the orthographic projection of the chip on the first bottom shielding layer is located in the peripheral outline of the first bottom shielding layer.

Therefore, the first bottom shielding layer, the plastic package shielding body and the magnetic conduction layer can be used for forming a magnetic shielding structure surrounding the chip, and the magnetic shielding effect on the chip can be further improved.

In some embodiments of the second aspect of the present application, after the chip is disposed on the first surface of the substrate and before the insulating layer and the magnetic conductive layer are covered on the surface of the chip, the method further includes:

connecting bonding wires between the circuit surface of the chip and the bonding pads on the first surface by adopting a wire bonding process; the circuit surface of the chip faces away from the first surface, and the bonding pads on the first surface are arranged on the periphery of the first bottom shielding layer.

Therefore, the connecting process is simple, the cost is low, and the efficiency is high. Moreover, when the packaged chip structure further comprises a first bottom shielding layer, the connection mode does not interfere with the arrangement of the first bottom shielding layer. Moreover, when the packaged chip structure further comprises a first bottom shielding layer, the connection mode does not interfere with the arrangement of the first bottom shielding layer. The bonding lead is covered by the insulating layer, so that the bonding lead cannot penetrate through the plastic package shielding body and the magnetic conduction layer, and the problem of magnetic leakage is prevented. The length of the bonding wires, i.e., the signal and power paths, is advantageously shortened, thereby advantageously increasing the operating speed of the chip. For example, for MRAM, it is advantageous to secure the speed of data reading, writing, and erasing.

Illustratively, in order to ensure the smoothness of the wire bonding process and to improve the reliable connection of the bonding wires and the chips and the bonding pads, and to prevent the short circuit problem caused by the dirt (such as residual moisture and organic matters on the chip) and the like existing in the chip, the first bottom shielding layer and the substrate as a whole, the steps of plasma cleaning and drying the chip, the first bottom shielding layer and the substrate as a whole are further included after the chip is arranged on the first surface of the substrate and before the wire bonding process.

Illustratively, in order to prevent dirt from remaining on the chip or the substrate after the wire bonding process, the wire bonding process further includes the step of plasma cleaning and drying the bonding wire, the chip, the first bottom shielding layer and the substrate as a whole.

In a third aspect, the present application provides an electronic device comprising: a housing, a circuit board and a packaged chip structure. The shell is provided with an accommodating space, the circuit board is arranged in the accommodating space, the packaging chip structure is of any one of the technical schemes, the substrate is provided with a second surface opposite to the first surface, the second surface faces the circuit board, and the packaging chip structure is arranged on the circuit board and is electrically connected with the circuit board.

In the electronic equipment provided by the embodiment of the application, the chip can be packaged on the substrate by using the plastic package shielding body through the structure of the packaging chip, so that the purposes of water resistance and dust resistance are achieved, and the magnetic field shielding effect can be realized. The plastic package shielding layer also encapsulates the magnetic conduction layer, so that on the premise of not increasing the thickness of the packaged chip structure, the magnetic shielding filler in the plastic package shielding body can be used for shielding the magnetic field in the external environment where the chip is positioned, thereby weakening the magnetic field strength of the magnetic field entering the magnetic conduction layer, and then the magnetic field is further shielded by the magnetic conduction layer, so that the magnetic field strength of the magnetic field entering the chip is further reduced. That is, the magnetic field in the external environment where the packaged chip structure is located is shielded by adopting the multi-layer shielding layer, which is favorable for improving the magnetic shielding effect on the chip, so that the chip can still work normally even in the environment with higher magnetic field.

In some embodiments of the third aspect of the present application, the electronic device further includes a shielding member, the shielding member being located on a side of the circuit board remote from the packaged chip structure, and an orthographic projection of the packaged chip structure on a plane on which the first surface is located overlaps with an orthographic projection of the shielding member on the plane on which the first surface is located. In this way, when no shielding structure is provided between the chip and the substrate, the shielding member on the side of the circuit board away from the packaged chip structure can be used for magnetic shielding, so that the shielding effect on the magnetic field from the side of the circuit board away from the packaged chip structure can be improved at least to some extent. When be equipped with first bottom shielding layer between chip and the base plate, perhaps be equipped with first bottom shielding layer and second bottom shielding layer simultaneously, the setting of shield can be favorable to improving the shielding effect to the magnetic field from the one side of keeping away from the encapsulation chip architecture of circuit board more.

In some embodiments of the third aspect of the present application, the orthographic projection of the packaged chip structure on the plane of the first surface is located within the orthographic projection of the shielding member on the plane of the first surface. Thereby, it is advantageous to further improve the magnetic shielding effect.

In some embodiments of the third aspect of the application, the shield is defined by a portion of the housing. Therefore, the structural layout of the electronic equipment is reasonably optimized.

Illustratively, the shield is a soft magnetic material. Because the magnetic permeability of the soft magnetic material is higher, when the material of the shielding piece is the soft magnetic material, the shielding piece has higher magnetic permeability, and the shielding effect is improved. Of course, in other examples, the shield may also be metal, such as copper.

Drawings

FIG. 1 is a schematic diagram of an MRAM architecture;

Fig. 2 is a schematic structural view of a circuit board assembly provided in the related art;

fig. 3 is a schematic structural diagram of an electronic device according to some embodiments of the present application;

fig. 4 is a perspective view of a main body portion in the electronic device shown in fig. 3;

FIG. 5 is an exploded view of the body portion according to FIG. 4;

FIG. 6 is a schematic view of a circuit board assembly in the body portion according to FIG. 5;

FIG. 7 is a schematic top view of the circuit board assembly shown in FIG. 6;

FIG. 8 is a schematic diagram of a circuit board assembly according to other embodiments of the present application;

FIG. 9 is a schematic diagram of a circuit board assembly according to still other embodiments of the present application;

FIG. 10 is a schematic diagram of a circuit board assembly according to other embodiments of the present application;

FIG. 11 is an exploded schematic view of a main body portion in an electronic device employing the circuit board assembly shown in FIG. 10;

FIG. 12 is a flow chart of a method of processing a packaged chip structure according to some embodiments of the present application;

FIG. 13 is a process flow diagram of a packaged chip structure according to other embodiments of the present application;

FIG. 14 is a process flow diagram of a packaged chip structure according to still further embodiments of the present application;

FIG. 15 is a process flow diagram of a packaged chip structure according to other embodiments of the present application;

fig. 16 is a schematic diagram illustrating a specific processing procedure of a packaged chip structure according to an embodiment of the present application.

Reference numerals:

100. An electronic device;

1. watchband; 11. a first wristband; 111. a first locking part; 12. a second wristband; 121. a second locking part;

2. A main body portion; 21. a display module; 211. a screen; 212. a decorative ring; 22. a housing; 22a, a back shell; 22b, a frame;

3. A circuit board assembly; 31. a circuit board; 311. a first face; 312. a second face; 32. packaging the chip structure; 321. a chip; 321a, MRAM;321a1, a free layer; 321a2, a tunnel layer; 321a3, a fixed layer;

322a, a plastic sealing layer; 322b, plastic packaging the shielding body; 323. a substrate; 3231. a first surface; 32311. a bonding pad; 3232. a second surface; 324. a magnetically conductive layer; 325. an insulating layer; 326. a first bottom shielding layer; 327. bonding wires; 328. a second bottom shielding layer; 33. a metal shield; 34. an electrical connection structure;

4. battery cell

5. A shield.

Detailed Description

In embodiments of the present application, the terms "exemplary" or "such as" and the like are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In embodiments of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.

In the description of embodiments of the application, the term "at least one" means one or more, and "a plurality" means two or more. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

In the description of embodiments of the present application, the term "and/or" refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term "and/or" is an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B, and may mean: a exists alone, A and B exist together, and B exists alone. In the present application, the character "/" generally indicates that the front and rear related objects are an or relationship.

In the description of embodiments of the present application, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and for example, "connected" may be either detachably connected or non-detachably connected; may be directly connected or indirectly connected through an intermediate medium.

References to orientation terms, such as "inner", "outer", etc., in the embodiments of the present application are only with reference to the orientation of the drawings, and thus, the use of orientation terms is intended to better and more clearly describe and understand the embodiments of the present application, rather than to indicate or imply that the apparatus or elements being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the embodiments of the present application.

In the description of embodiments of the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

A Non-Volatile magnetic random access memory (Magnetic Random Access Memory, MRAM) has high-speed read-write capability of Static Random Access Memory (SRAM) and high integration of Dynamic Random Access Memory (DRAM), and can be basically rewritten indefinitely. Therefore, they are widely used in electronic devices such as watches.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an MRAM. The core memory cell of an MRAM is a magnetic tunnel junction (magnetic tunnel junction, MTJ). The MTJ includes a free layer 321a1, a tunnel layer 321a2, and a fixed layer 321a3. Among them, the fixed layer 321a3 and the free layer 321a1 are both ferromagnetic materials, and the tunnel layer 321a2 is an insulating material, a semiconductor material, a ferroelectric material, or the like. The magnetization direction of the fixed layer 321a3 is not changed during information writing. The magnetization direction of the free layer 321a1 may be changed such that the magnetization direction of the free layer 321a1 is aligned parallel or antiparallel to the magnetization direction of the fixed layer 321a3, i.e., information is written. When the magnetization direction of the free layer 321a1 is parallel to the magnetization direction of the fixed layer 321a3, the MTJ has a low resistance characteristic; when the two are antiparallel, the MTJ has a high resistance characteristic, i.e., the MTJ exhibits a tunneling magnetoresistance (tunneling magneto resistance, TMR) effect. The high and low resistance characteristics of an MTJ represent two different logical informations (e.g., "0" or "1"). When the data stored in the MTJ is read, it is possible to determine what kind of logic information is stored in the MTJ by judging the level of the MTJ resistance. Thereby realizing the read-write function of the MRAM.

The upper and lower ends of the MTJ are electrically connected to Word Lines (WL) and Bit Lines (BL) that are perpendicular to each other, respectively. By applying a voltage between WL and BL, a magnetic field is generated when a current passes through WL and BL, and the magnetization direction of the free layer is changed by the magnetic field.

The magnetization direction of the free layer in MRAM changes upon excitation by a magnetic field/current. Thus, MRAM is caused to be exceptionally sensitive to external magnetic fields. The external magnetic field may be a magnetic field generated by other chips in the electronic device, or may be a magnetic field in an external environment where the electronic device is located, for example, a magnetic field in a market trip, a household small magnet, a double-sided glass wiper, etc. in a daily life scene. Depending on the magnetic field strength, the distance between the MRAM and the magnetic signal source, etc., different degrees of influence may be exerted on the MRAM, for example, causing increased power consumption, reverse magnetic poles, information loss, etc., which may seriously cause irreversible failure of the MRAM.

Therefore, in order to improve the reliability of the operation of the MRAM chip, the interference of the external magnetic field to the normal operation of the MRAM chip is prevented. The design of anti-magnetic interference for such chips is becoming increasingly important.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a circuit board assembly 3 provided in the related art. The circuit board assembly 3 includes a circuit board 31, a packaged chip structure 32, and a metal shield 33. The packaged chip structure 32 includes a substrate 323, a chip 321, and a molding layer 322a. The chip 321 is disposed on the substrate 323, and the molding layer 322a is disposed on the substrate 323 and encapsulates the chip 321. The package chip structure 32 is disposed on the circuit board 31. The metal shielding case 33 is disposed on the circuit board 31, and covers the package chip structure 32. Thereby achieving the purpose of magnetic shielding of the chip 321.

However, the above structural form has the following drawbacks:

first, the magnetic field shielding effect is poor, and it cannot be guaranteed that the magnetic field strength entering the chip 321 through the metal shielding case 33 is lower than the failure threshold of the chip 321 in a strong magnetic field environment.

Secondly, the volume of the metal shielding case 33 is relatively large, and in addition, an assembly gap often exists between the metal shielding case 33 and the packaging chip structure 32, which results in relatively large volume occupied by the metal shielding case 33 and the packaging chip structure 32 as a whole, and is not beneficial to the miniaturization design of the electronic device 100; in addition, the weight of the metal shield 33 is also relatively large, which is disadvantageous in the lightweight design of the electronic device 100.

Third, since the circuit board 31 is often provided with the other packaged chips 321 except for the packaged chip structure 32, when the packaged chip structure 32 is covered with the metal shield 33, it is necessary to consider avoidance between the metal shield 33 and the other packaged chips adjacent to the packaged chip structure 32. That is, compatibility between the metal shield 33 and the external shape of other packaged chips needs to be considered, which results in a complicated structure of the metal shield 33, which is disadvantageous in production and manufacture of the metal shield 33.

Fourth, in order to facilitate input/output of signals and power sources on the circuit board 31, wiring openings are often provided on the metal shield 33, which necessarily results in a reduction in the shielding effect of the metal shield 33.

In order to solve the technical problems, the application provides a packaged chip structure which can package a chip and has a magnetic field shielding function. In the application, the plastic package shielding body is used for replacing the plastic package layer in the previous description, and the plastic package shielding body not only can realize plastic package of the chip so as to achieve the aim of water resistance and dust resistance, but also can play a role of shielding a magnetic field. Meanwhile, a magnetic guide layer for magnetic shielding is arranged between the plastic package shielding body and the chip. Namely, the magnetic conduction layer and the plastic package shielding body are utilized to form a multi-layer magnetic field shielding layer, so that a chip in a strong magnetic field environment can be well shielded and protected, and the magnetic field shielding effect on the chip is improved. And when this encapsulation chip structure sets up on the circuit board, need not to set up the metal shield in addition on the circuit board to be favorable to reducing the whole volume and the weight of circuit board and encapsulation chip structure, realize electronic equipment's miniaturization and lightweight design. In addition, avoidance between the metal shielding case and other packaging chips adjacent to the metal shielding case in the related art is not needed to be considered, so that layout space on a circuit board is saved, and more electronic components are integrated on the circuit board.

The following describes the structure of the packaged chip provided by the application in a specific application scenario.

The present application provides an electronic device including, but not limited to, wearable devices (e.g., watches, bracelets, glasses, etc.), cell phones, tablet computers (tablet personal computer), laptop computers (lap computers), personal Digital Assistants (PDAs), personal computers, notebook computers (notebooks), in-vehicle devices, etc.

Referring to fig. 3, fig. 3 is a schematic structural diagram of an electronic device 100 according to some embodiments of the application. In this embodiment, the electronic device 100 is a wristwatch or a bracelet. In this embodiment, the electronic device 100 includes a wristband 1 and a main body portion 2.

It is to be understood that fig. 3 and the following related drawings only schematically illustrate some components comprised by the electronic device 100, and the actual shape, actual size, actual position and actual configuration of these components are not limited by fig. 3 and the following drawings. Also, when the electronic device is another type of electronic device such as a mobile phone, the electronic device may not include the wristband 1.

For convenience of description of the embodiments below, an XYZ coordinate system is established. Specifically, the thickness direction of the electronic device 100 is the Z-axis direction. The two directions perpendicular to the Z-axis direction are the X-axis direction and the Y-axis direction, respectively, and it is understood that the coordinate system of the electronic device 100 may be flexibly set according to actual needs, which is not specifically limited herein.

The wristband 1 may comprise a first wristband 11 and a second wristband 12. The first band 11 and the second band 12 may be provided on opposite sides of the main body portion 2 in the Y-axis direction.

The first band 11 is provided with a first locking portion 111. The second band 12 is provided with a second locking portion 121. The first and second locking parts 111 and 121 are detachably locked to each other to wear the electronic device 100 on the wrist of the user. It should be understood that the mating structure between the first locking portion 111 and the second locking portion 121 may be a clasp, a hidden clasp, a butterfly clasp, a folding safety clasp, a folding clasp, or a needle clasp, which is not particularly limited in the present application. The material of the wristband 1 includes, but is not limited to, plastic, rubber or dermis.

Referring to fig. 4 and 5, fig. 4 is a perspective view of the main body 2 in the electronic device 100 shown in fig. 3, and fig. 5 is an exploded view of the main body 2 shown in fig. 4. The main body part 2 may include a display module 21, a housing 22, a circuit board assembly 3, and a battery 4.

It will be appreciated that fig. 4 and 5 and the following related drawings only schematically illustrate some of the components comprised by the body portion 2, the actual shape, actual size, actual position and actual configuration of which are not limited by fig. 4 and 5 and the following drawings.

With continued reference to fig. 5, the display module 21 includes a screen 211 and a bezel 212. A bezel 212 surrounds the periphery of the screen 211. The bezel 212 may protect and decorate the periphery of the screen 211. It will be appreciated that in other examples, the display module 21 may not be provided with the bezel 212.

The screen 211 is used to display images, video, data, and the like. The screen 211 may be a flexible display screen or a rigid display screen. For example, the screen 211 may be an organic light-emitting diode (OLED) display screen, an active-matrix organic light-emitting diode (AMOLED) display screen, a mini-light-emitting diode (mini organic light-emitting diode) display screen, a micro-light-emitting diode (micro organic light-emitting diode) display screen, a micro-organic light-emitting diode (micro organic light-emitting diode) display screen, a quantum dot LIGHT EMITTING diodes (QLED) display screen, a liquid crystal display (liquid CRYSTAL DISPLAY, LCD).

The shape of the screen 211 is not limited in the present application. The display surface of the screen 211 may be circular or rectangular, for example. When the shape of the screen 211 is changed, the shape of other parts of the main body part 2, such as the case 22 and the bezel 212, also changes with the shape of the screen 211.

The housing 22 has an accommodating space therein, and the housing 22 is used for accommodating and protecting the internal structure of the electronic device 100. With continued reference to fig. 4 and 5, the housing 22 may include a back shell 22a and a rim 22b. The back shell 22a and the screen 211 are arranged in the Z-axis direction and are disposed at intervals. The frame 22b surrounds the outer periphery of the back shell 22a and is located between the back shell 22a and the screen 211. The frame 22b is fixed to the back shell 22 a. Illustratively, the bezel 22b may be fixedly attached to the back shell 22a by adhesive. The frame 22b may also be integrally formed with the back shell 22a, i.e., the frame 22b and the back shell 22a are a unitary structure. The decorative ring 212 of the display module 21 is fixed on the frame 22b. In some embodiments, bezel 212 may be secured to bezel 22b by adhesive. The accommodation space in the housing 22 may be surrounded by the back shell 22a and the frame 22b. The display module 21 covers the opening of the accommodation space. The accommodation space accommodates the circuit board assembly 3, the battery 4, and the like therein.

It is understood that the forming manner of the housing 22 is not limited thereto, and in other examples, when the electronic device 100 does not include the display module 21, the housing 22 may be a closed housing 22.

The battery 4 is provided in the accommodation space. The battery 4 is used to supply power to the screen 211, the circuit board assembly 3, and the like. The battery 4 includes, but is not limited to, a lithium battery and a lead-acid battery.

The circuit board assembly 3 is located in the accommodation space. In the Z-axis direction, the circuit board assembly 3 is between the battery 4 and the screen 211. Of course, it will be appreciated that in other examples, the circuit board assembly 3 may also be located between the battery 4 and the back shell 22a in the Z-axis direction.

Referring to fig. 6, fig. 6 is a schematic diagram of the circuit board assembly 3 in the main body 2 shown in fig. 5. The circuit board assembly 3 may include a circuit board 31 and a packaged chip structure 32.

It will be appreciated that fig. 6 and the following related drawings only schematically illustrate some of the components comprised by the circuit board assembly 3, the actual shape, actual size, actual position and actual configuration of which are not limited by fig. 6 and the following drawings.

The circuit board 31 has a first face 311 and a second face 312 disposed opposite to each other in the own thickness direction (i.e., Z-axis direction). Wherein the first face 311 may be directed towards the screen 211 described above. The second face 312 may face the back shell 22a. In other examples, the first face 311 may face the back shell 22a described above. The second face 312 may be oriented toward the screen 211.

The circuit board 31 may be a printed circuit (Printed Circuit Board, PCB) board or a flexible circuit (Flexible Printed Circuit, FPC) board, for example.

The package chip structure 32 may be disposed on the first surface 311 of the circuit board 31 and electrically connected to the circuit board 31. Thereby enabling the packaged chip structure 32 to communicate signals with other chips 321 or other modules on the circuit board 31. The number of the package chip structures 32 on the circuit board 31 is not limited in the present application, and may be one, two or more.

Specifically, referring to fig. 6, the package chip structure 32 is fixed to the first surface 311 of the circuit board 31 by the electrical connection structure 34, and is electrically connected to the circuit board 31. The electrical connection 34 may be a Ball Grid Array (BGA) GRID ARRAY.

With continued reference to fig. 6, the packaged chip structure 32 includes a chip 321, a substrate 323, a magnetic conductive layer 324, and a plastic package shield 322b.

The chip 321 may be MRAM, or may be a radio frequency chip, a WiFi chip, or a power chip, which needs to perform magnetic shielding. In addition, the chip 321 may be a bare chip (i.e., SINGLE DIE), or may be a packaged chip obtained by packaging one or more bare chips.

The substrate 323 has a first surface 3231 and a second surface 3232 disposed opposite to each other in its own thickness direction (i.e., Z-axis direction). Illustratively, the substrate 323 may be a printed circuit board or a flexible circuit board.

The chip 321 is disposed on the first surface 3231 and electrically connected to the substrate 323. The first surface 3231 is a surface of the substrate 323 facing away from the circuit board 31. The second surface 3232 faces the first surface 311. The electrical connection structure 34 is connected between the second surface 3232 and the first surface 311.

The insulating layer 325 is disposed on the first surface 3231 and covers the chip 321. Specifically, the insulating layer 325 may be manufactured by an injection molding (molding) process, and the insulating layer 325 thus manufactured may be attached to the first surface 3231 and the chip 321. Thus, the protection effect of the insulating layer 325 on the chip 321 is improved.

Exemplary materials for insulating layer 325 include, but are not limited to, epoxy and polyimide. Of course, other materials may be used.

The magnetically permeable layer 324 is on a side of the insulating layer 325 remote from the chip 321 and covers the insulating layer 325. Thus, the magnetic conductive layer 324 and the chip 321 can be isolated by the insulating layer, so that the magnetic conductive layer 324 and the chip 321 can be prevented from being short-circuited, and further, the circuit failure of the chip 321 is avoided.

The plastic package shielding body 322b is encapsulated on the first surface 3231 and covers the magnetic conductive layer 324. Wherein the plastic package shield 322b includes a resin matrix and a magnetic shielding filler. Exemplary materials for the resin matrix include, but are not limited to, epoxy or polyimide. The magnetic shielding filler is distributed in the resin matrix so that the plastic package shielding body 322b can have a magnetic shielding effect.

Therefore, the plastic package shielding body 322b is utilized to replace a plastic package layer in the related technology, so that the chips 321 can be packaged on the substrate 323, the purposes of water resistance and dust resistance are achieved, and the magnetic field shielding effect can be achieved. The plastic package shielding body 322b also encapsulates the magnetically conductive layer 324, so that the magnetic field in the external environment where the chip 321 is located can be shielded by the magnetic shielding filler in the plastic package shielding body 322b without increasing the thickness of the packaged chip structure 32, so that the magnetic field strength of the magnetic field entering the magnetically conductive layer 324 is weakened, and then the magnetic field is further shielded by the magnetically conductive layer 324, so that the magnetic field strength of the magnetic field entering the chip 321 is further reduced. That is, the magnetic field in the external environment where the packaging chip structure 32 is located is shielded by the multi-layer shielding layer, which is favorable for improving the magnetic shielding effect on the chip 321, so that the chip 321 can still work normally even in a higher magnetic field environment, especially, when the chip 321 is an MRAM, the power consumption of the MRAM can be reduced, the information loss of the MRAM is prevented, and the occurrence of irreversible failure of the MRAM is avoided.

And, based on the multilayer shielding effect that the packaging chip structure 32 itself has, thereby need not to set up the metal shield that is used for covering the packaging chip structure 32 in addition on the circuit board 31, be favorable to the cost reduction, need not to consider the metal shield 33 among the related art and the problem of dodging between this metal shield 33 and other packaging chips adjacent to this metal shield 33, saved the space that metal shield 33 occupy on the circuit board 31, be favorable to reducing the overall size and the weight of circuit board assembly 3, save the overall arrangement space on the circuit board 31, then be favorable to realizing miniaturized design and the lightweight design of electronic equipment 100, still be favorable to integrating more electronic components on the circuit board 31.

In addition, based on the good shielding effect of the package chip structure 32, more possibilities are provided for the layout of the chip 321 on the circuit board 31, which is beneficial to avoiding the situation that the two chips 321 need to be set far because of serious mutual interference, and avoiding the situation that the chip 321 needs to be set close to the center of the electronic device 100 because the chip 321 needs to be kept at a certain distance from the magnetic field in the external environment where the electronic device 100 is located. In addition, the doping of the magnetic shielding filler in the plastic package shielding body 322b is also beneficial to improving the structural strength and toughness of the plastic package shielding body 322 b.

In some embodiments, the saturation induction of the plastic encapsulated shield 322b is different from the saturation induction of the magnetically permeable layer 324, and the magnetic permeability of the plastic encapsulated shield 322b is different from the magnetic permeability of the magnetically permeable layer 324. In this way, the multilayer shielding layer is beneficial to have the characteristics of high magnetic permeability and difficult magnetic saturation on the whole, so that the magnetic shielding effect of the packaged chip structure 32 is beneficial to be further optimized.

In some specific examples, the saturation induction of the plastic encapsulated shield 322b is greater than the saturation induction of the magnetically permeable layer 324, and the magnetic permeability of the plastic encapsulated shield 322b is less than the magnetic permeability of the magnetically permeable layer 324. Specifically, magnetic saturation tends to occur more easily due to the shielding layer having high magnetic permeability, by making the saturation induction of the plastic-sealed shielding body 322b larger than that of the magnetic conductive layer 324, and the magnetic permeability of the plastic-sealed shielding body 322b smaller than that of the magnetic conductive layer 324. Therefore, the plastic package shielding body 322b which is not easy to be magnetically saturated can be adopted to initially weaken the external magnetic field intensity. Because the plastic package shielding body 322b primarily weakens the magnetic field, the inner magnetic conductive layer 324 is not easy to reach magnetic saturation, the possibility of the magnetic saturation of the magnetic conductive layer 324 is reduced, the magnetic field is greatly weakened by the magnetic conductive layer 324 with high magnetic conductivity, and the shielding effect is greatly improved.

Of course, it is understood that in other examples, the saturation induction of the plastic encapsulated shielding body 322b may also be less than the saturation induction of the magnetic conductive layer 324, and the magnetic permeability of the plastic encapsulated shielding body 322b is greater than the magnetic permeability of the magnetic conductive layer 324. Alternatively, the saturation induction of the plastic-sealed shield 322b may be equal to the saturation induction of the magnetically permeable layer 324, and the permeability of the plastic-sealed shield 322b may be equal to the permeability of the magnetically permeable layer 324.

It should be appreciated that the difference in magnetic permeability and saturation induction between the plastic encapsulated shielding body 322b and the magnetic conductive layer 324 may be achieved by a difference in at least one of appearance, size, material, and process between the plastic encapsulated shielding body 322b and the magnetic conductive layer 324. The difference in appearance may be a difference in shape between the plastic shielding body 322b and the magnetic conductive layer 324. The difference in size refers to the difference in thickness between the two. Process variations include, but are not limited to, process variations of the two, variations in process parameters, and the like.

To provide a difference in magnetic permeability and saturation induction between the plastic encapsulated shield 322b and the magnetically permeable layer 324, in some embodiments, the material of the magnetic shielding filler is pure iron, and/or silicon steel. That is, the magnetic shielding filler may be pure iron particles, silicon steel particles, or both pure iron and silicon steel. Pure iron and silicon steel have higher saturation induction intensity, so that the plastic package shielding body 322b is favorable to have higher saturation induction intensity, the plastic package shielding body 322b is less likely to generate magnetic saturation in a strong magnetic environment, and the pure iron and silicon steel are low in price, so that the processing and manufacturing cost of the packaged chip structure 32 is reduced.

To provide a difference in magnetic permeability and saturation induction between plastic encapsulated shield 322b and magnetically permeable layer 324, in some embodiments, magnetically permeable layer 324 is a soft magnetic material. Because the magnetic permeability of the soft magnetic material is higher, when the material of the magnetic conductive layer 324 is soft magnetic material, the magnetic conductive layer 324 has higher magnetic permeability, which is beneficial to improving the shielding effect.

In some embodiments, the soft magnetic material is a soft magnetic alloy material and/or ferrite. Wherein the soft magnetic alloy material is at least one of nickel-iron alloy (also called permalloy), silicon-iron alloy, iron-silicon-chromium alloy and cobalt-iron alloy. That is, the soft magnetic alloy material is nickel-iron alloy, silicon-iron alloy, iron-silicon-chromium alloy or cobalt-iron alloy; the soft magnetic alloy material may also be two, three or all of nickel-iron alloy, silicon-iron alloy, iron-silicon-chromium alloy and cobalt-iron alloy. Thus, not only is the shielding effect improved, but also the material price is low, and the processing and manufacturing cost of the packaged chip structure 32 is reduced.

To provide a difference in magnetic permeability and saturation induction between the plastic encapsulated shield 322b and the magnetically permeable layer 324, in some embodiments, the thickness of the plastic encapsulated shield 322b is greater than the thickness of the magnetically permeable layer 324. In this way, it is beneficial to ensure that the plastic package shielding body 322b has a relatively thicker thickness, and to increase the weight of the magnetic shielding filler compared with the thinner thickness of the plastic package shielding body 322b, thereby being beneficial to improving the magnetic permeability and the saturation magnetic induction intensity of the plastic package shielding body 322b and further improving the shielding effect.

Here, it should be noted that the thickness of the plastic package shielding body 322b refers to a dimension between a surface of the plastic package shielding body 322b facing away from the chip 321 and a surface facing the magnetic conductive layer 324. Similarly, the thickness of the magnetically permeable layer 324 refers to the dimension between the surface of the magnetic layer 324 facing the insulating layer 325 and the surface of the magnetically permeable layer 324 facing the plastic molded shield 322 b.

In some embodiments, the weight portion of the magnetic shielding filler is 30-90 parts in 100 parts by weight of the plastic molded shield 322 b. In this way, on the one hand, the packaging effect of the plastic packaging shielding body 322b is guaranteed, and on the other hand, the shielding effect of the plastic packaging shielding body 322b is improved.

The weight portion is the mass ratio of each of several substances, and 1 part is taken as an example, the mass of the plastic package shielding body 322b is 100g, and the mass of the magnetic shielding filler is 30g to 90g. That is, when the mass of the plastic molded shield 322b is 100g, the mass of the magnetic shielding filler is any value of 30g to 90g.

Illustratively, the weight parts of the magnetic shielding filler are 35, 40, 45, 50, 55, 60, 65, 70, 75, 80 or 85 parts when the weight parts of the plastic package shield 322b are 100 parts.

Of course, it is understood that in other examples, the weight relationship of the plastic package shield 322b and the magnetic shielding filler may be other parameter values, for example, 20 parts, 25 parts or 95 parts of the magnetic shielding filler in 100 parts by weight of the plastic package shield 322 b.

In some embodiments, the magnetic shielding filler may be in particulate form. Thus, the granular magnetic shielding filler is more easily uniformly distributed in the resin matrix, thereby improving the uniformity of the magnetic permeability and the magnetic saturation strength of the plastic-sealed shield 322 b. In other examples, the magnetic shielding filler may also be in the form of a wire or sheet.

In some examples, the equivalent diameter of the magnetic shielding filler is on the order of nanometers. That is, the equivalent diameter of the magnetic shielding filler is 1 nanometer (nm) or more and less than 1000nm. In particular, the equivalent dip of the magnetic shielding filler can be 5nm, 10nm, 20nm, 100nm, 200nm, 400nm, 500nm, 650nm, 800nm, 900nm or 950nm. Thus, on one hand, the uniformity of the distribution of the magnetic shielding filler in the resin matrix is facilitated, on the other hand, the distribution density of the magnetic shielding filler in the resin matrix is facilitated to be improved, the magnetic induction intensity and the magnetic permeability of the plastic package shielding body 322b can be improved through the two aspects, and the shielding effect of the plastic package shielding body 322b is improved. In addition, the structural strength of the plastic package shielding body 322b is further improved.

In other examples, the equivalent diameter of the magnetic shielding filler may also be on the order of micrometers. That is, the equivalent diameter of the magnetic shielding filler is greater than or equal to 1 micrometer (um) and less than 1000um. Specifically, the equivalent of the magnetic shielding filler may be 5um, 10um, 20um, 100um, 200um, 500um, 800um, 900um, or 950um. Thus, the processing cost of the magnetic shielding filler is low, which is beneficial to reducing the overall manufacturing cost of the packaged chip structure 32.

In some embodiments, in order to achieve both the shielding effect of the plastic package shielding body 322b and the processing and manufacturing cost of the magnetic shielding filler, the equivalent diameter of the magnetic shielding filler is in the range of 500nm to 50um, that is, 500nm to 50000nm. Illustratively, the equivalent diameter of the magnetic shielding filler ranges from 800nm to 30um.

Equivalent diameter refers to Equivalent Sphere Diameter (ESD) SPHERICAL DIAMETER, which refers to an irregularly shaped object that has the same volume as the diameter of a sphere. The equivalent diameter of the magnetic shielding filler is the diameter of a sphere with the same volume as the outer surface of the magnetic shielding filler. When the magnetic shielding filler is spherical, the equivalent diameter is the outer diameter of the magnetic shielding filler.

In some embodiments, the magnetically permeable layer 324 is attached to the surface of the insulating layer 325 by a spray process or a printing process. Since the plastic-sealed shielding body 322b is formed by injection molding, the processing process of the magnetic conductive layer 324 is different from the processing process of the plastic-sealed shielding body 322b, so that the difference between the magnetic permeability and the saturation induction intensity between the plastic-sealed shielding body 322b and the magnetic conductive layer 324 is facilitated by the difference of the processing processes. Furthermore, the spraying process or the printing process is simple and the cost is low.

Of course, the application is not limited in this regard, and in other embodiments, the magnetically permeable layer 324 may be bonded to the insulating layer 325 by a glue layer (not shown). Therefore, the connecting process is simple, the cost is low, and the processing efficiency is improved.

With continued reference to fig. 6, in some embodiments, the packaged chip structure 32 further includes a first bottom shielding layer 326. The first bottom shielding layer 326 is disposed between the first surface 3231 and the chip 321. The orthographic projection of the chip 321 on the first bottom shielding layer 326 is located within the outer peripheral outline of the first bottom shielding layer 326. In this way, the first bottom shielding layer 326, the plastic package shielding body 322b and the magnetic conductive layer 324 can be advantageously utilized to form a magnetic shielding structure surrounding the chip 321, thereby being advantageous to further improve the magnetic shielding effect on the chip 321.

Illustratively, the first bottom shield 326 is bonded to the first surface 3231 with a first insulating glue (not shown). In this way, on the one hand, the first bottom shielding layer 326 and the first surface 3231 can be relatively fixed, and on the other hand, the first insulating glue can be used to perform an insulating function, so that a short circuit between the substrate 323 and the first bottom shielding layer 326 is prevented, and the reliability of the operation of the packaged chip structure 32 is improved.

Illustratively, the chip 321 is bonded to the first bottom shielding layer 326 using a second insulating adhesive. In this way, on the one hand, the relative fixation between the first bottom shielding layer 326 and the chip 321 can be realized, and on the other hand, the second insulating adhesive can also be utilized to play an insulating role, so that the short circuit between the chip 321 and the first bottom shielding layer 326 is prevented, and the reliability of the operation of the packaged chip structure 32 is improved.

In some embodiments, the material of the first bottom shielding layer 326 is a soft magnetic material. Because the magnetic permeability of the soft magnetic material is higher, when the material of the first bottom shielding layer 326 is the soft magnetic material, the first bottom shielding layer 326 has higher magnetic permeability, and the shielding effect is improved.

Illustratively, the soft magnetic material is a soft magnetic alloy material and/or ferrite. Wherein the soft magnetic alloy material is at least one of nickel-iron alloy, silicon-iron alloy, iron-silicon-chromium alloy and cobalt-iron alloy. That is, the soft magnetic alloy material is nickel-iron alloy, silicon-iron alloy, iron-silicon-chromium alloy or cobalt-iron alloy; the soft magnetic alloy material may also be two, three or all of nickel-iron alloy, silicon-iron alloy, iron-silicon-chromium alloy and cobalt-iron alloy. Thus, not only is the shielding effect improved, but also the material price is low, and the processing and manufacturing cost of the packaged chip structure 32 is reduced.

Specifically, the first bottom shielding layer 326 is made of nickel-iron alloy, which is not only beneficial to improving the magnetic permeability of the first bottom shielding layer 326, but also facilitates the forming of the first bottom shielding layer 326.

Since the first bottom shielding layer 326 is located between the first surface 3231 and the chip 321, in order to facilitate the fixing of the chip 321 and the electrical connection between the chip 321 and the substrate 323, a Wire Bonding (also called Wire Bonding) process may be used to electrically connect the chip 321 and the substrate 323. Specifically, with continued reference to fig. 6, and in conjunction with fig. 7, fig. 7 is a schematic top view of the circuit board assembly 3 according to fig. 6, only the substrate 323, the chip 321, the first bottom shielding layer 326 and the bonding wires 327 are shown in fig. 7. The first surface 3231 has pads 32311. The pad 32311 is on the outer peripheral side of the first bottom shield 326. The chip 321 has a circuit surface 3211. The circuit surface 3211 faces away from the substrate 323. The packaged chip structure 32 also includes bonding wires 327. One end of the bonding wire 327 is fixed to the circuit surface 3211 and electrically connected to the chip 321. The other end of the bonding wire 327 is fixed to a pad 32311 and is electrically connected to the substrate 323. In this way, the connection process between the substrate 323 and the chip 321 is simple, high in efficiency and low in cost.

On this basis, to achieve protection of bond wire 327 and bond pad 32311, please continue to refer to fig. 6, insulating layer 325 covers bond wire 327 and bond pad 32311. In this way, the insulating layer 325 is beneficial to further protecting the electrical connection between the chip 321 and the substrate 323, so that the bonding wire 327 cannot penetrate the plastic package shielding body 322b and the magnetic conductive layer 324, thereby preventing the magnetic leakage problem. It is advantageous to shorten the length of the bonding wire 327, that is, to shorten the signal and power paths, thereby facilitating an increase in the operating speed of the chip. For example, for MRAM, it is advantageous to secure the speed of data reading, writing, and erasing.

It will be appreciated that when the insulating layer 325 is formed by an injection molding process, the insulating layer 325 is bonded to the first surface 3231 and the chip 321 and also bonded to the surface of the bonding wire 327 and the bonding pad 32311, that is, the insulating layer 325 does not only cover and bond to the surface of the bonding wire 327 and the bonding pad 32311, but also fills the space around the bonding wire 327 and encapsulates the bonding wire 327. Thus, the protective effect of the insulating layer 325 is advantageously improved.

Referring to fig. 8, fig. 8 is a schematic diagram of a circuit board assembly 3 according to another embodiment of the application. This embodiment differs from the embodiment shown in fig. 6 in that: the packaged chip structure 32 also includes a second bottom shield layer 328. The second bottom shielding layer 328 is stacked between the first bottom shielding layer 326 and the first surface 3231, and the insulating layer 325 also covers the second bottom shielding layer 328. In this way, the first bottom shielding layer 326, the second bottom shielding layer 328, the plastic-sealed shielding body 322b, and the magnetic conductive layer 324 can be advantageously integrated to form a multi-layer magnetic shielding structure surrounding the chip 321, thereby further improving the magnetic shielding effect on the chip 321. It will be appreciated that in other examples, the second bottom shield layer 328 may not be provided.

On this basis, when the packaged chip structure 32 further includes the bonding wires 327 and the pads 32311 described above, the pads 32311 are at the outer periphery of the second bottom shield layer 328. Thereby facilitating the secure connection of bond wire 327 to bond pad 32311 and preventing interference with the securement of second bottom shield 328 therebetween.

Illustratively, the second bottom shield 328 is bonded to the first surface 3231 with a third insulating adhesive. In this way, on the one hand, the second bottom shielding layer 328 and the first surface 3231 can be relatively fixed, and on the other hand, the third insulating adhesive can also be used to perform an insulating function, so that the short circuit between the substrate 323 and the second bottom shielding layer 328 is prevented, and the reliability of the operation of the packaged chip structure 32 is improved.

Illustratively, the first bottom shield 326 is bonded to the second bottom shield 328 using a first insulating glue. In this way, a relative fixation between the first bottom shield 326 and the second bottom shield 328 may be achieved.

In some embodiments, the saturation induction of the second bottom shielding layer 328 is different than the saturation induction of the first bottom shielding layer 326, and the magnetic permeability of the second bottom shielding layer 328 is different than the magnetic permeability of the first bottom shielding layer 326. In this way, the first bottom shielding layer 326 and the second bottom shielding layer 328 are beneficial to have the characteristics of high magnetic permeability and less susceptibility to magnetic saturation as a whole, thereby being beneficial to further optimizing the shielding effect.

Specifically, the saturation induction of the second bottom shielding layer 328 is greater than the saturation induction of the first bottom shielding layer 326, and the magnetic permeability of the second bottom shielding layer 328 is less than the magnetic permeability of the first bottom shielding layer 326. Specifically, magnetic saturation tends to occur more easily due to the shielding layer having high magnetic permeability, by making the saturation induction intensity of the second bottom shielding layer 328 larger than that of the first bottom shielding layer 326, and the magnetic permeability of the second bottom shielding layer 328 smaller than that of the first bottom shielding layer 326. Therefore, the second bottom shielding layer 328 which is not easy to be saturated in magnetism can be adopted to weaken the external magnetic field strength preliminarily, and the second bottom shielding layer 328 weakens the magnetic field preliminarily, so that the first bottom shielding layer 326 inside is not easy to be saturated in magnetism, the possibility of the first bottom shielding layer 326 being saturated in magnetism is reduced, the first bottom shielding layer 326 with high magnetic conductivity can weaken the magnetic field greatly, and the shielding effect is improved greatly.

In some embodiments, to further enhance the magnetic shielding effect, the orthographic projection of the first bottom shielding layer 326 on the first surface 3231 is located within the orthographic projection of the second bottom shielding layer 328 on the first surface 3231. Of course, it is understood that in other examples, the front projection of the first bottom shielding layer 326 on the first surface 3231 may coincide with the front projection of the second bottom shielding layer 328 on the first surface 3231.

In some embodiments, the material of the second bottom shielding layer 328 is pure iron, and/or silicon steel. That is, the second bottom shielding layer 328 may be made of pure iron, silicon steel, or a combination of pure iron and silicon steel. Pure iron and silicon steel both have higher saturation induction intensity, thereby being favorable for the second bottom shielding layer 328 to have higher saturation induction intensity, so that the second bottom shielding layer 328 is less likely to generate magnetic saturation in a strong magnetic environment, and the pure iron and silicon steel are low in price, thereby being favorable for reducing the manufacturing cost of the packaged chip structure 32.

Referring to fig. 9, fig. 9 is a schematic diagram of a circuit board assembly 3 according to still other embodiments of the present application. This embodiment differs from the embodiment shown in fig. 6 in that: the insulating layer 325 is a double-sided tape. One side surface of the insulating layer 325 is adhered to the first surface 3231 and covers the chip 321, the first bottom shielding layer 326 and the bonding wire 327, and the insulating layer 325 does not wrap the surface of the bonding wire 327. The other side surface of the insulating layer 325 is bonded to the magnetically conductive layer 324. In this way, by providing the insulating layer 325 as a double-sided tape, the connection process between the insulating layer 325 and the first surface 3231 and between the insulating layer 325 and the magnetic conductive layer 324 is simplified, and the cost is reduced.

It is understood that the manner of forming the insulating layer 325 is not limited thereto, and in other examples, the insulating layer 325 may also be a rigid insulating cover. The rigid insulating cover encloses the chip 321, the second shielding layer and the leads. Illustratively, when the insulating layer 325 is a rigid insulating cover, the material of the insulating layer 325 includes, but is not limited to, plastic.

Referring to fig. 10, fig. 10 is a schematic diagram of a circuit board assembly 3 according to some other embodiments of the present application, and a dashed box in fig. 10 is a schematic diagram of a shielding member 5. This embodiment differs from the embodiment shown in fig. 3-9 in that: no magnetic shielding structure (e.g., the first bottom shielding layer 326 and the second bottom shielding layer 328, as described above) is provided between the chip 321 and the substrate 323.

On the basis of this, in order to improve the magnetic shielding effect on the chip 321, please continue to refer to fig. 10, and fig. 11 is a schematic exploded view of the main body 2 in the electronic device 100 using the circuit board assembly 3 shown in fig. 10. The electronic device 100 further comprises a shield 5. The shield 5 is on the side of the circuit board 31 remote from the packaged chip structure 32, i.e. the side of the shield 5 towards which the second face 312 is facing. The orthographic projection of the packaged chip structure 32 in the plane of the first surface 3231 is located in the orthographic projection of the metallic magnetic shield 5 in the plane of the first surface 3231. In this way, when no shielding structure is provided between the chip 321 and the substrate 323, the shielding member 5 on the side of the circuit board 31 away from the packaged chip structure 32 can be used for magnetic shielding, so that the shielding effect against the magnetic field from the side of the circuit board 31 away from the packaged chip structure 32 can be improved at least to some extent.

It will be appreciated that in other examples, a portion of the orthographic projection of the packaged chip structure 32 on the plane of the first surface 3231 coincides with a portion of the orthographic projection of the shield 5 on the plane of the first surface 3231, or the orthographic projection of the packaged chip structure 32 on the plane of the first surface 3231 coincides entirely with the orthographic projection of the shield 5 on the plane of the first surface. Or the front projection of the shield 5 on the plane of the first surface 3231 is within the front projection of the packaged chip structure 32 on the plane of the first surface 3231. As long as it is ensured that the orthographic projection of the packaged chip structure 32 onto the plane of the first surface 3231 overlaps (i.e. at least partially overlaps) the orthographic projection of the shielding member 5 onto the plane of the first surface 3231.

It should be appreciated that, in other examples, when the first bottom shielding layer 326 is disposed between the chip 321 and the substrate 323, or the first bottom shielding layer 326 and the second bottom shielding layer 328 are disposed simultaneously, the shielding member 5 may also be disposed on the side of the circuit board 31 away from the packaged chip structure 32, where the shielding effect of the magnetic field from the side of the circuit board 31 away from the packaged chip structure 32 can be further improved.

In some specific examples, the shield 5 may be defined by a portion of the housing 22 in order to reasonably optimize the structural layout of the electronic device 100. For example, the shield 5 may be defined by a portion of the back shell 22a in the foregoing, or by the entire back shell 22 a.

Of course, the shield 5 may be a structure that is additionally provided in the housing 22. In this case, the shield 5 may be positioned between the battery 4 and the circuit board 31, for example, so that the shield 5 may be positioned close to the circuit board 31, thereby improving the magnetic shielding effect of the shield 5 on the chip 321. Of course, in other examples, the metallic magnetic shield 5 may also be between the back shell 22a and the battery 4.

Specifically, the shielding member 5 is made of soft magnetic material. Because the magnetic permeability of the soft magnetic material is higher, when the material of the shielding piece 5 is the soft magnetic material, the shielding piece 5 has higher magnetic permeability, and the shielding effect is improved. Illustratively, the soft magnetic material is a soft magnetic alloy material and/or ferrite; wherein the soft magnetic alloy material is at least one of nickel-iron alloy, silicon-iron alloy, iron-silicon-chromium alloy and cobalt-iron alloy. Thus, not only is the shielding effect improved, but also the material price is low, and the processing and manufacturing cost of the packaged chip structure 32 is reduced. Of course, in other examples, the material of the shielding member 5 may be metal, such as copper.

The following describes a method for processing the packaged chip structure provided by the application.

The application also provides a processing method of the packaged chip structure in the embodiment. Referring to fig. 12, fig. 12 is a flowchart illustrating a method for processing a packaged chip structure according to some embodiments of the application. The processing method comprises the following steps:

S10: the chip is disposed on the first surface of the substrate.

S20: covering an insulating layer and a magnetic conductive layer on the surface of the chip; wherein the insulating layer is connected to the first surface and is between the magnetically permeable layer and the chip. The insulating layer can insulate the magnetically conductive layer from the chip, thereby playing a role in isolating and protecting the chip.

S30: fully mixing the first packaging material and the magnetic shielding filler to prepare plastic packaging slurry; and setting the plastic package slurry on the first surface through an injection molding process, and enabling the plastic package slurry to cover the magnetic conduction layer so as to form the plastic package shielding body. It will be appreciated that the first encapsulant material, after injection molding, may form a resin matrix and that the magnetic shielding filler may be distributed within the resin matrix.

For example, the first encapsulating material and the magnetic shielding filler are thoroughly mixed with a stirrer to obtain a molding compound. Thus, the mixing uniformity can be improved. Among them, the mixers include, but are not limited to, propeller type mixers, turbine type mixers, paddle type mixers, anchor type mixers, ribbon type mixers, magnetic heating mixers, hinge type mixers, variable frequency double layer mixers, and side entry type mixers.

Therefore, the plastic package shielding body is utilized to replace a plastic package layer in the related technology, so that chips can be packaged on a substrate, the purposes of water resistance and dust resistance are achieved, and the magnetic field shielding effect can be achieved. The plastic package shielding layer also encapsulates the magnetic conduction layer, so that on the premise of not increasing the thickness of the packaged chip structure, the magnetic shielding filler in the plastic package shielding body can be used for shielding the magnetic field in the external environment where the chip is positioned, thereby weakening the magnetic field strength of the magnetic field entering the magnetic conduction layer, and then the magnetic field is further shielded by the magnetic conduction layer, so that the magnetic field strength of the magnetic field entering the chip is further reduced. That is, the magnetic field in the external environment where the packaging chip structure is located is shielded by adopting the multi-layer shielding layer, which is favorable for improving the magnetic shielding effect on the chip, so that the chip can still work normally even in a higher magnetic field environment, and especially, when the chip is an MRAM, the power consumption of the MRAM can be reduced, the information loss of the MRAM is prevented, and the occurrence of irreversible failure of the MRAM is avoided.

And, based on the multilayer shielding effect that encapsulation chip structure self had, thereby need not to set up in addition on the circuit board and be used for covering the metal shield cover of establishing encapsulation chip structure, need not to consider the metal shield cover among the correlation technique and with this metal shield cover adjacent other encapsulation chip between dodge the problem, saved the space that the metal shield cover took on the circuit board, be favorable to reducing the overall size and the weight of circuit board subassembly, save the overall dimension on the circuit board, then be favorable to realizing miniaturized design and the lightweight design of electronic equipment, still be favorable to integrating more electronic components on the circuit board.

Exemplary materials for the resin matrix include, but are not limited to, epoxy or polyimide.

In some embodiments, the saturation induction of the plastic package shield is different from the saturation induction of the magnetically permeable layer, and the permeability of the plastic package shield is different from the permeability of the magnetically permeable layer. Therefore, the multilayer shielding layer is favorable for integrally having the characteristics of high magnetic permeability and difficult magnetic saturation, and the magnetic shielding effect of the packaged chip structure is further optimized.

In some specific examples, the saturation induction of the plastic package shield is greater than the saturation induction of the magnetically permeable layer, and the permeability of the plastic package shield is less than the permeability of the magnetically permeable layer. Specifically, because of the shielding layer with high magnetic permeability, magnetic saturation is often easier to generate, and the magnetic permeability of the plastic package shielding body is smaller than that of the magnetic conductive layer by enabling the saturation magnetic induction intensity of the plastic package shielding body to be larger than that of the magnetic conductive layer. Therefore, the plastic package shielding body which is not easy to be saturated in magnetism can be adopted to initially weaken the intensity of the external magnetic field. Because the plastic package shielding body primarily weakens the magnetic field, the magnetic conduction layer inside is not easy to achieve magnetic saturation, the possibility of the magnetic saturation of the magnetic conduction layer is reduced, the magnetic conduction layer with high magnetic conductivity can weaken the magnetic field greatly, and the shielding effect is improved greatly.

In some embodiments, the magnetic shielding filler may be in particulate form. Thus, the granular magnetic shielding filler is more easily uniformly distributed in the resin matrix, thereby improving the uniformity of the magnetic permeability and the magnetic saturation strength of the plastic-sealed shield 322 b.

In some embodiments, referring to fig. 13, fig. 13 is a process flow diagram of a packaged chip structure according to another embodiment of the application. In this embodiment, step S20 specifically includes the steps of:

And S21, disposing a second packaging material on the first surface through an injection molding process, and enabling the second packaging material to cover the chip so as to form an insulating layer.

S22: the magnetic conductive layer is arranged on the surface of the insulating layer.

With continued reference to fig. 14, fig. 14 is a process flow diagram of a packaged chip structure according to still other embodiments of the present application. In this embodiment, step S22 specifically includes the steps of:

and S221, fully mixing the solvent and the magnetic shielding particles to prepare the shielding slurry.

For example, the solvent and the magnetic shielding particles are thoroughly mixed using a stirrer to obtain a shielding slurry. Thus, the mixing uniformity can be improved. Among them, the mixers include, but are not limited to, propeller type mixers, turbine type mixers, paddle type mixers, anchor type mixers, ribbon type mixers, magnetic heating mixers, hinge type mixers, variable frequency double layer mixers, and side entry type mixers.

And S222, covering the surface of the insulating layer with shielding slurry through a spraying process or a printing process. Exemplary spray coating processes include, but are not limited to, spin coating, drop coating, knife coating.

And S223, drying the shielding slurry on the surface of the insulating layer to volatilize the solvent in the shielding slurry so as to form the magnetically conductive layer.

The drying process may be a drying process. For example, the temperature of the drying may be greater than or equal to 50 ℃ and less than or equal to 90 ℃. Specifically, the temperature of the drying may be 55 ℃, 70 ℃,72 ℃, 75 ℃, 80 ℃, 85 ℃, 88 ℃, or 90 ℃.

In some embodiments, the equivalent diameter of the magnetic shielding particles is on the order of nanometers. That is, the equivalent diameter of the magnetic shielding particles is 1 nanometer (nm) or more and less than 1000nm. In particular, the equivalent of the magnetic shielding particles may be 5nm, 10nm, 20nm, 100nm, 200nm, 500nm, 800nm, 900nm or 950nm. Thus, the compact magnetically permeable layer is formed, so that the saturation induction intensity and the magnetic permeability of the magnetically permeable layer are improved, and the shielding effect of the magnetically permeable layer is improved.

In other examples, the equivalent diameter of the magnetic shielding particles may also be on the order of microns. That is, the equivalent diameter of the magnetic shielding particles is greater than or equal to 1 micrometer (um) and less than 1000um. In particular, the equivalent of the magnetic shielding particles may be 5um, 10um, 20um, 100um, 200um, 500um, 800um, 900um or 950um. In this way, the processing cost of the magnetic shielding particles is low, which is beneficial to reducing the overall manufacturing cost of the packaged chip structure.

With reference to fig. 15, fig. 15 is a process flow diagram of a packaged chip structure according to other embodiments of the present application. In this embodiment, before step S10, the following steps are further included:

s01: the first bottom shielding layer is disposed on the first surface of the substrate.

Illustratively, in step S01, a first bottom shielding layer is bonded to a first surface using a first insulating adhesive. Therefore, on one hand, the relative fixation between the first bottom shielding layer and the first surface can be realized, and on the other hand, the first insulating glue can be used for playing an insulating role, so that the short circuit between the substrate and the first bottom shielding layer is prevented, and the working reliability of the packaged chip structure is improved.

In some examples, referring to fig. 15, step S10 specifically includes: the chip is arranged on one side surface of the first bottom shielding layer, which is far away from the first surface, and the orthographic projection of the chip on the first bottom shielding layer is positioned in the peripheral outline of the first bottom shielding layer.

Illustratively, in step S10, a second insulating glue is used to adhere the chip to the first bottom shielding layer. Therefore, on one hand, the relative fixation between the first bottom shielding layer and the chip can be realized, and on the other hand, the insulating adhesive can be utilized to play an insulating role, so that the working reliability of the packaged chip structure is improved.

In some embodiments, please continue to refer to fig. 15, between step 10 and step S21, further comprising the steps of:

s11: bonding wires are connected between the circuit surface of the chip and the pads on the first surface using a wire bonding process. Wherein the circuit face of the chip faces away from the first surface. The pads on the first surface are at the outer periphery of the first bottom shield layer.

Therefore, the connecting process is simple, the cost is low, and the efficiency is high. Moreover, when the packaged chip structure further comprises a first bottom shielding layer, the connection mode does not interfere with the arrangement of the first bottom shielding layer.

Illustratively, in order to ensure the smoothness of the wire bonding process and to improve the reliable connection of the bonding wires and the chips and the bonding pads, and to prevent the short circuit problem caused by the chip, the first bottom shielding layer and the substrate as a whole having some dirt (such as residual moisture and organic matters on the chip) and the like, the steps of plasma cleaning and drying the chip, the first bottom shielding layer and the substrate as a whole are further included between the step S10 and the step S11.

Illustratively, in order to prevent dirt remaining on the chip or the substrate after the wire bonding process, the method further includes the step of plasma cleaning and drying the bonding wire, the chip, the first bottom shielding layer and the substrate as a whole, prior to step S21.

The specific processing of the packaged chip structure and the processing of the circuit board assembly are described in detail below in one specific example.

Referring to fig. 16, fig. 16 is a schematic view illustrating a processing procedure of a packaged chip structure according to still other embodiments of the present application.

A chip, a substrate, and a first bottom shielding layer are fabricated. The chip can be obtained through thinning, cutting and other treatments of the silicon crystal bar. The first bottom shielding layer may be formed by cutting a plate material.

The first bottom shielding layer is adhered to the first surface of the substrate by using a first insulating adhesive.

And bonding the chip to the first bottom shielding layer by adopting a second insulating adhesive.

And carrying out plasma cleaning treatment and drying treatment on the chip, the first bottom shielding layer and the whole substrate in sequence.

Bonding wires are connected between the circuit face of the chip and pads on the first surface of the substrate using a wire bonding process.

And (5) carrying out plasma cleaning treatment and drying treatment on the semi-finished product after the wire bonding process.

The second packaging material is arranged on the first surface through an injection molding process, and covers the chip to form the insulating layer.

Thoroughly mixing a solvent and magnetic shielding particles to prepare a shielding slurry; covering the surface of the insulating layer by a spraying process or a printing process; and drying the shielding slurry on the surface of the insulating layer to volatilize the solvent in the shielding slurry so as to form the magnetically conductive layer.

Fully mixing the first packaging material and the magnetic shielding filler to prepare plastic packaging slurry; and setting the plastic package slurry on the first surface through an injection molding process, and enabling the plastic package slurry to cover the magnetic conduction layer so as to form the plastic package shielding body.

And arranging a tin ball array on the second surface of the substrate.

And performing reflow soldering on the tin ball array to form a solder ball array, so that the packaged chip structure is soldered with the circuit board by using the solder ball array as a pin.

Subsequently, surface marking (i.e., identifying the type of chip), separating, inspecting, and testing packaging may be performed. Thus, the chip packaging structure can be processed.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A packaged chip structure, comprising:

A substrate having a first surface;

the chip is arranged on the first surface;

The insulating layer is arranged on the first surface and covers the chip;

the magnetic conduction layer covers the insulating layer and is attached to the surface of the insulating layer through a spraying process or a printing process;

The plastic package shielding body is packaged on the first surface and covers the magnetic conduction layer, and comprises a resin matrix and magnetic shielding filler, wherein the magnetic shielding filler is distributed in the resin matrix;

The first bottom shielding layer is arranged between the first surface and the chip, and the orthographic projection of the chip on the first surface is positioned in the orthographic projection of the first bottom shielding layer on the first surface;

A second bottom shielding layer laminated between the first bottom shielding layer and the first surface;

The orthographic projection of the first bottom shielding layer on the first surface is positioned in the orthographic projection of the second bottom shielding layer on the first surface; or the orthographic projection of the first bottom shielding layer on the first surface coincides with the orthographic projection of the second bottom shielding layer on the first surface.

2. The packaged chip structure of claim 1 wherein a saturation induction of the plastic package shield is different from a saturation induction of the magnetically permeable layer and a permeability of the plastic package shield is different from a permeability of the magnetically permeable layer.

3. The packaged chip structure of claim 1 or 2, wherein a saturation induction of the plastic package shield is greater than a saturation induction of the magnetically permeable layer, and a permeability of the plastic package shield is less than a permeability of the magnetically permeable layer.

4. A packaged chip structure according to any one of claims 1 to 3 wherein the magnetic shielding filler is in particulate form.

5. The packaged chip structure of claim 4 wherein said magnetic shielding filler has an equivalent diameter in the range of 500nm to 50um.

6. The packaged chip structure of claim 4 or 5 wherein the equivalent diameter of the magnetic shielding filler is in the order of microns.

7. The package chip structure according to any one of claims 1 to 6, wherein the magnetically permeable layer is made of soft magnetic material.

8. The packaged chip structure of claim 7, wherein the soft magnetic material is a soft magnetic alloy material and/or ferrite;

wherein the soft magnetic alloy material is at least one of nickel-iron alloy, silicon-iron alloy, iron-silicon-chromium alloy and cobalt-iron alloy.

9. The packaged chip structure of any one of claims 1-8 wherein the material of the magnetic shielding filler is pure iron, and/or silicon steel.

10. The packaged chip structure of any one of claims 1-9 wherein a thickness of said plastic package shield is greater than a thickness of said magnetically permeable layer.

11. The packaged chip structure of any one of claims 1-10 wherein said insulating layer is attached to said first surface and said chip by an injection molding process.

12. The packaged chip structure of any one of claims 1-10 wherein said insulating layer is double sided tape, said insulating layer being bonded to said first surface and said magnetically permeable layer, respectively.

13. The packaged chip structure of any one of claims 1-12 wherein said insulating layer covers said first bottom shielding layer.

14. The packaged chip structure of claim 1 wherein the saturation induction of the second bottom shielding layer is greater than the saturation induction of the first bottom shielding layer and the magnetic permeability of the second bottom shielding layer is less than the magnetic permeability of the first bottom shielding layer, the insulating layer covering the second bottom shielding layer.

15. The packaged chip structure of any one of claims 1-14, wherein the chip has a circuit face facing away from the substrate;

the first surface is provided with a bonding pad, and the bonding pad is positioned on the periphery of the first bottom shielding layer;

the packaging chip structure further comprises a bonding wire, wherein one end of the bonding wire is fixed on the circuit surface and is electrically connected with the chip, and the other end of the bonding wire is fixed on the bonding pad and is electrically connected with the substrate;

the insulating layer covers the bonding wire and the pad.

16. The packaged chip structure of any one of claims 1-15 wherein the chip is a bare chip.

17. The packaged chip structure of any one of claims 1-16 wherein said chip is an MRAM.

18. The processing method of the packaged chip structure is characterized by comprising the following steps of:

Laminating the second bottom shielding layer and the first bottom shielding layer on the first surface; the second bottom shielding layer is stacked between the first bottom shielding layer and the first surface, and the orthographic projection of the first bottom shielding layer on the first surface is positioned in the orthographic projection of the second bottom shielding layer on the first surface; or the orthographic projection of the first bottom shielding layer on the first surface coincides with the orthographic projection of the second bottom shielding layer on the first surface;

Disposing a chip on a first surface of a substrate, and disposing the chip on a side surface of the first bottom shielding layer away from the first surface; the orthographic projection of the chip on the first surface is positioned in the orthographic projection of the first bottom shielding layer on the first surface;

Covering an insulating layer and a magnetic conductive layer on the surface of the chip; wherein the insulating layer is further connected to the first surface and covers the chip, and the insulating layer is located between the magnetically permeable layer and the chip; the magnetic conductive layer is arranged on the surface of the insulating layer, and the magnetic conductive layer comprises the steps of fully mixing a solvent and magnetic shielding particles to prepare shielding slurry; covering the surface of the insulating layer with the shielding slurry through a spraying process or a printing process; drying the shielding slurry on the surface of the insulating layer to volatilize a solvent in the shielding slurry so as to form the magnetic conductive layer;

and fully mixing the first packaging material and the magnetic shielding filler to prepare plastic packaging slurry, setting the plastic packaging slurry on the first surface through an injection molding process, and enabling the plastic packaging slurry to cover the magnetic conduction layer to form the plastic packaging shielding body.

19. The method of claim 18, wherein the covering the surface of the chip with the insulating layer and the magnetic conductive layer comprises:

Disposing a second encapsulation material on the first surface by an injection molding process, and enabling the second encapsulation material to cover the chip so as to form the insulating layer;

and arranging the magnetic conduction layer on the surface of the insulating layer.

20. The method of claim 18, further comprising, after disposing the die on the first surface of the substrate and before covering the surface of the die with the insulating layer and the magnetically permeable layer:

Connecting bonding wires between a circuit surface of the chip and bonding pads on the first surface by using a wire bonding process; the circuit surface of the chip faces away from the first surface, and the bonding pads on the first surface are arranged on the periphery of the first bottom shielding layer.

21. The method of processing a packaged chip structure according to any one of claims 18 to 20, wherein the equivalent diameter of the magnetic shielding particles is in the order of micrometers.

22. An electronic device, comprising:

a housing having an accommodation space;

The circuit board is arranged in the accommodating space;

A packaged chip structure according to any one of claims 1 to 17, wherein the substrate has a second surface opposite to the first surface, the second surface facing the circuit board, and the packaged chip structure is disposed on the circuit board and electrically connected to the circuit board.

23. The electronic device of claim 22, further comprising a shield on a side of the circuit board remote from the packaged chip structure, wherein an orthographic projection of the packaged chip structure onto a plane of the first surface overlaps an orthographic projection of the shield onto the plane of the first surface.

24. The electronic device of claim 23, wherein an orthographic projection of the packaged chip structure on a plane in which the first surface lies is within an orthographic projection of the shield on the plane in which the first surface lies.

25. The electronic device of claim 23 or 24, wherein the shield is defined by a portion of the housing.