JP2004207322A - Magnetic memory device - Google Patents

Magnetic memory device Download PDF

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Publication number
JP2004207322A
JP2004207322A JP2002371691A JP2002371691A JP2004207322A JP 2004207322 A JP2004207322 A JP 2004207322A JP 2002371691 A JP2002371691 A JP 2002371691A JP 2002371691 A JP2002371691 A JP 2002371691A JP 2004207322 A JP2004207322 A JP 2004207322A
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Japan
Prior art keywords
magnetic
memory
layer
magnetic shield
mram
Prior art date
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Abandoned
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JP2002371691A
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Japanese (ja)
Inventor
Katsumi Okayama
克巳 岡山
Yoshihiro Kato
義寛 加藤
Kaoru Kobayashi
薫 小林
Tetsuya Yamamoto
哲也 山元
Minoru Igarashi
実 五十嵐
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Sony Corp
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Sony Corp
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Priority to JP2002371691A priority Critical patent/JP2004207322A/en
Publication of JP2004207322A publication Critical patent/JP2004207322A/en
Abandoned legal-status Critical Current

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  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
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  • General Physics & Mathematics (AREA)
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  • Power Engineering (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To guarantee an operation having no problem for a magnetic field from an environment to which an MRAM cell is applied by completely magnetically shielding the MRAM cell even for a large external magnetic field. <P>SOLUTION: A plurality of magnetic random access memories (MRAM) 30 each made of a TMR element 10 is obtained by laminating magnetization fixing layers 4, 6 in which magnetizing directions are fixed, and a magnetic layer (memory layer) 2 in which the magnetizing direction can be changed, or the other cell 38 such as a DRAM, etc., are laminated. Magnetic shield layers 33, 34 for magnetically shielding the memory 30 are provided on at least the occupied area region of the memory 30, or the magnetic shield layers 33, 34 are provided on the front surface side and the rear surface side, respectively, and intervals between these magnetic shielding layers are specified to 3.5mm or less. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、磁化方向が固定された磁化固定層と、磁化方向の変化が可能な磁性層とが積層されてなるメモリ素子からなる磁気ランダムアクセスメモリ、いわゆる不揮発性メモリであるＭＲＡＭ（Magnetic Random Access Memory）として構成された磁気メモリ装置、又は磁化可能な磁性層を有するメモリ素子からなる磁気メモリ装置に関するものである。
【０００２】
【従来の技術】
情報通信機器、特に携帯端末などの個人用小型機器の飛躍的な普及に伴い、これを構成するメモリやロジックなどの素子には、高集積化、高速化、低電力化など、一層の高性能化が要求されている。
【０００３】
特に不揮発性メモリは、ユビキタス時代に必要不可欠であると考えられている。電源の消耗やトラブルが生じた場合や、サーバーとネットワークが何らかの障害により切断された場合でも、不揮発性メモリは、個人情報を含めた重要な情報を保護することができる。また、最近の携帯機器は、不要の回路ブロックをスタンバイ状態にしてできるだけ消費電力を抑えるように設計されているが、高速のワークメモリと大容量ストレージメモリを兼ねることができる不揮発性メモリが実現できれば、消費電力とメモリの無駄を無くすことができる。また、高速の大容量不揮発性メモリが実現できれば、電源を入れると瞬時に起動できる“インスタント・オン”機能も可能になってくる。
【０００４】
不揮発性メモリとしては、半導体を用いたフラッシュメモリや、強誘電体を用いたＦＲＡＭ（Ferroelectric Random Access Memory ）なども挙げられる。
【０００５】
しかしながら、フラッシュメモリは、書き込み速度がμ秒のオーダーと遅いという欠点がある。一方、ＦＲＡＭにおいては、書き換え可能回数が１０１２〜１０１４であり、完全にＳＲＡＭ（Static Random Access Memory）やＤＲＡＭ（Dynamic Random Access Memory）に置き換えるには持久力（Endurance）が小さく、また強誘電体キャパシタの微細加工が難しいという問題が指摘されている。
【０００６】
これらの欠点を有さず、高速、大容量（高集積化）、低消費電力の不揮発性メモリとして注目されているのが、例えばWang et al., IEEE Trans. Magn. 33 (1997), 4498に記載されているような、ＭＲＡＭ（Magnetic Random Access Memory ）と称される磁気メモリであり、近年のＴＭＲ(Tunnel Magnetoresistance)材料の特性向上により、注目を集めるようになってきている。
【０００７】
ＭＲＡＭは、ナノ磁性体特有のスピン依存伝導現象に基づく磁気抵抗効果を利用した半導体磁気メモリであり、外部から電力を供給することなしに記憶を保持できる不揮発性メモリである。しかも、ＭＲＡＭは、構造が単純であるために高集積化が容易であり、また磁気モーメントの回転により記録を行うために書き換え可能回数が大であり、アクセス時間についても非常に高速であることが予想され、既に１００ＭＨｚで動作可能であることがR.Scheuerlein et al, ISSCC Digest of Technical Papers,pp.128-129,Feb.2000で報告されている。最近では、k.Inomata, 第２６回応用磁気学会学術講演概要集18aA-1などの報告にあるように、次世代不揮発性メモリの主役としての役割が期待されている。
【０００８】
こうしたＭＲＡＭについて更に詳細に説明すると、図１４に例示するように、ＭＲＡＭのメモリセルの記憶素子となるＴＭＲ素子１０は、支持基板９上に設けられた、磁化が比較的容易に回転する記憶層２と磁化固定層４、６とを含む。
【０００９】
磁化固定層は第１の磁化固定層４と第２の磁化固定層６の二つの磁化固定層を持ち、これらの間には、これらの磁性層が反強磁性的に結合するような導体層５が配置されている。記憶層２と磁化固定層４、６には、ニッケル、鉄又はコバルト、或いはこれらの合金からなる強磁性体が用いられ、また導体層５の材料としては、ルテニウム、銅、クロム、金、銀などが使用可能である。第２の磁化固定層６は反強磁性体層７と接しており、これらの層間に働く交換相互作用によって、第２の磁化固定層６は強い一方向の磁気異方性を持つことになる。反強磁性体層７の材料としては、鉄、ニッケル、白金、イリジウム、ロジウムなどのマンガン合金、コバルトやニッケル酸化物などを使用できる。
【００１０】
また、磁性層である記憶層２と第１の磁化固定層４との間には、アルミニウム、マグネシウム、シリコン等の酸化物又は窒化物等からなる絶縁体によるトンネルバリア層３が挟持されており、記憶層２と磁化固定層４との磁気的結合を切るとともに、トンネル電流を流すための役割を担う。これらの磁性層及び導体層は主にスパッタリング法により形成されるが、トンネルバリア層３は、スパッタリングで形成された金属膜を酸化もしくは窒化させることにより得ることができる。トップコート層１は、ＴＭＲ素子１０とこのＴＭＲ素子に接続される配線との相互拡散防止、接触抵抗低減及び記憶層２の酸化防止という役割があり、通常は、Ｃｕ、Ｔａ、ＴｉＮ等の材料を使用できる。下地電極層８は、ＴＭＲ素子と直列に接続されるスイッチング素子との接続に用いられる。この下地層８は反強磁性体層７を兼ねてもよい。
【００１１】
このように構成されたメモリセルにおいては、後述するように、磁気抵抗効果によるトンネル電流変化を検出して情報を読み出すが、その効果は記憶層と磁化固定層との相対磁化方向に依存する。
【００１２】
図１５は、一般的なＭＲＡＭの一部を簡略化して示す拡大斜視図である。ここでは、簡略化のために読み出し回路部分は省略してあるが、例えば９個のメモリセルを含み、相互に交差するビット線１１及び書き込み用ワード線１２を有する。これらの交点には、ＴＭＲ素子１０が配置されていて、ＴＭＲ素子１０への書き込みは、ビット線１１及び書き込み用ワード線１２に電流を流し、これらから発生する磁界の合成磁界によって、ビット線１１と書き込み用ワード線１２との交点にあるＴＭＲ素子１０の記憶層２の磁化方向を磁化固定層に対して平行又は反平行にして書き込みを行う。
【００１３】
図１６は、メモリセルの断面を模式的に示していて、例えばｐ型シリコン半導体基板１３内に形成されたｐ型ウェル領域１４内に形成されたゲート絶縁膜１５、ゲート電極１６、ソース領域１７、ドレイン領域１８よりなるｎ型の読み出し用電界効果型トランジスタ１９が配置され、その上部に、書き込み用ワード線１２、ＴＭＲ素子１０、ビット線１１が配置されている。ソース領域１７には、ソース電極２０を介してセンスライン２１が接続されている。電界効果トランジスタ１９は、読み出しのためのスイッチング素子として機能し、ワード線１２とＴＭＲ素子１０との間から引き出された読み出し用配線２２がドレイン電極２３を介してドレイン領域１８に接続されている。なお、トランジスタ１９は、ｎ型又はｐ型電界効果トランジスタであってよいが、こうしたトランジスタに代えて、ダイオード、バイポーラトランジスタ、ＭＥＳＦＥＴ（Metal Semiconductor Field Effect Transistor）等、各種のスイッチング素子も使える。
【００１４】
図１７は、ＭＲＡＭの等価回路図を示すが、例えば６個のメモリセルを含み、相互に交差するビット線１１及び書き込み用ワード線１２を有し、これらの書き込み線の交点には、記憶素子１０と共に、記憶素子１０に接続されて読み出しの際に素子選択を行う電界効果トランジスタ１９及びセンスライン２１を有する。センスライン２１は、センスアンプ２３に接続され、記憶された情報を検出する。なお、図中の２４は双方向の書き込み用ワード線電流駆動回路、２５はビット線電流駆動回路である。
【００１５】
図１８は、ＭＲＡＭの書き込み条件を示すアステロイド曲線であって、印加された磁化容易軸方向磁界ＨＥＡ及び磁化困難軸方向磁界ＨＨＡによる記憶層磁化方向の反転しきい値を示している。このアステロイド曲線の外部に、相当する合成磁界ベクトルが発生すると、磁界反転を生じるが、アステロイド曲線の内部の合成磁界ベクトルは、その電流双安定状態の一方からセルを反転させることはない。また、電流を流しているワード線及びビット線の交点以外のセルにおいても、ワード線又はビット線単独で発生する磁界が印加されるため、それらの大きさが一方向反転磁界ＨK以上の場合は、交点以外のセルの磁化方向も反転してしまうため、合成磁界が図中の灰色の領域にある場合のみに、選択されたセルを選択書き込みが可能となるようにしておく。
【００１６】
このように、ＭＲＡＭでは、ビット線とワード線の２本の書き込み線を使用することにより、アステロイド磁化反転特性を利用して、指定されたメモリセルだけが磁性スピンの反転により選択的に書き込むことが一般的である。単一記憶領域における合成磁化は、それに印加された磁化容易軸方向磁界ＨＥＡと磁化困難軸方向磁界ＨＨＡとのベクトル合成によって決まる。ビット線を流れる書き込み電流は、セルに磁化容易軸方向の磁界ＨＥＡを印加し、またワード線を流れる電流は、セルに磁化困難軸方向の磁界ＨＨＡを印加する。
【００１７】
図１９は、ＭＲＡＭの読み出し動作を説明するものである。ここでは、ＴＭＲ素子１０の層構成を概略図示しており、上記した磁化固定層を単一層２６として示し、記憶層２及びトンネルバリア層３以外は図示省略している。
【００１８】
即ち、上記したように、情報の書き込みは、マトリックス状に配線したビット線１１とワード線１２との交点の合成磁場によってセルの磁性スピンを反転させて、その向きを“１”、“０”の情報として記録する。また、読み出しは、磁気抵抗効果を応用したＴＭＲ効果を利用して行なうが、ＴＭＲ効果とは、磁性スピンの向きによって抵抗値が変化する現象であり、磁性スピンが反平行の抵抗の高い状態と、磁性スピンが平行の抵抗の低い状態により、情報の“１”、“０”を検出する。この読み出しは、ワード線１２とビット線１１との間に読み出し電流（トンネル電流）を流し、上記の抵抗の高低に応じた出力を上記した読み出し用電界効果トランジスタ１９を介してセンスライン２１に読み出すことによって行う。
【００１９】
上記したように、ＭＲＡＭは、高速かつ不揮発性の大容量メモリとして期待されるが、記憶の保持に磁性体を用いているため、外部磁界の影響によって情報が消去されたり、或いは書きかえられてしまうという問題がある。図１８で述べた磁化容易軸方向の反転磁界及び磁化困難軸方向の反転磁界ＨSWは、材料にもよるが２０〜２００エルステッド（Ｏｅ）であり、電流に換算すると数ｍＡ(R.H.Koch et al.,Phys.Rev.Lett.84,5419(2000), J.Z.Sun et al.,2001 8th Joint Magnetism and Magnetic Material参照)と小さいからである。しかも、書き込み時の保磁力（Ｈｃ）は例えば数Ｏｅ〜１０Ｏｅ程度であるため、それ以上の外部磁界による内部漏洩磁界が作用すれば、所定のメモリセルに選択的に書き込みを行うことが不可能となることがある。
【００２０】
従って、ＭＲＡＭの実用化へのステップとして、外部磁気対策、即ち素子を外部の電磁波からシールドする磁気シールド構造の確立が切望されている。
【００２１】
ＭＲＡＭが実装されて使用される環境は、主として高密度実装基板上であり、電子機器内部である。電子機器の種類にもよるが、近年の高密度実装の発達により、高密度実装基板上は半導体素子や通信用素子、超小型モータなどが高密度に実装されており、また、電子機器内部にはアンテナ素子や各種メカニカル部品、電源などが高密度実装され、１つの機器を構成している。
【００２２】
このように混載が可能であることは、不揮発性メモリとしてのＭＲＡＭの特長の１つであるが、ＭＲＡＭの周囲には直流、低周波数から高周波数に亘る広い周波数範囲の磁界成分が混在する環境となっているので、ＭＲＡＭの記録保持の信頼性確保のためには、ＭＲＡＭ自身の実装方法やシールド構造を工夫することにより外部磁界からの耐性を向上させることが求められている。
【００２３】
こうした外部磁界の大きさとしては、例えばクレジットカードや銀行のキャッシュカードのような磁気カードでは、５００〜６００Ｏｅの磁界に対して耐性を持たせることが規定されている。このため、磁気カードの分野ではＣｏ被覆γ−Ｆｅ２Ｏ３やＢａフェライトなどの保磁力の大きな磁性材料を用いて対応している。また、プリペイドカードの分野でも３５０〜６００Ｏｅのような磁界に対して耐性を持つ必要がある。ＭＲＡＭ素子は電子機器筐体内に実装され、持ち運ぶことも想定されるデバイスであるので、磁気カード類と同等の強い外部磁界からの耐性を持たせる必要があり、特に上記した理由から内部（漏洩）磁界の大きさを１０〜２０Ｏｅ以下に抑える必要がある。
【００２４】
ＭＲＡＭの磁気シールド構造としては、ＭＲＡＭ素子のパシベーション膜に絶縁性のフェライト(ＭｎＺｎ及びＮｉＺｎフェライト)層を使うことにより磁気シールド特性を持たせる提案がなされている（後述の特許文献１参照）。また、パーマロイのような高透磁率磁性体をパッケージの上及び下から取り付けることにより磁気シールド効果をもたせ、内部素子への磁束の侵入を防ぐ提案がなされている（後述の特許文献２参照）。更に、軟鉄等の磁性材料により素子にシールド蓋を被せる構造が開示されている（後述の特許文献３参照）。
【００２５】
【特許文献１】
米国特許第5,902,690号明細書及び図面（第５欄、FIG.1及びFIG.3）
【特許文献２】
米国特許第5,939,772号明細書及び図面（第２欄、Fig.1及びFig.2）
【特許文献３】
特開2001-250206号公報（第５頁右欄、図６）
【００２６】
【発明が解決しようとする課題】
ＭＲＡＭのメモリセルへの外部磁束の侵入を防ぐためには、高い透磁率を持つ磁性材料を素子の周囲に巡らせ、磁束を内部へ侵入させない磁路を設けることが最も重要である。
【００２７】
しかしながら、特許文献１（米国特許第5,902,690号）のように素子のパッシベーション膜をフェライトで形成すると、フェライト自身の飽和磁化が低い(一般的なフェライト材料で０．２〜０．５テスラ（Ｔ）)ため、外部磁界の侵入を完全に防ぐことが不可能である。フェライト自身の飽和磁化はＮｉＺｎフェライトで０．２〜０．３５Ｔ、ＭｎＺｎフェライトでは０．３５〜０．４７Ｔ程度であるが、ＭＲＡＭ素子へ侵入する外部磁界の大きさは数１００Ｏｅと大きいため、フェライト程度の飽和磁化ではフェライトの磁気飽和により透磁率はほぼ１となり、機能しなくなる。また、特許文献１には、膜厚の記述はないが、通常パッシベーション膜では高々０．１μｍ程度であるため、磁気シールド層としては薄すぎることからも、効果はほとんど期待できない。しかも、フェライトをパッシベーション膜に用いる場合、フェライトは酸化物磁性体であるため、スパッタ法により成膜するときには酸素欠損が生じ易く、完全なフェライトをパッシベーション膜として用いることは困難である。
【００２８】
また、特許文献２（米国特許第5,939,772号）では、パッケージの上下をパーマロイ層で覆う構造が記述されており、パーマロイを用いることによりフェライトパッシベーション膜よりも高いシールド性能が得られる。しかしながら、特許文献２に開示されているミューメタル（Mu Metal）の透磁率はμｉ＝１００，０００程度と極めて高いものの、飽和磁化は０．７〜０．８Ｔと低く、容易に外部磁界に対し飽和してμ＝１となってしまうため、完全な磁気遮蔽効果を得るためにはシールド層の厚さはかなり厚くなければならないという欠点がある。従って、実用上、数１００Ｏｅの磁界を侵入させないための構造としては、パーマロイの飽和磁化が小さすぎること、並びにその厚さが薄すぎることの両面から、磁気シールド層として不完全である。
【００２９】
また、特許文献３（特開2001-250206号）では、軟鉄などを用いた磁気シールド構造が開示されているが、これは素子上部を覆うのみであるために磁気シールドが不完全となると共に、軟鉄の飽和磁化は１．７Ｔ、透磁率はμiで３００程度と、磁気特性が不十分である。従って、特許文献３に記述されている構造にて磁気シールドを行ったとしても、外部磁界の侵入を完全に防ぐことは極めて困難である。
【００３０】
本発明は、上記の如き実情に鑑みてなされたものであって、その目的は、大きな外部磁界に対しても十二分にＭＲＡＭ素子を磁気的にシールドし、ＭＲＡＭ素子が適用される環境からの磁界に対して問題のない動作を保証することを可能にすることにある。
【００３１】
【課題を解決するための手段】
即ち、本発明は、磁化方向が固定された磁化固定層と、磁化方向の変化が可能な磁性層とが積層されてなるメモリ素子からなる磁気ランダムアクセスメモリとして構成された磁気メモリ装置において、又は、磁化可能な磁性層を有するメモリ素子からなる磁気メモリ装置において、前記メモリ素子の複数個、又は前記メモリ素子と他の素子とが積層され、少なくとも前記メモリ素子の占有面積領域に、前記メモリ素子を磁気シールドするための磁気シールド層が設けられていることを特徴とする磁気メモリ装置（以下、本発明の第１の磁気メモリ装置と称する。）に係るものである。
【００３２】
本発明はまた、磁化方向が固定された磁化固定層と、磁化方向の変化が可能な磁性層とが積層されてなるメモリ素子からなる磁気ランダムアクセスメモリとして構成された磁気メモリ装置において、又は、磁化可能な磁性層を有するメモリ素子からなる磁気メモリ装置において、前記メモリ素子を磁気シールドするための磁気シールド層が前記メモリ素子の表面側及び裏面側にそれぞれ設けられ、これらの磁気シールド層間の間隔が３．５ｍｍ以下であることを特徴とする磁気メモリ装置（以下、本発明の第２の磁気メモリ装置と称する。）も提供するものである。
【００３３】
本発明者は、ＭＲＡＭ等の磁気メモリ装置においてメモリ素子に対する磁気シールドについて検討を行ったところ、次のような認識を持つに至った。磁気シールド効果は、磁気シールド層を形成する磁性材料の磁気飽和とともに減衰していくが、板状などの形状を有する磁気シールド層の磁化飽和は、反磁界が最小となる場所、つまりエッジ部から最も離れているところから始まるため、パッケージに磁気シールド層を施した場合、最もシールド効果が弱い部分はパッケージ中心部となる。
【００３４】
ところが、既述した従来の技術のいずれにおいても、パッケージの大きさ、及び磁気シールド層の大きさに関する知見は示されていない。通常、磁気シールドにおいては、外部磁界に対して磁気シールド材料が磁気的に飽和しないことが必須であるが、Ｆｅ−Ｎｉ系軟磁性合金のように保磁力が小さい（言い換えると、異方性磁界が小さい）磁性材料は、わずかな磁界で磁気飽和に至るため、ＭＲＡＭ素子におけるような大きな外部磁界を遮蔽するには適さない。特に、磁気シールド層が大面積になると、磁気シールド層の中心部では形状異方性によって自らの磁気モーメントが容易に面内に配向する状態となり、実際にはシールド効果が減少してしまうため、シールド面積にも注意が必要である。
【００３５】
本発明者は、こうした認識の下で鋭意検討を行った結果、磁気メモリ装置、特にＭＲＡＭにおいて、メモリ素子の複数個を積層するか、或いはＤＲＡＭ等の他の素子と積層し、少なくともメモリ素子の占有面積領域にメモリ素子を磁気シールドするための磁気シールド層を設けることによって、素子の積層に対応して素子面積又はパッケージサイズが減少するので、磁気シールド層のサイズをメモリ素子の占有面積相当分にまで小さくして磁気シールド層のエッジ部から中心部までの距離を短くし、中心部での磁気飽和を十二分に抑えて磁気シールド効果を向上させ、磁気メモリ装置の動作保証が可能になることを見出し、本発明の第１の磁気メモリ装置に到達したものである。
【００３６】
また、磁気メモリ装置、特にＭＲＡＭにおいて、メモリ素子を磁気シールドするための磁気シールド層をメモリ素子の表面側及び裏面側にそれぞれ設け、これらの磁気シールド層間の間隔を３．５ｍｍ以下と特定することによって、メモリ素子に対する磁気シールド効果を向上させ、磁気メモリ装置の動作保証が可能になることも見出し、本発明の第２の磁気メモリ装置に到達したものである。
【００３７】
ここで、磁気シールド層は、ＭＲＡＭ素子の占有面積領域と同一サイズであってよいが、実質的に同一サイズであれば幾分大きめ又は小さめであってよく、ＭＲＡＭ素子のサイズや形状に応じてサイズや形状を変化させてよい。
【００３８】
【発明の実施の形態】
本発明の第１及び第２の磁気メモリ装置においては、一層の前記磁気シールド層においてその対向辺間の距離が１５ｍｍ以下であると、磁気シールド層の中心部での磁気飽和を確実かつ十二分に抑制することができる。ここで、対向辺間の距離とは、互いに平行な（或いは平行ではないが対向している）二辺間の距離を意味し、例えば正方形状であればその一辺の長さ、長方形状であれば長辺の長さである。
【００３９】
また、本発明の第２の磁気メモリ装置において、前記メモリ素子の複数個、又は前記メモリ素子とＤＲＡＭ等の他の素子とが積層され、少なくとも前記メモリ素子の占有面積領域に前記磁気シールド層が設けられていると、本発明の第１の磁気メモリ装置による効果も併せて得ることができる。
【００４０】
本発明の第１及び第２の磁気メモリ装置において、前記メモリ素子の複数個、又は前記メモリ素子とＤＲＡＭ等の他の素子とが基体上に混載されていてよい。
【００４１】
また、前記磁気シールド層がその磁気シールド効果を発揮するには、前記メモリ素子のパッケージの上部及び／又は下部、或いは／並びに、前記メモリ素子のパッケージ中において前記メモリ素子の上部及び／又は下部に配置されているのが望ましい。また、前記磁気シールド層が、前記素子の積層構造中における中間層として設けられていてよい。
【００４２】
例えば、ＭＲＡＭパッケージ構造として、複数のチップを含むマルチチップモジュールタイプの積層構造のモジュールにおいて、その上、下層又は中間層として前記磁気シールド層を設けてよい。また、ＳＩＰ（System in Package）タイプのＭＲＡＭ混載モジュールにおいて、スタック実装、積層実装、多層実装など複数のＩＣ（集積回路）チップを高さ方向に積層した構造のパッケージにおいて、ＭＲＡＭの磁気シールド層をその上部、下部又は中間層として設けてもよい。また、ＳＩＰなどのＭＲＡＭ混載モジュールにおいては同一平面上にも複数のＩＣチップを配するが、高さ方向にも複数のＩＣチップを積層する構造において、ＭＲＡＭの磁気シールド層をその上部、下部又は中間層として設けてもよい。いずれも、外部磁界に対する磁気遮蔽効果を高めることができる。
【００４３】
また、前記磁気シールド層を形成する軟磁性材料が、Ｆｅ、Ｃｏ及びＮｉのうち少なくとも１種を含む高飽和磁化、高透磁率の軟磁性体からなる、特にＦｅＣｏＶ、ＦｅＮｉ、ＦｅＳｉＡｌ、ＦｅＳｉＢ、ＦｅＡｌ等の高飽和磁化、高透磁率の軟磁性体からなるのが好ましい。
【００４４】
また、前記封止材中に軟磁性フィラーを含有していると、磁気シールド効果を一層向上させることができる。
【００４５】
本発明はＭＲＡＭに好適であるが、このようなＭＲＡＭは、前記磁化固定層と前記磁性層との間に絶縁体層又は導電体層が挟持され、前記メモリ素子の上面及び下面に設けられたビット線及びワード線としての配線にそれぞれ電流を流すことによって誘起される磁界で前記磁性層を所定方向に磁化して情報を書き込み、この書き込み情報を前記配線間でのトンネル磁気抵抗効果（ＴＭＲ効果）によって読み出すように構成されるのがよい。
【００４６】
以下、本発明の好ましい実施の形態を図面参照下に具体的に説明する。
【００４７】
図１〜図３は、本実施の形態による各種の磁気シールド構造を有する、ＭＲＡＭ素子の複数個又はＭＲＡＭ素子と他の素子とを混載したパッケージ（ＭＲＡＭ素子混載パッケージ）をそれぞれ例示するものである。
【００４８】
図１に示す例では、図１４〜図１６に示したＭＲＡＭ素子（メモリセル部及び周辺回路部も含めたチップ）３０と、ＤＲＡＭ、ＭＰＵ(Micro Processing Unit)、ＤＳＰ(Digital Signal Processor)、ＲＦ（Radio Frequency）素子等の他の素子３８とがダイパッド４０上に積層して設けられ、ボンディングワイヤ４１によって、実装基板（図示せず）に接続される外部リード３１に接続され、モールド樹脂（例えばエポキシ樹脂）等の封止材３２によって封止されている（ここでは、ＭＲＡＭ素子３０は、既述したＭＲＡＭと同様の構造及び動作原理を有するので、その説明は省略し、またダイパッド４０を含むリードフレームは簡略図示している）。この例は、ＱＦＰタイプのパッケージであり、複数のチップが積層されて１チップ化されている、いわゆるＳＩＰと称されるパッケージにおいてＭＲＡＭ素子３０を封止し、磁気シールド層を設けた１パッケージの半導体モジュールである。
【００４９】
そして、本発明に基づいてパーマロイ（ＦｅＮｉ）等からなる磁気シールド層３３、３４が、封止材３２の上面及び下面に接してＭＲＡＭ素子３０の占有面積領域に相当する面積領域にそれぞれ設けられている。
【００５０】
図２は、高速、多ピン化用のＢＧＡ（Ball Grid Aray）タイプのパッケージを示し、パッケージ中で複数のチップ（ＭＲＡＭ素子３０や他のＩＣチップ３８）が積層され、再配置配線による端子電極にはんだバンプ４２を有するインターポーザ基板４３にワイヤ４４でボンディングされ、封止材３２で封止されて１チップ化された多機能モジュールパッケージである。そして、このパッケージの表面上及びパッケージ中のＭＲＡＭ素子の下部には、パーマロイ等の磁気シールド層３３、４５が設けられている。
【００５１】
図３は、ＵＦＰＬ(Ultra Fine Pitch Lead frame)４６にはんだバンプ４７でＭＲＡＭ素子３０を４層スタックした構造を封止材３２で封止し、パッケージ上に磁気シールド層３３を設けた例を示す。各ＬＦＰＬ４５間は層間バンプ４８で接続されており、最下部のＵＦＰＬ４５はメイン基板（回路基板）４９に接続されている。
【００５２】
ＭＲＡＭ素子は通常、ＱＦＰ(Quad Flat Package)、ＳＯＰ(Small Outline Package)などのパッケージに樹脂封止されてから基板上へ実装され、実用に供される。その大きさはピン数によりほぼ規格で決まっており、例えばピン数が４８本あるものではＱＦＰ−４８ＰＩＮなどと称している。ＭＲＡＭ素子は不揮発性メモリ素子であり、多ピンのパッケージが必要とされ、１Ｍｂｉｔクラスの記憶容量を持つＭＲＡＭ素子の場合、パッケージとしてはＱＦＰ１６０ＰＩＮあるいはＱＦＰ２０８ＰＩＮ程度のパッケージを用いる必要がある。
【００５３】
ところが、上述した特許文献２（米国特許第5,939,772号）では、パッケージの上下をパーマロイ板で覆うことにより磁気シールドを達成していると開示されているが、前述のようにパーマロイでは飽和磁化が低いことと、中心部で容易に飽和することなどから、実用上許容できる範囲のシールド構成は得られない。
【００５４】
以上の図１〜図３に示したいずれのパッケージにおいても、本発明に基づいて、ＭＲＡＭ素子３０の複数個又はＭＲＡＭ素子３０と他の素子３８とが積層されているので、各素子を平面上に混載する場所よりもパッケージサイズを小さくすることができ、従って磁気シールド層３３、３４のサイズは一辺を１５ｍｍ以下に減少させて、磁気シールド効果を向上させることができる。
【００５５】
そこで、本発明者は、ＭＲＡＭ素子の正常な動作を保証するために、最大５００Ｏｅの大きな直流外部磁界が印加されても、内部（ＭＲＡＭ素子部）へは１０〜２０Ｏｅ以下になるような性能を得ることを目的として実験を行った。図４（Ａ）には、その実験時の概略図を示すが、例えば長さＬ２８ｍｍ×Ｌ２８ｍｍ、厚さｔ＝２００μｍの２枚のパーマロイの磁気シールド層３３、３４を３．４５ｍｍの間隔ｄで配置し、その中心部（空洞部）にガウスメータ３７を配置して、５００Ｏｅの直流磁界を磁気シールド層と平行に印加し、ガウスメータ３７を磁気シールド層と平行に移動させることにより、端部から中心部までの内部磁界強度（磁気シールド層からの漏洩磁界強度）を測定し、効果的な磁気シールド材料を検討した。
【００５６】
図５は、図４（Ａ）に示した方法によって測定した結果を示すが、これは、２８ｍｍ×２８ｍｍ、３．４５ｍｍ厚のＱＦＰ１６０ＰＩＮパッケージにパーマロイ板を上下に配置した構造におけるパッケージ内部の磁界強度分布に相当するものである。即ち、外部印加磁界強度は５００Ｏｅであり、ＱＦＰ１６０ＰＩＮパッケージは図４（Ｂ）に示すように一辺が約２８ｍｍ、厚さが３．４５ｍｍであり、ＭＲＡＭ素子３０’のみが中心部に配置されている。
【００５７】
図５より明らかなように、磁気シールド層端部では約５００Ｏｅの磁界強度であり、その磁気シールド層端部から内部へ約１．５ｍｍ程度入ったところの内部磁界強度は約３７０Ｏｅである。しかし、それ以上に内部に入ったところにおいても内部磁界強度は小さくならず、３７０〜４００Ｏｅの磁界強度が存在する。この磁界強度は、ＭＲＡＭ素子３０’の記憶動作に支障がある大きさを超えており、磁気シールドとしては意味をなさない。これは、磁気シールド層中心部では形状異方性のため、外部磁界が印加される前からすでに磁気モーメントが面内に配向しているためであり、磁気シールドとしては役に立っていない。
【００５８】
通常、ＭＲＡＭの記憶動作を保証するためには、少なくともＭＲＡＭ素子部において１０〜２０Ｏｅ以下の磁界強度に低減させることが必要である。
【００５９】
そこで、本発明者は、磁気シールド層の一辺の長さがどの程度であれば磁気飽和が防げるかを詳細に検討した。図６には、パッケージ上下両方に磁気シールド層を作製した時の内部磁界の大きさを図４（Ａ）に示した方法で測定し、パッケージ端からの距離を横軸にとってプロットした結果を示す。磁気シールド材料として、飽和磁化Ｍｓ＝２．３Ｔ、初透磁率μｉ＝１０００のＦｅＣｏＶを用い、その厚さを２００μｍとした。また、磁気シールド層の一辺の大きさが１０、１５、２０、２８ｍｍと４種の試料について外部印加磁界強度５００Ｏｅで測定した。
【００６０】
図６の結果から分かるように、一辺が２０ｍｍ、２８ｍｍでは、内部で磁気飽和しているために、中心部での磁界強度が大きくなっている。これに対し、一辺が１５ｍｍ、１０ｍｍであれば、中心部の磁界強度は著しく低減し、１０〜２０Ｏｅ以下となる。従って、磁気シールド層としてＦｅＣｏＶを用いた際、５００Ｏｅ以上の高い磁界強度を遮蔽する場合には、磁気シールド層の一辺（又は対向辺間の距離）を１５ｍｍ以下に抑える必要がある。但し、磁気シールド層の一辺があまり短いと却って磁気シールド効果が乏しくなるので、その一辺（又は対向辺間の距離）はＭＲＡＭ素子のサイズも考慮すると３ｍｍ以上、更には５ｍｍ以上とするのがよい。
【００６１】
ＭＲＡＭ素子は１Ｍｂｉｔクラスのものでも通常数ｍｍ角サイズであることが多く、磁気シールド層の一辺が１０ｍｍであれば、その有効な磁気シールド領域は一辺約８ｍｍとなるため、問題なく磁気シールドされることが分かる。従って、上述した特許文献２（米国特許第5,939,772号）に示されているように、パッケージのほぼ全てを覆う構造は磁気シールド性能を劣化させることになるが、本発明に基づいて実質的にＭＲＡＭ素子３０の占有面積領域のみに磁気シールド層を設けると、この磁気シールド層のサイズは一辺が１５ｍｍ以下、望ましくは１０ｍｍ以下となり、磁気シールド層の磁気飽和を効果的に抑制して磁気シールド効果を大きく向上させることができる。
【００６２】
特に、ＲＡＭ素子のパッケージ厚さは、実装面からの制約によってある一定値以下にしなければならず、またピン数も多く取らなければならない。そして、ＭＲＡＭ素子は、ＤＲＡＭ等の他の素子３８と共に混載され、ＭＲＡＭ素子単独で使用される場合よりも他のＩＣと共に実装されて使用に供される場合が多いが、このようなＭＲＡＭ素子混載パッケージにおいて、本発明に基づいてＭＲＡＭ素子を他の素子と積層し、実質的にＭＲＡＭ素子３０の占有面積領域のみに磁気シールド層３３、３４を設けることによって、パッケージサイズを減少させて磁気シールド層３３、３４の一辺を１５ｍｍ以下にでき、磁気シールド効果が大きく向上することは、上記した結果から明らかである（これは、図１〜図３に示した例や後述の他の例についても同様である）。
【００６３】
以上に述べたことから、図６に示したように、磁気シールド層の一辺の長さが１５ｍｍ以下であれば、厚さ２００μｍのシールド材にて磁気遮蔽効果が期待でき、また、一辺が１０ｍｍの磁気シールド層では、同じ効果が厚さ約１５０μｍの磁気シールド層で期待することができる。
【００６４】
但し、磁気シールド層間の間隔が必要以上に大きくなると、磁気シールド効果は低下するはずであるので、本発明者は続いて、この点に関しても詳細に検討を行った。
【００６５】
例えば、図７に示すように、磁気シールド層の一辺１０ｍｍに固定したパッケージにおいて、磁気シールド層３３と３４との間の間隔ｄに対し、内部の磁界強度の変化を図４（Ａ）の方法で測定した結果を図８（Ａ）に示す。磁気シールド層はＦｅＣｏＶ合金で形成し、磁気シールド層厚は２００μｍ、外部印加磁界強度は５００Ｏｅとした。
【００６６】
この結果から、パッケージ上下の磁気シールド層間の間隔を大きくしていき、３．５ｍｍを超えると、内部の磁界強度が急激に大きくなってしまうため、一辺が１０ｍｍの磁気シールドを用いる際は、シールド間距離を３．５ｍｍ以下にすることが必要である。
【００６７】
また、磁気シールド層の一辺を１５ｍｍとして同様に測定したところ、図８（Ｂ）に示すように、磁気シールド層３３と３４との間隔ｄが３ｍｍを超えると内部の磁界強度が急激に大きくなってしまうため、一辺が１５ｍｍの磁気シールドを用いる際は、シールド間距離を３ｍｍ以下にすることが必要であることも分った。
【００６８】
この結果から、ＭＲＡＭの磁気シールドには、磁性シールド層の特性、厚み、一辺の長さ、シールド間隔で定まる、有効なシールド範囲があり、例えばＦｅＣｏＶ合金で磁気シールド層厚が２００μｍのシールド構造では、磁気シールド層の一辺の長さを１０ｍｍ以下としたとき、磁気シールド層間の距離が３．５ｍｍ以下のスペースにＭＲＡＭ素子を高密度に実装する必要があるということが分かった。但し、ＭＲＡＭ素子のサイズ及び厚み等を考慮すると、磁気シールド層の一辺は３ｍｍ以上、好ましくは５ｍｍ以上とし、また磁気シールド層間の間隔は、ＭＲＡＭチップの厚みが１００〜４００μｍ程度であることから、少なくとも０．２ｍｍ、好ましくは０．５ｍｍ以上とするのがよい。
【００６９】
ＭＲＡＭ素子は単体で用いられることもあるが、多くはＭＰＵ、ＤＳＰ、ＲＦ素子などと共に用いられるため、ＭＲＡＭ混載素子にすることが考えられるが、磁気シールド層の一辺の大きさによる制限を考慮すると、小さい面積により高密度に実装することが必要になる。本発明に基づけば、図１〜図３に示したように、ベアチップのスタック実装のプロセスを応用して、高密度実装であってＭＲＡＭの外部磁気シールドも同時に達成した高機能パッケージを提供することができる。
【００７０】
次に、例えば図３に示した磁気シールド層付きのＭＲＡＭ多層スタック実装構造の作製プロセスを図９に示す。
【００７１】
まず、図９（ａ）に示すように、厚さ１００〜１５０μｍの銅合金をベース材５０とし、電気めっき法によりＡｕ−Ｎｉ−Ｃｕ配線部５１を形成する。次に図９（ｂ）に示すように、導体パターン５１の一部を残してポリイミド絶縁層５２を形成する。そして、図９（ｃ）に示すように絶縁層５２の開口部５３には、再びめっき法によりＡｕ／Ｎｉの外部端子（バンプ）５４を形成する。この状態から、図９（ｄ）に示すように、ベース材５０の不要部分をエッチングにより除去し、更に図９（ｅ）に示すように、絶縁保護膜５５を被覆し、インターポーザ基板（ＵＦＰＬ）４６を完成する。
【００７２】
続いて、図９（ｆ）に示すように、このインターポーザ基板４６に、はんだバンプ４７を設けたＭＲＡＭ素子３０をフリップチップ実装する。この際、例えば特開２００２−２２２９０１号公報に示されているように、周辺部に露出した層間電極５６をプラズマ洗浄等の方法でエッチング処理すると、その後の組み立ての信頼性が良好となる。
【００７３】
層間電極５６の上に同様のＵＦＰＬインターポーザ基板を実装し、この工程をチップ層数だけ繰り返すことにより、図３に示した積層構造のパッケージを構成する。そして、全体を樹脂封止した後、外部磁気シールド層３３を封止材３２の上部に配置することにより、磁気シールド効果を発揮させる。この磁気シールド層はパッケージの下部にも設けることができる。
【００７４】
しかし、図３の如き積層構造において、例えば下部２層がＭＲＡＭ素子であり、上部は外部磁気遮蔽の必要がない素子である場合は、下部２層を積層した後、層間電極上に磁気シールド層を設けることにより、より効果的に磁気シールドを行うことも可能である。
【００７５】
同様に、中間部の２層目及び３層目がＭＲＡＭ素子であるようなＳＩＰタイプの積層モジュールの場合は、１層目と２層目の間に下部磁気シールド層を設け、また３層目と４層目の間に上部磁気シールド層を設けることにより、効果的に磁気シールドすることも可能である。
【００７６】
本発明に基づくパッケージは、ＭＲＡＭ素子の積層構造からなるので、小さな面積の磁気シールド層であっても磁気シールド効果が良好な高密度実装のＭＲＡＭパッケージ構造を実現することができる。従って、パッケージ構造は上述したものに限られることはなく、例えば図１の変形例として、図１０に示すように、ＭＲＡＭ素子１０のパッケージの複数個を積層し、この積層パッケージの上、下に磁気シールド層３３、３４を設けることも、上述した磁気シールド効果と同等の磁気シールド効果を得ることができる。この例では、上下のパッケージ間に第３の磁気シールド層（図示せず）を設けてもよい。
【００７７】
また、図１１に平面図を示すように、ＭＲＡＭ素子３０は、ＤＲＡＭ等の他の素子３８と共に共通の基板上に混載したＳＩＰタイプの例えばＱＦＰ６０とし、ＭＲＡＭ素子３０の占有領域に磁気シールド層を設けることもできる。この混載パッケージは、図１や図１０に示した構造のいずれにおいても適用することができる。
【００７８】
また、パッケージの封止材３２を形成する樹脂としては、公知のシリカフィラーを用いた封止樹脂を用いることが可能である。しかし、磁気シールド効果を向上させるためには、図１２に例示するように、例えばフェライト粉末（フィラー）５６を含む封止樹脂などを用いるのがよい。
【００７９】
即ち、図１に示したように、フェライトフィラーを含まないパッケージに磁気シールド層３３、３４を設置した場合と、図１２に示したように、ＮｉＺｎフェライトフィラー（平均粒径２５μｍ、添加量８０重量%）含有のパッケージに磁気シールド層３３、３４を設置した場合とにおける内部磁界強度の差は、図１３に示すようになった。図１３は、これら２者の構造における、パッケージの長さ（測定距離）に対する内部侵入磁界強度の測定結果を示している。シールド材料としては、飽和磁化Ｍｓ＝２．３Ｔと高い飽和磁化を有するＦｅ−４９Ｃｏ−２Ｖを用い、磁気シールド層厚は３００μｍとし、外部印加磁界強度を５００Ｏｅとした。
【００８０】
図１３より、５００Ｏｅの外部磁界において、図１のシールド構造では内部磁界強度が１４６．９Ｏｅであるのに対して、図１２のシールド構造では内部磁界強度を７０．４Ｏｅに抑えることができることが確認できた。
【００８１】
この実験では、フェライトフィラーとしてＮｉＺｎフェライトを用いたが、フェライトフィラーとしてはこれに限らず、ＭｎＺｎフェライトやＢａフェライト、Ｓｒフェライトなど、酸化物磁性体なら何でもよい。また、金属軟磁性粉末の表面を絶縁処理したフィラーを用いても、同等もしくはそれ以上の磁気シールド効果を有することが期待できる。このようなフィラーの粒径は１０〜４０μｍ、添加量は７０〜９０重量％とするのが望ましい。フェライトフィラーがパッケージに対して７０重量%未満の含有量であると、良好なシールド効果が期待できず、また逆に９０重量%を超える場合は、成形時の熔融粘度が高くなり、パッケージ樹脂としての成形性に欠けてしまうことがある。
【００８２】
なお、上記の例では、磁気シールド層３３、３４は、封止材３２による封止後に封止材３２上に接着するか、或いは封止時に予めダイパッド４０下に接着しておくか或いは金型内に配置しておけばよい。図１の場合は、ＭＲＡＭ素子３０が、磁気シールド層３３、３４間に配置されたサンドウィッチ構造をなしているが、上記のいずれの構造でも、ＭＲＡＭのパッケージと一体化されていて、実装基板（回路基板）への実装を考慮すると望ましい構造である。
【００８３】
上述したいずれの磁気シールド構造においても、磁気シールド層３３、３４がＭＲＡＭ素子３０の占有面積領域に設けられているため、磁気シールド層のサイズが特に１５ｍｍ以下と小さくなり、その中心部では外部磁界による磁気飽和が生じ難くなっており、ＭＲＡＭ素子３０を外部印加磁界から十二分に磁気シールドする効果を有する。この場合、磁気シールド層３３、３４は、外部との間で閉じた磁気回路を形成していないが、これでも外部印加磁界を効果的に集めて磁気シールドすることができる。また、磁気シールド層３３、３４は、ＭＲＡＭ素子３０の上、下にそれぞれ存在するのがよいが、少なくとも一方に存在していてもシールド効果は発揮される。
【００８４】
また、上述したいずれの例においても、図８に示した結果から、上下の磁気シールド層間の間隔は３．５ｍｍ以下、特に３ｍｍ以下とするのが望ましい。
【００８５】
以上に説明した実施の形態は、本発明の技術的思想に基づいて種々の変形が可能である。
【００８６】
例えば、上述の磁気シールド材料の組成、種類、磁気シールド層の厚さや配置、ＭＲＡＭの構造等は様々に変化させてよい。磁気シールド層のサイズは、ＭＲＡＭ素子の占有面積領域と同一又は実質的に同一であってよく、実質的に同一の場合はＭＲＡＭ素子よりも幾分大きめ又は小さめであってもよく、また一辺が１５ｍｍ以内であれば様々に変化させてよい。磁気シールド層はＭＲＡＭ素子又はパッケージの上部及び下部の双方だけでなく、パッケージ中のＭＲＡＭ素子の上部及び／又は下部、或いは／並びに、ＭＲＡＭ素子のパッケージの上部及び／又は下部に配置されてよい。
【００８７】
また、本発明はＭＲＡＭに好適であるが、磁化可能な磁性層を有するメモリ素子からなる他の磁気メモリ装置にも適用可能である。
【００８８】
【発明の作用効果】
本発明は、上述したように、磁気メモリ装置、特にＭＲＡＭにおいて、メモリ素子の複数個を積層するか、或いはＤＲＡＭ等の他の素子と積層し、少なくともメモリ素子の占有面積領域に、メモリ素子を磁気シールドするための磁気シールド層を設けることによって（或いは、磁気シールド層をメモリ素子の表面側及び裏面側にそれぞれ設け、これらの磁気シールド層間の間隔を３．５ｍｍ以下と特定することによって）、素子の積層に対して素子面積又はパッケージサイズが減少するので、磁気シールド層のサイズをメモリ素子の占有面積相当分にまで小さくして磁気シールド層のエッジ部から中心部までの距離を短くし、中心部での磁気飽和を十二分に抑え、或いはメモリ素子に対する磁気シールドを十二分なものとし、磁気シールド効果を向上させ、磁気メモリ装置の動作を保証することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態によるＭＲＡＭパッケージの概略断面図である。
【図２】同、他のＭＲＡＭパッケージの概略断面図である。
【図３】同、他のＭＲＡＭパッケージの概略断面図である。
【図４】同、磁気シールド層間の内部磁界強度測定時の概略断面図、及び試料パッケージの概略断面図である。
【図５】同、ＱＦＰ１６０ＰＩＮパッケージに磁気シールド層（パーマロイ板）を上下に配置したときのパッケージ内部の磁界強度分布図である。
【図６】同、パッケージ上下両方に磁気シールド層を配置した時の内部磁界の大きさを、パッケージ端からの距離を横軸にとってプロットした磁界強度分布図である。
【図７】本発明の実施の形態による他のＭＲＡＭパッケージの概略断面図である。
【図８】同、磁気シールド層間の間隔に対する内部磁界強度分布図である。
【図９】同、図３のパッケージにおけるＭＲＡＭ実装構造の作製フローを示す断面図である。
【図１０】同、他のＭＲＡＭパッケージの概略断面図である。
【図１１】同、他のＭＲＡＭパッケージ（ＱＦＰ）の概略平面図である。
【図１２】同、更に他のＭＲＡＭパッケージの概略断面図である。
【図１３】同、内部磁界の測定距離（シールド長さ）に対する内部磁界強度分布図である。
【図１４】ＭＲＡＭのＴＭＲ素子の概略斜視図である。
【図１５】ＭＲＡＭのメモリセル部の一部の概略斜視図である。
【図１６】ＭＲＡＭのメモリセルの概略断面図である。
【図１７】ＭＲＡＭの等価回路図である。
【図１８】ＭＲＡＭの書き込み時の磁界応答特性図である。
【図１９】ＭＲＡＭの読み出し動作原理図である。
【符号の説明】
１…トップコート層、２…記憶層、３…トンネルバリア層、
４…第１の磁化固定層、５…反強磁性結合層、６…第２の磁化固定層、
７…反強磁性体層、８…下地層、９…支持基板、
１０…メモリセル（ＴＭＲ素子）、１１…ビット線、
１２…書き込み用ワード線、１３…シリコン基板、１４…ウェル領域、
１５…ゲート絶縁膜、１６…ゲート電極、１７…ソース領域、
１８…ドレイン領域、
１９…読み出し用電界効果トランジスタ（選択用トランジスタ）、
２０…ソース電極、２１…センスライン、２２…読み出し用配線、
２３…ドレイン電極、２６…磁化固定層、
３０…ＭＲＡＭ素子（ＴＭＲ素子内蔵）、３１…外部リード、３２…封止材、
３３、３４、４１…磁気シールド層、３７…ガウスメータ、
３８…他の素子（チップ）、４０…ダイパッド、４１…ボンディングワイヤ、
４２、４７…はんだバンプ、４６…ＵＦＰＬ、４８…層間バンプ、
４９…メイン基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an MRAM (Magnetic Random Access) which is a so-called nonvolatile memory, a magnetic random access memory comprising a memory element in which a magnetization fixed layer with a fixed magnetization direction and a magnetic layer capable of changing the magnetization direction are stacked. The present invention relates to a magnetic memory device configured as a memory) or a magnetic memory device including a memory element having a magnetizable magnetic layer.
[0002]
[Prior art]
With the rapid spread of information communication devices, especially small personal devices such as mobile terminals, the elements such as memory and logic that make up these devices have higher performance such as higher integration, higher speed, and lower power consumption. Is required.
[0003]
In particular, nonvolatile memories are considered essential in the ubiquitous era. The nonvolatile memory can protect important information including personal information even when power is consumed or trouble occurs or the server and the network are disconnected due to some trouble. In addition, recent portable devices are designed to reduce power consumption as much as possible by setting unnecessary circuit blocks to the standby state. However, if a non-volatile memory that can serve both as a high-speed work memory and a large-capacity storage memory can be realized. , Power consumption and memory waste can be eliminated. In addition, if a high-speed, large-capacity nonvolatile memory can be realized, an “instant-on” function that can be instantly started when the power is turned on becomes possible.
[0004]
Examples of the non-volatile memory include a flash memory using a semiconductor and an FRAM (Ferroelectric Random Access Memory) using a ferroelectric.
[0005]
However, the flash memory has a drawback that the writing speed is as slow as the order of μ seconds. On the other hand, in FRAM, the number of rewritable times is 10. 12 -10 14 However, it has been pointed out that the endurance is small and the microfabrication of the ferroelectric capacitor is difficult to replace completely with SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).
[0006]
For example, Wang et al., IEEE Trans. Magn. 33 (1997), 4498 are attracting attention as non-volatile memories with high speed, large capacity (high integration), and low power consumption. Is a magnetic memory called MRAM (Magnetic Random Access Memory), and has been attracting attention due to recent improvements in the properties of TMR (Tunnel Magnetoresistance) materials.
[0007]
The MRAM is a semiconductor magnetic memory using a magnetoresistive effect based on a spin-dependent conduction phenomenon peculiar to nanomagnets, and is a non-volatile memory that can hold a memory without supplying power from the outside. In addition, since the MRAM has a simple structure, it can be easily integrated, and since the recording can be performed by rotating the magnetic moment, the number of rewrites is large, and the access time is very high. It is anticipated and has already been reported in R. Scheuerlein et al, ISSCC Digest of Technical Papers, pp. 128-129, Feb. 2000 that it can operate at 100 MHz. Recently, as reported in k. Inomata, the 26th Annual Meeting of the Magnetic Society of Japan, 18aA-1, etc., it is expected to play a leading role in next-generation nonvolatile memory.
[0008]
Describing in more detail about such an MRAM, as illustrated in FIG. 14, a TMR element 10 serving as a memory element of an MRAM memory cell includes a memory layer provided on a support substrate 9 and whose magnetization is relatively easily rotated. 2 and the magnetization fixed layers 4 and 6.
[0009]
The magnetization fixed layer has two magnetization fixed layers of a first magnetization fixed layer 4 and a second magnetization fixed layer 6, and a conductor layer in which these magnetic layers are antiferromagnetically coupled between them. 5 is arranged. The memory layer 2 and the magnetization fixed layers 4 and 6 are made of a ferromagnetic material made of nickel, iron, cobalt, or an alloy thereof, and the material of the conductor layer 5 is ruthenium, copper, chromium, gold, silver Etc. can be used. The second magnetization fixed layer 6 is in contact with the antiferromagnetic material layer 7, and the second magnetization fixed layer 6 has a strong unidirectional magnetic anisotropy due to the exchange interaction acting between these layers. . As a material for the antiferromagnetic material layer 7, manganese alloys such as iron, nickel, platinum, iridium, and rhodium, cobalt, nickel oxide, and the like can be used.
[0010]
In addition, a tunnel barrier layer 3 made of an insulator made of an oxide or nitride such as aluminum, magnesium, or silicon is sandwiched between the storage layer 2 that is a magnetic layer and the first magnetization fixed layer 4. In addition to cutting off the magnetic coupling between the storage layer 2 and the fixed magnetization layer 4, it plays a role for flowing a tunnel current. Although these magnetic layers and conductor layers are mainly formed by sputtering, the tunnel barrier layer 3 can be obtained by oxidizing or nitriding a metal film formed by sputtering. The topcoat layer 1 has a role of preventing mutual diffusion between the TMR element 10 and wiring connected to the TMR element, reducing contact resistance, and preventing oxidation of the memory layer 2, and is usually made of a material such as Cu, Ta, or TiN. Can be used. The base electrode layer 8 is used for connection with a switching element connected in series with the TMR element. The underlayer 8 may also serve as the antiferromagnetic layer 7.
[0011]
In the memory cell configured as described above, as described later, information is read out by detecting a tunnel current change due to the magnetoresistive effect, and the effect depends on the relative magnetization directions of the storage layer and the magnetization fixed layer.
[0012]
FIG. 15 is an enlarged perspective view showing a part of a general MRAM in a simplified manner. Here, the read circuit portion is omitted for simplification, but includes, for example, nine memory cells, and has a bit line 11 and a write word line 12 that intersect each other. The TMR element 10 is disposed at these intersections, and writing to the TMR element 10 causes a current to flow through the bit line 11 and the write word line 12, and the bit line 11 is generated by a combined magnetic field generated therefrom. Is written with the magnetization direction of the storage layer 2 of the TMR element 10 at the intersection of the write word line 12 parallel or antiparallel to the magnetization fixed layer.
[0013]
FIG. 16 schematically shows a cross section of a memory cell. For example, a gate insulating film 15, a gate electrode 16, and a source region 17 formed in a p-type well region 14 formed in a p-type silicon semiconductor substrate 13. The n-type read field effect transistor 19 including the drain region 18 is disposed, and the write word line 12, the TMR element 10, and the bit line 11 are disposed thereon. A sense line 21 is connected to the source region 17 through a source electrode 20. The field effect transistor 19 functions as a switching element for reading, and a read wiring 22 drawn from between the word line 12 and the TMR element 10 is connected to the drain region 18 via the drain electrode 23. The transistor 19 may be an n-type or p-type field effect transistor, but various switching elements such as a diode, a bipolar transistor, and a MESFET (Metal Semiconductor Field Effect Transistor) can be used instead.
[0014]
FIG. 17 shows an equivalent circuit diagram of the MRAM, which includes, for example, six memory cells, has a bit line 11 and a write word line 12 that intersect each other, and a storage element is located at the intersection of these write lines. 10 includes a field effect transistor 19 and a sense line 21 which are connected to the memory element 10 and perform element selection at the time of reading. The sense line 21 is connected to the sense amplifier 23 and detects stored information. In the figure, 24 is a bidirectional write word line current drive circuit, and 25 is a bit line current drive circuit.
[0015]
FIG. 18 is an asteroid curve showing the write condition of the MRAM, and the applied easy magnetization axial magnetic field H EA And hard magnetic axis H HA Shows the reversal threshold value of the magnetization direction of the storage layer. When a corresponding synthetic magnetic field vector is generated outside the asteroid curve, magnetic field reversal occurs, but the synthetic magnetic field vector inside the asteroid curve does not invert the cell from one of its current bistable states. Also, in the cells other than the intersection of the word line and the bit line through which a current is flowing, a magnetic field generated by the word line or the bit line alone is applied. K In the above case, the magnetization direction of the cells other than the intersection is also reversed, so that the selected cell can be selectively written only when the combined magnetic field is in the gray region in the figure.
[0016]
As described above, in the MRAM, by using the two write lines of the bit line and the word line, only the designated memory cell is selectively written by the reversal of the magnetic spin using the asteroid magnetization reversal characteristic. It is common. The combined magnetization in the single storage area is the easy magnetization axial magnetic field H applied to it. EA And hard magnetic axis H HA And is determined by vector composition. The write current flowing through the bit line causes the cell to have a magnetic field H in the direction of easy magnetization. EA And the current flowing through the word line causes the cell to have a magnetic field H in the direction of the hard axis. HA Apply.
[0017]
FIG. 19 explains the read operation of the MRAM. Here, the layer configuration of the TMR element 10 is schematically illustrated, the above-described magnetization fixed layer is shown as a single layer 26, and the components other than the storage layer 2 and the tunnel barrier layer 3 are not illustrated.
[0018]
That is, as described above, the information is written by inverting the magnetic spin of the cell by the combined magnetic field at the intersections of the bit lines 11 and the word lines 12 wired in a matrix and changing the direction to “1”, “0”. Record as information. The reading is performed using the TMR effect applying the magnetoresistive effect. The TMR effect is a phenomenon in which the resistance value changes depending on the direction of the magnetic spin, and the magnetic spin is antiparallel and has a high resistance state. Information “1” and “0” are detected based on a low resistance state in which the magnetic spins are parallel. In this reading, a read current (tunnel current) is caused to flow between the word line 12 and the bit line 11 and an output corresponding to the level of the resistance is read to the sense line 21 via the read field effect transistor 19 described above. By doing.
[0019]
As described above, MRAM is expected as a high-speed and nonvolatile large-capacity memory. However, since a magnetic material is used for storage, information is erased or rewritten due to the influence of an external magnetic field. There is a problem of end. The switching magnetic field in the easy axis direction and the switching magnetic field H in the hard axis direction described in FIG. SW Is 20 to 200 oersted (Oe) depending on the material, and is several mA when converted into current (RHKoch et al., Phys. Rev. Lett. 84, 5419 (2000), JZSun et al., 2001 8 th This is because it is small (see Joint Magnetism and Magnetic Material). Moreover, since the coercive force (Hc) at the time of writing is, for example, about several Oe to 10 Oe, it is impossible to selectively write to a predetermined memory cell if an internal leakage magnetic field due to an external magnetic field higher than that acts. It may become.
[0020]
Therefore, as a step toward the practical application of MRAM, there is an urgent need to establish an external magnetic countermeasure, that is, a magnetic shield structure that shields the element from external electromagnetic waves.
[0021]
The environment in which the MRAM is mounted and used is mainly on the high-density mounting substrate and inside the electronic device. Depending on the type of electronic equipment, due to the recent development of high-density mounting, semiconductor elements, communication elements, ultra-small motors, etc. are mounted with high density on high-density mounting boards. The antenna element, various mechanical parts, power supply, etc. are mounted with high density to constitute one device.
[0022]
Such mixed mounting is one of the features of MRAM as a non-volatile memory. However, an environment in which a magnetic field component in a wide frequency range from DC to low frequencies is mixed around MRAM. Therefore, in order to ensure the reliability of MRAM recording and holding, it is required to improve the resistance from an external magnetic field by devising the mounting method and shield structure of the MRAM itself.
[0023]
As the magnitude of such an external magnetic field, for example, in a magnetic card such as a credit card or a bank cash card, it is defined that the magnetic field is resistant to a magnetic field of 500 to 600 Oe. For this reason, in the field of magnetic cards, Co-coated γ-Fe 2 O 3 This can be achieved by using a magnetic material having a large coercive force such as Ba ferrite. Also in the field of prepaid cards, it is necessary to have resistance to a magnetic field such as 350 to 600 Oe. Since the MRAM element is a device that is mounted in an electronic device casing and is supposed to be carried, it is necessary to have resistance against a strong external magnetic field equivalent to that of magnetic cards. It is necessary to suppress the magnitude of the magnetic field to 10 to 20 Oe or less.
[0024]
As a magnetic shield structure of MRAM, a proposal has been made to provide magnetic shield characteristics by using an insulating ferrite (MnZn and NiZn ferrite) layer for a passivation film of an MRAM element (see Patent Document 1 described later). In addition, a proposal has been made to provide a magnetic permeability effect by attaching a high-permeability magnetic material such as permalloy from above and below the package to prevent magnetic flux from entering the internal elements (see Patent Document 2 described later). Furthermore, a structure in which a shield cover is placed on the element with a magnetic material such as soft iron is disclosed (see Patent Document 3 described later).
[0025]
[Patent Document 1]
US Pat. No. 5,902,690 specification and drawing (column 5, FIG. 1 and FIG. 3)
[Patent Document 2]
US Pat. No. 5,939,772 specification and drawings (column 2, FIGS. 1 and 2)
[Patent Document 3]
Japanese Patent Laid-Open No. 2001-250206 (right column on page 5, FIG. 6)
[0026]
[Problems to be solved by the invention]
In order to prevent the external magnetic flux from entering the memory cell of the MRAM, it is most important to provide a magnetic path that prevents the magnetic flux from entering the inside by circulating a magnetic material having a high magnetic permeability around the element.
[0027]
However, when the element passivation film is formed of ferrite as in Patent Document 1 (US Pat. No. 5,902,690), the saturation magnetization of the ferrite itself is low (0.2 to 0.5 Tesla (T) with a general ferrite material). Therefore, it is impossible to completely prevent the external magnetic field from entering. The saturation magnetization of the ferrite itself is about 0.2 to 0.35 T for NiZn ferrite and about 0.35 to 0.47 T for MnZn ferrite, but the magnitude of the external magnetic field penetrating into the MRAM element is as large as several hundred Oe. At about the saturation magnetization, the magnetic permeability of the ferrite is almost 1, and the function is lost. In Patent Document 1, there is no description of the film thickness. However, since the passivation film is usually about 0.1 μm at most, it is too thin as a magnetic shield layer, so that almost no effect can be expected. Moreover, when ferrite is used for the passivation film, since the ferrite is a magnetic oxide, oxygen deficiency is likely to occur when the film is formed by sputtering, and it is difficult to use complete ferrite as the passivation film.
[0028]
Patent Document 2 (US Pat. No. 5,939,772) describes a structure in which the top and bottom of a package are covered with a permalloy layer. By using permalloy, higher shielding performance than that of a ferrite passivation film can be obtained. However, although the magnetic permeability of Mu Metal disclosed in Patent Document 2 is as high as about μi = 100,000, the saturation magnetization is as low as 0.7 to 0.8 T, and can easily be applied to an external magnetic field. Since saturation becomes μ = 1, there is a disadvantage that the thickness of the shield layer must be considerably thick in order to obtain a complete magnetic shielding effect. Therefore, as a structure for preventing the magnetic field of several hundred Oe from penetrating practically, it is imperfect as a magnetic shield layer from the viewpoint that the saturation magnetization of permalloy is too small and its thickness is too thin.
[0029]
Patent Document 3 (Japanese Patent Laid-Open No. 2001-250206) discloses a magnetic shield structure using soft iron or the like, but this only covers the upper part of the element, so that the magnetic shield is incomplete, Soft iron has a saturation magnetization of 1.7 T, a magnetic permeability of about 300 in μi, and has insufficient magnetic properties. Therefore, even if the magnetic shield is performed with the structure described in Patent Document 3, it is extremely difficult to completely prevent the intrusion of the external magnetic field.
[0030]
The present invention has been made in view of the above circumstances, and its object is to sufficiently shield the MRAM element even against a large external magnetic field and from the environment where the MRAM element is applied. It is possible to guarantee a problem-free operation with respect to the magnetic field.
[0031]
[Means for Solving the Problems]
That is, the present invention relates to a magnetic memory device configured as a magnetic random access memory including a memory element in which a magnetization fixed layer having a fixed magnetization direction and a magnetic layer capable of changing the magnetization direction are stacked, or In a magnetic memory device comprising a memory element having a magnetizable magnetic layer, a plurality of the memory elements, or the memory elements and other elements are stacked, and at least in the area occupied by the memory elements, the memory elements The present invention relates to a magnetic memory device (hereinafter referred to as a first magnetic memory device of the present invention) characterized in that a magnetic shield layer is provided for magnetically shielding the magnetic field.
[0032]
The present invention also provides a magnetic memory device configured as a magnetic random access memory including a memory element in which a magnetization fixed layer having a fixed magnetization direction and a magnetic layer capable of changing the magnetization direction are stacked, or In a magnetic memory device including a memory element having a magnetizable magnetic layer, a magnetic shield layer for magnetically shielding the memory element is provided on each of a front surface side and a back surface side of the memory element, and a space between these magnetic shield layers A magnetic memory device (hereinafter referred to as a second magnetic memory device of the present invention) is also provided.
[0033]
The present inventor has studied magnetic shielding for memory elements in magnetic memory devices such as MRAM, and has come to recognize the following. The magnetic shield effect attenuates with the magnetic saturation of the magnetic material forming the magnetic shield layer, but the magnetization saturation of the magnetic shield layer having a plate shape or the like is from the place where the demagnetizing field is minimized, that is, from the edge portion. Since the magnetic shield layer is applied to the package, the portion having the weakest shielding effect is the center of the package because it starts from the farthest point.
[0034]
However, in any of the conventional techniques described above, knowledge about the size of the package and the size of the magnetic shield layer is not shown. Normally, in a magnetic shield, it is essential that the magnetic shield material is not magnetically saturated with respect to an external magnetic field, but the coercive force is small as in an Fe-Ni soft magnetic alloy (in other words, an anisotropic magnetic field). Magnetic materials (which are small in size) reach magnetic saturation with a small magnetic field and are not suitable for shielding a large external magnetic field as in an MRAM device. In particular, when the magnetic shield layer has a large area, its magnetic moment is easily oriented in the plane due to shape anisotropy at the center of the magnetic shield layer, and the shielding effect actually decreases. Attention should also be paid to the shield area.
[0035]
As a result of intensive studies based on such recognition, the present inventor has laminated a plurality of memory elements or laminated with other elements such as a DRAM in a magnetic memory device, particularly an MRAM, and at least the memory elements. By providing a magnetic shield layer for magnetically shielding the memory element in the occupied area region, the element area or the package size is reduced corresponding to the stacking of the elements. Therefore, the size of the magnetic shield layer is reduced to the equivalent of the occupied area of the memory element. The distance from the edge to the center of the magnetic shield layer is shortened to a minimum, the magnetic saturation at the center is sufficiently suppressed, the magnetic shield effect is improved, and the operation of the magnetic memory device can be guaranteed. And the first magnetic memory device of the present invention has been reached.
[0036]
In a magnetic memory device, particularly an MRAM, a magnetic shield layer for magnetically shielding a memory element is provided on each of the front surface side and the back surface side of the memory element, and the distance between these magnetic shield layers is specified to be 3.5 mm or less. Thus, it has been found that the magnetic shield effect on the memory element is improved and the operation of the magnetic memory device can be guaranteed, and the second magnetic memory device of the present invention has been reached.
[0037]
Here, the magnetic shield layer may be the same size as the area occupied by the MRAM element, but may be somewhat larger or smaller as long as it is substantially the same size, depending on the size and shape of the MRAM element. You may change the size and shape.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
In the first and second magnetic memory devices of the present invention, if the distance between the opposing sides of the magnetic shield layer of one layer is 15 mm or less, magnetic saturation at the center of the magnetic shield layer is ensured and twelfth. Can be suppressed in minutes. Here, the distance between opposite sides means the distance between two sides parallel to each other (or not parallel but facing each other). For example, in the case of a square shape, the length of one side may be a rectangular shape. It is the length of the long side.
[0039]
In the second magnetic memory device of the present invention, a plurality of the memory elements or a plurality of the memory elements and other elements such as a DRAM are stacked, and the magnetic shield layer is provided at least in an area occupied by the memory elements. If provided, the effect of the first magnetic memory device of the present invention can also be obtained.
[0040]
In the first and second magnetic memory devices of the present invention, a plurality of the memory elements, or the memory elements and other elements such as a DRAM may be mixedly mounted on a substrate.
[0041]
In addition, in order for the magnetic shield layer to exhibit the magnetic shield effect, it is provided on the upper and / or lower portion of the memory device package and / or on the upper and / or lower portion of the memory device in the package of the memory device. It is desirable that they are arranged. The magnetic shield layer may be provided as an intermediate layer in the laminated structure of the elements.
[0042]
For example, in a multi-chip module type stacked structure module including a plurality of chips as the MRAM package structure, the magnetic shield layer may be provided as a lower layer or an intermediate layer. In addition, in a SIP (System in Package) type MRAM mixed module, a MRAM magnetic shield layer is provided in a package having a structure in which a plurality of IC (integrated circuit) chips are stacked in the height direction, such as stack mounting, stacked mounting, and multilayer mounting. You may provide as the upper part, the lower part, or an intermediate | middle layer. In addition, in an MRAM mixed module such as SIP, a plurality of IC chips are arranged on the same plane, but in a structure in which a plurality of IC chips are stacked in the height direction, the magnetic shield layer of the MRAM is placed above, below or It may be provided as an intermediate layer. In either case, the magnetic shielding effect against an external magnetic field can be enhanced.
[0043]
The soft magnetic material forming the magnetic shield layer is made of a soft magnetic material having a high saturation magnetization and a high permeability containing at least one of Fe, Co, and Ni. In particular, FeCoV, FeNi, FeSiAl, FeSiB, FeAl It is preferably made of a soft magnetic material having a high saturation magnetization, such as high magnetic permeability.
[0044]
Further, when the sealing material contains a soft magnetic filler, the magnetic shielding effect can be further improved.
[0045]
The present invention is suitable for an MRAM. In such an MRAM, an insulator layer or a conductor layer is sandwiched between the magnetization fixed layer and the magnetic layer, and provided on the upper surface and the lower surface of the memory element. Information is written by magnetizing the magnetic layer in a predetermined direction by a magnetic field induced by passing currents through the wirings as the bit line and the word line, and this write information is used for the tunnel magnetoresistance effect (TMR effect) between the wirings. ).
[0046]
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0047]
1 to 3 respectively illustrate a plurality of MRAM elements or a package in which MRAM elements and other elements are mixedly mounted (MRAM element mixed package) having various magnetic shield structures according to the present embodiment. .
[0048]
In the example shown in FIG. 1, the MRAM element (chip including the memory cell portion and the peripheral circuit portion) 30 shown in FIGS. 14 to 16, DRAM, MPU (Micro Processing Unit), DSP (Digital Signal Processor), RF (Radio Frequency) Other elements 38 such as elements are stacked on the die pad 40, and are connected by bonding wires 41 to external leads 31 connected to a mounting substrate (not shown). Sealed by a sealing material 32 such as epoxy resin (here, the MRAM element 30 has the same structure and operation principle as those of the MRAM described above, and therefore the description thereof is omitted and the die pad 40 is included. The lead frame is shown in simplified form). This example is a QFP type package, in which a MRAM element 30 is sealed in a so-called SIP package in which a plurality of chips are stacked to form a single chip, and a magnetic shield layer is provided. It is a semiconductor module.
[0049]
In accordance with the present invention, magnetic shield layers 33 and 34 made of permalloy (FeNi) or the like are provided in the area regions corresponding to the occupied area region of the MRAM element 30 in contact with the upper and lower surfaces of the sealing material 32, respectively. Yes.
[0050]
FIG. 2 shows a BGA (Ball Grid Aray) type package for high speed and high pin count, in which a plurality of chips (MRAM element 30 and other IC chips 38) are stacked, and terminal electrodes are formed by rearrangement wiring. The multi-function module package is bonded to an interposer substrate 43 having solder bumps 42 by wires 44 and sealed with a sealing material 32 to form a single chip. Magnetic shield layers 33 and 45 such as permalloy are provided on the surface of the package and below the MRAM element in the package.
[0051]
FIG. 3 shows an example in which a structure in which four layers of MRAM elements 30 are stacked on a UFPL (Ultra Fine Pitch Lead frame) 46 with solder bumps 47 is sealed with a sealing material 32, and a magnetic shield layer 33 is provided on the package. . Each LFPL 45 is connected by an interlayer bump 48, and the lowermost UFPL 45 is connected to a main board (circuit board) 49.
[0052]
The MRAM element is usually put on a substrate after being resin-sealed in a package such as QFP (Quad Flat Package), SOP (Small Outline Package), etc., and is put to practical use. The size is almost determined by the standard depending on the number of pins. For example, a device having 48 pins is called QFP-48PIN. The MRAM element is a non-volatile memory element, and a multi-pin package is required. In the case of an MRAM element having a storage capacity of 1 Mbit class, it is necessary to use a package of about QFP160PIN or QFP208PIN.
[0053]
However, in Patent Document 2 (US Pat. No. 5,939,772) described above, it is disclosed that a magnetic shield is achieved by covering the top and bottom of the package with permalloy plates. However, as described above, permalloy has low saturation magnetization. In addition, because of the fact that it is easily saturated at the center, a shield configuration in a practically acceptable range cannot be obtained.
[0054]
In any of the packages shown in FIGS. 1 to 3, a plurality of MRAM elements 30 or a plurality of MRAM elements 30 and other elements 38 are stacked in accordance with the present invention. Therefore, the size of the magnetic shield layers 33 and 34 can be reduced to 15 mm or less to improve the magnetic shield effect.
[0055]
Therefore, in order to guarantee the normal operation of the MRAM element, the present inventor has the performance that the internal (MRAM element part) is 10 to 20 Oe or less even when a large DC external magnetic field of 500 Oe at the maximum is applied. An experiment was conducted with the aim of obtaining. FIG. 4A shows a schematic diagram at the time of the experiment. For example, two permalloy magnetic shield layers 33 and 34 each having a length L28 mm × L28 mm and a thickness t = 200 μm are arranged at a distance d of 3.45 mm. The Gauss meter 37 is arranged at the center (hollow part), a DC magnetic field of 500 Oe is applied in parallel with the magnetic shield layer, and the Gauss meter 37 is moved in parallel with the magnetic shield layer, so that the center is formed from the end. The internal magnetic field strength (leakage magnetic field strength from the magnetic shield layer) up to the part was measured, and an effective magnetic shield material was examined.
[0056]
FIG. 5 shows the results measured by the method shown in FIG. 4A, which shows the magnetic field strength inside the package in a structure in which permalloy plates are arranged vertically on a 28 mm × 28 mm, 3.45 mm thick QFP160PIN package. It corresponds to the distribution. That is, the externally applied magnetic field strength is 500 Oe, and the QFP160PIN package has a side of about 28 mm and a thickness of 3.45 mm as shown in FIG. 4B, and only the MRAM element 30 ′ is arranged at the center. .
[0057]
As can be seen from FIG. 5, the magnetic field strength is about 500 Oe at the end of the magnetic shield layer, and the internal magnetic field strength is about 370 Oe when entering about 1.5 mm from the end of the magnetic shield layer. However, the internal magnetic field strength does not decrease even when it enters the interior further, and a magnetic field strength of 370 to 400 Oe exists. This magnetic field strength exceeds the magnitude that hinders the memory operation of the MRAM element 30 ′, and does not make sense as a magnetic shield. This is because the magnetic anisotropy is already in the plane before the external magnetic field is applied due to the shape anisotropy in the central portion of the magnetic shield layer, and is not useful as a magnetic shield.
[0058]
Usually, in order to guarantee the storage operation of the MRAM, it is necessary to reduce the magnetic field strength to 10 to 20 Oe or less in at least the MRAM element portion.
[0059]
Therefore, the present inventor has studied in detail how much the length of one side of the magnetic shield layer can prevent magnetic saturation. FIG. 6 shows a result of measuring the magnitude of the internal magnetic field when the magnetic shield layers are formed on both the upper and lower sides of the package by the method shown in FIG. . As the magnetic shield material, FeCoV having a saturation magnetization Ms = 2.3T and an initial permeability μi = 1000 was used, and its thickness was 200 μm. Moreover, the size of one side of the magnetic shield layer was 10, 15, 20, and 28 mm, and measurement was performed at an external applied magnetic field strength of 500 Oe.
[0060]
As can be seen from the results of FIG. 6, when the sides are 20 mm and 28 mm, the magnetic field intensity at the center is increased because the inside is magnetically saturated. On the other hand, if one side is 15 mm or 10 mm, the magnetic field strength at the center is remarkably reduced to 10 to 20 Oe or less. Therefore, when using FeCoV as the magnetic shield layer, when shielding a high magnetic field strength of 500 Oe or more, it is necessary to suppress one side (or the distance between opposite sides) of the magnetic shield layer to 15 mm or less. However, if one side of the magnetic shield layer is too short, the magnetic shielding effect will be poor. Therefore, the one side (or the distance between the opposing sides) should be 3 mm or more, more preferably 5 mm or more in consideration of the size of the MRAM element. .
[0061]
Even if the MRAM element is of the 1 Mbit class, it is usually a few mm square size, and if one side of the magnetic shield layer is 10 mm, the effective magnetic shield area is about 8 mm on one side, so that it can be magnetically shielded without any problem. I understand that. Therefore, as shown in the above-mentioned Patent Document 2 (US Pat. No. 5,939,772), the structure covering almost all of the package deteriorates the magnetic shield performance. However, according to the present invention, the MRAM is substantially reduced. When a magnetic shield layer is provided only in the area occupied by the element 30, the size of the magnetic shield layer is 15 mm or less on each side, preferably 10 mm or less. It can be greatly improved.
[0062]
In particular, the package thickness of the RAM element must be a certain value or less due to restrictions on the mounting surface, and a large number of pins must be taken. The MRAM element is mounted together with another element 38 such as a DRAM, and is often mounted and used together with other ICs rather than the case where the MRAM element is used alone. In the package, the MRAM element is stacked with other elements according to the present invention, and the magnetic shield layers 33 and 34 are provided substantially only in the area occupied by the MRAM element 30, thereby reducing the package size and the magnetic shield layer. It is clear from the above results that one side of 33 and 34 can be made 15 mm or less and the magnetic shielding effect is greatly improved (this is the same for the examples shown in FIGS. 1 to 3 and other examples described later). Is).
[0063]
As described above, as shown in FIG. 6, if the length of one side of the magnetic shield layer is 15 mm or less, a magnetic shielding effect can be expected with a shield material having a thickness of 200 μm, and one side is 10 mm. The same effect can be expected with a magnetic shield layer having a thickness of about 150 μm.
[0064]
However, since the magnetic shield effect should be reduced if the gap between the magnetic shield layers becomes larger than necessary, the present inventor subsequently examined this point in detail.
[0065]
For example, as shown in FIG. 7, in a package fixed to a side of 10 mm of the magnetic shield layer, the change in the internal magnetic field strength with respect to the distance d between the magnetic shield layers 33 and 34 is changed as shown in FIG. The result of measurement is shown in FIG. The magnetic shield layer was formed of FeCoV alloy, the magnetic shield layer thickness was 200 μm, and the externally applied magnetic field strength was 500 Oe.
[0066]
From this result, the gap between the magnetic shield layers on the top and bottom of the package is increased, and if it exceeds 3.5 mm, the internal magnetic field strength increases rapidly. Therefore, when using a magnetic shield with a side of 10 mm, the shield It is necessary to set the distance to 3.5 mm or less.
[0067]
Further, when one side of the magnetic shield layer was measured similarly at 15 mm, as shown in FIG. 8B, when the distance d between the magnetic shield layers 33 and 34 exceeded 3 mm, the internal magnetic field strength suddenly increased. Therefore, when using a magnetic shield having a side of 15 mm, it has been found that the distance between the shields must be 3 mm or less.
[0068]
From this result, the magnetic shield of the MRAM has an effective shield range determined by the characteristics, thickness, length of one side, and shield interval of the magnetic shield layer. For example, in a shield structure with a magnetic shield layer thickness of 200 μm in an FeCoV alloy It has been found that when the length of one side of the magnetic shield layer is 10 mm or less, it is necessary to mount the MRAM elements at a high density in a space where the distance between the magnetic shield layers is 3.5 mm or less. However, considering the size and thickness of the MRAM element, one side of the magnetic shield layer is 3 mm or more, preferably 5 mm or more, and the interval between the magnetic shield layers is about 100 to 400 μm in thickness of the MRAM chip. The thickness is at least 0.2 mm, preferably 0.5 mm or more.
[0069]
An MRAM element may be used alone, but most of them are used together with an MPU, DSP, RF element, etc., so it can be considered to be an MRAM mixed element, but considering the limitation due to the size of one side of the magnetic shield layer It is necessary to mount with high density due to a small area. According to the present invention, as shown in FIG. 1 to FIG. 3, a high-functional package that achieves high-density mounting and external magnetic shielding of MRAM at the same time by applying the bare chip stack mounting process is provided. Can do.
[0070]
Next, for example, a manufacturing process of an MRAM multilayer stack mounting structure with a magnetic shield layer shown in FIG. 3 is shown in FIG.
[0071]
First, as shown in FIG. 9A, an Au—Ni—Cu wiring portion 51 is formed by electroplating using a copper alloy having a thickness of 100 to 150 μm as a base material 50. Next, as shown in FIG. 9B, a polyimide insulating layer 52 is formed leaving part of the conductor pattern 51. Then, as shown in FIG. 9C, Au / Ni external terminals (bumps) 54 are formed again in the opening 53 of the insulating layer 52 by plating. From this state, as shown in FIG. 9 (d), unnecessary portions of the base material 50 are removed by etching, and further, as shown in FIG. 9 (e), an insulating protective film 55 is covered to form an interposer substrate (UFPL). Complete 46.
[0072]
Subsequently, as shown in FIG. 9F, the MRAM element 30 provided with the solder bumps 47 is flip-chip mounted on the interposer substrate 46. At this time, as shown in, for example, Japanese Patent Application Laid-Open No. 2002-222901, if the interlayer electrode 56 exposed in the peripheral portion is etched by a method such as plasma cleaning, the reliability of the subsequent assembly is improved.
[0073]
A similar UFPL interposer substrate is mounted on the interlayer electrode 56, and this process is repeated as many times as the number of chip layers, thereby forming the package having the stacked structure shown in FIG. And after sealing the whole with resin, the magnetic shielding effect is exhibited by arranging the external magnetic shielding layer 33 on the upper part of the sealing material 32. This magnetic shield layer can also be provided under the package.
[0074]
However, in the laminated structure as shown in FIG. 3, for example, when the lower two layers are MRAM elements and the upper part is an element that does not require external magnetic shielding, after the lower two layers are laminated, the magnetic shield layer is formed on the interlayer electrode. By providing the magnetic shield, it is possible to more effectively perform magnetic shielding.
[0075]
Similarly, in the case of a SIP type laminated module in which the second and third layers in the middle are MRAM elements, a lower magnetic shield layer is provided between the first and second layers, and the third layer By providing an upper magnetic shield layer between the first layer and the fourth layer, it is possible to effectively shield the magnetic layer.
[0076]
Since the package according to the present invention has a laminated structure of MRAM elements, it is possible to realize a high-density mounting MRAM package structure having a good magnetic shield effect even with a small area magnetic shield layer. Therefore, the package structure is not limited to that described above. For example, as a modification of FIG. 1, a plurality of MRAM element 10 packages are stacked as shown in FIG. Providing the magnetic shield layers 33 and 34 can also obtain a magnetic shield effect equivalent to the magnetic shield effect described above. In this example, a third magnetic shield layer (not shown) may be provided between the upper and lower packages.
[0077]
As shown in the plan view of FIG. 11, the MRAM element 30 is a SIP type QFP 60, for example, embedded on a common substrate together with another element 38 such as a DRAM, and a magnetic shield layer is provided in the occupied area of the MRAM element 30. It can also be provided. This mixed package can be applied to any of the structures shown in FIGS.
[0078]
Further, as a resin for forming the package sealing material 32, a sealing resin using a known silica filler can be used. However, in order to improve the magnetic shield effect, for example, a sealing resin containing a ferrite powder (filler) 56 may be used as illustrated in FIG.
[0079]
That is, as shown in FIG. 1, when the magnetic shield layers 33 and 34 are installed in a package not containing a ferrite filler, and as shown in FIG. 12, a NiZn ferrite filler (average particle size 25 μm, added amount 80 wt. The difference in the internal magnetic field strength between the case where the magnetic shield layers 33 and 34 are installed in the package containing%) is as shown in FIG. FIG. 13 shows the measurement results of the internal penetration magnetic field strength with respect to the package length (measurement distance) in these two structures. As the shield material, Fe-49Co-2V having a saturation magnetization Ms = 2.3T and high saturation magnetization was used, the magnetic shield layer thickness was 300 μm, and the externally applied magnetic field strength was 500 Oe.
[0080]
From FIG. 13, it is confirmed that the internal magnetic field strength can be suppressed to 70.4 Oe in the shield structure of FIG. 12 while the internal magnetic field strength is 146.9 Oe in the shield structure of FIG. 1 in the external magnetic field of 500 Oe. did it.
[0081]
In this experiment, NiZn ferrite was used as the ferrite filler. However, the ferrite filler is not limited to this, and any oxide magnetic material such as MnZn ferrite, Ba ferrite, and Sr ferrite may be used. Moreover, even if the filler which insulated the surface of the metal soft magnetic powder is used, it can be expected to have a magnetic shielding effect equivalent to or higher than that. The particle size of such a filler is desirably 10 to 40 μm and the addition amount is 70 to 90% by weight. If the ferrite filler content is less than 70% by weight with respect to the package, a good shielding effect cannot be expected. Conversely, if it exceeds 90% by weight, the melt viscosity at the time of molding becomes high, and as a package resin. The moldability may be lacking.
[0082]
In the above example, the magnetic shield layers 33 and 34 are bonded on the sealing material 32 after sealing with the sealing material 32, or are bonded in advance under the die pad 40 at the time of sealing, or a mold. Just place it inside. In the case of FIG. 1, the MRAM element 30 has a sandwich structure disposed between the magnetic shield layers 33 and 34. However, in any of the above structures, the MRAM element 30 is integrated with the MRAM package and mounted on the mounting substrate ( This is a desirable structure in consideration of mounting on a circuit board.
[0083]
In any of the magnetic shield structures described above, since the magnetic shield layers 33 and 34 are provided in the area occupied by the MRAM element 30, the size of the magnetic shield layer is particularly small at 15 mm or less. The magnetic saturation due to the magnetic field is less likely to occur, and the MRAM element 30 is sufficiently shielded from the externally applied magnetic field. In this case, the magnetic shield layers 33 and 34 do not form a closed magnetic circuit with the outside, but even this can effectively collect the externally applied magnetic field and shield it. The magnetic shield layers 33 and 34 are preferably provided above and below the MRAM element 30, respectively, but the shielding effect is exhibited even if they are present on at least one of them.
[0084]
In any of the above-described examples, it is desirable from the results shown in FIG. 8 that the distance between the upper and lower magnetic shield layers is 3.5 mm or less, particularly 3 mm or less.
[0085]
The embodiment described above can be variously modified based on the technical idea of the present invention.
[0086]
For example, the composition and type of the magnetic shield material described above, the thickness and arrangement of the magnetic shield layer, the structure of the MRAM, and the like may be variously changed. The size of the magnetic shield layer may be the same as or substantially the same as the area occupied by the MRAM element, and may be somewhat larger or smaller than the MRAM element if the area is substantially the same. Various changes may be made within 15 mm. The magnetic shield layer may be disposed not only on the top and bottom of the MRAM device or package, but also on the top and / or bottom of the MRAM device in the package, and / or on the top and / or bottom of the package of the MRAM device.
[0087]
The present invention is suitable for an MRAM, but can also be applied to other magnetic memory devices including a memory element having a magnetizable magnetic layer.
[0088]
[Effects of the invention]
As described above, according to the present invention, in a magnetic memory device, in particular, an MRAM, a plurality of memory elements are stacked or stacked with other elements such as a DRAM, and at least the memory elements are arranged in an area occupied by the memory elements. By providing a magnetic shield layer for magnetic shielding (or by providing a magnetic shield layer on each of the front surface side and the back surface side of the memory element and specifying an interval between these magnetic shield layers of 3.5 mm or less), Since the element area or package size is reduced with respect to the stack of elements, the size of the magnetic shield layer is reduced to the equivalent of the area occupied by the memory element, and the distance from the edge portion to the center portion of the magnetic shield layer is shortened. The magnetic saturation at the center is sufficiently suppressed, or the magnetic shield for the memory element is sufficient. The improved, it is possible to ensure the operation of the magnetic memory device.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of an MRAM package according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of another MRAM package.
FIG. 3 is a schematic sectional view of another MRAM package.
FIG. 4 is a schematic cross-sectional view when measuring the internal magnetic field strength between magnetic shield layers, and a schematic cross-sectional view of a sample package.
FIG. 5 is a magnetic field intensity distribution diagram inside the package when magnetic shield layers (permalloy plates) are vertically arranged in the QFP160 PIN package.
FIG. 6 is a magnetic field intensity distribution diagram in which the magnitude of the internal magnetic field when magnetic shield layers are arranged on both the upper and lower sides of the package is plotted with the distance from the package edge as the horizontal axis.
FIG. 7 is a schematic cross-sectional view of another MRAM package according to an embodiment of the present invention.
FIG. 8 is an internal magnetic field strength distribution diagram with respect to a gap between magnetic shield layers.
9 is a cross-sectional view showing a manufacturing flow of the MRAM mounting structure in the package of FIG. 3; FIG.
FIG. 10 is a schematic sectional view of another MRAM package.
FIG. 11 is a schematic plan view of another MRAM package (QFP).
FIG. 12 is a schematic cross-sectional view of still another MRAM package.
FIG. 13 is an internal magnetic field strength distribution diagram with respect to a measurement distance (shield length) of the internal magnetic field.
FIG. 14 is a schematic perspective view of a TMR element of MRAM.
FIG. 15 is a schematic perspective view of a part of a memory cell portion of an MRAM.
FIG. 16 is a schematic cross-sectional view of an MRAM memory cell.
FIG. 17 is an equivalent circuit diagram of the MRAM.
FIG. 18 is a magnetic field response characteristic diagram at the time of writing in the MRAM.
FIG. 19 is a diagram illustrating a read operation principle of the MRAM.
[Explanation of symbols]
1 ... top coat layer, 2 ... memory layer, 3 ... tunnel barrier layer,
4 ... 1st magnetization fixed layer, 5 ... Antiferromagnetic coupling layer, 6 ... 2nd magnetization fixed layer,
7 ... Antiferromagnetic material layer, 8 ... Underlayer, 9 ... Support substrate,
10 ... Memory cell (TMR element), 11 ... Bit line,
12 ... word line for writing, 13 ... silicon substrate, 14 ... well region,
15 ... Gate insulating film, 16 ... Gate electrode, 17 ... Source region,
18 ... drain region,
19: Field effect transistor for reading (selection transistor),
20 ... source electrode, 21 ... sense line, 22 ... readout wiring,
23 ... Drain electrode, 26 ... Magnetization fixed layer,
30 ... MRAM element (embedded TMR element), 31 ... External lead, 32 ... Sealing material,
33, 34, 41 ... magnetic shield layer, 37 ... gauss meter,
38 ... Other elements (chips), 40 ... Die pads, 41 ... Bonding wires,
42, 47 ... solder bumps, 46 ... UFPL, 48 ... interlayer bumps,
49 ... Main board

Claims (12)

磁化方向が固定された磁化固定層と、磁化方向の変化が可能な磁性層とが積層されてなるメモリ素子からなる磁気ランダムアクセスメモリとして構成された磁気メモリ装置において、前記メモリ素子の複数個、又は前記メモリ素子と他の素子とが積層され、少なくとも前記メモリ素子の占有面積領域に、前記メモリ素子を磁気シールドするための磁気シールド層が設けられていることを特徴とする磁気メモリ装置。In a magnetic memory device configured as a magnetic random access memory including a memory element in which a magnetization fixed layer with a fixed magnetization direction and a magnetic layer capable of changing the magnetization direction are stacked, a plurality of the memory elements, Alternatively, a magnetic memory device, wherein the memory element and another element are stacked, and a magnetic shield layer for magnetically shielding the memory element is provided at least in an area occupied by the memory element. 磁化可能な磁性層を有するメモリ素子からなる磁気メモリ装置において、前記メモリ素子の複数個、又は前記メモリ素子と他の素子とが積層され、少なくとも前記メモリ素子の占有面積領域に、前記メモリ素子を磁気シールドするための磁気シールド層が設けられていることを特徴とする磁気メモリ装置。In a magnetic memory device including a memory element having a magnetizable magnetic layer, a plurality of the memory elements, or the memory elements and other elements are stacked, and the memory elements are arranged at least in an area occupied by the memory elements. A magnetic memory device comprising a magnetic shield layer for magnetic shielding. 磁化方向が固定された磁化固定層と、磁化方向の変化が可能な磁性層とが積層されてなるメモリ素子からなる磁気ランダムアクセスメモリとして構成された磁気メモリ装置において、前記メモリ素子を磁気シールドするための磁気シールド層が前記メモリ素子の表面側及び裏面側にそれぞれ設けられ、これらの磁気シールド層間の間隔が３．５ｍｍ以下であることを特徴とする磁気メモリ装置。In a magnetic memory device configured as a magnetic random access memory including a memory element in which a magnetization fixed layer having a fixed magnetization direction and a magnetic layer capable of changing the magnetization direction are stacked, the memory element is magnetically shielded. Magnetic shield layers are provided on the front side and the back side of the memory element, respectively, and the distance between these magnetic shield layers is 3.5 mm or less. 磁化可能な磁性層を有するメモリ素子からなる磁気メモリ装置において、前記メモリ素子を磁気シールドするための磁気シールド層が前記メモリ素子の表面側及び裏面側にそれぞれ設けられ、これらの磁気シールド層間の間隔が３．５ｍｍ以下であることを特徴とする磁気メモリ装置。In a magnetic memory device including a memory element having a magnetizable magnetic layer, a magnetic shield layer for magnetically shielding the memory element is provided on each of a front surface side and a back surface side of the memory element, and a space between these magnetic shield layers Is 3.5 mm or less, A magnetic memory device. 前記メモリ素子の複数個、又は前記メモリ素子と他の素子とが積層され、少なくとも前記メモリ素子の占有面積領域に、前記磁気シールド層が設けられている、請求項３又は４に記載した磁気メモリ装置。5. The magnetic memory according to claim 3, wherein a plurality of the memory elements, or the memory elements and other elements are stacked, and the magnetic shield layer is provided at least in an area occupied by the memory elements. apparatus. 一層の前記磁気シールド層においてその対向辺間の距離が１５ｍｍ以下である、請求項１〜５のいずれか１項に記載した磁気メモリ装置。The magnetic memory device according to claim 1, wherein a distance between opposite sides of the magnetic shield layer in one layer is 15 mm or less. 前記メモリ素子の複数個、又は前記メモリ素子と他の素子とが基体上に混載されている、請求項１〜５のいずれか１項に記載した磁気メモリ装置。The magnetic memory device according to claim 1, wherein a plurality of the memory elements, or the memory elements and other elements are mixedly mounted on a base. 前記磁気シールド層が、前記メモリ素子のパッケージの上部及び／又は下部、或いは／並びに、前記メモリ素子のパッケージ中において前記メモリ素子の上部及び／又は下部に配置されている、請求項１〜５のいずれか１項に記載した磁気メモリ装置。6. The magnetic shield layer according to claim 1, wherein the magnetic shield layer is disposed at an upper part and / or a lower part of the package of the memory element and / or an upper part and / or a lower part of the memory element in the package of the memory element. The magnetic memory device described in any one of the items. 前記磁気シールド層が、前記素子の積層構造中における中間層として設けられている、請求項１〜５のいずれか１項に記載した磁気メモリ装置。The magnetic memory device according to claim 1, wherein the magnetic shield layer is provided as an intermediate layer in the stacked structure of the elements. 前記磁気シールド層を形成する軟磁性材料が、Ｆｅ、Ｃｏ及びＮｉのうち少なくとも１種を含む高飽和磁化、高透磁率の軟磁性体からなる、請求項１〜５のいずれか１項に記載した磁気メモリ装置。The soft magnetic material forming the magnetic shield layer is made of a soft magnetic material having high saturation magnetization and high permeability including at least one of Fe, Co, and Ni. Magnetic memory device. 前記封止材中に軟磁性フィラーを含有している、請求項１〜５のいずれか１項に記載した磁気メモリ装置。The magnetic memory device according to claim 1, wherein a soft magnetic filler is contained in the sealing material. 前記磁化固定層と前記磁性層との間に絶縁体層又は導電体層が挟持され、前記メモリ素子の上面及び下面に設けられた配線にそれぞれ電流を流すことによって誘起される磁界で前記磁性層を所定方向に磁化して情報を書き込み、この書き込み情報を前記配線間でのトンネル磁気抵抗効果によって読み出すように構成された、請求項１又は３に記載した磁気メモリ装置。An insulator layer or a conductor layer is sandwiched between the magnetization pinned layer and the magnetic layer, and the magnetic layer is induced by a magnetic field induced by passing current through wirings provided on the upper surface and the lower surface of the memory element, respectively. 4. The magnetic memory device according to claim 1, wherein information is written by magnetizing the magnetic field in a predetermined direction, and the written information is read by a tunnel magnetoresistive effect between the wirings.
JP2002371691A 2002-12-24 2002-12-24 Magnetic memory device Abandoned JP2004207322A (en)

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WO2008105315A1 (en) * 2007-02-27 2008-09-04 Renesas Technology Corp. Method for manufacturing magnetic memory chip device
US7692956B2 (en) 2005-10-03 2010-04-06 Nec Corporation Magnetic random access memory
JPWO2011111789A1 (en) * 2010-03-10 2013-06-27 日本電気株式会社 Magnetic body device and manufacturing method thereof
JP2017188647A (en) * 2016-03-31 2017-10-12 Tdk株式会社 Electronic circuit package arranged by using composite magnetic sealing material
JP2017188646A (en) * 2016-03-31 2017-10-12 Tdk株式会社 Composite magnetic sealing material
JP2018514077A (en) * 2015-04-27 2018-05-31 東芝メモリ株式会社 Magnetic memory device
US10256194B2 (en) 2016-03-31 2019-04-09 Tdk Corporation Electronic circuit package using composite magnetic sealing material
US10269727B2 (en) 2016-03-31 2019-04-23 Tdk Corporation Composite magnetic sealing material and electronic circuit package using the same as mold material
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Publication number Priority date Publication date Assignee Title
US7692956B2 (en) 2005-10-03 2010-04-06 Nec Corporation Magnetic random access memory
US8124425B2 (en) 2007-02-27 2012-02-28 Renesas Electronics Corporation Method for manufacturing magnetic memory chip device
JP5062248B2 (en) * 2007-02-27 2012-10-31 ルネサスエレクトロニクス株式会社 Manufacturing method of magnetic memory chip device
US8524510B2 (en) 2007-02-27 2013-09-03 Renesas Electronics Corporation Method for manufacturing magnetic memory chip device
WO2008105315A1 (en) * 2007-02-27 2008-09-04 Renesas Technology Corp. Method for manufacturing magnetic memory chip device
JPWO2011111789A1 (en) * 2010-03-10 2013-06-27 日本電気株式会社 Magnetic body device and manufacturing method thereof
JP2018514077A (en) * 2015-04-27 2018-05-31 東芝メモリ株式会社 Magnetic memory device
US10644225B2 (en) 2015-04-27 2020-05-05 Toshiba Memory Corporation Magnetic memory device
JP2017188647A (en) * 2016-03-31 2017-10-12 Tdk株式会社 Electronic circuit package arranged by using composite magnetic sealing material
US10256194B2 (en) 2016-03-31 2019-04-09 Tdk Corporation Electronic circuit package using composite magnetic sealing material
US10269727B2 (en) 2016-03-31 2019-04-23 Tdk Corporation Composite magnetic sealing material and electronic circuit package using the same as mold material
US10615089B2 (en) 2016-03-31 2020-04-07 Tdk Corporation Composite magnetic sealing material
JP2017188646A (en) * 2016-03-31 2017-10-12 Tdk株式会社 Composite magnetic sealing material

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