CN117133338A

CN117133338A - Bit line voltage clamp read circuit for in-memory computing operation

Info

Publication number: CN117133338A
Application number: CN202310600267.3A
Authority: CN
Inventors: K·J·多里; H·拉瓦特; P·库玛; N·乔拉; M·阿尤蒂亚瓦斯
Original assignee: STMicroelectronics International NV Switzerland
Current assignee: STMicroelectronics International NV Switzerland
Priority date: 2022-05-25
Filing date: 2023-05-25
Publication date: 2023-11-28

Abstract

The present disclosure relates to a bit line voltage clamp read circuit for in-memory computing operations. An in-memory computing circuit includes a memory array having SRAM cells connected in rows by word lines and in columns by bit lines. The row controller circuit concurrently activates the word lines in parallel for in-memory computing operations. The column processing circuit includes a clamp circuit that clamps the voltage on the bit line to a level that exceeds the SRAM cell bit flip voltage during performance of the in-memory computing operation. The column processing circuitry may also include current mirror circuitry that mirrors the read current formed on each bit line in response to simultaneous actuation to generate a decision output for in-memory computing operations. The mirrored read current is integrated by an integrating capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

Description

Bit line voltage clamp read circuit for in-memory computing operation

Cross Reference to Related Applications

The present application claims priority from U.S. patent provisional application No.63/345,518, filed 5/25 at 2022, the disclosure of which is incorporated herein by reference.

Technical Field

Embodiments relate to an in-memory computing circuit utilizing a Static Random Access Memory (SRAM) array, and in particular to a read circuit that clamps bit line voltages for in-memory computing operations during simultaneous access of multiple rows of the SRAM array.

Background

Referring to fig. 1, fig. 1 shows a schematic diagram of an in-memory computing circuit 10. The circuit 10 utilizes a Static Random Access Memory (SRAM) array 12, which SRAM array 12 is formed from standard 6T SRAM memory cells 14 arranged in a matrix format having N rows and M columns. Alternatively, standard 8T memory cells or SRAMs with similar functionality and topology may be used. Each memory cell 14 is programmed to store bits of kernel data (kernel data) or computation weights for in-memory computing operations. In this context, in-memory computing operations are understood to be a form of high-dimensional Matrix Vector Multiplication (MVM) that supports multi-bit weights stored in multi-bit cells of a memory. The set of bitcells (in the case of multi-bit weights) may be considered virtual synaptic elements (virtual synaptic element). Each bit of the computation weight has a logical "1" or logical "0" value.

Each SRAM cell 14 includes a word line WL and a pair of complementary bit lines BLT and BLC. The 8T-type SRAM cell will additionally include a read word line RWL and a read bit line BLR. The cells 14 in a common row of the matrix are connected to each other by a common word line WL (and in an 8T-type implementation by a common read word line RWL). The cells 14 in a common column of the matrix are connected to each other by a common pair of complementary bit lines BLT and BLC (and by a common read bit line BLR in an 8T-type implementation). Each word line WL, RWL is driven by a word line driver circuit 16, which word line driver circuit 16 may be implemented as a CMOS driver circuit (e.g., a pair of series-connected p-channel and n-channel MOSFET transistors forming a logic inverter circuit). The word line signals applied to the word lines and driven by the word line driver circuit 16 are generated from the characteristic data input to the in-memory computing circuit 10, and are controlled by the row controller circuit 18. Column processing circuitry 20 senses analog current signals on respective pairs of complementary bit lines BLT and BLC (and/or read bit line BLR) of the M columns and generates decision outputs for in-memory computation operations from these analog current signals. Column processing circuitry 20 may be implemented to support processing in which analog current signals on columns are first processed individually and then the multiple column outputs are recombined.

Although not explicitly shown in fig. 1, it is to be understood that the circuit 10 also includes conventional row decoding, column decoding, and read-write circuitry known to those skilled in the art for use in connection with writing bits of computational weights to the SRAM cells 14 of the memory array 12 and reading bits of computational weights from the SRAM cells 14 of the memory array 12.

Referring now to fig. 2, each memory cell 14 includes two cross-coupled CMOS inverters 22 and 24, each comprising a pair of p-channel and n-channel MOSFET transistors connected in series. The inputs and outputs of inverters 22 and 24 are coupled to form a latch circuit having a true data storage node QT and a complementary data storage node QC that stores the complementary logic states of the stored data bits. The cell 14 also includes two pass gate transistors 26 and 28, the gate terminals of the transistors 26 and 28 being driven by a word line WL. The source-drain path of transistor 26 is connected between true data storage node QT and a node associated with true bit line BLT. The source-drain path of transistor 28 is connected between the complementary data storage node QC and the node associated with the complementary bit line BLC. The source terminals of p-channel transistors 30 and 32 in each inverter 22 and 24 are coupled to receive a high supply voltage (e.g., vdd) at a high supply node, while the source terminals of n-channel transistors 34 and 36 in each inverter 22 and 24 are coupled to receive a low supply voltage (e.g., ground (Gnd) reference) at a low supply node. Although fig. 2 is specific to the use of 6T cells, those skilled in the art recognize that an 8T cell is similarly configured and will also include a signal path coupled to one of the storage nodes and include a pass (gate) transistor coupled to the read bit line BLR and driven by a signal gate on the read word line RWL. The word line driver circuit 16 is also typically coupled to receive a high supply voltage (Vdd) at a high supply node and to reference a low supply voltage (Gnd) at a low supply node.

The row controller circuit 18 performs the following functions: selecting which of the word lines WL <0> through WL < N-1> are to be simultaneously accessed (or activated) in parallel during an in-memory computing operation, and controlling application of a pulsed signal to the word lines according to characteristic data for the in-memory computing operation. Fig. 1 shows, by way of example only, that all N word lines are simultaneously actuated with pulsed word line signals, it being understood that in-memory computing operations may instead utilize simultaneous actuation of fewer than all rows of the SRAM array. The analog signal on a given pair of complementary bit lines BLT and BLC (or on the read bit line RBL in an 8T implementation) is a function of the logic state of the bits of the computational weight stored in the memory cells 14 of the corresponding column and the width(s) of the pulsed word line signal applied to those memory cells 14.

The implementation shown in fig. 1 illustrates an example of a Pulse Width Modulated (PWM) form of an applied word line signal for in-memory computing operations. The use of PWM or periodic pulse modulation (PTM) on the applied word line signal is a common technique for in-memory computing operations based on the linearity of vectors for multiply-accumulate (MAC) operations. The pulsed word line signal format may be further developed into coded bursts to manage the block sparsity (blcok sparsity) of the feature data of in-memory computing operations. It is thus recognized that when multiple word lines are driven simultaneously, any one set of encoding schemes for the applied word line signals may be used. Furthermore, in a simpler implementation, it should be appreciated that all word line signals applied in a simultaneous actuation may instead have the same pulse width.

FIG. 3 is a timing diagram showing the simultaneous application of example pulse width modulated word line signals to rows of memory cells 14 in an SRAM array 12 in a given in-memory computing operation, and the response of cell read currents (I) due to the pulse width(s) of those word line signals and the logic states of the bits of the computation weights stored in the memory cells 14 _R ) Voltages Va, T and Va, C formed over time on the corresponding complementary bit lines BLT and BLC, respectively. The representation of the voltage Va level shown is only one example. After the completion of the computation cycle of the in-memory computation operation, the voltage Va level returns to the bit line precharge Vdd level. It will be noted that there is a risk that the voltage on at least one of the bit lines BLT and BLC may drop from the Vdd voltage to a level below the write margin (margin) where an undesired data flip occurs with respect to the data bit value stored in one of the memory cells 14 of the column. For example, a logic "1" state stored in a column of cells 14 may be flipped to a logic "0" state. This data inversion introduces data errors into the computational weights stored in the memory cells, thereby compromising the accuracy of subsequent in-memory computational operations.

The undesired data flip that occurs due to excessive bit line voltage drop is primarily the result of concurrent access to the word lines in matrix vector multiplication mode during in-memory computing operations. This problem is different from the normal data flip of SRAM bit cells due to Static-Noise-Margin (SNM) issues that occur in serial bit cell accesses when the bit lines approach the level of the supply voltage Vdd. During serial access, normal data flip is caused by ground bounce of the data storage node QT or QC.

A known solution to the problem of serial bit cell access SNM failures is to reduce the word line voltage by a small amount, and this is typically achieved through the use of a shorting and bleeding path for the word line driver. However, parallel access to multiple word lines during in-memory computing operations requires aggressive WL reduction/modulation (RWLM) techniques. Furthermore, a known solution to the above problem is to apply a fixed word line voltage reduction (e.g., apply a voltage V equal to Vdd/2) across all integrated circuit process corners (process corner) _WLUD ) To ensure (secure) the worst integrated circuit process corner. However, such word line under-drive (WLUD) solutions have the known disadvantage of cell read current (I _R ) This may have a negative impact on computational performance with a corresponding decrease. Furthermore, the use of a fixed word line under-drive voltage increases the variability of read current across the array, resulting in a loss of accuracy in the in-memory computing operation.

Another solution is to use a dedicated bit cell circuit design for each memory cell 14 that is less likely to suffer from unwanted data flipping during simultaneous (parallel) access of multiple rows for in-memory computing operations. One problem with this solution is the increase in the occupied circuit area of such a bit cell circuit. For some in-memory computing circuit applications, it is preferable to retain the advantages provided by using standard 6T SRAM cells (FIG. 2) or 8T SRAM cells or topologically similar bit cells in array 12.

Disclosure of Invention

In one embodiment, an in-memory computing circuit includes: a memory array comprising a plurality of Static Random Access Memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row comprising a word line connected to the SRAM cells of the row and each column comprising a first bit line connected to the SRAM cells of the column; a word line driver circuit for each row having an output connected to drive a word line of the row; a row controller circuit configured to actuate a plurality of word lines simultaneously for in-memory computing operations by applying pulses to the word lines through the word line driver circuit; and column processing circuitry including first read circuitry coupled to each first bit line.

Each first reading circuit includes: a first differential amplifier having a first input coupled to the first bit line, a second input configured to receive a reference voltage (wherein the reference voltage is at a level greater than a bit flip voltage of the SRAM cell during simultaneous actuation of the plurality of word lines for in-memory computing operations), and an output; a first MOS transistor having a drain coupled to the first bit line to receive the first read current and a gate coupled to the output of the first differential amplifier; a second MOS transistor having a gate coupled to the output of the first differential amplifier and a drain configured to output a first mirrored read current; and a first integrating capacitor configured to integrate the first mirrored read current to generate a first output voltage.

The first differential amplifier and the first MOS transistor are used to clamp the voltage on the first bit line to the reference voltage.

In one embodiment, an in-memory computing circuit includes: a memory array comprising a plurality of Static Random Access Memory (SRAM) cells arranged in a matrix having a plurality of rows and first and second columns, each row comprising a word line connected to the SRAM cells of the row, and each of the first and second columns comprising a first bit line connected to the SRAM cells of the column; a word line driver circuit for each row having an output connected to drive a word line of the row; a row controller circuit configured to actuate a plurality of word lines simultaneously for in-memory computing operations by applying pulses to the word lines through the word line driver circuit; a column processing circuit.

The column processing circuit includes: a first reading circuit and a second reading circuit. The first reading circuit includes: a first voltage clamp circuit configured to clamp a voltage on a first bit line of a first column to a reference voltage during simultaneous actuation of a plurality of word lines for an in-memory computing operation; and a first current mirror circuit (current mirroring circuit) connected to the first voltage clamp circuit and coupled to the first bit line of the first column, the first current mirror circuit having a first current mirror ratio and configured to mirror a first read current on the first bit line of the first column to generate a first mirrored read current. The second reading circuit includes: a second voltage clamp circuit configured to clamp a voltage on a first bit line of a second column to a reference voltage during simultaneous actuation of the plurality of word lines for an in-memory computing operation; and a second current mirror circuit connected to the second voltage clamp circuit and coupled to the first bit line of the second column, the second current mirror circuit having a second current mirror ratio and configured to mirror a second read current on the first bit line of the second column to generate a second mirrored read current. The first integrating capacitor is configured to integrate a sum of the first and second mirrored read currents to generate a first output voltage.

During simultaneous actuation of multiple word lines for in-memory computing operations, the reference voltage is at a level greater than the bit flip voltage of the SRAM cell.

In one embodiment, an in-memory computing circuit includes: a memory array comprising a plurality of 6T Static Random Access Memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row comprising a word line connected to the SRAM cells of the row and each column comprising a first bit line connected to the 6T SRAM cells of the column; a word line driver circuit for each row having an output connected to drive a word line of the row; a row controller circuit configured to actuate a plurality of word lines simultaneously for in-memory computing operations by applying pulses to the word lines through the word line driver circuit; a column processing circuit.

The column processing circuit includes first read circuits coupled to each first bit line, wherein each first read circuit includes: a first differential amplifier having a first input coupled to the first bit line, a second input configured to receive a reference voltage, and an output; and a first feedback resistor coupled between a first input and an output of the first differential amplifier, wherein the output is configured to generate a first output voltage in accordance with the reference voltage and a first read current on the first bit line. The first differential amplifier is for clamping a voltage on the first bit line to the reference voltage, wherein the reference voltage is at a level greater than a bit flip voltage of the SRAM cell during simultaneous actuation of the plurality of word lines for in-memory computing operations.

Drawings

For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings in which:

FIG. 1 is a schematic diagram of an in-memory computing circuit;

FIG. 2 is a circuit diagram of a standard 6T Static Random Access Memory (SRAM) cell of a memory array using the in-memory computing circuit shown in FIG. 1;

FIG. 3 is a timing diagram illustrating an in-memory computing operation;

FIGS. 4A and 4B are circuit diagrams of a bit line read circuit;

FIG. 5 is a circuit diagram of a differential signaling (signaling) implementation of a bit line read circuit;

FIG. 6 is a circuit diagram of a single-ended signaling implementation of a bit line read circuit;

FIGS. 7A and 7B are circuit diagrams of an implementation of a bit line read circuit supporting multi-bit weight data;

FIG. 8 is a circuit diagram of a differential signaling implementation of a bit line read circuit supporting multi-bit weight data;

FIG. 9 is a circuit diagram of a single-ended signaling implementation of a bit line read circuit supporting multi-bit weight data;

FIG. 10 is a circuit diagram of a bit line read circuit;

FIG. 11 is a circuit diagram of a differential signaling implementation of a bit line read circuit;

FIGS. 12-13 are circuit diagrams of bias voltage generators;

FIG. 14 is a flow chart illustrating the operation of the circuit shown in FIG. 13; and

Fig. 15 is a block diagram of an analog-to-digital converter circuit.

Detailed Description

Referring now to fig. 4A, fig. 4A shows a circuit diagram of a bit line read circuit 100 for use within column processing circuit 20. The bit line BL of a given column of memory cells 14 in array 12 is coupled, preferably directly connected to the non-inverting input of differential amplifier 109, and coupled, preferably directly connected to the drain terminal of p-channel MOS transistor M1. The bit line BL may, for example, comprise any one of a complementary bit line BLT, BLC or a read bit line BLR for a column of memory. The inverting input of differential amplifier 109 is coupled to receive a reference voltage Vwm having a voltage level set to be greater than the write margin voltage of memory cell 14. The write margin voltage is the bit line voltage (e.g., vwm is equal to at or about Vdd/2) in the event that the risk of an unexpected bit flip in the 6T SRAM cell during a simultaneous word line access for in-memory computing operations occurs. The output of differential amplifier 109 is coupled, preferably directly connected, to the gate terminal of p-channel MOS transistor M1 and coupled, preferably directly connected, to the gate terminal of p-channel MOSFET transistor M2. The source terminal of transistor M2 is coupled to the supply voltage Vdd node through switch S1. The open/close state of the switch S1 is controlled by the logic state of the integration signal INT. The drain terminal of transistor M2 is coupled, preferably directly connected, to intermediate node 102. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102 and the second terminal is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. Intermediate node 102 is further coupled to a reference voltage node through switch S2. The open/close state of the switch S2 is controlled by the logic state of the reset signal RST.

The switches S1, S2 may each be implemented, for example, using MOS transistors controlled by an appropriate one of the control signals RST and INT.

In an alternative embodiment, switch S1 may be positioned between the drain of transistor M2 and intermediate node 102, as shown in FIG. 4B. In either case, transistors M1 and M2 together with switch S1 form a selectively actuatable (in response to control signal INT) current mirror circuit configured to read current I from bit line BL during an in-memory computing operation when a plurality of word lines in word line WL are simultaneously actuated with word line signal pulses in accordance with the received characteristic data _R Generating mirrored read current I _Rm The bitLine BL read current I _R Is the cell current I through the memory cells 14 in the column _CELL Formed by the sum of (a) and (b). Mirror read current I _Rm And then applied to charge the integrating capacitor Cint and generate the output voltage Vout.

It will be appreciated that for each column of memory, one bit line read circuit 100 is provided in the column processing circuit 20.

The intermediate node 102 is further coupled to an input of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the analog voltage Vout across the integrating capacitor Cint into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each column. Alternatively, one ADC circuit 104 may be shared by multiple columns through a time division multiplexing operation. The digital signals MACout from each column may be output from the column processing circuit 20 as decisions (decisions), or combined with each other to generate decisions.

The operation of the bit line read circuit 100 is as follows: at the beginning of a calculation cycle of the in-memory calculation operation, the reset signal RST is asserted to close switch S2 and discharge the integrating capacitor Cint. Word line signals are then simultaneously applied to rows of memory cells 14 in the SRAM array 12 for in-memory computing operations in accordance with the received characteristic data, and a read current I _R Formed on the bit line BL. Read current I _R The magnitude of (2) depends on the current I sunk to ground by the memory cells 14 of the column involved in the in-memory computation operation _CELL Is a sum of (a) and (b). The integration signal INT is asserted to close switch S1 and begin the integration period (integration time period). The amplifier 109 and transistor M1 function as a voltage clamp circuit configured to prevent the voltage on the bit line BL from falling below a reference voltage Vwm (which is greater than the write margin voltage in the event of a risk of an unexpected bit flip). In other words, the circuitry is used to inhibit the voltage on the bit line from falling below the bit flip voltage during an in-memory computing operation when multiple word lines are simultaneously activated. Transistors M1 and M2 function as a current mirror circuit and mirror the read current I _Rm Is applied to charge the integrating capacitor Cint to generate a voltage vout=i _Rm *t/CWhere t is the duration of the integration period (when switch S1 is closed) and C is the capacitance of the integration capacitor Cint. When the integration period expires, the integration signal INT is de-asserted to open switch S1. The voltage Vout across the integrating capacitor Cint is then converted into a digital signal MACout by the ADC circuit 104.

Referring now to fig. 5, fig. 5 shows a circuit diagram of a differential signal implementation of the bit line read circuit 100. Like reference numerals refer to the same or similar components. In this implementation, the currents on the true bit line BLT and the complementary bit line BLC are handled by the bit line read circuit 100. The use of the suffix "_t" designates the component associated with the processing of the read current on the true bit line BLT, and the use of the suffix "_c" designates the component associated with the processing of the read voltage on the complementary bit line BLC. Thus, the bit line read circuit 100 includes a circuit for handling the read current I on the true bit line BLT _{R_T} True read circuit 100_t for processing read current I on complementary bit line BLC _{R_C} Is provided for the complementary read circuit 100_c. The circuit configuration of each of the read circuits 100_t, 100_c is the same as that shown in fig. 4A, and each circuit operates in the above-described manner. The differential signaling implementation in fig. 5 differs from the implementations of fig. 4A-4B in that the differential integrated voltage vout_ T, vout _c is generated by the bit line read circuits 100_t, 100_c and the ADC circuit 104 operates to convert the difference between the voltages vout_ T, vout _c to obtain the digital signal MACout.

Referring now to true read circuit 100_t, the true bit line BLT of a given column of memory cells 14 in array 12 is coupled, preferably directly connected, to the non-inverting input of differential amplifier 109_t and to the drain terminal of p-channel MOS transistor m1_t. The source terminal of transistor m1_t is coupled, preferably directly connected, to the supply voltage Vdd node. The inverting input of differential amplifier 109 is coupled to receive a reference voltage Vwm having a voltage level set to be greater than the write margin voltage of memory cell 14. The write margin voltage is the bit line voltage (e.g., vwm is equal to at or about Vdd/2) in the event that the risk of an unexpected bit flip in the 6T SRAM cell during a word line access occurs while there is an in-memory computation operation. The output of the differential amplifier 109_t is coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor m1_t and coupled, preferably directly connected, to the gate terminal of the p-channel MOSFET transistor m2_t. The source terminal of transistor m2_t is coupled to the supply voltage Vdd node through switch s1_t. The open/close state of the switch s1_t is controlled by the logic state of the integration signal INT. The drain terminal of transistor m2_t is coupled, preferably directly connected, to intermediate node 102_t. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102_t, and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. The intermediate node 102_t is further coupled to a reference voltage node through a switch s2_t. The open/close state of the switch s2_t is controlled by the logic state of the reset signal RST.

For the complementary read circuit 100_C, the complementary bit line BLC of a given column of memory cells 14 in the array 12 is coupled, preferably directly connected, to the non-inverting input of the differential amplifier 109_C and to the drain terminal of the p-channel MOS transistor M1_C. The source terminal of transistor m1_c is coupled, preferably directly connected, to the supply voltage Vdd node. The inverting input of the differential amplifier 109_c is coupled to receive the reference voltage Vwm. The output of the differential amplifier 109_c is coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor m1_c and coupled, preferably directly connected, to the gate terminal of the p-channel transistor m2_c. The source terminal of transistor m2_c is coupled to the supply voltage Vdd node through switch s1_c. The open/close state of the switch s1_c is controlled by the logic state of the integration signal INT. The drain terminal of transistor m2_c is coupled, preferably directly connected, to intermediate node 102_c. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102_c, and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. The intermediate node 102_c is further coupled to a reference voltage node through a switch s2_c. The open/close state of the switch s2_c is controlled by the logic state of the reset signal RST.

The switches s1_ T, S1_ C, S2 _2_ T, S2_c may each be implemented, for example, using a MOS transistor that is gate-controlled by an appropriate one of the control signals RST and INT.

It will be appreciated that each of the read circuits 100_t, 100_c in fig. 5 may alternatively be implemented in the manner shown in fig. 4B, and that in this configuration the switch s1_ T, S1_c would instead be located between the drain of transistor m2_ T, M2 _2_c and the intermediate nodes 102_t, 102_c, respectively. In either case, transistors M1_T and M2_T and switch S1_T, transistors M1_C and M2_C and switch S1_C form a selectively actuatable (in response to control signal INT) current mirror circuit, respectively, configured to read current I from bit line BL _R Generating mirrored read current I _Rm The bit line BL reads the current I _R Is the cell current I through the memory cells 14 in the column _CELL Formed by the method. Mirror read current I _Rm And then applied to charge the integrating capacitor Cint and generate the output voltage Vout.

It should be understood that for each column of the memory, a pair of bit line read circuits 100_t, 100_c are provided in the column processing circuit 20.

The intermediate nodes 102_t, 102_c are further coupled to differential inputs of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the difference between the analog voltages vout_ T, vout _c into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each column. Alternatively, one ADC circuit 104 may be shared by multiple columns through a time division multiplexing operation. The digital signals MACout from each column may be output from the column processing circuit 20 as a precision, or combined with each other to generate a precision.

The operation of the bit line read circuit 100 is as follows: at the beginning of a calculation cycle of the in-memory calculation operation, the reset signal RST is asserted to close the switch s2_ T, S2_c and discharge the integrating capacitor Cint. Word line signals are then simultaneously applied to rows of memory cells 14 in the SRAM array 12 for in-memory computing operations in accordance with the received characteristic data, and the current I is actually read _{R_T} Complementary read current I _{R_C} Formed on complementary bit lines BLT, BLC. Read current I _{R_T} 、I _{R_C} The magnitude of (2) depends on the current I sunk to ground by the memory cells 14 of the column involved in the in-memory computation operation _CELL Is a sum of (a) and (b). The integration signal INT is asserted to close the switch s1_ T, S1_c and begin the integration period. The amplifiers 109_t, 109_c and the transistor m1_ T, M1_c function as a voltage clamp configured to prevent the voltage on each of the complementary bit lines BLT, BLC from falling below a reference voltage Vwm (which is greater than the write margin voltage in the presence of a risk of an unexpected bit flip). In other words, the circuitry is used to inhibit the voltage on the bit line from falling below the bit flip voltage during an in-memory computing operation when multiple word lines are simultaneously activated. Transistors m1_t and m2_ T, M1_c and m2_c are used as current mirror circuits and correspond to mirror read current I _{Rm_T} 、I _{Rm_C} Is applied to charge an integrating capacitor Cint to generate a voltage dependent on I _{Rm_T} *t/C、I _{Rm_C} * Voltage vout_ T, vout _c of T/C, where T is the duration of the integration period (when switches s1_t and s1_c are closed), and C is the capacitance of the integration capacitor Cint. When the integration period expires, the integration signal INT is de-asserted to open the switch s1_ T, S1_c. The difference between the voltages vout_ T, vout _c across the integrating capacitor Cint is then converted to a digital signal MACout by the ADC circuit 104.

Referring now to fig. 6, fig. 6 shows a circuit diagram of a single-ended signaling implementation of the bit line read circuit 100. Like reference numerals refer to the same or similar components. In this implementation, the currents on the true bit line BLT and the complementary bit line BLC are handled by the bit line read circuit 100. The use of the suffix "_t" designates the component associated with the processing of the read current on the true bit line BLT, and the use of the suffix "_c" designates the component associated with the processing of the read voltage on the complementary bit line BLC. Thus, the bit line read circuit 100 includes a circuit for handling the read current I on the true bit line BLT _{R_T} True read circuit 100_t for processing read current I on complementary bit line BLC _{R_C} Is provided for the complementary read circuit 100_c. The configuration of the read circuits 100_t, 100_c is similar to the implementation shown in fig. 4B, and each operates in the manner described above. Single port signaling in fig. 6 The main difference between the implementation and the differential signaling implementation in fig. 5 is that the single output voltage Vout is read by a mirrored read current I _{Rm_T} 、I _{Rm_C} The integration of the difference between the two results in the output voltage Vout being subsequently converted by the ADC circuit 104 to generate a digital signal MACout.

Referring now to true read circuit 100_t, the true bit line BLT of a given column of memory cells 14 in array 12 is coupled, preferably directly connected, to the non-inverting input of differential amplifier 109_t and to the drain terminal of p-channel MOS transistor m1_t. The source terminal of transistor m1_t is coupled, preferably directly connected, to the supply voltage Vdd node. The inverting input of differential amplifier 109 is coupled to receive a reference voltage Vwm having a voltage level set to be greater than the write margin voltage of memory cell 14. The write margin voltage is the bit line voltage (e.g., vwm is equal to at or about Vdd/2) in the event that the risk of an unexpected bit flip in the 6T SRAM cell during a word line access occurs while there is an in-memory computation operation. The output of the differential amplifier 109_t is coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor m1_t and coupled, preferably directly connected, to the gate terminal of the p-channel MOSFET transistor m2_t. The source terminal of transistor m2_t is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor m2_t is coupled, preferably directly connected, to current summing node 103.

For the complementary read circuit 100_C, the complementary bit line BLC of a given column of memory cells 14 in the array 12 is coupled, preferably directly connected, to the non-inverting input of the differential amplifier 109_C and to the drain terminal of the p-channel MOS transistor M1_C. The source terminal of transistor m1_c is coupled, preferably directly connected, to the supply voltage Vdd node. The inverting input of the differential amplifier 109_c is coupled to receive the reference voltage Vwm. The output of the differential amplifier 109_c is coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor m1_c and the gate terminal of the p-channel transistor m2_c. The source terminal of transistor m2_c is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor m2_c is coupled, preferably directly connected, to the current input node 105 of the n-channel current mirror circuit 107 formed by the input transistor Ma and the output transistor Mb sharing a common gate terminal and a common source terminal, wherein the drain and gate of the input transistor Ma are directly connected at the input node 105. The output of the current mirror circuit 107 at the drain of transistor Mb is coupled, preferably directly, to the current summing node 103.

At the current summing node 103, the current I is read from the mirror image of the true read circuit 100_T _{Rm_T} The mirrored read current I from the complementary read circuit 100_C is subtracted _{Rm_C} To generate the resulting output read current I _Rout 。

Output read current I from current summing node 103 _Rout Coupled to the intermediate node 102 via a switch S1. The open/close state of the switch S1 is controlled by the logic state of the integration signal INT. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102 and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. Intermediate node 102 is further coupled to a reference voltage node through switch S2. The open/close state of the switch S2 is controlled by the logic state of the reset signal RST.

The switches S1, S2 may each be implemented, for example, using MOS transistors that are gate controlled by an appropriate one of the control signals RST and INT.

It will be appreciated that each of the read circuits 100_t, 100_c in fig. 6 may alternatively be implemented in the manner shown in fig. 4A, and that in this configuration the switch S1 would instead be implemented by a switch s1_ T, S1_c located between the source of the transistor m2_ T, M2_c and the supply voltage node, respectively.

The intermediate node 102 is further coupled to an input of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the analog voltage Vout across the integrating capacitor Cint into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each column. Alternatively, one ADC circuit 104 may be shared by multiple columns through a time division multiplexing operation. The digital signals MACout from each column may be output from the column processing circuit 20 as a precision, or combined with each other to generate a precision.

The operation of the bit line read circuit 100 is as follows: at the beginning of a calculation cycle of the in-memory calculation operation, the reset signal RST is asserted to close switch S2 and discharge the integrating capacitor Cint. Applying word line signals to multiple rows of memory cells 14 in the SRAM array 12 simultaneously for in-memory computing operations in accordance with the received characteristic data, and true read current I _{R_T} And complementary read current I _{R_C} Formed on complementary bit lines BLT, BLC. Read current I _{R_T} 、I _{R_C} The magnitude of (2) depends on the current I sunk to ground by the memory cells 14 of the column involved in the in-memory computation operation _CELL Is a sum of (a) and (b). The integration signal INT is asserted to close switch S1 and begin the integration period. The amplifiers 109_t, 109_c and the transistor m1_ T, M1_c function as a voltage clamp configured to prevent the voltage on each of the complementary bit lines BLT, BLC from falling below a reference voltage Vwm (which is greater than the write margin voltage in the presence of a risk of an unexpected bit flip). In other words, the circuitry is used to inhibit the voltage on the bit line from falling below the bit flip voltage during an in-memory computing operation when multiple word lines are simultaneously activated. Transistors m1_t and m2_ T, M1_c and m2_c are used as current mirror circuits and correspond to mirror read current I _{Rm_T} 、I _{Rm_C} Is applied to the current summing node 103. Reading current I from mirror image _{Rm_T} Subtracting the mirrored read current I _{Rm_C} And applying the resulting output read current I _Rout To charge the integrating capacitor Cint and generate a dependent I _Rout * the output voltage Vout of t/C, where t is the duration of the integration period (when switch S1 is closed), and C is the capacitance of the integration capacitor Cint. When the integration period expires, the integration signal INT is de-asserted to open switch S1. The voltage Vout across the integrating capacitor Cint is then converted into a digital signal MACout by the ADC circuit 104.

The foregoing implementation illustrates the operation of in-memory calculations that are processing unit weight data. However, it should be appreciated that the foregoing implementations of the read circuit 100 are equally applicable when processing multi-bit weight data. Referring to FIG. 7A (which generally corresponds to the implementation of FIG. 4B), an implementation is shown in which the weight data includes two bits stored in two columns of memory cells 14a and 14B in the array associated with bit lines BL <0> and BL <1 >. In this example, the less significant bits (lsb) of the weight data are stored in the memory unit 14a, while the more significant bits (msb) of the weight data are stored in the memory unit 14 b.

The bit line BL <0> of the lower significant bit column of memory cells 14 in array 12 is coupled, preferably directly connected to the non-inverting input of differential amplifier 109lsb, and coupled, preferably directly connected to the drain terminal of p-channel MOS transistor M1. For example, the bit line BL may include any one of the complementary bit lines BLT, BLC or read bit line BLR for a column of memory (in the case of an 8T bit cell). The inverting input of differential amplifier 109lsb is coupled to receive a reference voltage Vwm having a voltage level set to be greater than the write margin voltage of memory cell 14. The write margin voltage is the bit line voltage (e.g., vwm is equal to at or about Vdd/2) in the event that the risk of an unexpected bit flip in the 6T SRAM cell during a word line access occurs while there is an in-memory computation operation. The output of differential amplifier 109lsb is coupled, preferably directly connected, to the gate terminal of p-channel MOS transistor M1 and to the gate terminal of p-channel transistor M2. The source terminal of transistor M2 is coupled, preferably directly connected, to current summing node 103.

Transistors M1 and M2 and differential amplifier 109lsb form a 1:1 mirror ratio current mirror circuit configured to depend on the cell current I from memory cells 14 in the column _CELL The bit line BL formed reads current I _Rlsb Generating mirrored read current I _Rmlsb (wherein I _Rmlsb ＝I _Rlsb )。

The bit line BL <1> of the more significant bit column of memory cells 14 in array 12 is coupled, preferably directly connected to the non-inverting input of differential amplifier 109msb, and coupled, preferably directly connected to the drain terminal of p-channel MOS transistor M3. For example, the bit line BL may include any one of the complementary bit lines BLT, BLC or read bit line BLR for a column of memory (in the case of an 8T bit cell). The inverting input of differential amplifier 109msb is coupled to receive a reference voltage Vwm having a voltage level set to be greater than the write margin voltage of memory cell 14. The write margin voltage is the bit line voltage (e.g., vwm is equal to or about Vdd/2) in the event that the risk of an unexpected bit flip in the 6T SRAM cell during a word line access occurs while there is an in-memory computation operation. The output of differential amplifier 109msb is coupled, preferably directly connected, to the gate terminal of p-channel MOS transistor M3 and coupled, preferably directly connected, to the gate terminal of p-channel transistor M4. The source terminal of transistor M4 is coupled, preferably directly connected, to current summing node 103.

Transistors M3 and M4 and differential amplifier 109msb form a 2:1 mirror ratio current mirror circuit configured to depend on the cell current I from memory cells 14 in the column _CELL The bit line BL formed reads current I _Rmsb Generating mirrored read current I _Rmmsb (wherein I _Rmmsb ＝2*I _Rmsb )。

More generally, there is a weighted relationship between the current mirror ratios of the current mirror connected transistors on multiple columns of memory cells storing multi-bit weight data. Thus, if additional bit lines BLT <2> are involved, the current mirror connection transistors of the column may have a current mirror ratio of 1:4, according to a weighted relationship.

At the current summing node 103, the read current I is mirrored _Rmlsb And I _Rmmsb Are added together to generate the resulting output read current I _Rout . It will be noted that the current summation is implemented with binary weights (binary weights) due to the corresponding current mirror ratios of the current mirror circuits.

Output from current summing node 103Read current I _Rout Coupled to the intermediate node 102 via a switch S1. The open/close state of the switch S1 is controlled by the logic state of the integration signal INT. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102 and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. Intermediate node 102 is further coupled to a reference voltage node through switch S2. The open/close state of the switch S2 is controlled by the logic state of the reset signal RST.

The intermediate node 102 is further coupled to an input of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the analog voltage Vout across the integrating capacitor Cint into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each set of columns storing multi-bit weight data. Alternatively, one ADC circuit 104 may be shared by multiple sets of columns through a time division multiplexing operation. The digital signals MACout from each column may be output from the column processing circuit 20 as precision, or combined with each other to generate precision.

In an alternative implementation, the drain of transistor M2 may be coupled to summing node 103 through switch S3. The open/close state of switch S3 is controlled by the logic state of the multi-bit control signal MB. When the multi-bit control signal MB is in a first logic state corresponding to an operation when processing multi-bit weight data, the switch S3 is closed. In contrast, if the in-memory computation processing the unit weight data is operated, the multi-bit control signal MB is in a second logic state and switch S3 is open. In this mode the mirrored current output from transistor M2 will instead be coupled to be integrated by a different integrating capacitor and the resulting voltage converted by a different ADC circuit or by the shown ADC circuit at a different time in a time division multiplexed operation.

The switches S1, S2, S3 may each be implemented, for example, using MOS transistors that are gate-controlled by an appropriate one of the control signals RST, INT, and MB.

Referring to fig. 7B, it should be appreciated that each of the read circuits 100 may alternatively be implemented in the manner shown in fig. 4A. In this configuration, switches S1lsb, S1msb are positioned between the source of each transistor M2, M4 and the supply voltage node, respectively. Here, the summing node 103 is coupled, preferably directly connected, to the intermediate node 102.

The operation of the bit line read circuit 100 is as follows: at the beginning of a calculation cycle of the in-memory calculation operation, the reset signal RST is asserted to close switch S2 and discharge the integrating capacitor Cint. Word line signals are then simultaneously applied to rows of memory cells 14 in the SRAM array 12 for in-memory computing operations in accordance with the received characteristic data, and a lower significant bit read current I _Rlsb And a higher significant bit read current I _Rmsb Respectively bit lines BL<0>And BL (BL)<1>And is formed thereon. Read current I _Rlsb 、I _Rmsb The magnitude of (2) depends on the current I sunk to ground by the memory cells 14 of each column involved in the in-memory computing operation _CELL Is a sum of (a) and (b). The amplifier 109lsb and transistor M1, and the amplifier 109msb and transistor M3, respectively, function as a voltage clamp circuit configured to prevent the voltage on the bit line BL from falling below a reference voltage Vwm (which is greater than the write margin voltage in the presence of a risk of an unexpected bit flip). In other words, the circuitry is used to inhibit the voltage on the bit line from falling below the bit flip voltage during an in-memory computing operation when multiple word lines are simultaneously activated. The integration signal INT is asserted to close switch S1 and begin the integration period. Transistors M1 and M2, M3 and M4 serve as current mirror circuits and correspond to mirror read current I _Rmlsb 、I _Rmmsb Is applied to the current summing node 103 (via closed switch S3). Mirror read current I _Rmlsb 、I _Rmmsb Is added together and the resulting output read current I _Rout Is applied to charge an integrating capacitor Cint and generates a voltage dependent on I _Rout * the output voltage Vout of t/C, where t is the duration of the integration period (when switch S1 is closed), and C is the capacitance of the integration capacitor Cint. When the integration period expires, the integration signal INT is de-asserted to open switch S1. The voltage Vout across the integrating capacitor Cint is then converted into a digital signal MACout by the ADC circuit 104.

With respect to the application of the implementation in processing multi-bit weight data, reference is now made to FIG. 8 (which generally corresponds to the implementation of FIG. 5), which illustrates an implementation for processing weight data having two bits stored in two columns of memory cells 14a and 14b in an array associated with complementary bit lines BLT <0>, BLC <0> and BLT <1>, BLC <1 >. In this example, the less significant bits (lsb) of the weight data are stored in the memory unit 14a, while the more significant bits (msb) of the weight data are stored in the memory unit 14 b.

The true bit line BLT of the lower significant bit column of memory cells 14 in array 12<0>Coupled, preferably directly, to the non-inverting input of differential amplifier 109lsbT and coupled, preferably directly, to the drain terminal of p-channel MOS transistor M1. The source terminal of transistor M1 is coupled, preferably directly connected, to the supply voltage Vdd node. The inverting input of differential amplifier 109lsbT is coupled to receive a reference voltage Vwm having a voltage level set to be greater than the write margin voltage of memory cell 14. The write margin voltage is the bit line voltage (e.g., vwm is equal to at or about Vdd/2) in the event that the risk of an unexpected bit flip in the 6T SRAM cell during a word line access occurs while there is an in-memory computation operation. The output of differential amplifier 109lsbT is coupled, preferably directly connected, to the gate terminal of p-channel MOS transistor M1 and to the gate terminal of p-channel transistor M2. The source terminal of transistor M2 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M2 is coupled, preferably directly connected, to the true summing node 103_t. Transistors M1 and M2 form a current mirror circuit, and transistors M1, M2 are sized to bit line current I _RlsbT And mirror the bit line current I _RmlsbT Providing a current mirror ratio of 1:1 (i.e., I _RmlsbT ＝I _RlsbT )。

The true bit line BLT of the more significant bit column of memory cells 14 in array 12<1>Coupled, preferably directly, to the non-inverting input of differential amplifier 109msbT and coupled, preferably directly, to the drain terminal of p-channel MOS transistor M3. The source terminal of transistor M3 is coupled, preferably directly connected, to the supply voltage Vdd node. The inverting input of differential amplifier 109msbT is coupled to receive reference voltage Vwm. The output of differential amplifier 109msbT is coupled, preferably directly connected, to the gate terminal of p-channel MOS transistor M3 and to the gate terminal of p-channel transistor M4. The source terminal of transistor M4 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M4 is coupled, preferably directly connected, to the true summing node 103_t. Transistors M3 and M4 form a current mirror circuit, and transistors M3, M4 are sized to bit line current I _RmsbT And mirror the bit line current I _RmmsbT Providing a current mirror ratio of 1:2 (i.e., I _RmmsbT ＝2*I _RmsbT )。

At the current summing node 103_t, the read current I is mirrored _RmlsbT And I _RmmsbT Are added together to generate the resulting output true read current I _RoutT . It will be noted that the current summation is implemented with binary weights due to the corresponding current mirror ratios of the current mirror circuits.

Output read current I from current summing node 103_T _RoutT Is coupled to the intermediate node 102_t through the switch s1_t. The open/close state of the switch s1_t is controlled by the logic state of the integration signal INT. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102_t, and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. The intermediate node 102_t is further coupled to a reference voltage node through a switch s2_t. The open/close state of the switch s2_t is controlled by the logic state of the reset signal RST.

The switches s1_ T, S2_t may each be implemented, for example, using a MOS transistor that is gate-controlled by an appropriate one of the control signals RST and INT.

Complementary bit line BLC of the lower significant bit column of memory cells 14 in array 12<0>Coupled, preferably directly, to the non-inverting input of differential amplifier 109lsbC and coupled, preferably directly, to the drain terminal of p-channel MOS transistor M5. The source terminal of transistor M5 is coupled, preferably directly connected, to the supply voltage Vdd node. The inverting input of differential amplifier 109lsbC is coupled to receive reference voltage Vwm. The output of differential amplifier 109lsbC is coupled, preferably directly connected, to the gate terminal of p-channel MOS transistor M5 and coupled, preferably directly connected, to the gate terminal of p-channel MOS transistor M6. The source terminal of transistor M6 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M6 is coupled, preferably directly connected, to the complementary summing node 103_c. Transistors M5 and M6 form a current mirror circuit, and transistors M5, M6 are sized to bit line current I _RlsbC And mirror the bit line current I _RmlsbC Providing a current mirror ratio of 1:1 (i.e., I _RmlsbC ＝I _RlsbC )。

Complementary bit line BLC of the more significant bit column of memory cells 14 in array 12<1>Coupled, preferably directly, to the non-inverting input of differential amplifier 109msbC and coupled, preferably directly, to the drain terminal of p-channel MOS transistor M7. The source terminal of transistor M7 is coupled, preferably directly connected, to the supply voltage Vdd node. The inverting input of differential amplifier 109msbC is coupled to receive reference voltage Vwm. The output of differential amplifier 109msbC is coupled, preferably directly connected, to the gate terminal of p-channel MOS transistor M7 and the gate terminal of p-channel transistor M8. The source terminal of transistor M8 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M8 is coupled, preferably directly connected, to the complementary summing node 103_c. Transistors M7 and M8 form a current mirror circuit, and the crystalsThe size of the tubes M7, M8 is set to the bit line current I _RmsbC And mirror the bit line current I _RmmsbC Providing a current mirror ratio of 1:2 (i.e., I _RmmsbC ＝2*I _RmsbC )。

More generally, there is a weighted relationship between the current mirror ratios of the current mirror connected transistors on multiple columns of memory cells storing multi-bit weight data. Thus, if additional bit lines BLC <2> are involved, the current mirror connection transistors of the column may have a current mirror ratio of 1:4, according to a weighted relationship.

At the current summing node 103_C, the read current I is mirrored _RmlsbC And I _RmmsbC Are added together to generate the resulting output complementary read current I _RoutC . It will be noted that the current summation is implemented with binary weights due to the corresponding current mirror ratios of the current mirror circuits.

Output read current I from current summing node 103_C _RoutC Is coupled to the intermediate node 102_c through the switch s1_c. The open/close state of the switch s1_c is controlled by the logic state of the integration signal INT. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102_c, and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. The intermediate node 102_c is further coupled to a reference voltage node through a switch s2_c. The open/close state of the switch s2_c is controlled by the logic state of the reset signal RST.

The switches s1_ C, S2_c may each be implemented, for example, using a MOS transistor that is gate-controlled by an appropriate one of the control signals RST and INT.

The intermediate nodes 102_t, 102_c are further coupled to differential inputs of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the difference between the analog voltages vout_ T, vout _c into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each set of columns for storing multi-bit weight data. Alternatively, the ADC circuit 104 may be shared by multiple sets of columns through a time division multiplexing operation. The digital signals MACout from each column may be output from the column processing circuit 20 as a precision, or combined with each other to generate a precision.

The operation of the bit line read circuit 100 is as follows: at the beginning of a calculation cycle of the in-memory calculation operation, the reset signal RST is asserted to close the switch s2_ T, S2_c and discharge the integrating capacitor Cint. Word line signals are then simultaneously applied to rows of memory cells 14 in the SRAM array 12 for in-memory computing operations in accordance with the received characteristic data, and the current I is true read _RlsbT And I _RmsbT Formed on the true bit line BLT and complementary to the read current I _RlsbC And I _RmsbC Formed on the complementary bit line BLC. The magnitude of these read currents depends on the current I sunk to ground by the memory cells 14 of each column involved in the in-memory computation operation _CELL Is a sum of (a) and (b). The integration signal INT is asserted to close the switch s1_ T, S1_c and begin the integration period. The amplifiers 109lsbT, 109msbT, 109lsbC, 109msbC with transistors M1, M3, M5 and M7 serve as voltage clamp circuits configured to prevent bit line BLT<0>、BLC<0>、BLT<1>And BLC<1>The voltage on drops below the reference voltage Vwm during the read operation (which is greater than the write margin voltage in the presence of the risk of an unexpected bit flip). In other words, the circuitry is used to inhibit the voltage on the bit line from falling below the bit flip voltage during an in-memory computing operation when multiple word lines are simultaneously activated. True read current I _RlsbT And I _RmsbT Mirrored to generate true mirror read current I _RmlsbT And I _RmmsbT The true mirror image read current I _RmlsbT And I _RmmsbT Summed at true current summing node 103_T to generate an output true read current I _RoutT . The current is applied to charge an integrating capacitor Cint to generate a current dependent on I _RoutT * Voltage vout_t of T/C, where T is the duration of the integration period (when switch s1_t is closed), and C is the capacitance of integration capacitor Cint. Complementary read current I _RlsbC And I _RmsbC Mirrored to generate true mirror read current I _RmlsbC And I _RmmsbC The true mirror image read current I _RmlsbC And I _RmmsbC At complementary current summing junctionsSummed at point 103_C to generate an output complementary read current I _RoutC . The current is applied to charge an integrating capacitor Cint to generate a current dependent on I _RoutC * Voltage vout_c of t/C, where t is the duration of the integration period (when switch s1_c is closed), and C is the capacitance of integration capacitor Cint. When the integration period expires, the integration signal INT is de-asserted to open the switch s1_ T, S1_c. The difference between the voltages vout_ T, vout _c across the integrating capacitor Cint is then converted to a digital signal MACout by the ADC circuit 104.

Still further, with respect to the application of the implementation in processing multi-bit weight data, reference is now made to FIG. 9 (which generally corresponds to the implementation of FIG. 6), which illustrates an implementation for processing weight data having two bits stored in two columns of memory cells 14a and 14b in an array associated with complementary bit lines BLT <0>, BLC <0> and BLT <1>, BLC <1 >. In this example, the low-significant bits (lsb) of the weight data are stored in the memory unit 14a, and the high-significant bits (msb) of the weight data are stored in the memory unit 14 b.

The true bit line BLT of the lower significant bit column of memory cells 14 in array 12<0>Coupled, preferably directly, to the non-inverting input of differential amplifier 109lsbT and coupled, preferably directly, to the drain terminal of p-channel MOS transistor M1. The source terminal of transistor M1 is coupled, preferably directly connected, to the supply voltage Vdd node. The inverting input of differential amplifier 109lsbT is coupled to receive a reference voltage Vwm having a voltage level set to be greater than the write margin voltage of memory cell 14. The write margin voltage is the bit line voltage (e.g., vwm is equal to or about Vdd/2) in the event that the risk of an unexpected bit flip in the 6T SRAM cell during a word line access occurs while there is an in-memory computation operation. The output of differential amplifier 10lsbT9 is coupled, preferably directly, to the gate terminal of p-channel MOS transistor M1 and coupled, preferably directly, to the gate terminal of p-channel transistor M2. The source terminal of transistor M2 is coupled, preferably directly connected, to the supply voltage Vdd node. Drain terminal of transistor M2Coupled, preferably directly, to the current summing node 103. Transistors M1 and M2 form a current mirror circuit, and transistors M1, M2 are sized to bit line current I _RlsbT And mirror the bit line current I _RmlsbT Providing a current mirror ratio of 1:1 (i.e., I _RmlsbT ＝I _RlsbT )。

The true bit line BLT of the more significant bit column of memory cells 14 in array 12<1>Coupled, preferably directly, to the non-inverting input of differential amplifier 109msbT and coupled, preferably directly, to the drain terminal of p-channel MOS transistor M3. The source terminal of transistor M3 is coupled, preferably directly connected, to the supply voltage Vdd node. The inverting input of differential amplifier 109msbT is coupled to receive reference voltage Vwm. The output of differential amplifier 109msbT is coupled, preferably directly connected, to the gate terminal of p-channel MOS transistor M3 and the gate terminal of p-channel transistor M4. The source terminal of transistor M4 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M4 is coupled, preferably directly connected, to summing node 103. Transistors M3 and M4 form a current mirror circuit, and transistors M3, M4 are sized to bit line current I _RmsbT And mirror the bit line current I _RmmsbT Providing a current mirror ratio of 1:2 (i.e., I _RmmsbT ＝2*I _RmsbT )。

Complementary bit line BLC of the lower significant bit column of memory cells 14 in array 12<0>Coupled, preferably directly, to the non-inverting input of differential amplifier 109lsbC and coupled, preferably directly, to the drain terminal of p-channel MOS transistor M5. The source terminal of transistor M5 is coupled, preferably directly connected, to the supply voltage Vdd node. The inverting input of differential amplifier 109lsbC is coupled to receive reference voltage Vwm. The output of differential amplifier 109lsbCThe outcoupling is preferably directly connected to the gate terminal of the p-channel MOS transistor M5 and the gate terminal of the p-channel OS transistor M6. The source terminal of transistor M6 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M6 is coupled, preferably directly connected, to the input of the n-channel MOS current mirror circuit formed by transistors Ma and Mb. The output of the n-channel MOS current mirror circuit is coupled, preferably directly, to a current summing node 103. Transistors M5 and M6 form a current mirror circuit, and transistors M5, M6 are sized to bit line current I _RlsbC And mirror the bit line current I _RmlsbC Providing a current mirror ratio of 1:1 (i.e., I _RmlsbC ＝I _RlsbC )。

Complementary bit line BLC of the more significant bit column of memory cells 14 in array 12 <1>Coupled, preferably directly, to the non-inverting input of differential amplifier 109msbC and coupled, preferably directly, to the drain terminal of p-channel MOS transistor M7. The source terminal of transistor M7 is coupled, preferably directly connected, to the supply voltage Vdd node. The inverting input of differential amplifier 109msbC is coupled to receive reference voltage Vwm. The output of differential amplifier 109msbC is coupled, preferably directly connected, to the gate terminal of p-channel MOS transistor M7 and the gate terminal of p-channel transistor M8. The source terminal of transistor M8 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M8 is coupled, preferably directly connected, to the input of the n-channel MOS current mirror circuit formed by transistors Mc and Md. The output of the n-channel MOS current mirror circuit is coupled, preferably directly, to a current summing node 103. Transistors M7 and M8 form a current mirror circuit, and transistors M7, M8 are sized to bit line current I _RmsbC And mirror the bit line current I _RmssbC Providing a current mirror ratio of 1:2 (i.e., I _RmmsbC ＝2*I _RmsbC )。

At the current summing node 103, the current I is actually read from the mirror _RmlsbT And I _RmmsbT Subtracting the mirrored complementary read current I from the sum of (a) _RmlsbC And I _RmmsbC To generate a resulting output read current I _Rout (i.e., I _Rout ＝I _RmlsbT +I _RmmsbT -I _RmlsbC -I _RmmsbC )。

The intermediate node 102 is further coupled to an input of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the analog voltage Vout into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each set of columns storing multi-bit weight data. Alternatively, the ADC circuit 104 may be shared by multiple sets of columns through a time division multiplexing operation. The digital signals MACout from each column may be output from the column processing circuit 20 as a precision, or combined with each other to generate a precision.

The operation of the bit line read circuit 100 is as follows: at the beginning of a calculation cycle of the in-memory calculation operation, the reset signal RST is asserted to close switch S2 and discharge the integrating capacitor Cint. Word line signals are then simultaneously applied to rows of memory cells 14 in the SRAM array 12 for in-memory computing operations, depending on the received characteristic data, and the current I is actually read _RlsbT And I _RmsbT At the true bit line BLTFormed above, and complements the read current I _RlsbC And I _RmsbC Formed on the complementary bit line BLC. The magnitude of these read currents depends on the current I sunk to ground by the memory cells 14 of each column involved in the in-memory computation operation _CELL Is a sum of (a) and (b). The integration signal INT is asserted to close switch S1 and begin the integration period. The amplifiers 109lsbT, 109msbT, 109lsbC, 109msbC with transistors M1, M3, M5 and M7 serve as voltage clamp circuits configured to prevent bit line BLT<0>、BLC<0>、BLT<1>And BLC<1>The voltage on drops below the reference voltage Vwm during the read operation (which is greater than the write margin voltage in the presence of the risk of an unexpected bit flip). In other words, the circuitry is used to inhibit the voltage on the bit line from falling below the bit flip voltage during an in-memory computing operation when multiple word lines are simultaneously activated. True read current I _RlsbT And I _RmsbT Mirrored to generate true mirror read current I summed at current summing node 103 _RmlsbT And I _RmmsbT . Complementary read current I _RlsbC And I _RmsbC Mirrored to generate true mirror read current I subtracted from current summing node 103 _RmlsbC And I _RmmsbC . The result is the generation of an output read current I _Rout . The current is applied to charge an integrating capacitor Cint to generate a current dependent on I _Rout * the voltage Vout of t/C, where t is the duration of the integration period (when switch S1 is closed), and C is the capacitance of the integration capacitor Cint. When the integration period expires, the integration signal INT is de-asserted to open switch S1. The voltage Vout across the integrating capacitor Cint is then converted into a digital signal MACout by the ADC circuit 104.

Referring now to fig. 10, fig. 10 shows a circuit diagram of a bit line read circuit 100' for use within column processing circuit 20. The bit lines BL for a given column of memory cells 14 in the array 12 are coupled, preferably directly connected, to the inverting input of the differential amplifier 119. The output of differential amplifier 119 is coupled to the inverting input through feedback resistor Rfb. The non-inverting input of differential amplifier 109 is coupled to receive a reference voltage Vwm having a voltage level set to be greater than the write margin voltage of memory cell 14. The write margin voltage is the bit line voltage (e.g., vwm is equal to or about Vdd/2) in the event that the risk of an unexpected bit flip in the 6T SRAM cell during a word line access occurs while there is an in-memory computation operation. The output of the differential amplifier 119 is coupled, preferably directly connected, to the input of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the analog voltage Vout into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each column. Alternatively, one ADC circuit 104 may be shared by multiple columns through a time division multiplexing operation. The digital signals MACout from each column may be output from the column processing circuit 20 as a precision, or combined with each other to generate a precision.

It will be appreciated that for each column of memory, one bit line read circuit 100' is provided in the column processing circuit 20.

The operation of the bit line read circuit 100' is as follows: the word line signals according to the received characteristic data are applied simultaneously to multiple rows of memory cells 14 in the SRAM array 12 during the computation period of the in-memory computation operation. Read current I _R Formed on the bit line BL. Read current I _R The magnitude of (2) depends on the current I sunk to ground by the memory cells 14 of the column involved in the in-memory computation operation _CELL Is a sum of (a) and (b). The configuration of amplifier 119 with resistive feedback forms a voltage summing circuit that sums Vwm with voltage V _R Adding (wherein V _R ＝I _R * Rfb) to generate a voltage Vout at the output of the amplifier 119. The voltage Vout is then converted into a digital signal MACout by the ADC circuit 104. The amplifier 119 with resistive feedback further operates as a voltage clamp circuit to clamp the voltage on the bit line BL to the voltage Vwm and thus prevent the voltage on the bit line BL from dropping below the write margin level during in-memory computing operations where multiple word lines are simultaneously asserted.

Referring now to fig. 11, fig. 11 shows a circuit diagram of a differential signal implementation of the bit line read circuit 100'. Like reference numerals refer to the same or similar components. In this implementation, the current on the true bit line BLT and the complementary bit line BLC is determined by The bit line read circuit 100'. The use of the suffix "_t" designates the component associated with the processing of the read current on the true bit line BLT, and the use of the suffix "_c" designates the component associated with the processing of the read voltage on the complementary bit line BLC. Thus, the bit line read circuit 100' includes a circuit for handling the read current I on the true bit line BLT _{R_T} True read circuit 100' _t for processing read current I on complementary bit line BLC _{R_C} Complementary read circuit 100' _c of (a). The circuit configuration of each of the read circuits 100'_t, 100' _c is the same as that shown in fig. 10, and each operates in the above-described manner. The differential signaling implementation in fig. 11 differs from the implementation of fig. 10 in that the differential integrated voltage vout_ T, vout _c is generated by the bit line read circuits 100'_t, 100' _c, and the ADC circuit 104 operates to convert the difference between the voltages vout_ T, vout _c to obtain the digital signal MACout.

Referring now to true read circuit 100' _T, the true bit line BLT of a given column of memory cells 14 in array 12 is coupled, preferably directly, to the inverting input of differential amplifier 119_T. The output of differential amplifier 119_t is coupled to the inverting input through feedback resistor Rfb. The non-inverting input of differential amplifier 119_t is coupled to receive a reference voltage Vwm having a voltage level set to be greater than the write margin voltage of memory cell 14. The write margin voltage is the bit line voltage (e.g., vwm is equal to at or about Vdd/2) in the event that the risk of an unexpected bit flip in the 6T SRAM cell during a word line access occurs while there is an in-memory computation operation.

Referring now to complementary read circuit 100' _C, complementary bit line BLC of a given column of memory cells 14 in array 12 is coupled, preferably directly, to the inverting input of differential amplifier 119_C. The output of differential amplifier 119_c is coupled to the inverting input through feedback resistor Rfb. The non-inverting input of differential amplifier 119_c is coupled to receive a reference voltage Vwm.

The outputs of the differential amplifiers 119_t, 119_c are coupled, preferably directly connected, to differential inputs of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the difference between the analog voltages vout_t and vout_c into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each column. Alternatively, one ADC circuit 104 may be shared by multiple columns through a time division multiplexing operation. The digital signals MACout from each column may be output from the column processing circuit 20 as a precision, or combined with each other to generate a precision.

It should be appreciated that for each column of memory, a pair of bit line read circuits 100'_t, 100' _c are provided in the column processing circuit 20.

The operation of the bit line read circuit 100' is as follows: the word line signals according to the received characteristic data are applied simultaneously to multiple rows of memory cells 14 in the SRAM array 12 during the computation period of the in-memory computation operation. Read current I _{R_T} And I _{R_C} Formed on complementary bit lines BLT, BLC. Read current I _{R_T} And I _{R_C} The magnitude of (2) depends on the current I sunk to ground by the memory cells 14 of each column involved in the in-memory computing operation _CELL Is a sum of (a) and (b). The configuration of each amplifier 119 with resistive feedback forms a voltage summing circuit that sums the write margin voltage Vwm with the voltage V _{R_T} 、V _{R_C} Adding (wherein V _R ＝I _R * Rfb) to generate a voltage vout_ T, vout _c at the output of the amplifiers 119_t, 119_c. The difference between the voltages vout_ T, vout _c is then converted to a digital signal MACout by the ADC circuit 104. The amplifiers 119_t, 119_c with resistive feedback each further operate as voltage clamping circuits to clamp the voltage on the complementary bit lines BLT, BLC to the voltage Vwm and thus prevent the voltage on the bit lines BLT, BLC from dropping below the write margin level during in-memory computing operations where multiple word lines are simultaneously asserted.

The implementations in fig. 4A, 4B, 5, 6, 7A, 7B, 8, 9, 10, and 11 further utilize the adaptive supply voltage Vbias for word line driving. The supply voltage of the word line driver circuit 16 is not fixedly equal to Vdd (i.e., it is different from the array supply voltage) or is set to have a fixed word line undervoltage level (e.g., V _WLUD =vdd/2). In contrast, the supply voltage of the word line driver circuit 16 is self-modulated according to the integrated circuit process conditionsThe supply voltage Vbias is adapted. The voltage level of the adaptive supply voltage Vbias is less than the supply voltage Vdd and is generated by the voltage generator circuit 212, as shown in fig. 12, where the voltage level is proportional (by a factor of n) to the reference current Iref level. The reference current Iref has a magnitude defined by the fast n-channel MOS process lot. For example, the reference current Iref for a given bit cell is the current at which the multi-row access write margin (MRAWM, which is the maximum level of bit line voltage required to write the bit cell) is zero while allowing the bit line to swing entirely rail-to-rail (full rail swing) at the worst process corner. The n value of the scaling factor is set by design and is based on the desired variability of the adaptive supply voltage Vbias level (so that n copies will effectively minimize the change in Vbias due to local variations).

The voltage generator circuit 212 comprises a current source 214, the current source 214 being powered by a supply voltage Vdd and generating an output current Iout at a node 216, wherein the current source is connected in series with a series connection of a first n-channel MOS transistor 218 and a second n-channel transistor 220. The output current Iout is applied (i.e., forced) to a circuit having transistors 218 and 220 to generate a bias voltage Vbias, where transistors 218 and 220 effectively replicate the pass-gate and pull-down transistor configuration that depicts the read conditions of memory cell 14. First n-channel MOS transistor 218 has a drain coupled (preferably directly connected) to node 216 and a source coupled (preferably directly connected) to node 222. The gate of the first n-channel MOS transistor 218 is coupled (preferably directly connected) to the drain at node 216, thereby configuring the transistor 218 as a diode-connected device. The first n-channel MOS transistor 218 is a scaled replica (scaled replica) of the n-channel pass transistors 26 and 28 within each memory cell 14, where the scaling factor is equal to n. In this context, "scaled copy" means that transistor 218 is fabricated using the same integrated circuit process materials and parameters (doping levels, oxide thicknesses, gate materials, etc.) as each of transistors 26 and 28 of cell 14, but is n-fold repeated for a single transistor, thereby providing an effectively larger width. For example, transistor 218 may be fabricated by connecting n transistors in parallel that are identical (matched) to each of transistors 26 and 28. The second n-channel MOS transistor 220 has a drain coupled (preferably directly connected) to a node 222 and a source coupled (preferably directly connected) to a ground power supply reference. The gate of the second n-channel MOS transistor 220 is coupled (preferably directly connected) to receive the supply voltage Vdd. Second n-channel MOS transistor 220 is a scaled copy of n-channel pulldown transistors 34 and 36 within each memory cell 14, where the scaling factor is equal to n. For example, transistor 220 may be fabricated by connecting n transistors in parallel that are identical (matched) to each of transistors 34 and 36 of cell 14.

The bias voltage Vbias generated at node 216 is equal to:

vbias=n (Iref) (Rdson 218+rdson 220), wherein: rdson218 is the drain to source resistance of the diode connected first n-channel MOS transistor 218 and Rdson220 is the drain to source resistance of the second n-channel transistor 220 that is gate biased by the supply voltage Vdd. During a read operation, the series connected transistors 218 and 220 replicate the current path from the bit line (BL, BLT or BLC) to ground in the memory cell 14 by a scaling factor n, under which operating conditions the pass gate transistor and its pull-down transistor on one side of the memory cell are both on.

Differential amplifier circuit 224, configured as a unity gain voltage follower, receives the Vbias voltage at its non-inverting input and generates Vbias at its output 226 with sufficient drive capability (drive capability) to power all word line driver circuits 16 of the word lines that are simultaneously actuated during an in-memory computing operation. The output of the differential amplifier circuit 224 is shorted to the inverting input.

Referring now to fig. 13, fig. 13 shows a schematic diagram of an alternative embodiment of the voltage generator circuit 212. The voltage generator circuit 212 of fig. 13 differs from the implementation shown in fig. 12 in that further integrated circuit process and/or temperature-based tuning of the magnitude of the current Iout output by the current source 214 within the voltage generator circuit 212 is supported. In this context, current source 214 is formed by a variable current source having a basic (or nominal) current Inom size equal to n (Iref) and having a positive or negative adjustment adj with respect to the basic current size level set by the control signal. In other words, the magnitude of the current output Iout of the current source 214 is equal to n (Iref) ±adj, where adj is the adjustment set by the control signal. In one embodiment, the control signal is a multi-bit digital control signal Vsel, but it should be understood that the control signal may instead be implemented as an analog signal. The value of the control signal, in particular the digital value of the bit of the control signal Vsel, selects the degree of regulation of the magnitude of the current output by the current source 214. The control signal Vsel is generated by the control circuit 114 in response to integrated circuit process and/or temperature information. Thus, the level of the adaptive supply voltage Vbias is now additionally based on this integrated circuit process and/or temperature information.

The integrated circuit process information is a digital code that is generated and stored in memory M within control circuit 114. The digital code represents the center of the process lot and is generated by circuitry, such as a Ring Oscillator (RO), whose output frequency varies according to the integrated circuit process. Thus, the output frequency of the RO circuit represents the process center and can be easily converted to a digital code (e.g., by using a counter circuit). The process monitor circuit 116 within the control circuit 114 may generate a value of the control signal Vsel that depends on the stored digital code for the integrated circuit process. For example, the process monitor circuit 116 may include a look-up table (LUT) that correlates (correlate) each digital code to a value of the control signal Vsel for selecting a positive or negative adjustment adj for the nominal magnitude of the current generated by the current source 214 to ensure that the voltage level of the adaptive supply voltage Vbias will produce an optimal level for wordline underactuation at the integrated circuit process corner. The control circuit 114 outputs a value of the control signal Vsel that is related to the digital code, and the voltage generator circuit 212 responds by generating a corresponding voltage level of the adaptive supply voltage Vbias.

Temperature information is generated by the temperature sensing circuit 118 and is representative of the current temperature of the integrated circuit. The temperature sensing circuit 118 may modify or adjust the value of the control signal Vsel in accordance with the sensed temperature. For example, the temperature sensing circuit 118 may include a look-up table (LUT) that specifies a particular adjustment of the value of the control signal Vsel for providing a corresponding tuning of the magnitude of the current output by the current source 214 to ensure that the level of the adaptive supply voltage Vbias will produce an optimal level of wordline underdrive given the integrated circuit process corner and current temperature conditions.

Referring now to fig. 14, fig. 14 shows a flow chart of the operation of the control circuit 114 and the process monitoring circuit 116 of the circuit of fig. 13. In step 140, the stored digital code for the integrated circuit process is read from memory M. In one embodiment, the digital code of the integrated circuit process is loaded into memory M at the factory and is based on the identified integrated circuit process characteristics (fast/slow angle, etc.) of the integrated circuit manufacturing lot (e.g., source wafer) from which the integrated circuit was obtained. Next, in step 142, it is determined whether the read digital code of the integrated circuit process indicates that the n-channel MOS transistor of memory cell 12 is at a fast integrated circuit process corner (i.e., where the n-channel MOS is fast and the p-channel MOS is slow-an "FS" corner). If so, in step 144, a value of control signal Vsel is selected that corresponds to the digital code read and will cause a negative adjustment adj in the magnitude of the current output by current source 214 so that voltage regulator circuit 212 will produce a higher degree of word line under-actuation (i.e., the level of adaptive supply voltage Vbias will be lower than the nominal (or default) level of word line under-actuation set by nominal current magnitude n (Iref)). The effect of setting the adaptive supply voltage Vbias to a voltage level lower than the nominal (or default) voltage level is to reduce MRAWM. Reducing MRAWM results in reduced write capability and increased data flip rate of the bit cell, which is of interest at the fast n-channel MOS corner. Such a voltage level below nominal (or default) also allows for a higher headroom for bitline swing and thus a higher accuracy of bitline accumulation in memory computation operations. If no in step 142, then in step 146, a determination is made as to whether the read digital code of the integrated circuit process indicates that the n-channel MOS transistor of memory cell 12 is at a slow integrated circuit process corner (i.e., where the n-channel MOS is slow and the p-channel MOS is fast-the "SF" corner). If so, then in step 148, a value of control signal Vsel is selected that corresponds to the digital code read and will cause a positive adjustment adj in the magnitude of the current output by current source 214 so that voltage regulator circuit 212 will produce a lower degree of word line underdrive (i.e., the level of adaptive supply voltage Vbias is higher than the nominal (or default) level of word line underdrive set by nominal current magnitude n (Iref)). The effect of setting the adaptive supply voltage Vbias to a voltage level higher than the nominal (or default) voltage level is to increase the multi-row access write margin (MRAWM), thereby improving the cell current while still controlling the data flip rate, which is less of a concern at the slow NMOS corner. Such higher than nominal (or default) voltage levels also reduce the effects of local variations in the slow process corner. If no in step 146, then in step 150, the value of the control signal Vsel is selected, which corresponds to the digital code read, and will not cause an adjustment in the n (Iref) magnitude of the current output by the current source 214 (i.e., adj=0) so that the level of the adaptive supply voltage Vbias that the voltage regulator circuit 212 will produce is equal to the nominal (or default) level of the word line under-drive set by the nominal current Inom.

Although the process of fig. 14 contemplates three voltage control levels (above, below, and equal to the nominal voltage), it is understood that this is merely an example. Additional test steps may be added to the process of fig. 14 to test other integrated circuit process corners or process related conditions (e.g., fast-fast, FF) and/or slow-slow, SS) corners, each test having an associated digital code and a value of control signal Vsel for setting a corresponding level of regulation of the current output by current source 214 of voltage generator circuit 212.

Referring now to fig. 15, fig. 15 shows a circuit diagram of one embodiment of the ADC circuit 104. The ADC circuit 104 may be implemented as a Successive Approximation Register (SAR) type circuit as shown. The input of the sampling circuit 300 is coupled, preferably directly connected, to receive the output voltage Vout of the read circuit 100, 100'. The output of sampling circuit 300 is coupled, preferably straightIs connected to the non-inverting input of the comparator circuit 302. The inverting input of the comparator circuit 302 is coupled to receive a feedback voltage V _FB . The logic output of the comparator circuit 302 is coupled, preferably directly connected, to SAR logic 304 having a register 306. At the end of the conversion period, the output of the register 306 provides a digital signal MACOut (i.e., a digital value corresponding to the analog voltage Vout) of the ADC circuitry 104. The bits of register 306 are further coupled, preferably directly connected, to inputs of digital-to-analog converter (DAC) circuitry 308. In particular, DAC circuit 308 is implemented as a current DAC, where the bits of digital signal MACOut activate a current source to generate output current I _DAC And corresponding output voltage V _DAC . The current source of the current DAC 308 is referenced (i.e., mirrored) to a reference current source that generates a reference current Iref (which is also used in conjunction with the generation of the word line driver 16 bias voltage Vbias, as shown in fig. 12 and 13). The output of the current DAC 308 is coupled, preferably directly connected, to the inverting input of the differential amplifier circuit 310. The non-inverting input of the differential amplifier circuit 310 is coupled to receive a reference voltage Vwm (as shown in fig. 4A, 4B, 5, 6, 7A, 7B, 8, 9, 10, and 11) that is also used as a reference voltage for the clamp circuits of the read circuits 100, 100'. The reference voltage Vwm has a voltage level set to be greater than the write margin voltage of the memory cell 14, which represents a voltage greater than the bit line voltage in the event that the risk of an unexpected bit flip in the 6T SRAM cell during a simultaneous word line access while there is a computing operation occurs (e.g., vwm is equal to a voltage at or about Vdd/2). The output of the differential amplifier circuit 310 is coupled, preferably directly connected, to the inverting input through a feedback resistor Rfb. Configuration of an amplifier with resistive feedback forms the voltage V and Vwm _DAC And an added voltage adding circuit. (wherein V _DAC ＝I _DAC * Rfb). The output of the differential amplifier circuit 310 generates a feedback voltage V _FB 。

The output voltage Vout (from the read circuit 100, 100') is sampled and held by the sampling circuit 300. A binary search algorithm is then implemented by SAR logic 304 (binary search algorithm). In register 306The most significant bit is set to logic 1 and all other bits are set to logic 0. The current DAC circuit 308 converts it to a voltage V _DAC And feed back voltage V _FB (V _DAC +vwm) is compared (sampled) by comparator 302 with Vout. Here, it is noted that the voltage offset Vwm with feedback introduced by the amplifier 310 is required to compensate for the corresponding voltage offset (Vwm) introduced by the clamping circuit of the read circuit 100, 100' and thus ensure that the converted output digital signal MACout accurately reflects the read current. If Vout>V _FB The most significant bit remains set to logic 1. Otherwise, the most significant bit in register 306 is set to logic 0. The algorithm then moves to the next most significant bit and sets its value to 1 (the remaining bits are not changed at logic 0). Generating a voltage V _DAC And V _FB Wherein V is _FB A comparison (sampling) is made with Vout and as a result of the comparison, the logic value of the next most significant bit is set to logic 1 or 0. The recursive process continues to select bits in register 306 continuously until the least most significant bit is determined. At this time, the conversion period ends, and the digital signal MACout is ready to be output from the ADC circuit 104.

The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of exemplary embodiments of the invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.

Claims

1. An in-memory computing circuit comprising:

a memory array comprising a plurality of memory cells arranged in a matrix having a plurality of rows and a plurality of columns, each row comprising a word line connected to the memory cells of the row and each column comprising a first bit line connected to the memory cells of the column;

a word line driver circuit for each row having an output connected to drive the word lines of the row;

a row controller circuit configured to actuate the plurality of word lines simultaneously by applying pulses to the word lines through the word line driver circuit in response to characteristic data for an in-memory computing operation; and

column processing circuitry includes first read circuitry coupled to each first bit line, wherein each first read circuitry includes:

A first differential amplifier having a first input coupled to the first bit line, a second input configured to receive a reference voltage, and an output;

wherein the reference voltage is at a level greater than a bit flip voltage of the memory cell during the simultaneous actuation of the plurality of word lines for the in-memory computing operation;

a first MOS transistor having a drain coupled to the first bit line to receive the first read current and a gate coupled to the output of the first differential amplifier;

a second MOS transistor having a gate coupled to the output of the first differential amplifier and a drain configured to output a first mirrored read current; and

a first integrating capacitor configured to integrate the first mirrored read current to generate a first output voltage.

2. The circuit of claim 1, wherein the first differential amplifier and the first MOS transistor are to clamp a voltage on the first bit line to the reference voltage.

3. The circuit of claim 1, wherein the column processing circuit further comprises an analog-to-digital converter ADC circuit configured to convert the first output voltage to a digital output.

4. The circuit of claim 1, further comprising a switch coupled in series with the second MOS transistor, wherein the switch is actuated by an integration control signal to control integration of the first mirrored read current by the first integrating capacitor during the in-memory computing operation.

5. The circuit of claim 1, wherein the first integrating capacitor is discharged in response to assertion of a reset control signal at the beginning of the in-memory computing operation.

6. The circuit of claim 1, wherein each column further comprises a second bit line connected to the memory cells of the column, and wherein the column processing circuit further comprises a second read circuit coupled to each second bit line, wherein each second read circuit comprises:

a second differential amplifier having a first input coupled to the second bit line, a second input configured to receive the reference voltage, and an output;

a third MOS transistor having a drain coupled to the second bit line to receive the second read current and a gate coupled to the output of the second differential amplifier; and

a fourth MOS transistor having a gate coupled to the output of the second differential amplifier and a drain configured to output a second mirrored read current; and

A second integrating capacitor configured to integrate the second mirrored read current to generate a second output voltage.

7. The circuit of claim 6:

wherein the first differential amplifier and the first MOS transistor are for clamping a voltage on the first bit line to the reference voltage; and is also provided with

Wherein the second differential amplifier and the third MOS transistor are for clamping the voltage on the second bit line to the reference voltage.

8. The circuit of claim 6, wherein the column processing circuit further comprises an analog-to-digital converter ADC circuit configured to convert a difference between the first output voltage and the second output voltage to a digital output.

9. The circuit of claim 6, further comprising a switch coupled in series with each of the second MOS transistor and the fourth MOS transistor, wherein during the in-memory computing operation, the switch is actuated by an integration control signal to control integration of the first and second integration capacitors with the first and second mirrored read currents, respectively.

10. The circuit of claim 6, wherein the first integrating capacitor and the second integrating capacitor are discharged in response to assertion of a reset control signal at the beginning of the in-memory computing operation.

11. The circuit of claim 1, wherein each column further comprises a second bit line connected to the memory cells of the column, and wherein the column processing circuit further comprises a second read circuit coupled to each second bit line, wherein each second read circuit comprises:

a fourth MOS transistor having a gate coupled to the output of the second differential amplifier and a drain configured to output a second mirrored read current;

wherein the first integrating capacitor is configured to integrate a difference between the first mirrored read current and the second mirrored read current to generate the first output voltage.

12. The circuit of claim 11, wherein:

13. The circuit of claim 11, wherein the column processing circuit further comprises an analog-to-digital converter ADC circuit configured to convert the first output voltage to a digital output.

14. The circuit of claim 11, further comprising a switch coupled in series with at least one of the second MOS transistor and the fourth MOS transistor, wherein during the in-memory computing operation, the switch is actuated by an integration control signal to control integration of the first integration capacitor to a difference between the first mirrored read current and the second mirrored read current.

15. The circuit of claim 11, wherein the first integrating capacitor is discharged in response to assertion of a reset control signal at the beginning of the in-memory computing operation.

16. The circuit of claim 1, wherein the word line driver circuit is powered by an adaptive supply voltage, and the circuit further comprises:

a voltage generator circuit configured to generate the adaptive supply voltage for powering the word line driver circuit during the simultaneous actuation of the plurality of word lines for the in-memory computing operation, the adaptive supply voltage having a level according to integrated circuit process and/or temperature conditions.

17. The circuit of claim 16, wherein the voltage generator circuit comprises:

a current source configured to generate a current applied to the first node; and

a series connection of a first transistor and a second transistor between the first node and a reference node;

wherein the adaptive supply voltage is generated at the first node;

wherein the first transistor is a replica of a pass gate transistor within the memory cell;

wherein the second transistor is a replica of a pull-down transistor within the memory cell.

18. The circuit of claim 17, wherein:

the current generated by the current source has a magnitude set to depend on a reference current representing a current flowing through the pass gate transistor and the pull-down transistor for an applicable integrated circuit process corner; and is also provided with

The magnitude of the current generated by the current source is scaled by a factor applied to the reference current;

wherein the first transistor is scaled by the factor to the replica of the pass gate transistor; and is also provided with

Wherein the second transistor is scaled by the factor to the replica of the pull-down transistor.

19. The circuit of claim 18, wherein the column processing circuit further comprises a successive approximation register, SAR, analog-to-digital converter, ADC, circuit configured to convert the first output voltage to a digital output, the SAR ADC circuit comprising a feedback digital-to-analog converter, DAC, circuit having a selectively actuated current source referenced to the reference current.

20. The circuit of claim 17, further comprising an amplifier circuit having an input coupled to the first node and an output coupled to power the word line driver circuit.

21. The circuit of claim 17, wherein the current source is controlled to generate an adjustment to the current, and further comprising a control circuit configured to: a control signal to be applied to the current source is generated to modulate the level of the current away from a nominal level in response to an applicable integrated circuit process corner for a transistor device of the memory cell.

22. The circuit of claim 21, wherein the applicable integrated circuit process corner is indicated by programming code stored in the control circuit.

23. The circuit of claim 22, wherein the control circuit comprises a look-up table LUT that associates the programming code with a value of the control signal.

24. The circuit of claim 21, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to: causing a temperature dependent tuning of the level of the current responsive to the applicable integrated circuit process corner setting.

25. The circuit of claim 24, wherein the control circuit comprises a look-up table LUT relating sensed integrated circuit temperature to a tuning level of the value of the control signal.

26. The circuit of claim 1, wherein each memory cell is a 6TSRAM cell.

27. An in-memory computing circuit comprising:

a memory array comprising a plurality of memory cells arranged in a matrix having a plurality of rows and first and second columns, each row comprising a word line connected to the memory cells of the row, and each of the first and second columns comprising a first bit line connected to the memory cells of the column;

a column processing circuit comprising:

a first read circuit comprising:

a first voltage clamp circuit configured to clamp a voltage on the first bit line of the first column to a reference voltage during the simultaneous actuation of the plurality of word lines for the in-memory computing operation; and

a first current mirror circuit connected to the first voltage clamp circuit and coupled to the first bit line of the first column, the first current mirror circuit having a first current mirror ratio and configured to mirror a first read current on the first bit line of the first column to generate a first mirrored read current;

a second reading circuit comprising:

a second voltage clamp circuit configured to clamp a voltage on the first bit line of the second column to the reference voltage during the simultaneous actuation of the plurality of word lines for the in-memory computing operation; and

A second current mirror circuit connected to the second voltage clamp circuit and coupled to the first bit line of the second column, the second current mirror circuit having a second current mirror ratio and configured to mirror a second read current on the first bit line of the second column to generate a second mirrored read current; and

a first integrating capacitor configured to integrate a sum of the first mirrored read current and the second mirrored read current to generate a first output voltage;

wherein the reference voltage is at a level greater than a bit flip voltage of the memory cell during the simultaneous actuation of the plurality of word lines for the in-memory computing operation.

28. The circuit of claim 27, wherein the first and second mirror ratios are different and have binary weights.

29. The circuit of claim 27, wherein the column processing circuit further comprises an analog-to-digital converter ADC circuit configured to convert the first output voltage to a digital output.

30. The circuit of claim 27, wherein each of the first and second current mirror circuits comprises:

A differential amplifier having a first input coupled to the first bit line, a second input configured to receive the reference voltage, and an output;

a first MOS transistor having a drain coupled to the first bit line to receive the first read current or the second read current and a gate coupled to the output of the differential amplifier; and

a second MOS transistor having a gate coupled to the output of the differential amplifier and a drain configured to output the first mirrored read current or the second mirrored read current.

31. The circuit of claim 27, wherein each of the first and second current mirror circuits is switchably controlled to output the first and second mirrored read currents, respectively, in response to assertion of an integral control signal during the in-memory computing operation.

32. The circuit of claim 27, wherein the first integrating capacitor is discharged in response to assertion of a reset control signal at the beginning of the in-memory computing operation.

33. The circuit of claim 27, wherein each column further comprises a second bit line connected to the memory cells of the column, and wherein the column processing circuit further comprises:

A third read circuit comprising:

a third voltage clamp circuit configured to clamp a voltage on the second bit line of the first column to the reference voltage during the simultaneous actuation of the plurality of word lines for the in-memory computing operation; and

a third current mirror circuit connected to the third voltage clamp circuit and coupled to the second bit line of the first column, the third current mirror circuit having the first current mirror ratio and configured to mirror a third read current on the second bit line of the first column to generate a third mirrored read current;

a fourth read circuit comprising:

a fourth voltage clamp circuit configured to clamp a voltage on the second bit line of the second column to the reference voltage during the simultaneous actuation of the plurality of word lines for the in-memory computing operation; and

a fourth current mirror circuit connected to the fourth voltage clamp circuit and coupled to the second bit line of the second column, the fourth current mirror circuit having the second current mirror ratio and configured to mirror a fourth read current on the second bit line of the second column to generate a fourth mirrored read current; and a second integrating capacitor configured to integrate a sum of the third and fourth mirrored read currents to generate a second output voltage.

34. The circuit of claim 33, wherein the first and second mirror ratios are different and have binary weights.

35. The circuit of claim 33, wherein the column processing circuit further comprises an analog-to-digital converter ADC circuit configured to convert a difference between the first output voltage and the second output voltage to a digital output.

36. The circuit of claim 33, wherein each of the first, second, third, and fourth current mirror circuits comprises:

a differential amplifier having a first input coupled to the first bit line or the second bit line, a second input configured to receive the reference voltage, and an output;

a first MOS transistor having a drain coupled to the first bit line or the second bit line to receive the first read current, the second read current, the third read current, or the fourth read current, and a gate coupled to the output of the differential amplifier; and

a second MOS transistor having a gate coupled to the output of the differential amplifier and a drain configured to output the first mirrored read current, the second mirrored read current, the third mirrored read current, or the fourth mirrored read current.

37. The circuit of claim 33, wherein each of the first, second, third, and fourth current mirror circuits is switchably controlled to output the first, second, third, or fourth mirror read current, respectively, in response to assertion of an integration control signal during the in-memory computing operation.

38. The circuit of claim 33, wherein the first integrating capacitor and the second integrating capacitor are discharged in response to assertion of a reset control signal at the beginning of the in-memory computing operation.

39. The circuit of claim 27, wherein each column further comprises a second bit line connected to the memory cells of the column, and wherein the column processing circuit further comprises:

a third read circuit comprising:

a fourth read circuit comprising:

a fourth current mirror circuit connected to the fourth voltage clamp circuit and coupled to the second bit line of the second column, the fourth current mirror circuit having the second current mirror ratio and configured to mirror a fourth read current on the second bit line of the second column to generate a fourth mirrored read current; and wherein the first integrating capacitor is configured to integrate a difference between a sum of the first and second mirrored read currents and a sum of the third and fourth mirrored read currents to generate the first output voltage.

40. The circuit of claim 39, wherein the first and second mirror ratios are different and have binary weights.

41. The circuit of claim 40, wherein the column processing circuit further comprises an analog-to-digital converter ADC circuit configured to convert the first output voltage to a digital output.

42. The circuit of claim 39, wherein each of the first, second, third, and fourth current mirror circuits comprises:

43. The circuit of claim 39, wherein each of the first, second, third, and fourth current mirror circuits is switchably controlled to output the first, second, third, or fourth mirror read currents, respectively, in response to assertion of an integral control signal during the in-memory computing operation.

44. The circuit of claim 39, wherein the first integrating capacitor is discharged in response to assertion of a reset control signal at the beginning of the in-memory computing operation.

45. The circuit of claim 27, wherein the word line driver circuit is powered by an adaptive supply voltage, and further comprising:

a voltage generator circuit configured to generate the adaptive supply voltage for powering the word line driver circuit during the simultaneous actuation of the plurality of word lines by the in-memory computing operation, the adaptive supply voltage having a level according to an integrated circuit process and/or temperature condition.

46. The circuit of claim 45, wherein the voltage generator circuit comprises:

wherein the adaptive supply voltage is generated at the first node;

47. The circuit of claim 46, wherein:

the current generated by the current source has a magnitude set to depend on a reference current representing a current flowing through the pass gate transistor and the pull-down transistor for an applicable integrated circuit process corner; and

48. The circuit of claim 47, wherein the column processing circuit further comprises a successive approximation register, SAR, analog-to-digital converter, ADC, circuit configured to convert the first output voltage to a digital output, the SAR ADC circuit comprising a feedback digital-to-analog converter, DAC, circuit having a selectively actuated current source referenced to the reference current.

49. The circuit of claim 46, further comprising an amplifier circuit having an input coupled to the first node and an output coupled to power the word line driver circuit.

50. The circuit of claim 46, wherein the current source is controlled to generate an adjustment to the current, and further comprising a control circuit configured to: a control signal to be applied to the current source is generated in response to an applicable integrated circuit process corner of a transistor device of the memory cell to modulate a level of the current away from a nominal level.

51. The circuit of claim 50, wherein the applicable integrated circuit process corner is indicated by programming code stored in the control circuit.

52. The circuit of claim 51, wherein the control circuit comprises a look-up table LUT relating the programming code to a value of the control signal.

53. The circuit of claim 50, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to: causing temperature dependent tuning of the level of the current set in response to an applicable integrated circuit process corner.

54. The circuit of claim 53, wherein the control circuit comprises a look-up table LUT relating sensed integrated circuit temperature to a tuning level of the value of the control signal.

55. The circuit of claim 27, wherein each memory cell is implemented as a 6T SRAM cell.

56. An in-memory computing circuit comprising:

a memory array comprising a plurality of 6T memory SRAM cells arranged in a matrix having a plurality of rows and a plurality of columns, each row comprising a word line connected to the 6T SRAM cells of the row and each column comprising a first bit line connected to the 6T SRAM cells of the column;

A row controller circuit configured to actuate the plurality of word lines simultaneously by applying pulses to the word lines through the word line driver circuit in response to characteristic data for an in-memory computing operation;

a first differential amplifier having a first input coupled to the first bit line, a second input configured to receive a reference voltage, and an output; and

a first feedback resistor coupled between the output of the first differential amplifier and the first input, wherein the output is configured to generate a first output voltage, the first output voltage being a function of the reference voltage and a first read current on the first bit line;

wherein the reference voltage is at a level greater than a bit flip voltage of the 6T SRAM cell during the simultaneous actuation of the plurality of word lines for the in-memory computing operation.

57. The circuit of claim 56, wherein the first differential amplifier is used to clamp the voltage on the first bit line to the reference voltage.

58. The circuit of claim 56, wherein the column processing circuit further comprises an analog-to-digital converter ADC circuit configured to convert the first output voltage to a digital output.

59. The circuit of claim 56, wherein each column further comprises a second bit line connected to the 6T SRAM cells of the column, and wherein the column processing circuit further comprises a second read circuit coupled to each second bit line, wherein each second read circuit comprises:

a second differential amplifier having a first input coupled to the second bit line, a second input configured to receive the reference voltage, and an output; and

a second feedback resistor coupled between the output of the second differential amplifier and the first input, wherein the output is configured to generate a second output voltage that is a function of the reference voltage and a second read current on the second bit line.

60. The circuit of claim 59, wherein the column processing circuit further comprises an analog-to-digital converter ADC circuit configured to convert a difference between the first output voltage and the second output voltage to a digital output.

61. The circuit of claim 56, wherein the word line driver circuit is powered by an adaptive supply voltage, and the circuit further comprises:

62. The circuit of claim 61, wherein the voltage generator circuit comprises:

wherein the adaptive supply voltage is generated at the first node;

wherein the first transistor is a replica of a pass gate transistor within the 6T SRAM cell;

wherein the second transistor is a replica of a pull-down transistor within the 6T SRAM cell.

63. The circuit of claim 62, wherein:

64. The circuit of claim 63, wherein the column processing circuit further comprises a successive approximation register, SAR, analog-to-digital converter, ADC, circuit configured to convert the first output voltage to a digital output, the SAR ADC circuit comprising a feedback digital-to-analog converter, DAC, circuit having a selectively actuated current source referenced to the reference current.

65. The circuit of claim 63, wherein the column processing circuit further comprises a successive approximation register, SAR, analog-to-digital converter, ADC, circuit configured to convert the first output voltage to a digital output, the SAR ADC circuit comprising a feedback circuit comprising:

a digital-to-analog converter DAC circuit; and

a third differential amplifier having a first input coupled to the output of the DAC circuit, a second input configured to receive the reference voltage, and an output; and

A third feedback resistor is coupled between the output of the third differential amplifier and the first input, wherein the output is configured to generate a feedback voltage for comparison with the output voltage received by the SAR ADC circuit.

66. The circuit of claim 62, further comprising an amplifier circuit having an input coupled to the first node and an output coupled to power the word line driver circuit.

67. The circuit of claim 62, wherein the current source is controlled to generate an adjustment to the current, and further comprising a control circuit configured to: a control signal to be applied to the current source is generated in response to an applicable integrated circuit process corner of a transistor device of the 6T SRAM cell to modulate a level of the current away from a nominal level.

68. The circuit of claim 67, wherein the applicable integrated circuit process corners are indicated by programming code stored in the control circuit.

69. The circuit of claim 68, wherein the control circuit comprises a look-up table LUT that correlates the programming code to a value of the control signal.

70. The circuit of claim 67, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to: causing temperature dependent tuning of the level of the current set in response to an applicable integrated circuit process corner.

71. The circuit of claim 70, wherein the control circuit comprises a look-up table LUT relating sensed integrated circuit temperature to a tuning level of the value of the control signal.