CN117133336A

CN117133336A - Bit line read current mirror circuit for in-memory computing operations for simultaneous access to multiple rows of Static Random Access Memory (SRAM)

Info

Publication number: CN117133336A
Application number: CN202310591668.7A
Authority: CN
Inventors: K·J·多里; P·库玛; N·乔拉; H·拉瓦特; M·阿尤蒂亚瓦斯
Original assignee: STMicroelectronics International NV Switzerland
Current assignee: STMicroelectronics International NV Switzerland
Priority date: 2022-05-25
Filing date: 2023-05-24
Publication date: 2023-11-28

Abstract

An in-memory computing circuit includes a memory array having SRAM cells connected in rows by word lines and in columns by bit lines. The row controller circuit concurrently activates the word lines in parallel for in-memory computing operations. The column processing circuitry includes current mirror circuitry that mirrors the read current formed on each bit line in response to simultaneous actuation to generate a decision output for an in-memory computational operation. The configuration of the bias voltage and current mirror circuit for the word line driver suppresses the voltage on the bit line from falling below the bit flip voltage during execution of the computation operation in memory. The mirrored read current is integrated by an integrating capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

Description

Bit line read current mirror circuit for in-memory computing operations for simultaneous access to multiple rows of Static Random Access Memory (SRAM)

Cross Reference to Related Applications

The present application claims priority from U.S. patent provisional application No. 63/345,618, filed 5/25 at 2022, the disclosure of which is incorporated herein by reference.

Technical Field

Embodiments relate to an in-memory computation circuit utilizing a Static Random Access Memory (SRAM) array, and in particular to a read circuit that mirrors bit line read currents during simultaneous access of multiple rows of the SRAM array for in-memory computation operations.

Background

Referring to FIG. 1, FIG. 1 shows a schematic diagram of an in-memory computing circuit 10. The circuit 10 utilizes a Static Random Access Memory (SRAM) array 12, which SRAM array 12 is formed from standard 6T SRAM memory cells 14 arranged in a matrix format having N rows and M columns. Alternatively, standard 8T memory cells or SRAMs with similar functionality and topology may be used. Each memory cell 14 is programmed to store one bit of compute weights or kernel data for in-memory computing operations. In this context, an in-memory computing operation is understood to be a form of high-dimensional Matrix Vector Multiplication (MVM) that supports multi-bit weights stored in a plurality of bit cells of a memory. The set of bitcells (in the case of multi-bit weights) may be considered virtual synaptic elements. Each bit of the computation weight has a logical "1" or logical "0" value.

Each SRAM cell 14 includes a word line WL and a pair of complementary bit lines BLT and BLC. The 8T-type SRAM cell will additionally include a read word line RWL and a read bit line BLR. The cells 14 in a common row of the matrix are connected to each other by a common word line WL (and by a common read word line RWL in an 8T-type implementation). The cells 14 in a common column of the matrix are connected to each other by a common pair of complementary bit lines BLT and BLC (and by a common read bit line BLR in an 8T-type implementation). Each word line WL, RWL is driven by a word line driver circuit 16, which word line driver circuit 16 may be implemented as a CMOS driver circuit (e.g., a pair of series-connected p-channel and n-channel MOSFET transistors forming a logic inverter circuit). The word line signals applied to the word lines and driven by the word line driver circuit 16 are generated from the characteristic data input to the in-memory computing circuit 10, and are controlled by the row controller circuit 18. Column processing circuitry 20 senses analog current signals on respective pairs of complementary bit lines BLT and BLC (and/or read bit line BLR) of the M columns and generates decision outputs for in-memory computation operations from these analog current signals. Column processing circuitry 20 may be implemented to support the following: wherein the analog current signals on the columns are first processed individually and then the plurality of column outputs are recombined.

Although not explicitly shown in fig. 1, it is to be understood that the circuit 10 also includes conventional row decoding, column decoding, and read-write circuitry known to those skilled in the art for use in connection with writing bits of computational weights to and reading bits of computational weights from the SRAM cells 14 of the memory array 12.

Referring now to fig. 2, each memory cell 14 includes two cross-coupled CMOS inverters 22 and 24, each comprising a pair of p-channel and n-channel MOSFET transistors connected in series. The inputs and outputs of inverters 22 and 24 are coupled to form a latch circuit having a true data storage node QT and a complementary data storage node QC that stores the complementary logic states of the stored data bits. The cell 14 also includes two pass gate transistors 26 and 28, the gate terminals of the transistors 26 and 28 being driven by a word line WL. The source-drain path of transistor 26 is connected between true data storage node QT and a node associated with true bit line BLT. The source-drain path of transistor 28 is connected between the complementary data storage node QC and the node associated with the complementary bit line BLC. The source terminals of p-channel transistors 30 and 32 in each inverter 22 and 24 are coupled to receive a high supply voltage (e.g., vdd) at a high supply node, while the source terminals of n-channel transistors 34 and 36 in each inverter 22 and 24 are coupled to receive a low supply voltage (e.g., ground (Gnd) reference) at a low supply node. Although fig. 2 is specific to the use of a 6T cell, one skilled in the art recognizes that an 8T cell is similarly configured and will also include the following signal paths: the signal path is coupled to one of the storage nodes and includes a pass (channel gate) transistor that is coupled to the read bit line BLR and driven by a signal gate on the read word line RWL. The word line driver circuit 16 is also typically coupled to receive a high supply voltage (Vdd) at a high supply node and to reference a low supply voltage (Gnd) at a low supply node.

The row controller circuit 18 performs the following functions: selecting which of the word lines WL <0> to WL < N-1> are to be simultaneously accessed (or activated) in parallel during an in-memory computing operation, and controlling application of a pulse signal to the word lines according to characteristic data for the in-memory computing operation. Fig. 1 shows, by way of example only, that all N word lines are simultaneously actuated with pulsed word line signals in response to received feature data, it being understood that in-memory computing operations may instead utilize simultaneous actuation of less than all rows of an SRAM array. The analog signal on a given pair of complementary bit lines BLT and BLC (or on the read bit line RBL in an 8T implementation) depends on the logic state of the bits of the computational weight stored in the memory cells 14 of the corresponding column, as well as the width(s) of the pulsed word line signal applied to these memory cells 14.

The implementation shown in fig. 1 illustrates an example of a Pulse Width Modulated (PWM) form of an applied word line signal for an in-memory computing operation. The use of PWM or periodic pulse modulation (PTM) on the applied word line signal is a common technique for in-memory computing operations based on the linearity of vectors for multiply-accumulate (MAC) operations. The pulse word line signal format may be further developed to encode the pulse train to manage the block sparsity of the characteristic data of the in-memory computing operation. It is thus recognized that when multiple word lines are driven simultaneously, any one set of encoding schemes for the applied word line signals may be used. Furthermore, in a simpler implementation, it should be appreciated that all word line signals applied in a simultaneous actuation may instead have the same pulse width.

FIG. 3 is a timing diagram showing the simultaneous application of example pulse width modulated word line signals to multiple rows of memory cells 14 in the SRAM array 12 for a given in-memory computing operation, and the cell read current (I) in response to the logic states of bits due to the pulse width(s) of those word line signals and the computation weights stored in the memory cells 14 _R ) To form voltages Va, T and Va, C over time on a corresponding pair of complementary bit lines BLT and BLC, respectively. The representation of the voltage Va level shown is only one example. After the completion of the computation cycle of the intra-memory computation operation, the voltage Va level returns to the bit line precharge Vdd level. It will be noted that there is a risk that the voltage on at least one of the bit lines BLT and BLC may drop from the Vdd voltage to a level below the write margin, wherein an undesired data flip occurs with respect to the data bit value stored in one of the memory cells 14 of the column. For example, a logic "1" state stored in a column of cells 14 may be flipped to a logic "0" state. Such data flipping introduces data errors in the computational weights stored in the memory cells, thereby compromising the accuracy of the computational operations in subsequent memories.

The undesirable data flip that occurs due to excessive bit line voltage drop is primarily a result of concurrent access to the word lines in matrix vector multiplication mode during in-memory computing operations. This problem is different from the normal data flip of SRAM bitcells because of the Static Noise Margin (SNM) problem that occurs in serial bitcell accesses when the bit line approaches the level of the supply voltage Vdd. During serial access, normal data flip is caused by ground bounce of the data storage node QT or QC.

A known solution to the problem of serial bit cell access SNM failures is to reduce the word line voltage by a small amount, and this is typically achieved through the use of a shorting and bleeding path for the word line driver. However, parallel access to multiple word lines during in-memory computation operations requires aggressive WL reduction/modulation (RWLM)Techniques. Furthermore, a known solution to the above problem is to apply a fixed word line voltage reduction (e.g., apply a voltage V equal to Vdd/2 _WLUD ) To ensure the worst integrated circuit process corner. However, such word line under-drive (WLUD) solutions have the known disadvantage of cell read current (I _R ) This may have a negative impact on computational performance with a corresponding decrease. Furthermore, the use of a fixed word line under-drive voltage increases the variability of read current across the array, resulting in a loss of accuracy in the computational operations within the memory.

Another solution is to use a dedicated bit cell circuit design for each memory cell 14 that is less likely to suffer from unwanted data flipping during simultaneous (parallel) access of multiple rows for in-memory computing operations. One problem with this solution is the increase in the occupied circuit area of such a bit cell circuit. For some in-memory computing circuit applications, it is preferable to retain the advantages provided by using standard 6T SRAM cells (FIG. 2) or 8T SRAM cells or topologically similar bit cells in array 12.

Disclosure of Invention

In one embodiment, an in-memory computing circuit includes: a memory array comprising a plurality of Static Random Access Memory (SRAM) cells arranged in a matrix having a plurality of rows and a plurality of columns, each row comprising a word line connected to the SRAM cells of the row and each column comprising a first bit line connected to the SRAM cells of the column; a word line driver circuit for each row having an output connected to drive the word line of the row, wherein the word line driver circuit is powered by an adaptive supply voltage that depends on integrated circuit process and/or temperature conditions; a row controller circuit configured to actuate a plurality of word lines simultaneously for an in-memory computing operation by applying pulses to the word lines through the word line driver circuit; and column processing circuitry including first read circuitry coupled to each first bit line.

Each first reading circuit includes: a first current mirror circuit configured to mirror the first read current on the first bit line to generate a first mirrored read current; and a first integrating capacitor configured to integrate the first mirrored read current to generate a first output voltage. The configuration of the adaptive supply voltage and the first current mirror circuit suppresses the voltage on the first bit line from dropping below the bit flip voltage during simultaneous actuation of the plurality of word lines for a computational operation within the memory.

In one embodiment, an in-memory computing circuit includes: a memory array comprising a plurality of Static Random Access Memory (SRAM) cells arranged in a matrix having a plurality of rows and first and second columns, each row comprising a word line connected to an SRAM cell of the row, and each of the first and second columns comprising a first bit line connected to an SRAM cell of the column; a word line driver circuit for each row having an output connected to drive the word line of the row, wherein the word line driver circuit is powered by an adaptive supply voltage that depends on integrated circuit process and/or temperature conditions; a row controller circuit configured to actuate a plurality of word lines simultaneously for an in-memory computing operation by applying pulses to the word lines through the word line driver circuit; a column processing circuit.

The column processing circuit includes: a first read circuit having a first current mirror ratio coupled to the first bit line of the first column, the first read circuit including a first current mirror circuit configured to mirror the first read current on the first bit line of the first column to generate a first mirrored read current; wherein the configuration of the adaptive supply voltage and the first current mirror circuit inhibits the voltage on the first bit line of the first column from falling below the bit flip voltage during simultaneous actuation of the plurality of word lines for a computational operation in memory; a second read circuit having a second current mirror ratio coupled to the first bit line of the second column, the second read circuit including a second current mirror circuit configured to mirror the second read current on the first bit line of the second column to generate a second mirrored read current; wherein the configuration of the adaptive supply voltage and the second current mirror circuit inhibits the voltage on the first bit line of the second column from falling below the bit flip voltage during simultaneous actuation of the plurality of word lines for the in-memory computing operation; and a first integrating capacitor configured to integrate a sum of the first and second mirrored read currents to generate a first output voltage.

Drawings

For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings in which:

FIG. 1 is a schematic diagram of an in-memory computing circuit;

FIG. 2 is a circuit diagram of a standard 6T Static Random Access Memory (SRAM) cell used by the memory array of the in-memory computing circuit shown in FIG. 1;

FIG. 3 is a timing diagram illustrating an in-memory computing operation;

FIGS. 4A and 4B are circuit diagrams of a bit line read circuit;

FIG. 5 is a circuit diagram of a differential signaling implementation of a bit line read circuit;

FIG. 6 is a circuit diagram of a single-ended signaling implementation of a bit line read circuit;

FIG. 7 is a circuit diagram of an implementation of a bit line read circuit supporting multi-bit weight data;

FIG. 8 is a circuit diagram of a differential signaling implementation of a bit line read circuit supporting multi-bit weight data;

FIG. 9 is a circuit diagram of an implementation of a bit line read circuit supporting multi-bit weight data;

FIGS. 10-11 are circuit diagrams of bias voltage generators; and

fig. 12 shows a flow chart of the operation of the circuit shown in fig. 11.

Detailed Description

Referring now to fig. 4A, fig. 4A shows a circuit diagram of a bit line read circuit 100 for use within column processing circuit 20. The bit lines BL of a given column of memory cells 14 in array 12 are coupled, preferably directly connected to the gate and drain terminals of p-channel MOS transistor M1. The bit line BL may, for example, comprise any one of a complementary bit line BLT, BLC or a read bit line BLR for a column of memory. The source terminal of transistor M1 is coupled, preferably directly connected, to the supply voltage Vdd node. The bit line BL is further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor M2. The source terminal of transistor M2 is coupled to the supply voltage Vdd node through switch S1. The open/close state of the switch S1 is controlled by the logic state of the integration signal INT. The drain terminal of transistor M2 is coupled, preferably directly connected, to intermediate node 102. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102 and the second terminal is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. Intermediate node 102 is further coupled to a reference voltage node through switch S2. The open/close state of the switch S2 is controlled by the logic state of the reset signal RST.

The switches S1, S2 may each be implemented, for example, using MOS transistors controlled by an appropriate one of the control signals RST and INT.

In an alternative embodiment, switch S1 may be located between the drain of transistor M2 and intermediate node 102, as shown in FIG. 4B. In either case, transistors M1 and M2 together with switch S1 form a selectively actuatable (in response to control signal INT) current mirror circuit configured to read current I from bit line BL during a memory computational operation when multiple ones of word lines WL are simultaneously actuated with word line signal pulses that depend on the received characteristic data _R Generating mirrored read current I _Rm The bit line BL reads the current I _R Is the cell current I through the memory cells 14 in the column _CELL Formed by the sum of (a) and (b). Mirror read current I _Rm And then applied to charge the integrating capacitor Cint and generate the output voltage Vout.

It will be appreciated that for each column of memory, one bit line read circuit 100 is provided in the column processing circuit 20.

The intermediate node 102 is further coupled to an input of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the analog voltage Vout across the integrating capacitor Cint into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each column. Alternatively, one ADC circuit 104 may be shared by multiple columns through a time division multiplexing operation. The digital signals MACout from each column may be output from the column processing circuit 20 as decisions (decisions) or combined with each other to generate decisions.

The operation of the bit line read circuit 100 is as follows: at the beginning of a computation cycle of a computation operation within the memory, the reset signal RST is asserted (also referred to as "activated") to close switch S2 and discharge the integrating capacitor Cint. Word line signals are then applied simultaneously to rows of memory cells 14 in the SRAM array 12 for in-memory computing operations, depending on the received characteristic data, and the read current I _R Formed on the bit line BL. Read current I _R Is the current I sunk to ground by the memory cells 14 of the column participating in the in-memory computation operation _CELL Is a function of the sum of (a) and (b). The integration signal INT is asserted to close switch S1 and begin the integration period. Transistors M1 and M2 function as a current mirror circuit and mirror the read current I _Rm Is applied to charge the integrating capacitor Cint to generate a voltage vout=i _Rm * t/C, where t is the duration of the integration period (when switch S1 is closed) and C is the capacitance of the integration capacitor Cint. When the integration period expires, the integration signal INT is de-asserted to open switch S1. Then, the voltage Vout across the integrating capacitor Cint is converted into a digital signal MACout by the ADC circuit 104.

Importantly, the size of transistor M1 in the selectively actuatable current mirror circuit is appropriately selected to handle the read current I on bit line BL _R So that the bit line voltage does not drop below the write margin during a read operation with the risk of undesirable data flipping at one (or more) of the simultaneously accessed memory cells 14. The transistor M1 thus serves to suppress the voltage on the bit line from falling below the bit flip voltage. The design goal here is to size transistor M1 to support maximum current sourcing to the bit line, where all rows of the array are selected (i.e., the word line is activated) during the in-memory computing operation without risk of the bit line voltage level falling below the write margin. Those skilled in the art will know how to determine the transistor size needed to meet the design goals.

Referring now to FIG. 5, FIG. 5 showsA circuit diagram of a differential signaling implementation of the bit line read circuit 100 is shown. Like reference numerals refer to the same or similar components. In this implementation, the currents on the true bit line BLT and the complementary bit line BLC are handled by the bit line read circuit 100. The use of the suffix "_t" designates a component associated with the processing of the read current on the true bit line BLT, and the use of the suffix "_c" designates a component associated with the processing of the read current on the complementary bit line BLC. Thus, the bit line read circuit 100 includes a circuit for handling the read current I on the true bit line BLT _{R_T} True read circuit 100_t of (a), and for handling read current I on complementary bit line BLC _{R_C} Is provided for the complementary read circuit 100_c. The circuit configuration of each of the read circuits 100_t, 100_c is the same as that shown in fig. 4A, and each circuit operates in the above-described manner. The differential signaling implementation in fig. 5 differs from the implementations of fig. 4A-4B in that the differential integrated voltage vout_ T, vout _c is generated by the bit line read circuits 100_t, 100_c and the ADC circuit 104 operates to convert the difference between the voltages vout_ T, vout _c to obtain the digital signal MACout.

Referring now to true read circuit 100_t, the true bit line BLT of a given column of memory cells 14 in array 12 is coupled, preferably directly connected, to the gate and drain terminals of p-channel MOS transistor m1_t. The source terminal of transistor m1_t is coupled, preferably directly connected, to the supply voltage Vdd node. The true bit line BLT is further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor m2_t. The source terminal of transistor m2_t is coupled to the supply voltage Vdd node through switch s1_t. The open/close state of the switch s1_t is controlled by the logic state of the integration signal INT. The drain terminal of transistor m2_t is coupled, preferably directly connected, to intermediate node 102_t. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102_t, and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. The intermediate node 102_t is further coupled to a reference voltage node through a switch s2_t. The open/close state of the switch s2_t is controlled by the logic state of the reset signal RST.

For the complementary read circuit 100_c, the complementary bit line BLC of a given column of memory cells 14 in the array 12 is coupled, preferably directly connected, to the gate and drain terminals of the p-channel MOS transistor m1_c. The source terminal of transistor m1_c is coupled, preferably directly connected, to the supply voltage Vdd node. The complementary bit line BLC is further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor m2_c. The source terminal of transistor m2_c is coupled to the supply voltage Vdd node through switch s1_c. The open/close state of the switch s1_c is controlled by the logic state of the integration signal INT. The drain terminal of transistor m2_c is coupled, preferably directly connected, to intermediate node 102_c. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102_c, and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. The intermediate node 102_c is further coupled to a reference voltage node through a switch s2_c. The open/close state of the switch s2_c is controlled by the logic state of the reset signal RST.

The switches s1_ T, S1_ C, S2 _2_ T, S2_c can each be implemented, for example, using MOS transistors controlled by an appropriate one of the control signals RST and INT.

It will be appreciated that each of the read circuits 100_t, 100_c in fig. 5 may alternatively be implemented in the manner shown in fig. 4B, and that in this configuration the switch s1_ T, S1_c would instead be located between the drain of the transistor m2_ T, M2_c and the intermediate nodes 102_t, 102_c, respectively. In either case, transistors M1_T and M2_T and switch S1_T, transistors M1_C and M2_C and switch S1_C form a selectively actuatable (in response to control signal INT) current mirror circuit, respectively, configured to read current I from bit line BL _R Generating mirrored read current I _Rm The bit line BL reads the current I _R Is the cell current I through the memory cells 14 in the column _CELL Formed by the sum of (a) and (b). Mirror read current I _Rm And then applied to charge the integrating capacitor Cint and generate the output voltage Vout.

It should be understood that for each column of the memory, a pair of bit line read circuits 100_t, 100_c are provided in the column processing circuit 20.

The intermediate nodes 102_t, 102_c are further coupled to differential inputs of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the difference between the analog voltages vout_ T, vout _c into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each column. Alternatively, one ADC circuit 104 may be shared by multiple columns through a time division multiplexing operation. The digital signals MACout from each column may be output from the column processing circuit 20 as decisions or combined with each other to generate decisions.

The operation of the bit line read circuit 100 is as follows: at the beginning of a computation cycle of the intra-memory computation operation, the reset signal RST is asserted to close the switch s2_ T, S2_c and discharge the integrating capacitor Cint. Word line signals are then applied simultaneously to rows of memory cells 14 in the SRAM array 12 for in-memory computing operations, depending on the received characteristic data, and the current I is actually read _{R_T} Complementary read current I _{R_C} Formed on complementary bit lines BLT, BLC. Read current I _{R_T} 、I _{R_C} Is the current I sunk to ground by the memory cells 14 of the column participating in the in-memory computation operation _CELL Is a function of the sum of (a) and (b). The integration signal INT is asserted to close the switch s1_ T, S1_c and begin the integration period. Transistors m1_t and m2_ T, M1_c and m1_c are used as current mirror circuits and correspond to mirror read current I _{Rm_T} 、I _{Rm_C} Is applied to charge an integrating capacitor Cint to generate a voltage as I _Rm * Voltage vout_ T, vout _c as a function of T/C, where T is the duration of the integration period (when switches s1_t and s1_c are closed), and C is the capacitance of the integration capacitor Cint. When the integration period expires, the integration signal INT is de-asserted to open the switch s1_ T, S1_c. Then, the difference between the voltages vout_ T, vout _c across the integrating capacitor Cint is converted into a digital signal MACout by the ADC circuit 104.

Importantly, the size of transistor M1_ T, M1_C in the selectively actuatable current mirror circuit is appropriately selected to handle the read current I on bit lines BLT, BLC _{R_T} 、I _{R_C} So that the bit line voltage does not drop below the write margin during the read operationThe risk of undesired data flipping at one (or more) of the simultaneously accessed memory cells 14. Transistors m1_t and m1_c are thus used to suppress the voltage on the bit line from falling below the bit flip voltage. The design goal here is to set the size of transistors m1_t and m1_c to support maximum current sourcing to bit lines BLT and BLC, respectively, where all rows of the array are selected (i.e., the word lines are activated) during the in-memory computing operation without the risk of the bit line voltage level falling below the write margin. Those skilled in the art will know how to determine the transistor size needed to meet the design goals.

Referring now to fig. 6, fig. 6 shows a circuit diagram of a single-ended signaling implementation of the bit line read circuit 100. Like reference numerals refer to the same or similar components. In this implementation, the currents on the true bit line BLT and the complementary bit line BLC are handled by the bit line read circuit 100. The use of the suffix "_t" designates a component associated with the processing of the read current on the true bit line BLT, and the use of the suffix "_c" designates a component associated with the processing of the read current on the complementary bit line BLC. Thus, the bit line read circuit 100 includes a circuit for handling the read current I on the true bit line BLT _{R_T} True read circuit 100_t for processing read current I on complementary bit line BLC _{R_C} Is provided for the complementary read circuit 100_c. The main difference between the single-ended signaling implementation in fig. 6 and the differential signaling implementation in fig. 5 is that a single output voltage Vout is read by a mirrored read current I _{Rm_T} 、I _{Rm_C} The integration of the difference between the two results in the output voltage Vout being subsequently converted by the ADC circuit 104 to generate a digital signal MACout.

Referring now to true read circuit 100_t, the true bit line BLT of a given column of memory cells 14 in array 12 is coupled, preferably directly connected, to the gate and drain terminals of p-channel MOS transistor m1_t. The source terminal of transistor m1_t is coupled, preferably directly connected, to the supply voltage Vdd node. The true bit line BLT is further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor m2_t. The source terminal of transistor m2_t is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor m2_t is coupled, preferably directly connected, to current summing node 103.

For the complementary read circuit 100_c, the complementary bit line BLC of a given column of memory cells 14 in the array 12 is coupled, preferably directly connected, to the gate and drain terminals of the p-channel MOS transistor m1_c. The source terminal of transistor m1_c is coupled, preferably directly connected, to the supply voltage Vdd node. The complementary bit line BLC is further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor m2_c. The source terminal of transistor m2_c is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor m2_c is coupled, preferably directly connected, to the current input node 105 of the n-channel current mirror circuit 107 formed by the input transistor M3 and the output transistor M4 sharing a common gate terminal and a common source terminal, wherein the drain and gate of the input transistor M3 are directly connected at the input node 105. The output of the current mirror circuit 107 at the drain of transistor M4 is coupled, preferably directly, to the current summing node 103.

At the current summing node 103, the current I is read from the mirror image of the true read circuit 100_T _{Rm_T} The mirrored read current I from the complementary read circuit 100_C is subtracted _{Rm_C} To generate the resulting output read current I _Rout 。

Output read current I from current summing node 103 _Rout Coupled to the intermediate node 102 via a switch S1. The open/close state of the switch S1 is controlled by the logic state of the integration signal INT. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102 and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. Intermediate node 102 is further coupled to a reference voltage node through switch S2. The open/close state of the switch S2 is controlled by the logic state of the reset signal RST.

The intermediate node 102 is further coupled to an input of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the analog voltage Vout across the integrating capacitor Cint into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each column. Alternatively, one ADC circuit 104 may be shared by multiple columns through a time division multiplexing operation. The digital signals MACout from each column may be output from the column processing circuit 20 as decisions or combined with each other to generate decisions.

The operation of the bit line read circuit 100 is as follows: at the beginning of a computation cycle of the intra-memory computation operation, the reset signal RST is asserted to close switch S2 and discharge the integrating capacitor Cint. Simultaneously applying word line signals to rows of memory cells 14 in the SRAM array 12 for in-memory computing operations in response to received feature data, and true read current I _{R_T} And complementary read current I _{R_C} Formed on complementary bit lines BLT, BLC. Read current I _{R_T} 、I _{R_C} Is the current I sunk to ground by the memory cells 14 of the column participating in the in-memory computation operation _CELL Is a function of the sum of (a) and (b). The integration signal INT is asserted to close switch S1 and begin the integration period. Transistors m1_t and m2_ T, M1_c and m1_c, and M3 and M4 serve as current mirror circuits, and mirror the read current I correspondingly _{Rm_T} 、I _{Rm_C} Is applied to the current summing node 103. Reading current I from mirror image _{Rm_T} Subtracting the mirrored read current I _{Rm_C} And applying the resulting output read current I _Rout To charge the integrating capacitor Cint and generate as I _Rout * the output voltage Vout as a function of t/C, where t is the duration of the integration period (when switch S1 is closed) and C is the capacitance of the integration capacitor Cint. When the integration period expires, the integration signal INT is de-asserted to open switch S1. Then, the voltage Vout across the integrating capacitor Cint is converted into a digital signal MACout by the ADC circuit 104.

Importantly, the size of transistor M1_ T, M1_C in the selectively actuatable current mirror circuit is appropriately selected to handle the bit lines BLT, BLCRead current I _{R_T} 、I _{R_C} So that the bit line voltage does not drop below the write margin during a read operation with the risk of undesirable data flipping at one (or more) of the simultaneously accessed memory cells 14. Transistors m1_t and m1_c are thus used to suppress the voltage on the bit line from falling below the bit flip voltage. The design goal here is to size transistors m1_t and m1_c to support maximum current sourcing to bit lines BLT and BLC, respectively, where all rows of the array are selected (i.e., the word lines are activated) during the in-memory computing operation without risk of the bit line voltage level falling below the write margin. Those skilled in the art will know how to determine the transistor size needed to meet the design goals.

The foregoing implementation illustrates the operation of an in-memory computation that is processing single bit weight data. However, it should be understood that all of these implementations are equally applicable when processing multi-bit weight data. Referring to FIG. 7 (which generally corresponds to the implementation of FIG. 4B), an implementation is shown in which the weight data includes two bits stored in two columns of memory cells 14a and 14B associated with two bit lines BL <0> and BL <1> in the array. In this example, the less significant bits (lsb) of the weight data are stored in memory cell 14a, while the more significant bits (msb) of the weight data are stored in memory cell 14 b.

Bit lines BL of the less significant bit columns of memory cells 14 in array 12<0>Coupled, preferably directly connected, to the gate and drain terminals of the p-channel MOS transistor M1. Bit line BL<0>May for example comprise any one of the complementary bit lines BLT, BLC or read bit line BLR for a column of memory. The source terminal of transistor M1 is coupled, preferably directly connected, to the supply voltage Vdd node. Bit line BL<0>Further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor M2. The source terminal of transistor M2 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M2 is coupled, preferably directly connected, to current summing node 103. Transistors M1 and M2 form a current mirror circuit, and transistors M1, M2 are sized to bit line current I _Rlsb And mirror the bit line current I _Rmlsb Providing a current mirror ratio of 1:1 (i.e., I _Rmlsb ＝I _Rlsb )。

Bit line BL for the more significant bit column of memory cells 14 in array 12<1>Coupled, preferably directly connected, to the gate and drain terminals of the p-channel MOS transistor M3. Bit line BL<1>May for example comprise any one of the complementary bit lines BLT, BLC or read bit line BLR for a column of memory. The source terminal of transistor M3 is coupled, preferably directly connected, to the supply voltage Vdd node. Bit line BL <1>Further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor M4. The source terminal of transistor M4 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M4 is coupled, preferably directly connected, to current summing node 103. Transistors M3 and M4 form a current mirror circuit, and transistors M3, M4 are sized to bit line current I _Rmsb And mirror the bit line current I _Rmmsb Providing a current mirror ratio of 1:2 (i.e., I _Rmmsb ＝2*I _Rmsb )。

More generally, there is a weighted relationship between the current mirror ratios of the current mirror connected transistors on multiple columns of memory cells storing multi-bit weight data. Thus, if additional bit lines BL <2> are involved, the current mirror connected transistors of the column may have a current mirror ratio of 1:4 according to a weighted relationship.

At the current summing node 103, the read current I is mirrored _Rmlsb And I _Rmmsb Are added together to generate the resulting output read current I _Rout . It will be noted that the current summation is implemented with binary weights due to the respective weighted current mirror ratios of the current mirror circuits.

Output read current I from current summing node 103 _Rout Coupled to the intermediate node 102 via a switch S1. The open/close state of the switch S1 is controlled by the logic state of the integration signal INT. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102, and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected To a reference voltage (e.g., ground) node. Intermediate node 102 is further coupled to a reference voltage node through switch S2. The open/close state of the switch S2 is controlled by the logic state of the reset signal RST.

The intermediate node 102 is further coupled to an input of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the analog voltage Vout across the integrating capacitor Cint into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each set of columns storing multi-bit weight data. Alternatively, one ADC circuit 104 may be shared by groups of columns through a time division multiplexing operation. The digital signals MACout from each set of columns may be output from the column processing circuit 20 as decisions or combined with each other to generate decisions.

The operation of the bit line read circuit 100 is as follows: at the beginning of a computation cycle of the intra-memory computation operation, the reset signal RST is asserted to close switch S2 and discharge the integrating capacitor Cint. Word line signals are then simultaneously applied to rows of memory cells 14 in the SRAM array 12 for in-memory computing operations, depending on the received characteristic data, and a lower significant bit read current I _Rlsb And a higher significant bit read current I _Rmsb Respectively bit lines BL<0>And BL (BL)<1>And is formed thereon. Read current I _Rlsb 、I _Rmsb Is the current I sunk to ground by the memory cells 14 of the column participating in the in-memory computation operation _CELL Is a function of the sum of (a) and (b). The integration signal INT is asserted to close switch S1 and begin the integration period. Transistors M1 and M2, M3 and M4 serve as current mirror circuits and correspond to mirror read current I _Rmlsb 、I _Rmmsb Is applied to the current summing node 103. Mirror read current I _Rmlsb 、I _Rmmsb Is added together and the resulting output read current I _Rout Is applied to charge an integrating capacitor Cint and is generated as I _Rout * the output voltage Vout as a function of t/C, where t is the duration of the integration period (when switch S1 closed), and C is the capacitance of the integrating capacitor Cint. When the integration period expires, the integration signal INT is de-asserted to open switch S1. Then, the voltage Vout across the integrating capacitor Cint is converted into a digital signal MACout by the ADC circuit 104.

With respect to the application of the implementation in processing multi-bit weight data, reference is now made to FIG. 8 (generally corresponding to the implementation of FIG. 5), which illustrates an implementation for processing weight data having two bits stored in the array in two columns of memory cells 14a and 14b associated with complementary bit lines BLT <0>, BLC <0>, and BLT <1>, BLC <1 >. In this example, the less significant bits (lsb) of the weight data are stored in memory cell 14a, while the more significant bits (msb) of the weight data are stored in memory cell 14 b.

The true bit line BLT of the lower significant bit column of memory cells 14 in array 12<0>Coupled, preferably directly connected, to the gate and drain terminals of the p-channel MOS transistor M1. The source terminal of transistor M1 is coupled, preferably directly connected, to the supply voltage Vdd node. Bit line BLT<0>Further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor M2. The source terminal of transistor M2 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M2 is coupled, preferably directly connected, to the true current summing node 103_t. Transistors M1 and M2 form a current mirror circuit, and transistors M1, M2 are sized to bit line current I _RlsbT And mirror the bit line current I _RmlsbT Providing a current mirror ratio of 1:1 (i.e., I _RmlsbT ＝I _RlsbT )。

The true bit line BLT of the more significant bit column of memory cells 14 in array 12<1>Coupled, preferably directly connected, to the gate and drain terminals of the p-channel MOS transistor M3. The source terminal of transistor M3 is coupled, preferably directly connected, to the supply voltage Vdd node. Bit line BLT<1>Further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor M4. The source terminal of transistor M4 is coupled, preferably directly connected, to the supply voltage Vdd node. Drain terminal coupling of transistor M4 Preferably directly to the true current summing node 103_ t. Transistors M3 and M4 form a current mirror circuit, and transistors M3, M4 are sized to bit line current I _RmsbT And mirror the bit line current I _RmssbT Providing a current mirror ratio of 1:2 (i.e., I _RmmsbT ＝2*I _RmsbT )。

More generally, there is a weighted relationship between the current mirror ratios of the current mirror connected transistors on multiple columns of memory cells storing multi-bit weight data. Thus, if additional bit lines BLT <2> are involved, the current mirror connected transistors of the column may have a current mirror ratio of 1:4, according to a weighted relationship.

At the current summing node 103_t, the read current I is mirrored _RmlsbT And I _RmmsbT Are added together to generate the resulting output true read current I _RoutT . It will be noted that the current summation is implemented with binary weights due to the weighted current mirror ratio of the current mirror circuit.

Output read current I from current summing node 103_T _RoutT Is coupled to the intermediate node 102_t through the switch s1_t. The open/close state of the switch s1_t is controlled by the logic state of the integration signal INT. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102_t, and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. The intermediate node 102_t is further coupled to a reference voltage node through a switch s2_t. The open/close state of the switch s2_t is controlled by the logic state of the reset signal RST.

The switches s1_ T, S2_t may each be implemented, for example, using MOS transistors controlled by an appropriate one of the control signals RST and INT.

Complementary bit line BLC of the lower significant bit column of memory cells 14 in array 12<0>Coupled, preferably directly connected, to the gate and drain terminals of the p-channel MOS transistor M5. The source terminal of transistor M5 is coupled, preferably directly connected, to the supply voltage Vdd node. Bit line BLC<0>Further coupled, preferably directly connected, to the gate of p-channel MOS transistor M6And a polar terminal. The source terminal of transistor M6 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M6 is coupled, preferably directly connected, to the complementary current summing node 103_c. Transistors M5 and M6 form a current mirror circuit, and transistors M5, M6 are sized to bit line current I _RlsbC And mirror the bit line current I _RmlsbC Providing a current mirror ratio of 1:1 (i.e., I _RmlsbC ＝I _RlsbC )。

Complementary bit line BLC of the more significant bit column of memory cells 14 in array 12<1>Coupled, preferably directly connected, to the gate and drain terminals of the p-channel MOS transistor M7. The source terminal of transistor M7 is coupled, preferably directly connected, to the supply voltage Vdd node. Bit line BLC <1>Further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor M8. The source terminal of transistor M8 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M8 is coupled, preferably directly connected, to the complementary current summing node 103_c. Transistors M7 and M8 form a current mirror circuit, and transistors M7, M8 are sized to bit line current I _RmsbC And mirror the bit line current I _RmssbC Providing a current mirror ratio of 1:2 (i.e., I _RmmsbC ＝2*I _RmsbC )。

More generally, there is a weighted relationship between the current mirror ratios of the current mirror connected transistors on multiple columns of memory cells storing multi-bit weight data. Thus, if additional bit lines BLC <2> are involved, the current mirror connected transistors of the column may have a current mirror ratio of 1:4, according to a weighted relationship.

At the current summing node 103_C, the read current I is mirrored _RmlsbC And I _RmmsbC Are added together to generate the resulting output complementary read current I _RoutC . It will be noted that the current summation is implemented with binary weights due to the weighted current mirror ratio of the current mirror circuit.

Output read current I from current summing node 103_C _RoutC Is coupled to the intermediate node 102_c through the switch s1_c. Opening of switch S1_C The closed state is controlled by the logic state of the integrated signal INT. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102_c, and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. The intermediate node 102_c is further coupled to a reference voltage node through a switch s2_c. The open/close state of the switch s2_c is controlled by the logic state of the reset signal RST.

The switches s1_ C, S2_c may each be implemented, for example, using a MOS transistor that is gate-controlled by an appropriate one of the control signals RST and INT.

The intermediate nodes 102_t, 102_c are further coupled to differential inputs of an analog-to-digital converter (ADC) circuit 104, which ADC circuit 104 operates to convert the difference between the analog voltages vout_ T, vout _c into a digital signal MACout indicative of the result of the MAC operation. One ADC circuit 104 may be provided for each set of columns of multi-bit weight data. Alternatively, one ADC circuit 104 may be shared by multiple sets of columns through a time division multiplexing operation. The digital signals MACout from each set of columns may be output from the column processing circuit 20 as decisions or combined with each other to generate decisions.

The operation of the bit line read circuit 100 is as follows: at the beginning of a computation cycle of the intra-memory computation operation, the reset signal RST is asserted to close the switch s2_ T, S2_c and discharge the integrating capacitor Cint. Word line signals are then simultaneously applied to rows of memory cells 14 in the SRAM array 12 for in-memory computing operations, depending on the received characteristic data, and the current I is actually read _RlsbT And I _RmsbT Formed on the true bit line BLT and complementary to the read current I _RlsbC And I _RmsbC Formed on the complementary bit line BLC. The magnitude of these read currents is the current I sunk to ground by the memory cells 14 of the column involved in the in-memory computation operation _CELL Is a function of the sum of (a) and (b). The integration signal INT is asserted to close the switch s1_ T, S1_c and begin the integration period. True read current I _RlsbT And I _RmsbT Mirrored to generate true mirror read current I _RmlsbT And I _RmmsbT The true mirror image read current I _RmlsbT And I _RmmsbT Summed at true current summing node 103_T to generate an output true read current I _RoutT . The current is applied to charge an integrating capacitor Cint to generate a current as I _RoutT * Voltage vout_t as a function of T/C, where T is the duration of the integration period (when switch s1_t is closed), and C is the capacitance of integration capacitor Cint. Complementary read current I _RlsbC And I _RmsbC Mirrored to generate complementary mirrored read current I _RmlsbC And I _RmmsbC The complementary mirror image read current I _RmlsbC And I _RmmsbC Is summed at complementary current summing node 103_c to generate an output complementary read current I _RoutC . The current is applied to charge an integrating capacitor Cint to generate a current as I _RoutC * Voltage vout_c as a function of t/C, where t is the duration of the integration period (when switch s1_c is closed), and C is the capacitance of integration capacitor Cint. When the integration period expires, the integration signal INT is de-asserted to open the switch s1_ T, S1_c. Then, the difference between the voltages vout_ T, vout _c across the integrating capacitor Cint is converted into a digital signal MACout by the ADC circuit 104.

Still further, with respect to the application of the implementation in processing multi-bit weight data, reference is now made to FIG. 9 (generally corresponding to the implementation of FIG. 6), which shows an implementation for processing weight data having two bits stored in the array in two columns of memory cells 14a and 14b associated with complementary bit lines BLT <0>, BLC <0>, and BLT <1>, BLC <1 >. In this example, the less significant bits (lsb) of the weight data are stored in memory cell 14a, while the more significant bits (msb) of the weight data are stored in memory cell 14 b.

The true bit line BLT of the lower significant bit column of memory cells 14 in array 12<0>Coupled, preferably directly connected, to the gate and drain terminals of the p-channel MOS transistor M1. The source terminal of transistor M1 is coupled, preferably directly connected, to the supply voltage Vdd node. Bit line BLT<0>Further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor M2. The source terminal of transistor M2 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M2 is coupled, preferably directly connected, to current summing node 103. Transistors M1 and M2 form a current mirror circuit, and transistors M1, M2 are sized to bit line current I _RlsbT And mirror the bit line current I _RmlsbT Providing a current mirror ratio of 1:1 (i.e., I _RmlsbT ＝I _RlsbT )。

The true bit line BLT of the more significant bit column of memory cells 14 in array 12<1>Coupled, preferably directly connected, to the gate and drain terminals of the p-channel MOS transistor M3. The source terminal of transistor M3 is coupled, preferably directly connected, to the supply voltage Vdd node. Bit line BLT<1>Further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor M4. The source terminal of transistor M4 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M4 is coupled, preferably directly connected, to current summing node 103. Transistors M3 and M4 form a current mirror circuit, and transistors M3, M4 are sized to bit line current I _RmsbT And mirror the bit line current I _RmssbT Providing a current mirror ratio of 1:2 (i.e., I _RmmsbT ＝2*I _RmsbT )。

Complementary bit line BLC of the lower significant bit column of memory cells 14 in array 12 <0>Coupled, preferably directly connected, to the gate and drain terminals of the p-channel MOS transistor M5. The source terminal of transistor M5 is coupled, preferably directly connected, to the supply voltage Vdd node. Bit line BLC<0>Further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor M6. The source terminal of transistor M6 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M6 is coupled, preferably directly connected, to the input of the n-channel MOS current mirror circuit formed by transistors Ma and Mb. n-channelThe output of the MOS current mirror circuit is coupled, preferably directly, to a current summing node 103. Transistors M5 and M6 form a current mirror circuit, and transistors M5, M6 are sized to bit line current I _RlsbC And mirror the bit line current I _RmlsbC Providing a current mirror ratio of 1:1 (i.e., I _RmlsbC ＝I _RlsbC )。

Complementary bit line BLC of the more significant bit column of memory cells 14 in array 12<1>Coupled, preferably directly connected, to the gate and drain terminals of the p-channel MOS transistor M7. The source terminal of transistor M7 is coupled, preferably directly connected, to the supply voltage Vdd node. Bit line BLC<1>Further coupled, preferably directly connected, to the gate terminal of the p-channel MOS transistor M8. The source terminal of transistor M8 is coupled, preferably directly connected, to the supply voltage Vdd node. The drain terminal of transistor M8 is coupled, preferably directly connected, to the input of the n-channel MOS current mirror circuit formed by transistors Mc and Md. The output of the n-channel MOS current mirror circuit is coupled, preferably directly, to a current summing node 103. Transistors M7 and M8 form a current mirror circuit, and transistors M7, M8 are sized to bit line current I _RmsbC And mirror the bit line current I _RmmsbC Providing a current mirror ratio of 1:2 (i.e., I _RmmsbC ＝2*I _RmsbCT )。

At the current summing node 103, the current I is actually read from the mirror _RmlsbT And I _RmmsbT Subtracting the mirrored complementary read current I from the sum of (a) _RmlsbC And I _RmmsbC To generate a resulting output read current I _Rout (i.e., I _Rout ＝I _RmlsbT +I _RmmsbT -I _RmlsbC -I _RmmsbC )。

Output reading from current summing node 103Current I _Rout Coupled to the intermediate node 102 via a switch S1. The open/close state of the switch S1 is controlled by the logic state of the integration signal INT. The first terminal of the integrating capacitor Cint is coupled, preferably directly connected, to the intermediate node 102 and the second terminal of the integrating capacitor Cint is coupled, preferably directly connected, to a reference voltage (e.g., ground) node. Intermediate node 102 is further coupled to a reference voltage node through switch S2. The open/close state of the switch S2 is controlled by the logic state of the reset signal RST.

The operation of the bit line read circuit 100 is as follows: at the beginning of a computation cycle of the intra-memory computation operation, the reset signal RST is asserted to close switch S2 and discharge the integrating capacitor Cint. Word line signals are then simultaneously applied to rows of memory cells 14 in the SRAM array 12 for in-memory computing operations, depending on the received characteristic data, and the current I is actually read _RlsbT And I _RmsbT Formed on the true bit line BLT and complementary to the read current I _RlsbC And I _RmsbC Formed on the complementary bit line BLC. The magnitude of these read currents is the current I sunk to ground by the memory cells 14 of the column involved in the in-memory computation operation _CELL Is a function of the sum of (a) and (b). The integration signal INT is asserted to close switch S1 and begin the integration period. True read current I _RlsbT And I _RmsbT Mirrored to generate true mirror read current I summed at current summing node 103 _RmlsbT And I _RmmsbT . Complementary read current I _RlsbC And I _RmsbC Mirrored to generate a complementary mirrored read current I subtracted from current summing node 103 _RmlsbC And I _RmmsbC . The result is the generation of an output read current I _Rout . The current is applied to charge an integrating capacitor Cint to generate a current as I _Rout * the voltage Vout as a function of t/C, where t is the duration of the integration period (when switch S1 is closed) and C is the capacitance of the integration capacitor Cint. When the integration period expires, the integration signal INT is de-asserted toSwitch S1 is opened. Then, the voltage Vout across the integrating capacitor Cint is converted into a digital signal MACout by the ADC circuit 104.

The implementations in fig. 4A, 4B, 5, 6, 7, 8, and 9 further utilize the adaptive supply voltage Vbias for word line driving. The supply voltage of the word line driver circuit 16 is not fixedly equal to Vdd (i.e., it is different from the array supply voltage) or is set to have a fixed word line undervoltage level (e.g., V _WLUD =vdd/2). Instead, the supply voltage of the word line driver circuit 16 is an adaptive supply voltage Vbias that is modulated according to integrated circuit process conditions. The voltage level of the adaptive supply voltage Vbias is less than the supply voltage Vdd and is generated by the voltage generator circuit 212, as shown in fig. 10, where the voltage level is proportional (by a factor of n) to the reference current Iref level. The reference current Iref has a magnitude defined by a fast n-channel MOS process lot (process lot). For example, the reference current Iref for a given cell is a current with a multi-row access write margin (MRAWM) of zero while allowing the bit line to swing entirely rail-to-rail at the worst process corner. The n-value of the scaling factor is set by design and is based on the desired variability of the adaptive supply voltage Vbias level (so that n copies will effectively minimize the change in Vbias due to local variations).

The modulation of the supply voltage of the word line driver circuit 16 depends on integrated circuit process conditions, in combination with the configuration of the current mirror circuit of the read circuit coupled to each bit line, to inhibit the voltage on the bit line from falling below the bit flip voltage during simultaneous actuation of multiple word lines in a computational operation within the memory. Read current I of memory cell 14 by modulated supply voltage _CELL Control is performed and the voltage on the bit line is correspondingly controlled with the size setting of the current source transistor in the current mirror circuit to prevent the voltage on the bit line from decreasing below the write margin during simultaneous word line actuation. Advantageously, this configuration enables better linearity in the current mirror and supports the use of current mirror circuit configurations that do not require a cascode structure.

The voltage generator circuit 212 includes a current source 214, the current source 214 being powered by a supply voltage Vdd and generating an output current Iout at a node 216, wherein the current source is connected in series with a first n-channel MOS transistor 218 and a second n-channel transistor 220 connected in series. The output current Iout is applied (i.e., forced) to a circuit having transistors 218 and 220 to generate a bias voltage Vbias, where transistors 218 and 220 effectively replicate the channel gate and pull-down transistor configuration that delineates the read condition of memory cell 14. First n-channel MOS transistor 218 has a drain coupled (preferably directly connected) to node 216 and a source coupled (preferably directly connected) to node 222. The gate of the first n-channel MOS transistor 218 is coupled (preferably directly connected) to the drain at node 216, thereby configuring the transistor 218 as a diode-connected device. The first n-channel MOS transistor 218 is a scaled copy of the n-channel pass (channel gate) transistors 26 and 28 within each memory cell 14, where the scaling factor is equal to n. In this context, "scaled copy" means that transistor 218 is fabricated using the same integrated circuit process materials and parameters (doping levels, oxide thicknesses, gate materials, etc.) as each of transistors 26 and 28, but is n-fold repeated for a single transistor, providing an effectively greater width. For example, transistor 218 may be fabricated by connecting n transistors in parallel that are identical (matched) to each of transistors 26 and 28. The second n-channel MOS transistor 220 has a drain coupled (preferably directly connected) to a node 222 and a source coupled (preferably directly connected) to a ground power supply reference. The gate of the second n-channel MOS transistor 220 is coupled (preferably directly connected) to receive the supply voltage Vdd. Second n-channel MOS transistor 220 is a scaled copy of n-channel pulldown transistors 34 and 36 within each memory cell 14, where the scaling factor is equal to n. For example, transistor 220 may be fabricated by connecting n transistors in parallel that are identical (matched) to each of transistors 34 and 36.

The bias voltage Vbias generated at node 216 is equal to:

Vbias＝n(Iref)(Rdson218+Rdson220)，

wherein: rdson218 is the drain to source resistance of the diode connected first n-channel MOS transistor 218 and Rdson220 is the drain to source resistance of the second n-channel transistor 220 that is gate biased by the supply voltage Vdd. During a read operation, the series connected transistors 218 and 220 replicate the current path from the bit line (BLT or BLC) to ground in the memory cell 14 by a scaling factor n, under which operating conditions the channel gate transistor and its pull-down transistor on one side of the memory cell are both on.

Differential amplifier circuit 224, configured as a unity gain voltage follower, receives the Vbias voltage at its non-inverting input and generates Vbias at its output 226 with sufficient drive capacity to power all of the word line driver circuits 16 of the word lines that are simultaneously actuated during an intra-memory computing operation. The output of the differential amplifier circuit 224 is shorted to the inverting input.

Referring now to fig. 11, fig. 11 shows a schematic diagram of an alternative embodiment of the voltage generator circuit 212. The voltage generator circuit 212 of fig. 11 differs from the implementation shown in fig. 10 in that it supports further integrated circuit process and/or temperature based tuning of the magnitude of the current Iout output by the current source 214 within the voltage generator circuit 212. In this context, current source 214 is formed by a variable current source having a basic (or nominal) current Inom size equal to n (Iref) and having a positive or negative regulation adj from the basic current size level set by the control signal. In other words, the magnitude of the current output Iout of the current source 214 is equal to n (Iref) ±adj, where adj is the adjustment set by the control signal. In one embodiment, the control signal is a multi-bit digital control signal Vsel, but it should be understood that the control signal may instead be implemented as an analog signal. The value of the control signal, in particular the digital value of the bit of the control signal Vsel, selects the degree of regulation of the magnitude of the current output by the current source 214. The control signal Vsel is generated by the control circuit 114 in response to integrated circuit process and/or temperature information. Thus, the level of the adaptive supply voltage Vbias is now additionally dependent on the integrated circuit process and/or temperature information.

The integrated circuit process information is a digital code that is generated and stored in memory M within control circuit 114. The digital code represents the center of the process lot (center) and is generated by circuitry, such as a Ring Oscillator (RO), whose output frequency varies according to the integrated circuit process. Thus, the output frequency of the RO circuit represents the process center (process centering) and can be easily converted to a digital code (e.g., by using a counter circuit). Process monitoring circuitry 116 within control circuitry 114 may generate the value of control signal Vsel as a function of the stored digital code for the integrated circuit process. For example, the process monitor circuit 116 may include a look-up table (LUT) that correlates each digital code with a value of the control signal Vsel for selecting either positive or negative adjustment adj to the nominal magnitude of the current generated by the current source 214 to ensure that the voltage level of the adaptive supply voltage Vbias will produce an optimal level for wordline underactuation of the integrated circuit process corner. The control circuit 114 outputs a value of the control signal Vsel in relation to the digital code, and the voltage generator circuit 212 responds by generating a corresponding voltage level of the adaptive supply voltage Vbias.

Temperature information is generated by the temperature sensing circuit 118 and is representative of the current temperature of the integrated circuit. The temperature sensing circuit 118 may modify or adjust the value of the control signal Vsel in accordance with the sensed temperature. For example, the temperature sensing circuit 118 may include a look-up table (LUT) that specifies a particular adjustment of the value of the control signal Vsel for providing a corresponding tuning of the magnitude of the current output by the current source 214 to ensure that the level of the adaptive supply voltage Vbias will produce an optimal level of wordline underdrive given the integrated circuit process corner and current temperature conditions.

Referring now to fig. 12, fig. 12 shows a flow chart of the operation of the control circuit 114 and the process monitoring circuit 116 of the circuit of fig. 11. In step 140, the stored digital code for the integrated circuit process is read from memory M. In one embodiment, digital code for an integrated circuit process is loaded into memory M at the factory and is based on identified integrated circuit process characteristics (fast/slow inflection points, etc.) of an integrated circuit manufacturing lot (e.g., source wafer) from which the integrated circuit is obtained. Next, in step 142, it is determined whether the digital code read for the integrated circuit process indicates that the n-channel MOS transistor of memory cell 12 is at a fast integrated circuit process corner (i.e., where the n-channel MOS is fast and the p-channel MOS is slow-an "FS" corner). If so, in step 144, a value of the control signal Vsel is selected that corresponds to the digital code read and will cause a negative adjustment adj to the magnitude of the current output by the current source 214 so that the voltage regulator circuit 212 will produce a higher degree of word line under-actuation (i.e., the level of the adaptive supply voltage Vbias will be lower than the nominal (or default) level of word line under-actuation set by the nominal current magnitude n (Iref)). The effect of setting the adaptive supply voltage Vbias to a voltage level lower than the nominal (or default) voltage level is to reduce MRAWM, which is the maximum level of bit line voltage required to write the bit cell. Reducing MRAWM results in a reduction in the write capability of the bit cell and an increase in the data flip rate, which is of interest at the fast n-channel MOS inflection point. Such a voltage level below nominal (or default) also allows for higher headroom for bitline swing and thus higher precision bitline accumulation in the in-memory computing operation. If no in step 142, then in step 146, it is determined whether the read digital code for the integrated circuit process indicates that the n-channel MOS transistor of memory cell 12 is at a slow integrated circuit process corner (i.e., where the n-channel MOS is slow and the p-channel MOS is fast—an "SF" corner). If so, then in step 148, a value of control signal Vsel is selected that corresponds to the digital code read and will cause a positive adjustment adj to the magnitude of the current output by current source 214 such that voltage regulator circuit 212 will produce a lower degree of word line under-actuation (i.e., the level of adaptive supply voltage Vbias is higher than the nominal (or default) level of word line under-actuation set by nominal current magnitude n (Iref)). The effect of setting the adaptive supply voltage Vbias to a voltage level higher than the nominal (or default) voltage level is to increase the multi-row access write margin (MRAWM), thereby increasing the cell current while still controlling the data flip rate, which is less of a concern at the slow NMOS corner. Such higher than nominal (or default) voltage levels also reduce the effects of local variations in the slow process corner. If no in step 146, then in step 150, the value of the control signal Vsel is selected, which corresponds to the digital code read, and will not cause an adjustment (i.e., adj=0) to the n (Iref) magnitude of the current output by the current source 214, such that the level of the adaptive supply voltage Vbias that the voltage regulator circuit 212 will produce is equal to the nominal (or default) level of word line under-actuation set by the nominal current Inom.

Although the process of fig. 12 contemplates three voltage control levels (above, below, and equal to the nominal voltage), it is understood that this is merely an example. Additional test steps may be added to the process of fig. 12 to test other integrated circuit process corners or process related conditions (e.g., fast (FF) and/or slow (SS) corners), each test having an associated digital code and value of control signal Vsel for setting a corresponding level of regulation of the current output by current source 214 of voltage generator circuit 212.

The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of exemplary embodiments of the invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.

Claims

1. An in-memory computing circuit comprising:

a memory array comprising a plurality of memory cells arranged in a matrix having a plurality of rows and a plurality of columns, each row comprising a word line connected to memory cells of the row and each column comprising a first bit line connected to memory cells of the column;

A word line driver circuit for each row having an output connected to drive a word line of the row, wherein the word line driver circuit is powered by an adaptive supply voltage that depends on integrated circuit process and/or temperature conditions;

a row controller circuit configured to simultaneously actuate a plurality of word lines for in-memory computing operations by applying pulses to the word lines through the word line driver circuit; and

column processing circuitry includes first read circuitry coupled to each first bit line, wherein each first read circuitry includes:

a first current mirror circuit configured to mirror a first read current on the first bit line to generate a first mirrored read current; and

a first integrating capacitor configured to integrate the first mirrored read current to generate a first output voltage;

wherein the configuration of the adaptive supply voltage and the first current mirror circuit inhibits a voltage on the first bit line from dropping below a bit flip voltage during the simultaneous actuation of the plurality of word lines for an in-memory computing operation.

2. The circuit of claim 1, wherein the column processing circuit further comprises an analog-to-digital converter, ADC, circuit configured to convert the first output voltage to a digital output.

3. The circuit of claim 1, further comprising a voltage generator circuit configured to generate the adaptive supply voltage dependent on integrated circuit process and/or temperature conditions, the voltage generator circuit comprising:

a current source configured to generate a current applied to the first node; and

a first transistor and a second transistor connected in series between the first node and a reference node;

wherein the adaptive supply voltage is generated at the first node;

wherein the first transistor is a replica of a channel gate transistor within a memory cell;

wherein the second transistor is a replica of a pull-down transistor within the memory cell.

4. A circuit according to claim 3, wherein:

the current generated by the current source has a magnitude set according to a reference current representing a current flowing through the pass gate transistor and the pull-down transistor for an applicable integrated circuit process corner; and is also provided with

The magnitude of the current generated by the current source is scaled by a factor applied to the reference current;

wherein the first transistor scales with the factor for the copy of the channel gate transistor; and is also provided with

Wherein the second transistor scales by the factor for the replica of the pull-down transistor.

5. The circuit of claim 3, further comprising an amplifier circuit having an input coupled to the first node and an output coupled to power the word line driver circuit.

6. The circuit of claim 3, wherein the current source is controlled to generate the adjustment to the current, and further comprising a control circuit configured to generate a control signal responsive to an applicable integrated circuit process corner for a transistor device of a memory cell, the control signal for application to the current source to modulate a level of the current away from a nominal level.

7. The circuit of claim 6, wherein the applicable integrated circuit process corner is indicated by a programming code stored in the control circuit.

8. The circuit of claim 7, wherein the control circuit comprises a look-up table LUT that associates the programming code with a value of the control signal.

9. The circuit of claim 6, wherein the control circuit further comprises a temperature sensor, and wherein the control signal is configured to cause a temperature dependent adjustment of the level of the current set in response to an applicable integrated circuit process corner.

10. The circuit of claim 9, wherein the control circuit comprises a look-up table LUT that correlates sensed integrated circuit temperatures to adjustment levels for values of the control signal.

11. The circuit of claim 1, wherein the first current mirror circuit comprises:

a first MOS transistor having a drain and a gate directly connected to the first bit line to receive the first read current; and

a second MOS transistor having a gate directly connected to the gate of the first MOS transistor, and a drain configured to output the first mirrored read current;

wherein the first MOS transistor is sized to conduct the first read current without the voltage on the first bit line falling below the bit flip voltage during the simultaneous actuation of the plurality of word lines.

12. The circuit of claim 1, wherein the first current mirror circuit is switchably controlled to output the first mirrored read current in response to assertion of an integral control signal during the in-memory computing operation.

13. The circuit of claim 1, wherein the first integrating capacitor discharges at the beginning of the in-memory computing operation in response to assertion of a reset control signal.

14. The circuit of claim 1, wherein each column further comprises a second bit line connected to memory cells of the column, and wherein the column processing circuit further comprises a second read circuit coupled to each second bit line, wherein each second read circuit comprises:

a second current mirror circuit configured to mirror a second read current on the second bit line to generate a second mirrored read current; and

a second integrating capacitor configured to integrate the second mirrored read current to generate a second output voltage;

wherein the configuration of the adaptive supply voltage and the second current mirror circuit inhibits a voltage on the second bit line from dropping below the bit flip voltage during the simultaneous actuation of the plurality of word lines for the in-memory computing operation.

15. The circuit of claim 14, wherein the column processing circuit further comprises a converter ADC circuit configured to convert a difference between the first output voltage and the second output voltage to a digital output.

16. The circuit of claim 14, wherein the second current mirror circuit comprises:

A first MOS transistor having a drain and a gate directly connected to the second bit line to receive the second read current; and

a second MOS transistor having a gate directly connected to the gate of the first MOS transistor, and a drain configured to output the second mirrored read current;

wherein the first MOS transistor is sized to conduct the second read current without the voltage on the second bit line falling below the bit flip voltage during the simultaneous actuation of the plurality of word lines.

17. The circuit of claim 14, wherein the first and second current mirror circuits are switchably controlled to output the first and second mirrored read currents, respectively, in response to assertion of an integral control signal during the in-memory computing operation.

18. The circuit of claim 14, wherein the first integrating capacitor and the second integrating capacitor discharge at the beginning of the in-memory computing operation in response to assertion of a reset control signal.

19. The circuit of claim 1, wherein each column further comprises a second bit line connected to memory cells of the column, and wherein the column processing circuit further comprises a second read circuit coupled to each second bit line, wherein each second read circuit comprises:

A second current mirror circuit configured to mirror a second read current on the second bit line to generate a second mirrored read current;

wherein the first integrating capacitor is configured to integrate a difference between the first mirrored read current and the second mirrored read current to generate the first output voltage;

20. The circuit of claim 19, wherein the column processing circuit further comprises an analog-to-digital converter, ADC, circuit configured to convert the first output voltage to a digital output.

21. The circuit of claim 19, wherein the second current mirror circuit comprises:

22. The circuit of claim 19, wherein the first and second current mirror circuits are switchably controlled to output the first and second mirrored read currents, respectively, in response to assertion of an integral control signal during the in-memory computing operation.

23. The circuit of claim 19, wherein the first integrating capacitor discharges at the beginning of the in-memory computing operation in response to assertion of a reset control signal.

24. The circuit of claim 1, wherein each memory cell of the memory array is an SRAM cell, the SRAM cell being one of a 6T-type memory cell or an 8T-type memory cell.