CN117119846A - Display panel and display device - Google Patents
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- CN117119846A CN117119846A CN202311075666.9A CN202311075666A CN117119846A CN 117119846 A CN117119846 A CN 117119846A CN 202311075666 A CN202311075666 A CN 202311075666A CN 117119846 A CN117119846 A CN 117119846A
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- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000010409 thin film Substances 0.000 claims abstract description 27
- 230000002093 peripheral effect Effects 0.000 claims abstract description 18
- 239000003990 capacitor Substances 0.000 claims description 28
- 238000003860 storage Methods 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000003475 lamination Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
The embodiment of the disclosure provides a display panel and a display device. Wherein, the display panel includes: the substrate comprises a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a wiring area and a binding area, and the binding area is positioned at one side of the display area; the pixel units are arranged in an array mode and are positioned in the display area, and each pixel unit comprises a light emitting device and a thin film transistor; a first operating voltage line connected to the first electrode of the light emitting device; the first working voltage line at least comprises a first sub-line and a second sub-line which are connected with each other, the first sub-line is located in the peripheral area, the second sub-line is located in the wiring area, the first sub-line and the first electrode of the thin film transistor are arranged in the same layer, the second sub-line is located on one side, close to the substrate, of the first sub-line, and the width of the first sub-line is larger than that of the second sub-line.
Description
Technical Field
The disclosure relates to the technical field of display, in particular to a display panel and a display device.
Background
The display panel generally includes a display area in which pixel units are arrayed and a peripheral area disposed around the display area; the peripheral region is provided with a driving circuit, such as a gate driving circuit, a source driving circuit, and the like. An Organic Light-Emitting Diode (OLED) is disposed in the pixel unit, an anode of the OLED is connected to a driving transistor in the driving circuit, and a cathode of the OLED is connected to a VSS line in the driving circuit, so as to perform Light Emitting display by a driving signal provided by the driving circuit.
Since the VSS line has a certain on-line resistance, an IR Drop problem occurs on the VSS line when a power signal is supplied. And as the size of the display panel increases, the longer the VSS line is set, the more serious the IR Drop problem on the line, resulting in poor uniformity of the power supply signal. Meanwhile, the VSS line is connected to the cathode of the OLED, which is a current-driven type device whose brightness is very sensitive to changes in the input current. The brightness of different areas of the display panel can be inconsistent due to the IR Drop on the cathode of the light emitting device, and particularly, the brightness of the display panel far from the current input end and the brightness of the display panel near to the current input end can be greatly different, so that the uniformity of the display brightness of the display panel is affected.
Disclosure of Invention
The embodiment of the disclosure provides a display panel and a display device.
In a first aspect, embodiments of the present disclosure provide a display panel including:
the substrate comprises a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a wiring area and a binding area, and the binding area is positioned on one side of the display area;
the pixel units are arranged in an array mode, are positioned in the display area and comprise a light emitting device and a thin film transistor;
a first operating voltage line connected to a first electrode of the light emitting device;
the first operating voltage line includes at least a first sub-line and a second sub-line connected to each other, the first sub-line being located in the peripheral region, the second sub-line being located in the wiring region,
the first sub-line and the first electrode of the thin film transistor are arranged in the same layer, the second sub-line is positioned on one side of the first sub-line, which is close to the substrate, and the width of the first sub-line is larger than that of the second sub-line.
In some embodiments, the second sub-line is disposed in the same layer as the gate electrode of the thin film transistor.
In some embodiments, the pixel unit includes a pixel driving circuit for providing a driving signal to the light emitting device, the pixel driving circuit including the thin film transistor; the pixel driving circuit further comprises a storage capacitor, wherein a first pole of the storage capacitor and a grid electrode of the thin film transistor are arranged on the same layer, and a second pole of the storage capacitor is positioned at one side, far away from the substrate, of the first pole;
the second sub-line is arranged on the same layer as the second electrode of the storage capacitor.
In some embodiments, the pixel unit includes a pixel driving circuit for providing a driving signal to the light emitting device, the pixel driving circuit including the thin film transistor; the pixel driving circuit further comprises a storage capacitor, wherein a first pole of the storage capacitor and a grid electrode of the thin film transistor are arranged on the same layer, and a second pole of the storage capacitor is positioned at one side, far away from the substrate, of the first pole;
the first working voltage line further comprises a third sub-line, the third sub-line is connected with the second sub-line, one of the second sub-line and the third sub-line is arranged on the same layer as the first electrode of the storage capacitor, and the other sub-line is arranged on the same layer as the second electrode of the storage capacitor.
In some embodiments, an orthographic projection of a portion of the first sub-line located in the routing region on the substrate overlaps an orthographic projection of the second sub-line on the substrate.
In some embodiments, the third sub-line is located on a side of the second sub-line near the substrate,
and the orthographic projection of the second sub-line on the substrate covers the orthographic projection of the third sub-line on the substrate.
In some embodiments, the width of the first sub-line is 100-150 μm on the routing region.
In some embodiments, the routing region includes a first region, a second region, and a third region, the first region and the second region being located on opposite sides of the display region in a first direction, the third region and the bonding region being located on opposite sides of the display region in a second direction, the first direction and the second direction intersecting;
the display panel further comprises a gate driving circuit, wherein the gate driving circuit is positioned in the first area and the second area;
the first operating voltage line is located at a side of the gate driving circuit away from the display region in the first region and the second region.
In some embodiments, the display panel further includes a driving chip located at the bonding region,
and the part of the first sub-line positioned in the binding area is connected with the driving chip.
In a second aspect, embodiments of the present disclosure provide a display device including the display panel provided in the first aspect.
In the embodiment of the disclosure, the first working voltage line includes a first sub-line and a second sub-line, that is to say, the first working voltage line is separately arranged in the plurality of conductive layers, and the resistance on the first working voltage line is reduced in a multi-line parallel connection mode, so that the IR-Drop is reduced, and the display uniformity is improved. The arrangement can reduce the width of the first working voltage line under the condition that the resistance on the first working voltage line is fixed, and is beneficial to realizing the narrow frame design of the display panel. In addition, the width of the first sub-line is larger than that of the second sub-line, so that the problem that the signal stability is affected and the reliability of products is reduced due to overlarge section difference of different conductive layers corresponding to the edge positions in the preparation process caused by the fact that the edge positions of the first sub-line and the second sub-line are overlapped in the thickness direction of the substrate is avoided.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:
fig. 1 is a schematic plan view of a display panel according to an embodiment of the disclosure.
Fig. 2 is a schematic cross-sectional structure of a display area of a display panel according to an embodiment of the disclosure.
Fig. 3 is a schematic cross-sectional view taken along line AA in fig. 1.
Reference numerals illustrate:
substrate base plate 10: display area AA, peripheral area NA, binding area BA, wiring area PA: a first area pa1, a second area pa2, and a third area pa3; a first direction X and a second direction Y;
first operating voltage line VSS: a first sub-line vss1, a second sub-line vss2, and a third sub-line vss3;
a first via hole V1 and a second via hole V2;
an active layer Act, a Gate insulating layer GI1, a first conductive layer Gate1, a second insulating layer GI2, a second conductive layer Gate2, a first insulating layer ILD, a third conductive layer SD1, a passivation layer PVX, a fourth conductive layer SD2, and a planarization layer PLN;
a first pole C1 of the storage capacitor, a second pole C2 of the storage capacitor, and a first pole E1 of the light emitting device;
thin film transistor TFT: a first pole t1, a second pole t2, a grid Gate, an active pattern act0, a source electrode connection pattern a1 and a drain electrode connection pattern a2;
a gate driving circuit GOA, a second operating voltage line VDD.
Detailed Description
Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the disclosure, are not intended to limit the disclosure.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present between the layer or element and the other layer or substrate.
In the embodiments of the present disclosure, the a structure is located on the "side far from the substrate" or "above" the B structure, which merely means that the layer of the a structure is formed after the layer of the B structure in the lamination relationship, and does not indicate that there is projection overlap between the a structure and the B structure or that the distance between the a structure and the B structure and the substrate satisfies a specific relationship. In the embodiments of the present disclosure, the a structure is located "on the side of the B structure near the substrate" or "under" only means that the layer of the a structure is formed prior to the layer of the B structure in the lamination relationship, and does not indicate that there is projection overlap between the a structure and the B structure or that the distance between the a structure and the B structure and the substrate satisfies a specific relationship.
Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
Along with the rapid development of display technology, the requirements on the screen ratio of the display panel are higher and higher, and the display panel with high screen ratio has better visual experience, so that the display panel gradually develops to narrow frame.
The display panel generally includes a display area in which pixel units are arrayed and a peripheral area disposed around the display area; the peripheral region is provided with a driving circuit, such as a gate driving circuit, a source driving circuit, and the like. An Organic Light-Emitting Diode (OLED) is disposed in the pixel unit, an anode of the OLED is connected to a driving transistor in the driving circuit, and a cathode of the OLED is connected to a VSS line in the driving circuit, so as to perform Light Emitting display by a driving signal provided by the driving circuit.
Since the VSS line has a certain on-line resistance, an IR Drop problem occurs on the VSS line when a power signal is supplied. And as the size of the display panel increases, the longer the VSS line is set, the more serious the IR Drop problem on the line, resulting in poor uniformity of the power supply signal. Meanwhile, the VSS line is connected to the cathode of the OLED, which is a current-driven type device whose brightness is very sensitive to changes in the input current. The brightness of different areas of the display panel can be inconsistent due to the IR Drop on the cathode of the light emitting device, and particularly, the brightness of the display panel far from the current input end and the brightness of the display panel near to the current input end can be greatly different, so that the uniformity of the display brightness of the display panel is affected.
In the related art, the on-line resistance is reduced by increasing the area of the VSS line, but such arrangement increases the frame size of the display panel, which is not beneficial to the narrow frame design of the display panel.
In order to solve at least one of the above-mentioned ending problems, an embodiment of the present disclosure provides a display panel, which can realize a lower resistance on the VSS line by adjusting the structure of the VSS line, reduce IR Drop, improve display uniformity, and meet the requirements of a narrow frame of the display panel.
Fig. 1 is a schematic plan view of a display panel according to an embodiment of the disclosure, fig. 2 is a schematic sectional view of a display area AA of the display panel according to an embodiment of the disclosure, and fig. 3 is a schematic sectional view taken along line AA in fig. 1. As shown in fig. 1 to 3, the display panel includes a substrate base 10, a plurality of pixel units arranged in an array, and a first operating voltage line VSS. Wherein the substrate base 10 includes a display area AA and a peripheral area NA surrounding the display area AA, the peripheral area NA including a wiring area PA and a binding area BA, the binding area BA being located at one side of the display area AA. The pixel units are located in the display area AA, and each pixel unit comprises a light emitting device and a thin film transistor for providing a driving signal for the light emitting device.
The first operating voltage line VSS is connected to the first electrode E1 of the light emitting device, the first operating voltage line VSS includes at least a first sub-line VSS1 and a second sub-line VSS2 connected to each other, the first sub-line VSS1 is located in the peripheral area NA, the second sub-line VSS2 is located in the wiring area PA, the first sub-line VSS1 is arranged in the same layer as the first pole t1 of the thin film transistor, the second sub-line VSS2 is located at a side of the first sub-line VSS1 adjacent to the substrate 10, and a width of the first sub-line VSS1 is larger than a width of the second sub-line VSS 2.
In the embodiment of the disclosure, the first working voltage line VSS includes the first sub-line VSS1 and the second sub-line VSS2, that is, the first working voltage line VSS is divided into a plurality of conductive layers, and the resistance on the first working voltage line VSS is reduced by a multi-line parallel connection manner, so that IR-Drop is reduced, and display uniformity is improved. By the arrangement, under the condition that the resistance on the first working voltage line VSS is fixed, the width of the first working voltage line VSS can be reduced, and the narrow frame design of the display panel is facilitated. In addition, the width of the first sub-line vss1 is set to be larger than the width of the second sub-line vss2, so as to avoid the problem that the widths of the first sub-line vss1 and the second sub-line vss2 are equal, so that the edge positions of the first sub-line vss1 and the second sub-line vss2 overlap in the thickness direction of the substrate 10, and the step difference at the edge positions corresponding to different conductive layers in the preparation process is too large, thereby influencing the signal stability and reducing the reliability of the product.
Note that the first operating voltage line VSS is configured to supply a low-level signal to the light emitting device.
In some embodiments, the pixel unit includes a pixel driving circuit for providing a driving signal to the light emitting device, the pixel driving circuit including the thin film transistor; the pixel driving circuit further includes a storage capacitor, wherein a first pole C1 of the storage capacitor is arranged on the same layer as the Gate electrode Gate of the thin film transistor, and a second pole C2 of the storage capacitor is located at a side of the first pole away from the substrate 10.
In some embodiments, as shown in fig. 2, the display panel includes: an active layer Act, a Gate insulating layer GI1, a first conductive layer Gate1, a second insulating layer GI2, a second conductive layer Gate2, a first insulating layer ILD, a third conductive layer SD1, a passivation layer PVX, a fourth conductive layer SD2, and a planarization layer PLN are sequentially stacked on the substrate 10.
Wherein, the active layer Act includes: an active pattern act0, a source connection pattern a1, and a drain connection pattern a2 of each thin film transistor in the pixel driving circuit; the first conductive layer Gate1 includes: a grid electrode Gate, a reset control signal line, a grid line, a first electrode C1 of a storage capacitor and a light-emitting control signal line of each thin film transistor in the pixel driving circuit; the second conductive layer Gate2 includes: a reset voltage transmission line and a second pole C2 plate of the storage capacitor; the third conductive layer SD1 includes: a first pole t1 and a second pole t2 of each thin film transistor in the pixel driving circuit; the fourth conductive layer SD2 includes: the data line, the switching electrode E connecting the first electrode E1 of the light-emitting device and the first electrode t1 of the thin film transistor.
In some embodiments, as shown in fig. 1-3, the first sub-line VSS1 of the first operating voltage line VSS is arranged in the same layer as the first electrode t1 of the thin film transistor, i.e. the first sub-line VSS1 is located in the third conductive layer SD1.
In some embodiments, as shown in fig. 1-3, the second sub-line vss2 is disposed in the same layer as the Gate electrode Gate of the thin film transistor, that is, the second sub-line vss2 may be disposed in the first conductive layer Gate1.
The above-mentioned "same layer arrangement" means that a plurality of structures are formed by the same material layer through a patterning process, so that the structures are in the same layer in a lamination relation; but this does not mean that the distance between the several structures and the substrate base plate 10 must be the same.
In some embodiments, as shown in fig. 1-3, the second sub-line vss2 is disposed in the same layer as the second pole C2 of the storage capacitor, that is, the second sub-line vss2 may be disposed in the second conductive layer Gate2.
In some embodiments, the first operating voltage line VSS further includes a third sub-line VSS3, the third sub-line VSS3 is connected to the second sub-line VSS2, and one of the second sub-line VSS2 and the third sub-line VSS3 is arranged in the same layer as the first pole C1 of the storage capacitor, and the other is arranged in the same layer as the second pole C2 of the storage capacitor.
In the embodiment of the present disclosure, the first operating voltage line VSS includes a portion located in the second conductive layer Gate2 and/or the first conductive layer Gate1 in addition to the first sub-line VSS1 located in the third conductive layer SD1. The resistance on the first working voltage line VSS is reduced in a multi-line parallel connection mode, so that IR-Drop is reduced, and display uniformity is improved. By means of the arrangement, under the condition that the resistance on the first working voltage line VSS is fixed, the width of the first working voltage line VSS can be reduced, and the narrow frame design of the display panel is facilitated.
In some embodiments, as shown in fig. 3, the orthographic projection of the portion of the first sub-line vss1 located in the routing region PA on the substrate 10 overlaps the orthographic projection of the second sub-line vss2 on the substrate 10.
In some embodiments, as shown in fig. 3, the third sub-line vss3 is located on a side of the second sub-line vss2 near the substrate 10, and the orthographic projection of the second sub-line vss2 on the substrate 10 covers the orthographic projection of the third sub-line vss3 on the substrate 10.
It should be appreciated that the first sub-line vss1 and the second sub-line vss2 are connected through the plurality of first vias V1 on the first insulating layer ILD, and the second sub-line vss2 and the third sub-line vss3 are connected through the plurality of second vias V2 on the second insulating layer GI 2. In the process of manufacturing the display panel, each conductive layer is sequentially deposited on the substrate 10, so that the widths of the third sub-line vss3, the second sub-line vss2 and the first sub-line vss1 gradually increase in width along the direction away from the substrate 10, so that the wirings in the upper conductive layer are deposited through the via holes on the insulating layer and connected to the wirings in the lower conductive layer, thereby avoiding the risk of virtual connection caused by the deviation of the via holes.
In addition, if the widths of the first sub-line vss1, the second sub-line vss2 and the third sub-line vss3 are equal, the edge positions of the three will overlap in the thickness direction of the substrate 10, and this arrangement may result in too large step difference at the edge positions corresponding to the third conductive layer SD1, the second conductive layer Gate2 and the first conductive layer Gate1 in the manufacturing process, which affects the signal stability and reduces the yield and reliability of the product.
In the embodiment of the disclosure, the widths of the third sub-line vss3, the second sub-line vss2 and the first sub-line vss1 gradually increase and widen, and the orthographic projection of the first sub-line vss1 on the substrate 10 covers the orthographic projection of the second sub-line vss2 on the substrate 10, and the orthographic projection of the second sub-line vss2 on the substrate 10 covers the orthographic projection of the third sub-line vss3 on the substrate 10, so that the edge positions of the three sub-lines are not overlapped, the problem that the segment difference of the third conductive layer SD1, the second conductive layer Gate2 and the first conductive layer Gate1 at the corresponding routing edge is too large is avoided, and the preparation yield can be ensured.
In some embodiments, as shown in fig. 1, the width d of the first sub-line vss1 on the routing area PA is 100-150 μm, for example, d may take the values of 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, etc., which is not limited in the embodiments of the present disclosure.
In some embodiments, as shown in fig. 1, the routing area PA includes a first area PA1, a second area PA2, and a third area PA3, the first area PA1 and the second area PA2 being located at opposite sides of the display area AA in a first direction X, and the third area PA3 and the binding area BA being located at opposite sides of the display area AA in a second direction Y, the first direction X and the second direction Y intersecting. The display panel further comprises a gate driving circuit GOA, wherein the gate driving circuit GOA is positioned in the first area pa1 and the second area pa2; in the first area pa1 and the second area pa2, the first operating voltage line VSS is located at a side of the gate driving circuit GOA away from the display area AA.
In some embodiments, in order to further increase the area/length of the first operating voltage line and reduce the on-line resistance, the first operating voltage line may also be disposed on the conductive layer on the side of the third conductive layer SD1 remote from the substrate 10. In one example, the fourth conductive layer SD2 is provided with a fourth sub-line vss4, the fourth sub-line vss4 being located in the peripheral region and being connected in parallel with the first sub-line vss1 through at least one via located on the passivation layer.
Based on the same inventive concept as the above example, the orthographic projection of the fourth sub-line vss4 on the substrate 10 covers the orthographic projection of the first sub-line vss1 on the substrate 10. In this way, the edge positions of the fourth sub-line vss4 and the first sub-line vss1 are not overlapped, so that the problem that the step difference between the third conductive layer SD1 and the fourth conductive layer SD2 at the corresponding wire edge is too large is avoided. In some embodiments, as shown in fig. 1, the display panel further includes a driving chip (not shown in the drawing) located in the bonding area BA, and a portion of the first sub-line vss1 located in the bonding area BA is connected to the driving chip.
In addition, the bonding area BA further includes at least a second operating voltage line VDD for supplying a high-level signal to the pixel driving circuit, which is bonded to the driving chip. Also, the second operating voltage line VDD is located at the third conductive layer SD1, that is, the second operating voltage line VDD is disposed at the same layer as the first sub-line vss 1. In one example, the second operating voltage line VDD is configured to provide a high level signal.
It should be understood that since the third conductive layer SD1 is provided in at least one conductive layer close to the side of the substrate 10, other structures in the pixel driving circuit are also provided, and the pixel driving circuit needs to be supplied with power through the first and second operating voltage lines VSS and VDD. Therefore, in at least one of the conductive layers of the third conductive layer SD1 on the side close to the substrate base plate 10, a plurality of conductive patterns are further provided on the bonding area BA.
In order to avoid signal crosstalk, at least one conductive layer, namely the second conductive layer Gate2 and the first conductive layer Gate1, on the side of the third conductive layer SD1 close to the substrate 10, no first working voltage line is set in a portion corresponding to the bonding area BA, that is, orthographic projections of the second sub-line vss2 and the third sub-line vss3 on the substrate 10 respectively do not overlap with the bonding area BA.
Further, among the third conductive layer SD1 and at least one conductive layer located at a side of the third conductive layer SD1 away from the substrate base plate 10, a portion corresponding to the binding area BA may be provided with a first operating voltage line. In the case where the fourth conductive layer is added with the fourth sub-line vss4, the fourth sub-line vss4 may extend into the bonding area BA. That is, the portion of the first operating voltage line VSS located at the binding region BA may be disposed on the third conductive layer SD1 and the fourth conductive layer SD 2. At this time, the portion of the first sub-line vss1 located in the bonding area BA and the portion of the fourth sub-line vss4 located in the bonding area BA are connected in parallel and connected to the driving chip.
Based on the same inventive concept, the embodiments of the present disclosure also provide a display device including the display panel.
The display device may be: any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc., which is not limited in this disclosure.
It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.
Claims (10)
1. A display panel, comprising:
the substrate comprises a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a wiring area and a binding area, and the binding area is positioned on one side of the display area;
the pixel units are arranged in an array mode, are positioned in the display area and comprise a light emitting device and a thin film transistor;
a first operating voltage line connected to a first electrode of the light emitting device;
the first operating voltage line includes at least a first sub-line and a second sub-line connected to each other, the first sub-line being located in the peripheral region, the second sub-line being located in the wiring region,
the first sub-line and the first electrode of the thin film transistor are arranged in the same layer, the second sub-line is positioned on one side of the first sub-line, which is close to the substrate, and the width of the first sub-line is larger than that of the second sub-line.
2. The display panel of claim 1, wherein the second sub-line is disposed in the same layer as the gate electrode of the thin film transistor.
3. The display panel according to claim 1, wherein the pixel unit includes a pixel driving circuit for supplying a driving signal to the light emitting device, the pixel driving circuit including the thin film transistor; the pixel driving circuit further comprises a storage capacitor, wherein a first pole of the storage capacitor and a grid electrode of the thin film transistor are arranged on the same layer, and a second pole of the storage capacitor is positioned at one side, far away from the substrate, of the first pole;
the second sub-line is arranged on the same layer as the second electrode of the storage capacitor.
4. The display panel according to claim 1, wherein the pixel unit includes a pixel driving circuit for supplying a driving signal to the light emitting device, the pixel driving circuit including the thin film transistor; the pixel driving circuit further comprises a storage capacitor, wherein a first pole of the storage capacitor and a grid electrode of the thin film transistor are arranged on the same layer, and a second pole of the storage capacitor is positioned at one side, far away from the substrate, of the first pole;
the first working voltage line further comprises a third sub-line, the third sub-line is connected with the second sub-line, one of the second sub-line and the third sub-line is arranged on the same layer as the first electrode of the storage capacitor, and the other sub-line is arranged on the same layer as the second electrode of the storage capacitor.
5. The display panel of claim 1, wherein an orthographic projection of a portion of the first sub-line located in the routing region on the substrate overlaps an orthographic projection of the second sub-line on the substrate.
6. The display panel of claim 4, wherein the third sub-line is located on a side of the second sub-line adjacent to the substrate,
and the orthographic projection of the second sub-line on the substrate covers the orthographic projection of the third sub-line on the substrate.
7. The display panel according to claim 1, wherein a width of the first sub-line is 100-150 μm on the wiring region.
8. The display panel according to claim 1, wherein the wiring region includes a first region, a second region, and a third region, the first region and the second region being located on opposite sides of the display region in a first direction, the third region and the binding region being located on opposite sides of the display region in a second direction, the first direction and the second direction intersecting;
the display panel further comprises a gate driving circuit, wherein the gate driving circuit is positioned in the first area and the second area;
the first operating voltage line is located at a side of the gate driving circuit away from the display region in the first region and the second region.
9. The display panel of claim 1, further comprising a driver chip located in the bonding region,
and the part of the first sub-line positioned in the binding area is connected with the driving chip.
10. A display device comprising the display panel of any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311075666.9A CN117119846A (en) | 2023-08-24 | 2023-08-24 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311075666.9A CN117119846A (en) | 2023-08-24 | 2023-08-24 | Display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117119846A true CN117119846A (en) | 2023-11-24 |
Family
ID=88812299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311075666.9A Pending CN117119846A (en) | 2023-08-24 | 2023-08-24 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117119846A (en) |
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2023
- 2023-08-24 CN CN202311075666.9A patent/CN117119846A/en active Pending
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