CN117119074A - Data receiving and transmitting method, device, equipment and storage medium - Google Patents
Data receiving and transmitting method, device, equipment and storage medium Download PDFInfo
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- CN117119074A CN117119074A CN202311094137.3A CN202311094137A CN117119074A CN 117119074 A CN117119074 A CN 117119074A CN 202311094137 A CN202311094137 A CN 202311094137A CN 117119074 A CN117119074 A CN 117119074A
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 230000002093 peripheral effect Effects 0.000 claims abstract description 59
- 238000006243 chemical reaction Methods 0.000 claims abstract description 30
- 238000004590 computer program Methods 0.000 claims description 14
- 230000003993 interaction Effects 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 abstract description 11
- 238000010586 diagram Methods 0.000 description 7
- 238000004891 communication Methods 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
Abstract
The application discloses a data receiving and transmitting method, a device, equipment and a storage medium, which relate to the technical field of information transmission and comprise the following steps: transmitting a data receiving and transmitting request to an AXI2APB protocol conversion bridge through a central processing unit; converting the data receiving and transmitting request into an APB protocol instruction through an AXI2APB protocol conversion bridge to obtain an APB protocol instruction; sending an APB protocol instruction to a preset mode selector through an APB protocol to select a target data read-write mode corresponding to the data receiving-transmitting request based on the bit width of the APB protocol instruction; and distributing a corresponding number of input/output ports based on the target data read-write mode, connecting the input/output ports to the four-wire serial peripheral interface, and transmitting data to be transmitted corresponding to the data transmission and reception request to the SPI peripheral through the four-wire serial peripheral interface. The multiplexing and expanding of the SPI interface can be realized through the APB protocol and the preset mode selector, and various data receiving and transmitting modes are supported at the same time, so that the data receiving and transmitting efficiency of the SPI interface is improved.
Description
Technical Field
The present application relates to the field of information transmission technologies, and in particular, to a data transceiving method, device, equipment, and storage medium.
Background
Currently, when data is transmitted, an SPI (Serial Peripheral Interface ) protocol is generally used for transmitting and receiving data. However, based on the existing chip architecture, there are few threads available for data transmission, and a single-thread or double-thread data transmission mode is generally adopted separately, so that the data transmission rate of the SPI interface is relatively slow. Therefore, how to improve the data transceiving efficiency is a problem that is still further to be solved in the art.
Disclosure of Invention
Accordingly, the present application is directed to a data transceiving method, apparatus, device and storage medium, which can realize multiplexing and expansion of an SPI interface, and simultaneously support multiple data transceiving modes, thereby improving data transceiving efficiency of the SPI interface. The specific scheme is as follows:
in a first aspect, the present application discloses a data transceiving method, including:
when receiving a data receiving and transmitting request, the data receiving and transmitting request is sent to an AXI2APB protocol conversion bridge through a central processing unit;
converting the data receiving and transmitting request into an APB protocol instruction through the AXI2APB protocol conversion bridge to obtain an APB protocol instruction;
sending the APB protocol instruction to a preset mode selector through an APB protocol to select a target data read-write mode corresponding to the data receiving-transmitting request based on the bit width of the APB protocol instruction;
and distributing a corresponding number of input/output ports based on the target data read-write mode, connecting the input/output ports to a four-wire serial peripheral interface, and transmitting data to be transmitted corresponding to the data transmit-receive request to the SPI peripheral through the four-wire serial peripheral interface.
Optionally, the central processor adopts an open source instruction set architecture based on a reduced instruction set principle and has an AXI interface.
Optionally, the data transceiving method further includes:
and feeding back a flag signal generated by the SPI peripheral to the preset mode selector so as to replace the current target data read-write mode based on the flag signal.
Optionally, the data read-write mode in the preset mode selector includes a single-wire SPI transceiving mode, a two-wire SPI transceiving mode, and a four-wire SPI transceiving mode.
Optionally, the allocating a corresponding number of input/output ports based on the target data read-write mode includes:
and distributing a corresponding number of input/output ports through a tri-state gate output circuit based on the target data read-write mode.
Optionally, the data transceiving method further includes:
and controlling the state switch of the tri-state gate output circuit through a read-write type signal in the APB protocol.
Optionally, the data transceiving method further includes:
and displaying the data to be transmitted and received through an upper computer connected with the SPI peripheral equipment, and carrying out data interaction.
In a second aspect, the present application discloses a data transceiver, comprising:
the first information sending module is used for sending the data receiving and sending request to the AXI2APB protocol conversion bridge through the central processing unit when the data receiving and sending request is received;
the request conversion module is used for converting the data receiving and transmitting request into an APB protocol instruction through the AXI2APB protocol conversion bridge to obtain an APB protocol instruction;
the second information sending module is used for sending the APB protocol instruction to a preset mode selector through an APB protocol so as to select a target data read-write mode corresponding to the data receiving-transmitting request based on the bit width of the APB protocol instruction;
the port allocation module is used for allocating a corresponding number of input/output ports based on the target data read-write mode;
and the port connection module is used for connecting the input/output port to a four-wire serial peripheral interface so as to send the data to be received corresponding to the data receiving and sending request to the SPI peripheral through the four-wire serial peripheral interface.
In a third aspect, the application discloses an electronic device comprising a processor and a memory; the processor implements the data transceiving method when executing the computer program stored in the memory.
In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program when executed by the processor implements the aforementioned data transceiving method.
When receiving a data receiving and transmitting request, the application firstly transmits the data receiving and transmitting request to an AXI2APB protocol conversion bridge through a central processing unit, then converts the data receiving and transmitting request into an APB protocol instruction through the AXI2APB protocol conversion bridge to obtain an APB protocol instruction, and then transmits the APB protocol instruction to a preset mode selector through the APB protocol so as to select a target data read-write mode corresponding to the data receiving and transmitting request based on the bit width of the APB protocol instruction, and then allocates a corresponding number of input/output ports based on the target data read-write mode, and connects the input/output ports to a four-wire serial peripheral interface so as to transmit data to be received corresponding to the data receiving and transmitting request to an SPI peripheral through the four-wire serial peripheral interface. The multiplexing and expanding of the SPI interface can be realized through the APB protocol and the preset mode selector, and various data receiving and transmitting modes are supported at the same time, so that the data receiving and transmitting efficiency of the SPI interface is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a data transceiving method disclosed by the application;
FIG. 2 is a schematic diagram showing a specific correspondence between a pattern code and a read/write bit width according to the present application;
FIG. 3 is a schematic diagram showing a specific correspondence between a mode code and an input/output port according to the present application;
FIG. 4 is a schematic diagram illustrating a specific data transceiving method according to the present disclosure;
fig. 5 is a schematic structural diagram of a data transceiver according to the present disclosure;
fig. 6 is a block diagram of an electronic device according to the present disclosure.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The embodiment of the application discloses a data receiving and transmitting method, which is shown in fig. 1 and comprises the following steps:
step S11: when receiving the data receiving and transmitting request, the data receiving and transmitting request is sent to an AXI2APB protocol conversion bridge through a central processing unit.
In this embodiment, when the target chip receives the data transmission/reception request, the data transmission/reception request is sent to the AXI2APB protocol conversion bridge through the central processing unit (CPU, central Processing Unit). Wherein the central processor specifically adopts an open source instruction set architecture (RISC-V, reduced Instruction Set Computer-V) based on a reduced instruction set principle and has an AXI (Advanced eXtensible Interface, a bus protocol) interface; the AXI2APB protocol conversion bridge is used to convert AXI instructions to APB (Advanced Peripheral Bus, an advanced peripheral bus) instructions, or to convert APB instructions to AXI instructions, and to connect some APB peripherals to the AXI memory system. It should be noted that the target chip supports the chip architecture of RISC-V, and includes, in addition to the central processor, an AXI2APB protocol conversion bridge and an APB bus, for controlling signals of the APB protocol and mounting related peripherals supporting the APB protocol.
Step S12: and converting the data receiving and transmitting request into an APB protocol instruction through the AXI2APB protocol conversion bridge to obtain an APB protocol instruction.
In this embodiment, after the central processor sends the data transceiving request to the AXI2APB protocol conversion bridge, further, the AXI2APB protocol conversion bridge converts the received data transceiving request into an APB protocol instruction, so as to obtain a corresponding APB protocol instruction.
Step S13: and sending the APB protocol instruction to a preset mode selector through an APB protocol so as to select a target data read-write mode corresponding to the data receiving-transmitting request based on the bit width of the APB protocol instruction.
It should be noted that, in the present application, a mode selector is preset, and the data read-write mode supported in the mode selector includes a single-wire SPI transceiving mode (i.e., single-wire SPI receive, single-wire SPI transmit), a two-wire SPI transceiving mode (i.e., two-wire SPI receive, two-wire SPI transmit), and a four-wire SPI transceiving mode (i.e., four-wire SPI receive, four-wire SPI transmit).
In this embodiment, after the APB protocol command is obtained by converting the data transceiving request into the APB protocol command, the APB protocol command is sent to a preset mode selector through the APB protocol, and when the preset mode selector receives the APB protocol command, mode selection is performed. Specifically, one of the three different data transmission modes (i.e., a single-wire SPI transceiving mode, a two-wire SPI transceiving mode, and a four-wire SPI transceiving mode) may be selected as the target data read/write mode corresponding to the APB protocol command based on the bandwidth of the APB protocol command. It should be noted that, in the preset mode selector, corresponding mode codes are allocated in advance for different data read/write modes, for example, when the mode code is 001 as shown in fig. 2, the mode codes correspond to 8-bit write/read, i.e. a single-line SPI transceiving mode; when the mode code is 100/010/001, the mode code corresponds to 16-bit writing/reading, namely a two-wire SPI transceiving mode and 32-bit writing/reading mode, namely a four-wire SPI transceiving mode. In addition, when the writing/reading speed is larger than 32 bits, since a four-wire serial peripheral interface (namely, a four-wire SPI interface) is adopted, only a four-wire SPI transceiving mode can be selected at most.
Specifically, when the bit width of the signal (i.e., APB protocol command) is 8 bits, a default 001 mode, i.e., a single-wire SPI mode, may be used for data reading and writing; when the signal bit width is 16 bits, the reading and writing are performed in a 100-line SPI mode preferentially, but when the corresponding SPI peripheral is not provided with a plurality of interfaces, the feedback can be performed according to a flag signal (namely a flag signal) given by the SPI peripheral, and the two-line SPI transceiving mode or the single-line SPI transceiving mode is used for matching with the SPI peripheral; similarly, when the signal bit width is 32 bits, the four-wire SPI mode is preferentially used for reading and writing, but when the corresponding SPI peripheral is not provided with so many interfaces, the feedback is carried out according to the flag signal given by the SPI peripheral, and the two-wire SPI transceiving mode or the single-wire SPI transceiving mode is used for matching with the SPI peripheral; when the signal bit width is larger than 32 bits, the four-wire SPI transceiving mode is also used for reading and writing preferentially, and if the peripheral does not support the multi-wire SPI mode, namely the four-wire interface is not available, the peripheral can be gradually degraded into the two-wire SPI transceiving mode or the single-wire SPI transceiving mode according to the feedback signal of the SPI peripheral.
Step S14: and distributing a corresponding number of input/output ports based on the target data read-write mode, connecting the input/output ports to a four-wire serial peripheral interface, and transmitting data to be transmitted corresponding to the data transmit-receive request to the SPI peripheral through the four-wire serial peripheral interface.
In this embodiment, after the target data read/write mode corresponding to the data transmit/receive request is selected based on the bit width of the APB protocol command, a corresponding number of input/output ports are allocated based on the target data read/write mode, specifically, the corresponding register may be configured to control the input/output ports to allocate the corresponding number of I/O ports, and then the allocated input/output ports are connected to a four-wire serial peripheral interface, that is, a four-wire SPI interface, so that data to be transmitted corresponding to the data transmit/receive request is sent to the corresponding SPI peripheral through the four-wire serial peripheral interface. In one particular embodiment, referring to FIG. 3, when the mode code is 000, all four input/output ports are disabled; when the mode code is 001, port 0 in the four input/output ports allows data to be received and transmitted, and the other three input/output ports, namely port 1, port 2 and port 3, are disabled and correspond to a single-wire SPI receiving and transmitting mode; when the mode code is 010, the port 0 and the port 1 in the four input/output ports allow data to be received and transmitted, the port 2 and the port 3 are forbidden, and the two-wire SPI receiving and transmitting mode is corresponding; when the mode code is 100, all four input/output ports allow data to be transmitted and received, and the four-wire SPI transmission and reception mode is corresponding.
In this embodiment, the data to be transmitted and received may be displayed and interacted with each other by an upper computer connected to the SPI peripheral. The upper computer may be an upper computer having an SPI interface, a DSPI (Dual SPI, 4-wire SPI) interface, a QSPI (Quad SPI, 6-wire SPI) interface, and capable of transmitting and receiving data.
In addition, after selecting the target data read-write mode corresponding to the data transceiving request based on the bit width of the APB protocol instruction, a flag signal generated by the SPI peripheral may be specifically fed back to the preset mode selector, so that the current target data read-write mode may be replaced based on the flag signal. The data transceiving scheme provided by the application can be realized based on a corresponding data transceiving device, and referring to fig. 4, the device specifically comprises a chip module, a mode selection module (namely a mode selector), an I/O distribution module, an SPI multiplexing module (namely a four-wire serial peripheral interface) and an upper computer. The chip module specifically comprises a central processor, an AXI2APB protocol conversion bridge and an APB bus, wherein the central processor is used for receiving a data receiving and transmitting request, the AXI2APB protocol conversion bridge is used for converting the data receiving and transmitting request received by the central processor into an APB protocol, the APB bus is used for sending a converted APB protocol instruction to the mode selection module for mode selection, then the I/O distribution module is used for distributing I/O ports according to the mode code selected by the mode selection module, the distributed I/O ports are connected to the SPI multiplexing module, the data to be received and transmitted corresponding to the data receiving and transmitting request is sent to the SPI peripheral through the SPI multiplexing module, and the data to be received and transmitted can be displayed and interacted through the upper computer. The SPI multiplexing module supports single-wire SPI transceiving, double-wire SPI transceiving and four-wire SPI transceiving, and supports corresponding types of master machine and slave machine modes. And, the flag signal that SPI peripheral equipment generated can feed back to mode selection module changes the data read-write mode of current selection based on above-mentioned flag signal.
In addition, the allocating a corresponding number of input/output ports based on the target data read-write mode may specifically include: a corresponding number of input/output ports are allocated based on the target data read-write mode and through a tri-state gate output circuit (i.e., three-state gate). Specifically, referring to fig. 4, when a corresponding number of input/output ports are allocated, the control of the input/output ports may also be performed by a tri-state gate output circuit control signal generated by the APB bus. It is noted that the status switch of the tri-state gate output circuit may also be controlled by a read-write type signal (PWRITE signal) in the APB protocol.
It can be seen that when a data receiving and transmitting request is received, the embodiment of the present application firstly sends the data receiving and transmitting request to an AXI2APB protocol conversion bridge through a central processing unit, then converts the data receiving and transmitting request to an APB protocol command through the AXI2APB protocol conversion bridge to obtain an APB protocol command, and then sends the APB protocol command to a preset mode selector through the APB protocol, so as to select a target data read-write mode corresponding to the data receiving and transmitting request based on the bit width of the APB protocol command, and then allocates a corresponding number of input/output ports based on the target data read-write mode, and connects the input/output ports to a four-wire serial peripheral interface, so that data to be received corresponding to the data receiving and transmitting request is sent to an SPI peripheral through the four-wire serial peripheral interface. The embodiment of the application can realize multiplexing and expanding of the SPI interface through the APB protocol and the preset mode selector, and simultaneously supports various data receiving and transmitting modes, thereby improving the data receiving and transmitting efficiency of the SPI interface.
Correspondingly, the embodiment of the application also discloses a data transceiver, which is shown in fig. 5, and comprises:
the first information sending module 11 is configured to send, when receiving a data transceiving request, the data transceiving request to an AXI2APB protocol conversion bridge through a central processing unit;
a request conversion module 12, configured to convert the data transceiving request into an APB protocol instruction through the AXI2APB protocol conversion bridge, to obtain an APB protocol instruction;
a second information sending module 13, configured to send the APB protocol instruction to a preset mode selector through an APB protocol, so as to select a target data read-write mode corresponding to the data transceiving request based on a bit width of the APB protocol instruction;
a port allocation module 14 for allocating a corresponding number of input/output ports based on the target data read-write mode;
and the port connection module 15 is configured to connect the input/output port to a four-wire serial peripheral interface, so as to send data to be received corresponding to the data receiving and sending request to the SPI peripheral through the four-wire serial peripheral interface.
The specific workflow of each module may refer to the corresponding content disclosed in the foregoing embodiment, and will not be described herein.
It can be seen that when a data receiving and transmitting request is received, the embodiment of the present application firstly sends the data receiving and transmitting request to an AXI2APB protocol conversion bridge through a central processing unit, then converts the data receiving and transmitting request to an APB protocol command through the AXI2APB protocol conversion bridge to obtain an APB protocol command, and then sends the APB protocol command to a preset mode selector through the APB protocol, so as to select a target data read-write mode corresponding to the data receiving and transmitting request based on the bit width of the APB protocol command, and then allocates a corresponding number of input/output ports based on the target data read-write mode, and connects the input/output ports to a four-wire serial peripheral interface, so that data to be received corresponding to the data receiving and transmitting request is sent to an SPI peripheral through the four-wire serial peripheral interface. The embodiment of the application can realize multiplexing and expanding of the SPI interface through the APB protocol and the preset mode selector, and simultaneously supports various data receiving and transmitting modes, thereby improving the data receiving and transmitting efficiency of the SPI interface.
In some embodiments, the central processor employs an open source instruction set architecture based on the reduced instruction set principle and has an AXI interface.
In some specific embodiments, the data transceiver may further include:
and the signal feedback unit is used for feeding back a flag signal generated by the SPI peripheral to the preset mode selector so as to replace the current target data read-write mode based on the flag signal.
In some embodiments, the data read-write mode in the preset mode selector includes a single-wire SPI transceiving mode, a two-wire SPI transceiving mode, and a four-wire SPI transceiving mode.
In some specific embodiments, the port assignment module 16 may specifically include:
and the port allocation unit is used for allocating a corresponding number of input/output ports through the tri-state gate output circuit based on the target data read-write mode.
In some specific embodiments, the data transceiver may further include:
and the state switch control unit is used for controlling the state switch of the three-state gate output circuit through a read-write type signal in the APB protocol.
In some specific embodiments, the data transceiver may further include:
and the data display and interaction unit is used for displaying and interacting the data to be transmitted and received through an upper computer connected with the SPI peripheral.
Further, the embodiment of the present application further discloses an electronic device, and fig. 6 is a block diagram of an electronic device 20 according to an exemplary embodiment, where the content of the figure is not to be considered as any limitation on the scope of use of the present application.
Fig. 6 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. The memory 22 is configured to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the data transceiving method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in the present embodiment may be specifically an electronic computer.
In this embodiment, the power supply 23 is configured to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol to be followed is any communication protocol applicable to the technical solution of the present application, which is not specifically limited herein; the input/output interface 25 is used for acquiring external input data or outputting external output data, and the specific interface type thereof may be selected according to the specific application requirement, which is not limited herein.
The memory 22 may be a carrier for storing resources, such as a read-only memory, a random access memory, a magnetic disk, or an optical disk, and the resources stored thereon may include an operating system 221, a computer program 222, and the like, and the storage may be temporary storage or permanent storage.
The operating system 221 is used for managing and controlling various hardware devices on the electronic device 20 and computer programs 222, which may be Windows Server, netware, unix, linux, etc. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the data transceiving method performed by the electronic device 20 disclosed in any of the previous embodiments.
Further, the application also discloses a computer readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements the data transceiving method disclosed previously. For specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing has described in detail a data transceiving method, apparatus, device and storage medium according to the present application, and specific examples are applied herein to illustrate the principles and embodiments of the present application, and the above examples are only for aiding in understanding the method and core idea of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. A data transceiving method, comprising:
when receiving a data receiving and transmitting request, the data receiving and transmitting request is sent to an AXI2APB protocol conversion bridge through a central processing unit;
converting the data receiving and transmitting request into an APB protocol instruction through the AXI2APB protocol conversion bridge to obtain an APB protocol instruction;
sending the APB protocol instruction to a preset mode selector through an APB protocol to select a target data read-write mode corresponding to the data receiving-transmitting request based on the bit width of the APB protocol instruction;
and distributing a corresponding number of input/output ports based on the target data read-write mode, connecting the input/output ports to a four-wire serial peripheral interface, and transmitting data to be transmitted corresponding to the data transmit-receive request to the SPI peripheral through the four-wire serial peripheral interface.
2. The data transceiving method according to claim 1, wherein said central processor employs an open source instruction set architecture based on a reduced instruction set principle and has an AXI interface.
3. The data transceiving method according to claim 1, further comprising:
and feeding back a flag signal generated by the SPI peripheral to the preset mode selector so as to replace the current target data read-write mode based on the flag signal.
4. The data transceiving method according to claim 1, wherein the data read-write mode in the preset mode selector comprises a single-wire SPI transceiving mode, a two-wire SPI transceiving mode, a four-wire SPI transceiving mode.
5. The data transceiving method according to claim 1, wherein said allocating a corresponding number of input/output ports based on said target data read-write mode comprises:
and distributing a corresponding number of input/output ports through a tri-state gate output circuit based on the target data read-write mode.
6. The data transceiving method according to claim 5, further comprising:
and controlling the state switch of the tri-state gate output circuit through a read-write type signal in the APB protocol.
7. The data transceiving method according to any of claims 1 to 6, further comprising:
and displaying the data to be transmitted and received through an upper computer connected with the SPI peripheral equipment, and carrying out data interaction.
8. A data transceiver device, comprising:
the first information sending module is used for sending the data receiving and sending request to the AXI2APB protocol conversion bridge through the central processing unit when the data receiving and sending request is received;
the request conversion module is used for converting the data receiving and transmitting request into an APB protocol instruction through the AXI2APB protocol conversion bridge to obtain an APB protocol instruction;
the second information sending module is used for sending the APB protocol instruction to a preset mode selector through an APB protocol so as to select a target data read-write mode corresponding to the data receiving-transmitting request based on the bit width of the APB protocol instruction;
the port allocation module is used for allocating a corresponding number of input/output ports based on the target data read-write mode;
and the port connection module is used for connecting the input/output port to a four-wire serial peripheral interface so as to send the data to be received corresponding to the data receiving and sending request to the SPI peripheral through the four-wire serial peripheral interface.
9. An electronic device comprising a processor and a memory; wherein the processor, when executing the computer program stored in the memory, implements the data transceiving method according to any of claims 1 to 7.
10. A computer-readable storage medium storing a computer program; wherein the computer program when executed by a processor implements the data transceiving method according to any of claims 1 to 7.
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| CN202311094137.3A CN117119074A (en) | 2023-08-29 | 2023-08-29 | Data receiving and transmitting method, device, equipment and storage medium |
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| CN202311094137.3A CN117119074A (en) | 2023-08-29 | 2023-08-29 | Data receiving and transmitting method, device, equipment and storage medium |
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