CN117117012A - Avalanche photodiode and manufacturing method thereof - Google Patents
Avalanche photodiode and manufacturing method thereof Download PDFInfo
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 36
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 230000031700 light absorption Effects 0.000 claims description 27
- 238000001259 photo etching Methods 0.000 claims description 27
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- JGJLWPGRMCADHB-UHFFFAOYSA-N hypobromite Inorganic materials Br[O-] JGJLWPGRMCADHB-UHFFFAOYSA-N 0.000 claims description 9
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
- H01L31/03529—Shape of the potential jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
- H01L31/1844—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
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Abstract
The application relates to the technical field of chip manufacturing, in particular to an avalanche photodiode and a manufacturing method thereof, wherein at least a P-type contact layer, a basic function layer and an N-type contact layer are stacked on a semi-insulating substrate, an N-type electric field control layer and an I-type edge electric field buffer layer are further arranged between the basic function layer and the N-type contact layer, a first step is formed on the side peripheries of the semi-insulating substrate and the P-type contact layer, a second step is formed on the side peripheries of the P-type contact layer and the basic function layer, and a first passivation layer, a second passivation layer and a third passivation layer are sequentially covered on the side peripheries of the basic function layer, the N-type electric field control layer and the I-type edge electric field buffer layer. The application can reduce capacitance and improve bandwidth. In addition, in the process, the problem of under etching in the etching process can be solved, and the reliability of the whole chip can be improved.
Description
Technical Field
The application relates to the technical field of chip manufacturing, in particular to an avalanche photodiode and a manufacturing method thereof.
Background
In an optical fiber communication system of not more than 10Gbps, an optical receiving end chip is widely implemented by Avalanche Photodiodes (APDs), because of its internal gain, higher sensitivity can be obtained, and further distance signal transmission can be realized. However, in the avalanche photodiode design process, one of them cannot be considered unilaterally for all its structures, but rather a comprehensive consideration of its responsivity, bandwidth and gain is required. Wherein the responsivity and bandwidth are mutually constrained, and increasing the bandwidth requires reducing the thickness of the absorption layer and multiplication layer, which in turn results in a reduction in responsivity and an increase in capacitance, which in turn reduces the bandwidth. Therefore, when the optical fiber communication system is developed to 100G and 400G, the structure of the avalanche photodiode in the 10Gbps system is not applicable any more, and for the requirement, the traditional method adopts an evanescent wave detector structure and adopts a waveguide transmission mode to solve the crosstalk between an optical path and a circuit. However, this structure often causes a large difference in the responsivity of the TE and TM modes, resulting in a problem of coupling. And the waveguide mesa requirements for reliability are also unmatched by conventional normal incidence detectors.
In addition, for a conventional avalanche photodiode structure, its epitaxial structure is: n+ -I-P-I-P+ structure. An N-type InP contact layer, an I-type InAlAs multiplication layer, a P-type InP electric field control layer, an I-type InGaAs light absorption layer, an I-type InAlAs cladding layer, an I-type InP cap layer and a P-type InGaAs contact layer are sequentially stacked on an InP-doped Fe semi-insulating substrate by using a molecular beam weather epitaxy deposition (MBE) method. This structure can be used in 100G and 400G optical fiber communication systems, but it also has some drawbacks, such as: PN junction area is larger, the distance between P+N+ junctions is insufficient, so that capacitance is larger, and bandwidth is reduced. In addition, there are some problems in the existing manufacturing process of the avalanche photodiode, such as: the problem of under-etching easily occurs in the etching process; the passivation layer adopts the traditional vulcanization process, and the formed surface is not fine and precise enough.
New avalanche photodiode structures and fabrication processes are urgently needed to solve the above-mentioned problems in today's 100G and 400G systems.
In view of this, overcoming the above-mentioned drawbacks of the prior art is a challenge in the art.
Disclosure of Invention
The application provides an avalanche photodiode and a manufacturing method thereof, which are based on the problems that the PN junction area of the avalanche photodiode is large, the distance between P+N+ junctions is insufficient, the capacitance is large, the bandwidth is reduced, and the underetching easily occurs in the manufacturing process, and the formed surface is not fine and precise. The avalanche photodiode adopts a special P+ -I-N-I-P-I-N+ structure by designing an APD epitaxial wafer of InAlAs/InGaAs material, and can reduce the size of an active region, reduce the capacitance and improve the bandwidth by the special structure. In addition, in the process, a grading platform type corrosion process from outside to inside is adopted, the problem of under corrosion in the corrosion process is solved, and a cadmium sulfide passivation layer is formed to cover the platform type side wall in a twice chemical plating self-assembly mode, so that the reliability of the whole chip is improved.
The application is realized in the following way:
in a first aspect, the present application provides an avalanche photodiode, at least a P-type contact layer, a basic functional layer, and an N-type contact layer are stacked on a semi-insulating substrate, an N-type electric field control layer and an I-type edge electric field buffer layer are further disposed between the basic functional layer and the N-type contact layer, a first step is formed on a side periphery of the semi-insulating substrate and the P-type contact layer, a second step is formed on a side periphery of the P-type contact layer and the basic functional layer, and a first passivation layer, a second passivation layer, and a third passivation layer are sequentially covered on a side periphery of the basic functional layer, the N-type electric field control layer, and the I-type edge electric field buffer layer.
Further, the basic functional layer comprises an I-type light absorption layer, a P-type electric field control layer and an I-type multiplication layer, and specifically, the P-type contact layer, the I-type light absorption layer, the P-type electric field control layer, the I-type multiplication layer, the N-type electric field control layer, the I-type edge electric field buffer layer and the N-type contact layer are sequentially stacked on the semi-insulating substrate in a molecular beam weather epitaxial deposition mode.
Further, the N-type contact layer is disposed on the upper surface of the I-type edge electric field buffer layer and is in an annular structure, the P-type electric field control layer, the I-type multiplication layer, the N-type electric field control layer, the side periphery of the I-type edge electric field buffer layer and the side periphery of the I-type light absorption layer form a third step, the first passivation layer covers the third step, the second passivation layer covers the first passivation layer, the first step and part of the second step, and the third passivation layer covers the second passivation layer.
Further, a silicon nitride medium reflecting layer and a high-reflection metal layer are sequentially arranged at the bottom of the semi-insulating substrate, an N electrode metal contact layer is led out from the N type contact layer, a P electrode metal contact layer is led out from the P type contact layer, and the P electrode metal contact layer extends to the upper surface of the third passivation layer.
Further, the semi-insulating substrate comprises an InP doped Fe semi-insulating substrate, the P-type contact layer comprises a P-type InGaAs contact layer, the I-type light absorption layer comprises an I-type InGaAs light absorption layer, the P-type electric field control layer comprises a P-type InAlAs electric field control layer, the I-type multiplication layer comprises an I-type InAlAs multiplication layer, the N-type electric field control layer comprises an N-type InAlAs electric field control layer, the I-type edge electric field buffer layer comprises an I-type InP edge electric field buffer layer, the N-type contact layer comprises an N-type InGaAs contact layer, the first passivation layer comprises a CdS passivation layer, the second passivation layer comprises a BCB passivation layer, and the third passivation layer comprises a SiN anti-reflection passivation layer.
Further, the doping concentration of the P-type InGaAs contact layer is 1e19cm -3 Thickness is 0.5 μm; the doping concentration of the I type InGaAs light absorption layer is less than 5e15cm -3 A thickness in the range of 0.4 to 0.6 μm; the doping concentration of the P-type InAlAs electric field control layer is 1e18cm -3 A thickness in the range of 0.32 to 0.35 μm; the doping concentration of the I-type InAlAs multiplication layer is less than 5e15cm -3 A thickness in the range of 0.2 to 0.3 μm; the doping concentration of the N-type InAlAs electric field control layer is 1e18cm -3 A thickness in the range of 0.32 to 0.35 μm; the doping concentration of the I-type InP fringe electric field buffer layer is less than 5e15cm -3 A thickness in the range of 1 to 1.5 μm; the doping concentration of the N-type InGaAs contact layer is less than 1e19cm -3 The thickness was 0.15. Mu.m.
In a second aspect, the present application also provides a method for manufacturing an avalanche photodiode, the method comprising:
sequentially stacking a P-type contact layer, an I-type light absorption layer, a P-type electric field control layer, an I-type multiplication layer, an N-type electric field control layer, an I-type edge electric field buffer layer and an N-type contact layer on a semi-insulating substrate in a molecular beam weather epitaxial deposition mode;
forming an annular N-type contact layer through photoetching and corrosion processes, and forming a first step, a second step and a third step of the cylinder platform through photoetching and corrosion processes under the condition of not removing photoresist;
forming a first passivation layer, a second passivation layer and a third passivation layer under photoresist removal by means of photoetching, chemical plating process, passivation process, low-temperature plasma enhanced chemical vapor deposition and etching process, and exposing the P-type contact layer and the N-type contact layer;
forming a P electrode metal contact layer and an N electrode metal contact layer by adopting an electron beam evaporation and stripping process;
forming a silicon nitride medium reflecting layer and a high-reflection metal layer by heat treatment, thinning and polishing, and an enhanced plasma vapor deposition mode and an electron beam evaporation process;
cleaving the wafer to form 300X300 μm 2 Avalanche photodiode chip of (c).
Further, the forming the annular N-type contact layer through photolithography and etching processes, and forming the first step, the second step and the third step of the cylindrical mesa through photolithography and etching processes without photoresist removal specifically includes:
forming an annular N-type contact layer through photoetching and corrosion processes;
forming a first step through photoetching and corrosion processes, specifically: etching the I-type edge electric field buffer layer, the N-type electric field control layer, the I-type multiplication layer, the P-type electric field control layer, the I-type light absorption layer and the P-type contact layer by using a solution of hydrobromic acid, saturated bromine water and water in a ratio of 1:1:1 by using photoresist as a masking film, and stopping in the semi-insulating substrate to form a first step;
the photoresist is not removed, and a second step is formed continuously through photoetching and corrosion processes, specifically: etching the I-type edge electric field buffer layer, the N-type electric field control layer, the I-type multiplication layer, the P-type electric field control layer and the I-type light absorption layer by using a solution of hydrobromic acid, saturated bromine water and water in a ratio of 1:1:1 by using photoresist as a masking film, and stopping at the P-type contact layer to form a second step;
the photoresist is not removed, and a third step is formed continuously through photoetching and corrosion processes, and the method is as follows: and etching the I-type edge electric field buffer layer, the N-type electric field control layer, the I-type multiplication layer and the P-type electric field control layer by using a solution of hydrobromic acid, saturated bromine water and water in a ratio of 1:1:1 by using photoresist as a masking film, and finally stopping in the I-type light absorption layer to form a third step.
Further, forming the first passivation layer, the second passivation layer and the third passivation layer by means of photolithography, a chemical plating process, a passivation process, a low-temperature plasma enhanced chemical vapor deposition and an etching process under the photoresist removal condition, and exposing the P-type contact layer and the N-type contact layer specifically comprises:
photoresist is removed, and a first passivation layer is formed through photoetching and chemical plating processes, specifically: firstly, covering the whole surface of an epitaxial wafer with photoresist through a photoetching process, and leaking out the side wall of a cylindrical table; then placing in ammonium sulfide solution for 40-60min, and then placing in cadmium sulfate solution; drying, removing photoresist, and finally forming a CdS passivation layer of 10-20nm on the side wall;
forming a second passivation layer through photoetching and passivation processes, specifically: spin-coating photosensitive BCB on the surface of an epitaxial wafer, covering the surface of the epitaxial wafer on the side wall and the periphery of a cylinder table through a photoetching process, and passivating for 2 hours in a nitrogen atmosphere at 250 ℃ to form a BCB passivation layer;
formation of the first layer by low temperature plasma enhanced chemical vapor depositionThree passivation layers, specifically: deposition by means of low temperature plasma enhanced chemical vapor depositionA silicon nitride dielectric layer with the thickness to form a SiN anti-reflection passivation layer;
exposing the P-type contact layer and the N-type contact layer through photoetching and etching processes.
Further, the forming the silicon nitride dielectric reflecting layer and the high-reflection metal layer by heat treatment, thinning and polishing, enhanced plasma vapor deposition and electron beam evaporation specifically includes:
the epitaxial wafer is subjected to heat treatment for 1 to 3 minutes at the temperature of 300 to 360 ℃;
thinning and polishing the epitaxial wafer to 150 μm, and depositing on the polished surface of the epitaxial wafer by using an enhanced plasma vapor deposition modeA silicon nitride dielectric reflective layer of a thickness;
forming a Ti/Pt/Au high-reflection metal layer on the silicon nitride medium reflecting layer by adopting an electron beam evaporation process, wherein the thickness of Ti isPt thickness is +.>Au thickness of +.>
Compared with the prior art, the application has the beneficial effects that: by designing an APD epitaxial wafer made of InAlAs/InGaAs material and adopting a special P+ -I-N-I-P-I-N+ structure, the size of an active region can be reduced, the capacitance can be reduced, and the bandwidth can be improved through the special structure. In addition, in the process, a grading platform type corrosion process from outside to inside is adopted, the problem of under corrosion in the corrosion process is solved, and a cadmium sulfide passivation layer is formed to cover the platform type side wall in a twice chemical plating self-assembly mode, so that the reliability of the whole chip is improved.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an epitaxial structure of an avalanche photodiode according to embodiment 1 of the present application;
fig. 2 is a schematic cross-sectional structure of an avalanche photodiode according to embodiment 1 of the present application;
FIG. 3 is a schematic view of the electric field of an avalanche photodiode according to the present application in accordance with embodiment 2 of the present application;
FIG. 4 is a schematic diagram of the electric field of a conventional avalanche photodiode according to embodiment 2 of the present application;
fig. 5 is a flowchart of a method for manufacturing an avalanche photodiode according to embodiment 3 of the present application;
FIG. 6 is a detailed flowchart of step 200 provided in embodiment 3 of the present application;
FIG. 7 is a detailed flowchart of step 300 provided in embodiment 3 of the present application;
fig. 8 is a detailed flowchart of step 500 provided in embodiment 3 of the present application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the description of the present application, the terms "inner", "outer", "longitudinal", "transverse", "upper", "lower", "top", "bottom", etc. refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of describing the present application and do not require that the present application must be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Example 1
As shown in fig. 1, referring to fig. 2, embodiment 1 of the present application provides an avalanche photodiode, at least a P-type contact layer 2, a basic functional layer, and an N-type contact layer 8 are stacked on a semi-insulating substrate 1, an N-type electric field control layer 6 and an I-type edge electric field buffer layer 7 are further disposed between the basic functional layer and the N-type contact layer 8, wherein a first step is formed on a side periphery of the semi-insulating substrate 1 and the P-type contact layer 2, a second step is formed on a side periphery of the P-type contact layer 2 and the basic functional layer, and a first passivation layer 30, a second passivation layer 40, and a third passivation layer 50 are sequentially covered on a side periphery of the basic functional layer, the N-type electric field control layer 6, and the I-type edge electric field buffer layer 7.
In the preferred embodiment, the basic functional layer includes an I-type light absorbing layer 3, a P-type electric field control layer 4, and an I-type multiplication layer 5, specifically, referring to fig. 1, the P-type contact layer 2, the I-type light absorbing layer 3, the P-type electric field control layer 4, the I-type multiplication layer 5, the N-type electric field control layer 6, the I-type edge electric field buffer layer 7, and the N-type contact layer 8 are sequentially stacked on the semi-insulating substrate 1 by a molecular beam weather epitaxy deposition manner, so as to form an epitaxial structure of the avalanche photodiode, that is, a special p+ -I-N-I-P-I-n+ structure.
Referring to fig. 2, in the preferred embodiment, the N-type contact layer 8 is disposed on the upper surface of the I-type edge electric field buffer layer 7 and has a ring structure; the P-type electric field control layer 4, the I-type multiplication layer 5, the N-type electric field control layer 6, the side periphery of the I-type edge electric field buffer layer 7 and the side periphery of the I-type light absorbing layer 3 form a third step, the first passivation layer 30 covers the third step, the second passivation layer 40 covers the first passivation layer 30, the first step and part of the second step, and the third passivation layer 50 covers the second passivation layer 40. Specifically, the first step in this embodiment refers to the upper surface of the part of the semi-insulating substrate 1 that leaks out more than the P-type contact layer 2 in the figure, and the sidewall of the P-type contact layer 2, and the sidewall of the part of the semi-insulating substrate 1 that is connected to the sidewall of the P-type contact layer 2; the second step in this embodiment refers to the upper surface of the P-type contact layer 2 at the portion where more leaks out with respect to the I-type light absorbing layer 3 and the lower half sidewall of the I-type light absorbing layer 3; the second step in this embodiment refers to the upper surface of the P-type electric field control layer 4, the I-type multiplication layer 5, the N-type electric field control layer 6, and the I-type edge electric field buffer layer 7, which are more leaked from the second step, and the upper half sidewall of the I-type light absorption layer 3, and also refers to the sidewalls of the P-type electric field control layer 4, the I-type multiplication layer 5, the N-type electric field control layer 6, and the I-type edge electric field buffer layer 7. In this embodiment, each layer after forming three steps is similar in appearance to a three-layer cylinder mesa, the sidewall of the cylinder mesa is covered with the first passivation layer 30, most of the area of the surface of the first passivation layer 30 and the surface of the chip is covered with the second passivation layer 40, and the surface of the second passivation layer 40 and the photosensitive area of the center of the chip are covered with the third passivation layer 50.
In the preferred embodiment, the bottom of the semi-insulating substrate 1 is sequentially provided with a silicon nitride dielectric reflective layer 20 and a highly reflective metal layer 10, in addition, an N electrode metal contact layer 70 is led out on the N type contact layer 8, a P electrode metal contact layer 60 is led out on the P type contact layer 2, and the P electrode metal contact layer 60 extends to the upper surface of the third passivation layer 50, preferably, the heights of the P electrode metal contact layer 60 and the N electrode metal contact layer 70 are identical.
In the preferred embodiment, the semi-insulating substrate 1 comprises an InP Fe-doped semi-insulating substrate, the P-type contact layer 2 comprises a P-type InGaAs contact layer, the I-type light absorbing layer 3 comprises an I-type InGaAs light absorbing layer, the P-type electric field control layer 4 comprises a P-type inaias electric field control layer, the I-type multiplication layer 5 comprises an I-type inaias multiplication layer, the N-type electric field control layer 6 comprises an N-type inaias electric field control layer, the I-type edge electric field buffer layer 7 comprises an I-type InP edge electric field buffer layer, the N-type contact layer 8 comprises an N-type InGaAs contact layer, the first passivation layer 30 comprises a CdS passivation layer, the second passivation layer 40 comprises a BCB passivation layer, and the third passivation layer 50 comprises a SiN anti-reflection passivation layer.
Specifically, in the preferred embodiment, the doping concentration of the P-type InGaAs contact layer is 1e19cm -3 Thickness is 0.5 μm; the doping concentration of the I type InGaAs light absorption layer is less than 5e15cm -3 A thickness in the range of 0.4 to 0.6 μm; the doping concentration of the P-type InAlAs electric field control layer is 1e18cm -3 A thickness in the range of 0.32 to 0.35 μm; the doping concentration of the I-type InAlAs multiplication layer is less than 5e15cm -3 A thickness in the range of 0.2 to 0.3 μm; the doping concentration of the N-type InAlAs electric field control layer is 1e18cm -3 A thickness in the range of 0.32 to 0.35 μm; the doping concentration of the I-type InP fringe electric field buffer layer is less than 5e15cm -3 A thickness in the range of 1 to 1.5 μm; the doping concentration of the N-type InGaAs contact layer is less than 1e19cm -3 The thickness was 0.15. Mu.m.
In summary, according to the structural design of the embodiment, the APD epitaxial wafer made of the inaias/InGaAs material is designed, and a special p+ -I-N-I-P-I-n+ structure is adopted, so that the size of the active region can be reduced, the capacitance can be reduced, and the bandwidth can be increased through the special structure.
Example 2
Based on the avalanche photodiode provided in the above embodiment 1, the present embodiment 2 is compared with the avalanche photodiode of the conventional structure by the difference in electric field thereof, so as to better explain the advantages of the avalanche photodiode provided in the embodiment of the present application.
Fig. 3 is a schematic diagram of an electric field of an avalanche photodiode according to an embodiment of the present application. A P-type InGaAs contact layer (P-type contact layer 2), an I-type InGaAs light absorption layer (I-type light absorption layer 3), a P-type InAlAs electric field control layer (P-type electric field control layer 4), an I-type InAlAs multiplication layer (I-type multiplication layer 5), an N-type InAlAs electric field control layer (N-type electric field control layer 6), an I-type InP fringe electric field buffer layer (I-type fringe electric field buffer layer 7) and an N-type InGaAs contact layer (N-type contact layer 8) are stacked in sequence on an InP-doped Fe semi-insulating substrate (semi-insulating substrate 1) by a molecular beam epitaxy deposition Method (MBE). The epitaxial structure of the embodiment of the application is a P+ -I-N-I-P-I-N+ structure.
As shown in fig. 4, a schematic diagram of the electric field of a conventional avalanche photodiode is shown. An N-type InP contact layer 12, an I-type InAlAs multiplication layer 13, a P-type InP electric field control layer 14, an I-type InGaAs light absorption layer 15, an I-type InAlAs cladding layer (not shown in the figure for convenience of comparison), an I-type InP cap layer (not shown in the figure for convenience of comparison) and a P-type InGaAs contact layer 16 are sequentially stacked on an InP-doped Fe semi-insulating substrate 11 by using a molecular beam weather epitaxy deposition (MBE). The conventional epitaxial structure is an N+ -I-P-I-P+ structure.
By comparison, the active area of the embodiment of the application is the upper part of the trapezoid area of the broken line in the figure, and the traditional active area is the lower part of the trapezoid area of the broken line in the figure, so that the area of the active area of the upper part of the trapezoid is naturally smaller under the condition that the trapezoids are the same, namely the application can reduce the area of the active area compared with the traditional technology, and further, the reference electric field direction and the electric field intensity direction show, and under the same area of the active area, the structure provided by the embodiment of the application can effectively reduce the PN junction area, thereby reducing the capacitance and improving the bandwidth; in addition, compared with the traditional structure, the structure of the embodiment of the application has more N-type InAlAs electric field control layers and I-type InP fringe electric field buffer layers, increases the distance between P+N+ junctions, reduces the capacitance and improves the bandwidth.
Example 3
Based on the structural description of the avalanche photodiode provided in the present application in embodiment 1, embodiment 3 also provides a method for manufacturing an avalanche photodiode corresponding to the structural description.
As shown in fig. 5, a flowchart of a method for manufacturing an avalanche photodiode according to embodiment 3 is shown. The manufacturing method comprises the following process steps.
Step 100: a P-type contact layer 2, an I-type light absorption layer 3, a P-type electric field control layer 4, an I-type multiplication layer 5, an N-type electric field control layer 6, an I-type edge electric field buffer layer 7 and an N-type contact layer 8 are sequentially stacked on a semi-insulating substrate 1 in a molecular beam weather epitaxial deposition mode. Note that, in this embodiment, corresponding reference numerals of the layers refer to fig. 2 of embodiment 1.
Step 200: the annular N-type contact layer 8 is formed by a photolithography and etching process, and the first step, the second step, and the third step of the cylinder mesa are formed by a photolithography and etching process without photoresist removal.
Step 300: the first passivation layer 30, the second passivation layer 40, and the third passivation layer 50 are formed by photolithography, a chemical plating process, a passivation process, a low temperature plasma enhanced chemical vapor deposition (LPPECVD) and an etching process under photoresist removal, and the P-type contact layer 2 and the N-type contact layer 8 are exposed.
Step 400: the P-electrode metal contact layer 60 and the N-electrode metal contact layer 70 are formed using an electron beam evaporation and stripping process.
Step 500: the silicon nitride dielectric reflective layer 20 and the high reflection metal layer 10 are formed by a heat treatment, thinning and polishing, enhanced plasma vapor deposition (PECVD) and an electron beam evaporation process.
Step 600: cleaving the wafer to form 300X300 μm 2 Avalanche photodiode chip of (c).
As shown in fig. 6, in the present preferred embodiment, for the above step 200, the following steps may be specifically mentioned:
step 201: the annular N-type contact layer 8 (i.e., N-type InGaAs contact layer) is formed by photolithography and etching processes.
Step 202: the first step is formed by a photolithography and etching process. Specific: the photoresist is used as a masking film, and an I-type edge electric field buffer layer 7 (i.e. an I-type InP edge electric field buffer layer), an N-type electric field control layer 6 (i.e. an N-type InAlAs electric field control layer), an I-type multiplication layer 5 (i.e. an I-type InAlAs multiplication layer), a P-type electric field control layer 4 (i.e. a P-type InAlAs electric field control layer), an I-type light absorption layer 3 (i.e. an I-type InGaAs light absorption layer) and a P-type contact layer 2 (i.e. a P-type InGaAs contact layer) are corroded by using a solution with the ratio of hydrobromic acid, saturated bromine water and water of 1:1:1, and finally the photoresist is stopped in a semi-insulating substrate 1 (i.e. an InP-doped Fe semi-insulating substrate) to form a first step.
Step 203: and forming a second step by the photoetching and corrosion process without photoresist removal. Specific: and (3) taking the photoresist as a masking film, corroding the I-type edge electric field buffer layer 7, the N-type electric field control layer 6, the I-type multiplication layer 5, the P-type electric field control layer 4 and the I-type light absorption layer 3 by using a solution of hydrobromic acid, saturated bromine water and water in a ratio of 1:1:1, and finally stopping at the P-type contact layer 2 to form a second step.
Step 204: and forming a third step by the photoetching and corrosion process without photoresist removal. Specific: and (3) taking the photoresist as a masking film, corroding the I-type edge electric field buffer layer 7, the N-type electric field control layer 6, the I-type multiplication layer 5 and the P-type electric field control layer 4 by using a solution of hydrobromic acid, saturated bromine water and water in a ratio of 1:1:1, and finally stopping in the I-type light absorption layer 3 to form a third step.
In the steps, when the first step, the second step and the third step are corroded to form the cylindrical table, the largest step is corroded firstly, the smallest step is corroded finally, photoresist is not removed in the whole photoetching and corrosion process, compared with the traditional method that the small step is corroded firstly, the large step is corroded finally, and the under corrosion site in the corrosion process can be well protected.
As shown in fig. 7, in the present preferred embodiment, for the above step 300, the following steps may be specifically mentioned:
step 301: photoresist is removed and the first passivation layer 30 is formed through photolithography and electroless plating processes. Specific: firstly, covering the whole surface of an epitaxial wafer with photoresist through a photoetching process, and leaking out the side wall of a cylindrical table; then placing in ammonium sulfide solution for 40-60min, and then placing in cadmium sulfate solution; drying, photoresist removing and finally forming a CdS passivation layer with the thickness of 10-20nm on the side wall, namely a first passivation layer 30. The layer process is formed by two-step chemical plating self-assembly, and compared with the traditional vulcanization process, the surface can be formed to be more compact.
Step 302: the second passivation layer 40 is formed through photolithography and passivation processes. Specific: the photosensitive BCB is spin-coated on the surface of the epitaxial wafer, and then covered on the sidewall and the periphery of the cylinder table through a photolithography process, and then passivated in a nitrogen atmosphere at 250 degrees celsius for 2 hours to form the BCB passivation layer, i.e., the second passivation layer 40.
Step 303: by low temperature or the likeThe third passivation layer 50 is formed by ion-enhanced chemical vapor deposition. Specific: deposition by means of low temperature plasma enhanced chemical vapor depositionA silicon nitride dielectric layer is formed to a thickness to form an SiN anti-reflection passivation layer, i.e., the third passivation layer 50.
Step 304: the P-type contact layer 2 and the N-type contact layer 8 are exposed by photolithography and etching processes.
As shown in fig. 8, in the present preferred embodiment, for the above step 500, the following steps may be specifically mentioned:
step 501: the epitaxial wafer is subjected to heat treatment for 1 to 3 minutes at the temperature of 300 to 360 ℃.
Step 502: thinning and polishing the epitaxial wafer to about 150 μm, and depositing on the polished surface of the epitaxial wafer by enhanced plasma vapor depositionA silicon nitride dielectric reflective layer 20 of a thickness.
Step 503: forming a Ti/Pt/Au high-reflection metal layer 10 on the silicon nitride medium reflection layer 20 by adopting an electron beam evaporation process, wherein the thickness of Ti isPt thickness is +.>Au thickness of +.>
It should be noted that the data in all the above steps may have a certain error allowed in the field, and not be completely limited to the precise data.
Through the steps, compared with the prior art, the manufacturing process of the embodiment adopts a grading bench type corrosion process from outside to inside, solves the problem of under corrosion in the corrosion process, adopts a twice chemical plating self-assembly mode to form a cadmium sulfide passivation layer to cover the bench type side wall, and improves the reliability of the whole chip.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the application.
Claims (10)
1. The avalanche photodiode is characterized in that at least a P-type contact layer (2), a basic function layer and an N-type contact layer (8) are stacked on a semi-insulating substrate (1), an N-type electric field control layer (6) and an I-type edge electric field buffer layer (7) are further arranged between the basic function layer and the N-type contact layer (8), a first step is formed on the side periphery of the semi-insulating substrate (1) and the P-type contact layer (2), a second step is formed on the side periphery of the P-type contact layer (2) and the basic function layer, and a first passivation layer (30), a second passivation layer (40) and a third passivation layer (50) are sequentially covered on the side periphery of the basic function layer, the N-type electric field control layer (6) and the I-type edge electric field buffer layer (7).
2. The avalanche photodiode according to claim 1, characterized in that the basic functional layer comprises an I-type light absorbing layer (3), a P-type electric field control layer (4), an I-type multiplication layer (5), in particular the P-type contact layer (2), the I-type light absorbing layer (3), the P-type electric field control layer (4), the I-type multiplication layer (5), the N-type electric field control layer (6), the I-type edge electric field buffer layer (7), the N-type contact layer (8) are stacked on the semi-insulating substrate (1) in sequence by means of molecular beam weather epitaxial deposition.
3. The avalanche photodiode according to claim 2, wherein the N-type contact layer (8) is disposed on the upper surface of the I-type edge electric field buffer layer (7) and has a ring structure, the P-type electric field control layer (4), the I-type multiplication layer (5), the N-type electric field control layer (6), the side periphery of the I-type edge electric field buffer layer (7) and the side periphery of the I-type light absorption layer (3) form a third step, the first passivation layer (30) is covered on the third step, the second passivation layer (40) is covered on the first passivation layer (30), the first step and a part of the second step, and the third passivation layer (50) is covered on the second passivation layer (40).
4. The avalanche photodiode according to any one of claims 1 to 3, wherein a silicon nitride dielectric reflective layer (20) and a highly reflective metal layer (10) are sequentially arranged at the bottom of the semi-insulating substrate (1), an N electrode metal contact layer (70) is led out on the N type contact layer (8), a P electrode metal contact layer (60) is led out on the P type contact layer (2), and the P electrode metal contact layer (60) extends to the upper surface of the third passivation layer (50).
5. An avalanche photodiode according to any of claims 2-3, wherein the semi-insulating substrate (1) comprises an InP-doped Fe semi-insulating substrate, the P-type contact layer (2) comprises a P-type InGaAs contact layer, the I-type light absorbing layer (3) comprises an I-type InGaAs light absorbing layer, the P-type electric field control layer (4) comprises a P-type inaias electric field control layer, the I-type multiplication layer (5) comprises an I-type inaias multiplication layer, the N-type electric field control layer (6) comprises an N-type inaias electric field control layer, the I-type edge electric field buffer layer (7) comprises an I-type InP edge electric field buffer layer, the N-type contact layer (8) comprises an N-type InGaAs contact layer, the first passivation layer (30) comprises a CdS passivation layer, the second passivation layer (40) comprises a BCB passivation layer, and the third passivation layer (50) comprises a SiN antireflective passivation layer.
6. The avalanche photodiode according to claim 5 wherein said P-type InGaAs contact layer has a doping concentration of 1e19cm -3 Thickness is 0.5 μm; the doping concentration of the I type InGaAs light absorption layer is less than 5e15cm -3 A thickness in the range of 0.4 to 0.6 μm; the doping concentration of the P-type InAlAs electric field control layer is 1e18cm -3 A thickness in the range of 0.32 to 0.35 μm; the doping concentration of the I-type InAlAs multiplication layer is less than 5e15cm -3 A thickness in the range of 0.2 to 0.3 μm; the doping concentration of the N-type InAlAs electric field control layer is 1e18cm -3 Thickness of (a)In the range of 0.32 to 0.35 μm; the doping concentration of the I-type InP fringe electric field buffer layer is less than 5e15cm -3 A thickness in the range of 1 to 1.5 μm; the doping concentration of the N-type InGaAs contact layer is less than 1e19cm -3 The thickness was 0.15. Mu.m.
7. A method of fabricating an avalanche photodiode, comprising:
a P-type contact layer (2), an I-type light absorption layer (3), a P-type electric field control layer (4), an I-type multiplication layer (5), an N-type electric field control layer (6), an I-type edge electric field buffer layer (7) and an N-type contact layer (8) are sequentially stacked on a semi-insulating substrate (1) in a molecular beam weather epitaxial deposition mode;
forming an annular N-type contact layer (8) through a photoetching and corrosion process, and forming a first step, a second step and a third step of the cylinder platform through the photoetching and corrosion process under the condition of not removing photoresist;
forming a first passivation layer (30), a second passivation layer (40) and a third passivation layer (50) under the photoresist removal condition by means of photoetching, chemical plating process, passivation process, low-temperature plasma enhanced chemical vapor deposition and etching process, and exposing the P-type contact layer (2) and the N-type contact layer (8);
forming a P electrode metal contact layer (60) and an N electrode metal contact layer (70) by adopting an electron beam evaporation and stripping process;
forming a silicon nitride medium reflecting layer (20) and a high-reflection metal layer (10) through heat treatment, thinning and polishing and an enhanced plasma vapor deposition mode and an electron beam evaporation process;
cleaving the wafer to form 300X300 μm 2 Avalanche photodiode chip of (c).
8. The method for manufacturing an avalanche photodiode according to claim 7, wherein the forming the annular N-type contact layer (8) by photolithography and etching process, and forming the first step, the second step, and the third step of the cylindrical mesa by photolithography and etching process without photoresist removal, specifically comprises:
forming an annular N-type contact layer (8) through photoetching and corrosion processes;
forming a first step through photoetching and corrosion processes, specifically: etching an I-type edge electric field buffer layer (7), an N-type electric field control layer (6), an I-type multiplication layer (5), a P-type electric field control layer (4), an I-type light absorption layer (3) and a P-type contact layer (2) by using a solution with hydrobromic acid, saturated bromine water and water in a ratio of 1:1:1 by using photoresist as a masking film, and finally stopping in a semi-insulating substrate (1) to form a first step;
the photoresist is not removed, and a second step is formed continuously through photoetching and corrosion processes, specifically: etching the I-type edge electric field buffer layer (7), the N-type electric field control layer (6), the I-type multiplication layer (5), the P-type electric field control layer (4) and the I-type light absorption layer (3) by using a solution of hydrobromic acid, saturated bromine water and water in a ratio of 1:1:1 by using photoresist as a masking film, and finally stopping at the P-type contact layer (2) to form a second step;
the photoresist is not removed, and a third step is formed continuously through photoetching and corrosion processes, and the method is as follows: and (3) using the photoresist as a masking film, corroding the I-type edge electric field buffer layer (7), the N-type electric field control layer (6), the I-type multiplication layer (5) and the P-type electric field control layer (4) by using a solution of hydrobromic acid, saturated bromine water and water in a ratio of 1:1:1, and finally stopping in the I-type light absorption layer (3) to form a third step.
9. The method for manufacturing the avalanche photodiode according to claim 7, wherein forming the first passivation layer (30), the second passivation layer (40), the third passivation layer (50) and exposing the P-type contact layer (2) and the N-type contact layer (8) by photolithography, a chemical plating process, a passivation process, a low temperature plasma enhanced chemical vapor deposition process and an etching process under photoresist stripping comprises:
photoresist is removed, and a first passivation layer (30) is formed through photoetching and chemical plating processes, specifically: firstly, covering the whole surface of an epitaxial wafer with photoresist through a photoetching process, and leaking out the side wall of a cylindrical table; then placing in ammonium sulfide solution for 40-60min, and then placing in cadmium sulfate solution; drying, removing photoresist, and finally forming a CdS passivation layer of 10-20nm on the side wall;
forming a second passivation layer (40) by a photolithography and passivation process, in particular: spin-coating photosensitive BCB on the surface of an epitaxial wafer, covering the surface of the epitaxial wafer on the side wall and the periphery of a cylinder table through a photoetching process, and passivating for 2 hours in a nitrogen atmosphere at 250 ℃ to form a BCB passivation layer;
forming a third passivation layer (50) by means of low temperature plasma enhanced chemical vapor deposition, in particular: deposition by means of low temperature plasma enhanced chemical vapor depositionA silicon nitride dielectric layer with the thickness to form a SiN anti-reflection passivation layer;
exposing the P-type contact layer (2) and the N-type contact layer (8) through photoetching and etching processes.
10. The method for manufacturing the avalanche photodiode according to claim 7, wherein the forming the silicon nitride dielectric reflective layer (20) and the high-reflection metal layer (10) by heat treatment, thinning and polishing, enhanced plasma vapor deposition and electron beam evaporation specifically comprises:
the epitaxial wafer is subjected to heat treatment for 1 to 3 minutes at the temperature of 300 to 360 ℃;
thinning and polishing the epitaxial wafer to 150 μm, and depositing on the polished surface of the epitaxial wafer by using an enhanced plasma vapor deposition modeA silicon nitride dielectric reflective layer (20) of a thickness;
forming a Ti/Pt/Au high-reflection metal layer (10) on the silicon nitride medium reflection layer (20) by adopting an electron beam evaporation process, wherein the thickness of Ti isPt thickness is +.>Au thickness of +.>
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