CN110571300B - Epitaxial wafer, planar photodiode and preparation method thereof - Google Patents

Epitaxial wafer, planar photodiode and preparation method thereof Download PDF

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CN110571300B
CN110571300B CN201910708340.2A CN201910708340A CN110571300B CN 110571300 B CN110571300 B CN 110571300B CN 201910708340 A CN201910708340 A CN 201910708340A CN 110571300 B CN110571300 B CN 110571300B
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layer
depletion
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CN110571300A (en
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胡艳
岳爱文
钟行
李晶
李明
马卫东
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Wuhan Telecommunication Devices Co Ltd
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    • H01L31/1844—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P

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Abstract

The embodiment of the invention discloses an epitaxial wafer, which comprises: the epitaxial layer is positioned on the substrate; wherein the substrate comprises an N-type substrate; the epitaxial layer comprises a depletion region compensation layer and an I-type depletion layer which are sequentially positioned on the N-type substrate; the depletion region compensation layer is an N-type doped layer with the doping concentration of 1e16cm‑3To 5e16cm‑3Within the range of (1). In addition, the embodiment of the invention also discloses a planar photodiode, a passive optical network module with gigabit function and a preparation method of the planar photodiode.

Description

Epitaxial wafer, planar photodiode and preparation method thereof
Technical Field
The present invention relates to the field of photoelectric technologies, and in particular, to an epitaxial wafer, a planar photodiode, a passive optical network module having a gigabit function, and a method for manufacturing a planar photodiode.
Background
With The gradual end-To-end sound of 4G Network communication, The competition of Fiber To The Home (FTTH) in The access Network is becoming more and more popular, and The price competition of The Passive Optical Network (PON) which is used in large quantities inside is The first place.
In a 2.5Gbit/s Gigabit-Capable Passive Optical network (GPON), the first generation uses 2.5Gbit/s Avalanche Photodiode (APD) chips; for cost reasons, alternatives to the second generation of 10Gbit/s mesa type photodiode (mesa-type PD) chips in conjunction with super Trans-Impedance amplifiers (super TIA) have been developed in the art.
However, under the condition that the whole procurement cost is still continuously reduced and the demand is continuously reduced, a new technical scheme is urgently needed to greatly reduce the production cost.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide an epitaxial wafer, a planar photodiode, a passive optical network module with gigabit capability, and a method for manufacturing a planar photodiode.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
an embodiment of the present invention provides an epitaxial wafer, including: the epitaxial layer is positioned on the substrate; wherein,
the substrate comprises an N-type substrate;
the epitaxial layer comprises a depletion region compensation layer and an I-type depletion layer which are sequentially positioned on the N-type substrate; the depletion region compensation layer is an N-type doped layer with the doping concentration of 1e16cm-3To 5e16cm-3Within the range of (1).
In the above scheme, the thickness of the depletion region compensation layer ranges from 0.5 to 1.0 μm.
In the above scheme, the I-type depletion layer includes an I-type light absorption layer, and the thickness of the I-type light absorption layer ranges from 3.5 μm to 4.0 μm.
In the foregoing solution, the N-type substrate includes an N-type InP substrate, the depletion region compensation layer includes an N-type InP layer, and the I-type depletion layer includes a first I-type InGaAsP energy band transition layer, an I-type InGaAs light absorption layer, and a second I-type InGaAsP energy band transition layer, which are stacked in sequence.
In the above scheme, the epitaxial layer further includes an I-type cap layer and a P-type contact layer sequentially located on the I-type depletion layer; the doping concentration of the P-type contact layer is more than or equal to 1e19cm-3。
The embodiment of the invention also provides a planar photodiode, which is prepared on the basis of the epitaxial wafer in any one of the schemes, so that the planar photodiode at least comprisesComprises the following steps: the semiconductor device comprises an N-type substrate, an I-type depletion layer and a P-type semiconductor region, wherein the I-type depletion layer and the P-type semiconductor region are sequentially arranged on the N-type substrate; a depletion region compensation layer is further arranged between the N-type substrate and the I-type depletion layer, the depletion region compensation layer is an N-type doped layer, and the doping concentration of the depletion region compensation layer is 1e16cm-3To 5e16cm-3Within the range of (1).
In the above solution, the semiconductor device further includes an annular trench disposed along a direction perpendicular to the N-type substrate, where the annular trench surrounds the P-type semiconductor region;
and spin-on liquid glass SOG materials are filled in the annular grooves.
In the above solution, the semiconductor device further includes an annular trench disposed along a direction perpendicular to the N-type substrate, where the annular trench surrounds the P-type semiconductor region;
the annular grooves comprise a first annular groove and a second annular groove which are distributed along the direction vertical to the N-type substrate, the lower surface of the first annular groove is lower than the lower surface of the P-type semiconductor region, the second annular groove is positioned on the depletion region compensation layer, and the upper surface of the second annular groove is connected with the lower surface of the first annular groove;
the opening size of the first annular groove is larger than that of the second annular groove.
The embodiment of the present invention further provides a passive optical network GPON module with gigabit function, including: a super transimpedance amplifier and a planar photodiode according to any one of the preceding claims.
The embodiment of the invention also provides a preparation method of the planar photodiode, which comprises the following steps:
providing an N-type substrate;
sequentially forming a depletion region compensation layer, an I-type depletion layer and a P-type semiconductor region on the N-type substrate; wherein the depletion region compensation layer is an N-type doped layer with a doping concentration of 1e16cm-3To 5e16cm-3Within the range of (1).
In the above scheme, the thickness of the depletion region compensation layer ranges from 0.5 to 1.0 μm.
In the above scheme, the I-type depletion layer includes an I-type light absorption layer, and the thickness of the I-type light absorption layer ranges from 3.5 μm to 4.0 μm.
In the foregoing solution, the N-type substrate includes an N-type InP substrate, the depletion region compensation layer includes an N-type InP layer, and the I-type depletion layer includes a first I-type InGaAsP energy band transition layer, an I-type InGaAs light absorption layer, and a second I-type InGaAsP energy band transition layer, which are stacked in sequence.
In the above aspect, the forming the P-type semiconductor region includes: and forming an I-shaped cap layer on the second I-shaped InGaAsP energy band transition layer of the I-shaped depletion layer, and forming the P-shaped semiconductor region in the I-shaped cap layer and the second I-shaped InGaAsP energy band transition layer by a diffusion process.
In the above aspect, before forming the P-type semiconductor region, the method further includes:
etching the I-type cap layer and the I-type depletion layer to form an annular groove, wherein the annular groove surrounds the preset forming position of the P-type semiconductor region;
and filling spin-on liquid glass SOG materials in the annular groove.
In the above aspect, before forming the P-type semiconductor region, the method further includes:
etching the I-type cap layer and the I-type depletion layer by adopting a first wet etching process to form a first annular groove, wherein the first annular groove is terminated in the I-type InGaAs light absorption layer;
continuously etching the I-type depletion layer along the first annular groove by adopting a second wet etching process to form a second annular groove, wherein the second annular groove is terminated on the depletion region compensation layer;
the opening size of the first annular groove is larger than that of the second annular groove.
In the above scheme, the etching solution used in the first wet etching process includes hydrobromic acid: saturated bromine water: 1:1:1 mixed solution of water; the etching solution used in the second wet etching process comprises concentrated sulfuric acid: hydrogen peroxide: water is a mixed solution of 1:1: 5.
In the above-mentioned scheme, the first step of the method,the method further comprises the following steps: forming a P-type contact layer with the doping concentration of 1e19cm or more-3(ii) a The P-type contact layer is located at a position conductively connected with the P-type semiconductor region.
In the above scheme, the P-type contact layer is formed by a Metal Organic Chemical Vapor Deposition (MOCVD) process.
The epitaxial wafer, the planar photodiode, the passive optical network module with the gigabit function, and the method for manufacturing the planar photodiode provided by the embodiments of the present invention include: the epitaxial layer is positioned on the substrate; wherein the substrate comprises an N-type substrate; the epitaxial layer comprises a depletion region compensation layer and an I-type depletion layer which are sequentially positioned on the N-type substrate; the depletion region compensation layer is an N-type doped layer with the doping concentration of 1e16cm-3To 5e16cm-3Within the range of (1); thus, the depletion region compensation layer can play a role of buffering between the N-type substrate and the I-type depletion layer; more importantly, by setting the doping concentration at 1e16cm-3To 5e16cm-3The depletion region compensation layer within the range of (1) increases the thickness of the depletion region, reduces the capacitance of the planar photodiode prepared based on the epitaxial wafer, and avoids the problem of dark current increase caused by increasing the thickness of the I-type depletion layer while improving the responsivity. The planar photodiode in the embodiment of the invention has the advantages of high responsivity, low dark current, low parasitic capacitance and the like, thereby providing possibility for replacing the mesa photodiode to be matched with the super trans-impedance amplifier so as to meet the requirement of a receiving chip of a 2.5Gbit/s GPON module and providing a solution for reducing the production cost.
Drawings
Fig. 1 is a schematic cross-sectional view illustrating a planar photodiode according to an embodiment of the present invention;
fig. 2 is a schematic structural cross-sectional view of an epitaxial wafer according to an embodiment of the present invention;
fig. 3 is a schematic flow chart illustrating a method for fabricating a planar photodiode according to an embodiment of the present invention;
fig. 4a to 4h are schematic cross-sectional views of device structures in a manufacturing process of a planar photodiode according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In the second generation 2.5Gbit/s GPON, the key point of the scheme that the mesa type photodiode chip is matched with the super trans-impedance amplifier is as follows: 1. the responsivity of the mesa photodiode is generally more than 1.0A/W, and the dark current is generally less than 1 nA; 2. the capacitance of the mesa photodiode is less than 0.2 pF; thus, the super transimpedance amplifier can be matched. In response to these two requirements, the inventors of the present invention want to design a low-cost planar photodiode chip that can replace a mesa photodiode, so as to reduce the cost of the GPON module.
The planar photodiode chip generally needs to increase the thickness of the absorption layer in the I region to improve the responsivity, but the increase of the thickness of the absorption layer in the I region brings about the increase of dark current; in addition, the parasitic capacitance of the conventional planar photodiode chip is large. The above problems are all key problems that the planar photodiode chip cannot be matched with the super trans-impedance amplifier, and thus the planar photodiode chip is applied to a GPON module.
In view of the above, it is desirable to provide a planar photodiode that can increase the total thickness of the depletion region of the device without changing the thickness of the I-region absorption layer. For ease of understanding, the following description is made with specific reference to fig. 1. As shown, the planar photodiode includes: the semiconductor device comprises an N-type substrate 100, and an I-type depletion layer 120 and a P-type semiconductor region 170 which are sequentially arranged on the N-type substrate 100; wherein a depletion region compensation layer 110 is further included between the N-type substrate 100 and the I-type depletion layer 120, the depletion region compensation layer 110 is an N-type doped layer, and the doping concentration thereof is 1e16cm-3To 5e16cm-3Within the range of (1).
Before providing the planar photodiode, an epitaxial wafer may be provided first, so as to obtain an embodiment of manufacturing the planar photodiode based on the epitaxial wafer. Fig. 2 is a schematic structural cross-sectional view of an epitaxial wafer according to an embodiment of the present invention; as shown, the epitaxial wafer includes: a substrate 200, and an epitaxial layer on the substrate 200; wherein, theThe substrate comprises an N-type substrate; the epitaxial layer comprises a depletion region compensation layer 210 and an I-type depletion layer 220 which are sequentially positioned on the N-type substrate; the depletion region compensation layer 210 is an N-type doped layer with a doping concentration of 1e16cm-3To 5e16cm-3Within the range of (1).
In an alternative embodiment, the substrate 200 comprises an N-type InP substrate with a doping concentration of, for example, 1e19cm-3That is, the substrate 200 is specifically an N + + type InP substrate.
In an alternative embodiment, the depletion region compensation layer 210 comprises an N-type InP layer; the doping concentration of the depletion region compensation layer 210 is 1e16cm-3To 5e16cm-3In the range of (1), the N-type InP layer is specifically an N-type InP layer, so that not only a buffer effect between the N-type substrate 100 and the I-type depletion layer 120 can be achieved, but also the thickness of the depletion region can be increased. As shown in fig. 2, the depletion region compensation layer 210 is in direct contact with the I-type depletion layer 220, and no other structural layer is included in the middle. In one embodiment, the thickness of the depletion region compensation layer 210 ranges from 0.5 μm to 1.0 μm.
In an alternative embodiment, the I-type depletion layer 220 comprises an I-type light absorbing layer having a thickness in the range of 3.5 to 4.0 μm. It should be understood that in the I-type depletion layer 220, the I-type light absorbing layer is the most dominant structural layer portion thereof, and is also the portion of the device that mainly provides the depletion region; in some embodiments, the type I depletion layer 220 may include not only the type I light absorbing layer but also some other auxiliary layers, such as an energy band transition layer; in other embodiments, the I-type depletion layer 220 may also include only the I-type light absorbing layer.
As a specific embodiment, the I-type depletion layer 220 may include a first I-type InGaAsP energy band transition layer 221, an I-type InGaAs light absorption layer 222, and a second I-type InGaAsP energy band transition layer 223 sequentially stacked; the doping concentration of the three layers is less than 5e15cm, for example, as an intrinsic semiconductor layer-3(ii) a The thickness of the first I-type InGaAsP band transition layer 221 and the second I-type InGaAsP band transition layer 223 is, for example, in a range of 0.03 to 0.045 μm; the thickness of the I-type InGaAs light absorption layer 222 ranges from 3.5 to 4.0 μm, for example.
In an alternative embodiment, the epitaxial layer further comprises an I-type cap layer 230 on the I-type depletion layer 220; the I-cap layer 230 may include an I-InP layer; as an intrinsic semiconductor layer, the doping concentration of the I-type cap layer 230 is less than 5e15cm, for example-3(ii) a The thickness thereof is, for example, in the range of 0.5 to 1.0 μm.
In an alternative embodiment, the epitaxial layer further includes a P-type contact layer 240 on the I-type cap layer 230; the doping concentration of the P-type contact layer 240 is more than or equal to 1e19cm-3。
It is understood that the P-type contact layer 240 is embodied as a P + + type contact layer. The material of the P-type contact layer 240 includes, for example, P-type InGaAs; the thickness ranges from 0.1 to 0.15 μm. The P-type contact layer 240 is formed through an MOCVD process.
In an alternative embodiment, the depletion region compensation layer 210, the first I-type InGaAsP energy band transition layer 221, the I-type InGaAs light absorption layer 222, the second I-type InGaAsP energy band transition layer 223, the I-type cap layer 230, and the P-type contact layer 240 may be sequentially stacked on the substrate 200 by using an MOCVD process.
The epitaxial wafer provided by the embodiment is applied to the preparation of a planar photodiode, for example.
Next, a planar photodiode according to an embodiment of the present invention will be further explained.
It is understood that the planar photodiode provided by the embodiment of the present invention may be prepared based on the epitaxial wafer according to any of the above embodiments, so that the planar photodiode at least includes the following structure: the semiconductor device comprises an N-type substrate, an I-type depletion layer and a P-type semiconductor region, wherein the I-type depletion layer and the P-type semiconductor region are sequentially arranged on the N-type substrate; a depletion region compensation layer is further arranged between the N-type substrate and the I-type depletion layer, the depletion region compensation layer is an N-type doped layer, and the doping concentration of the depletion region compensation layer is 1e16cm-3To 5e16cm-3Within the range of (1).
In an alternative embodiment, the N-type substrate 100 comprises an N-type InP substrate with a doping concentration of, for example, 1e19cm-3That is, the N-type substrate 100 is specifically an N + + type InP substrate.
In an alternative embodiment, the depletion region compensation layer 110 comprises an N-type InP layer; the doping concentration of the depletion region compensation layer 110 is 1e16cm-3To 5e16cm-3In the range of (1), the N-type InP layer is specifically an N-type InP layer, so that not only a buffer effect between the N-type substrate 100 and the I-type depletion layer 120 can be achieved, but also the thickness of the depletion region can be increased. As shown in fig. 1, the depletion region compensation layer 110 is in direct contact with the I-type depletion layer 120, and no other structural layer is included in the middle. In one embodiment, the thickness of the depletion region compensation layer 110 is in a range of 0.5 to 1.0 μm.
In an alternative embodiment, the I-type depletion layer 120 includes an I-type light absorbing layer having a thickness in the range of 3.5 to 4.0 μm. It should be understood that in the I-type depletion layer 120, the I-type light absorbing layer is the most dominant structural layer portion thereof, and is also the portion of the device that mainly provides the depletion region; in some embodiments, the type I depletion layer 120 may include not only the type I light absorbing layer but also some other auxiliary layers, such as an energy band transition layer; in other embodiments, the I-type depletion layer 120 may also include only the I-type light absorbing layer.
When the thickness of the depletion region compensation layer 110 is in the range of 0.5 to 1.0 μm and the thickness of the I-type light absorption layer is in the range of 3.5 to 4.0 μm, the total thickness of the depletion region of the planar photodiode provided by the embodiment of the present invention can reach 4.0 to 5.0 μm (in the embodiment where the I-type depletion layer 120 further includes an energy band transition layer, the thickness of the energy band transition layer is generally negligible); thus, the thickness of the depletion region of the device can be increased without increasing the thickness of the light absorption layer by arranging the depletion region compensation layer.
As a specific embodiment, the I-type depletion layer 120 may include a first I-type InGaAsP energy band transition layer 121, an I-type InGaAs light absorbing layer 122, and a second I-type InGaAsP energy band transition layer 123 stacked in this order; the doping concentration of the three layers is less than 5e15cm, for example, as an intrinsic semiconductor layer-3(ii) a The thickness of the first I-type InGaAsP band transition layer 121 and the second I-type InGaAsP band transition layer 123 is, for example, in the range of 0.03 to 0.045 μm; the thickness of the I-type InGaAs light absorption layer 122 ranges from 3.5 to 4.0 μm, for example.
In an alternative embodiment, the planar photodiode further includes: and the I-type cap layer 130 is positioned on the second I-type InGaAsP energy band transition layer 123. The I-type cap layer 130 may include an I-type InP layer; as an intrinsic semiconductor layer, the doping concentration of the I-type cap layer 130 is, for example, less than 5e15cm-3(ii) a The thickness thereof is, for example, in the range of 0.5 to 1.0 μm.
The P-type semiconductor region 170 may be formed in the I-type cap layer 130 and the second I-type InGaAsP energy band transition layer 123 through a diffusion process. To form the P-type semiconductor region 170, the planar photodiode may further include a diffusion barrier layer 160 on the I-type cap layer 130, the diffusion barrier layer 160 having an opening exposing a predetermined formation location of the P-type semiconductor region 170. The diffusion barrier layer 160 has a thickness in the range of, for example
Figure BDA0002152891030000101
The material thereof includes, for example, silicon dioxide. It is understood that the cross-sectional shape of the P-type semiconductor region 170 is circular; the diameter of the circle may gradually decrease with the depth of doping, that is, the cross-sectional area of the P-type semiconductor region 170 gradually decreases in a direction close to the N-type substrate 100; the cross-sectional area of the P-type semiconductor region 170 at the upper surface of the I-type cap layer 130 may be larger than the open area of the diffusion barrier layer 160.
In an alternative embodiment, the planar photodiode further includes: and the annular groove 150 is arranged along the direction vertical to the N-type substrate 100, and the annular groove 150 surrounds the P-type semiconductor region 170. It can be understood that since a reverse bias voltage is applied when the planar photodiode operates, the P-type semiconductor region 170 will expand (or laterally expand) in the lateral direction while forming a PN junction with the bottom N-type substrate 100 under the action of the reverse bias voltage, thereby generating a non-negligible parasitic capacitance; the annular groove is arranged for isolating, so that parasitic capacitance can be well reduced, and the working reliability of the device is ensured.
The annular groove 150 is filled with spin-on liquid glass (SOG) material. As can be understood, the SOG material has good filling property and can endure high-temperature diffusion at 500 ℃ compared with the traditional polyimide and other materials; on the other hand, the dielectric constant of the SOG material is larger, so that the diffusion isolation can be better realized, and the parasitic capacitance is reduced. Therefore, the SOG material is filled in the annular groove, and compared with other dielectric materials, the SOG material has the advantages of simple process, low cost, good isolation, strong high-temperature diffusion resistance and the like.
The annular trench 150 is located at a distance 1703-5 μm from the P-type semiconductor region; i.e., in a direction parallel to the N-type substrate 100, the distance between the ring-shaped trench 150 and the P-type semiconductor region 170 is in a range of 3-5 μm.
It is understood that the depth of the ring-shaped trench 150 is greater than the depth of the P-type semiconductor region 170 in order to better achieve diffusion cutoff.
In an embodiment, the annular trench 150 may include a first annular trench 151 and a second annular trench 152 distributed along a direction perpendicular to the N-type substrate 100, a lower surface of the first annular trench 151 is lower than a lower surface of the P-type semiconductor region 170, the second annular trench 152 is located on the depletion region compensation layer 110, and an upper surface thereof is connected to the lower surface of the first annular trench 151; the opening size of the first annular groove 151 is larger than the opening size of the second annular groove 152.
Since the required annular trench 150 has a larger aspect ratio, the annular trench 150 tends to have a larger etching difficulty when being formed, and by forming an annular trench structure in which the opening size of the first annular trench 151 is larger than the opening size of the second annular trench 152 (i.e., the upper portion is wider than the lower portion is narrower), the control of the etching liquid in the trench can be facilitated; in addition, the lower surface of the first annular trench 151 is lower than the lower surface of the P-type semiconductor region 170 to ensure an isolation effect; as an embodiment, the first annular trench 151 may terminate within the I-type InGaAs light absorption layer 122, and since the thickness of the I-type InGaAs light absorption layer 122 is relatively large, the etching depth control for the first annular trench 151 is easier; the second ring-shaped trench 152 is terminated on the depletion region compensation layer 110, and due to the etching selection ratio difference caused by the different materials of the depletion region compensation layer 110 and the I-type depletion layer 120, the required etching of the ring-shaped trench 150 can be completed by using the depletion region compensation layer 110 as an etching barrier layer.
In an alternative embodiment, the planar photodiode further includes: a P-type contact layer 140 conductively connected to the P-type semiconductor region 170, the P-type contact layer 140 having a doping concentration of 1e19cm or more-3。
It is understood that the P-type contact layer 140 is embodied as a P + + type contact layer. The P-type contact layer is formed by diffusion, and the concentration of diffusion doping is only 1e18cm-3To 5e18cm-3Resulting in a device forward resistance of around 20 ohms; in the embodiment of the present application, the doping concentration of the P-type contact layer 140 is greater than or equal to 1e19cm-3The forward resistance can be effectively reduced (can be reduced to 10 ohms), and the matching with the super trans-impedance amplifier is facilitated; the P-type contact layer 140 in the embodiment of the present application is formed by a Metal-Organic Chemical Vapor Deposition (MOCVD) process.
In an alternative embodiment, the depletion region compensation layer 110, the first I-type InGaAsP energy band transition layer 121, the I-type InGaAs light absorption layer 122, the second I-type InGaAsP energy band transition layer 123, or the I-type cap layer 130 may be formed by using an MOCVD process.
The material of the P-type contact layer 140 includes, for example, P-type InGaAs; its thickness ranges from 0.1 to 0.15 μm; the P-type contact layer 140 may be ring-shaped.
In an alternative embodiment, the planar photodiode further includes: a P-type contact metal layer 191, the P-type contact metal layer 191 being in ohmic contact with the P-type contact layer 140. In one embodiment, the P-type contact metal layer 191 covers the P-type contact layer 140.
In an alternative embodiment, the planar photodiode further includes: an anti-reflection layer 180, wherein the anti-reflection layer 180 is at least located on the P-type semiconductor region 170 to play a role in anti-reflection and increasing light transmission; the anti-reflection layer 180 covers at least the central region of the P-type semiconductor region 170, which isIn addition, the anti-reflection layer 180 may also be located on the diffusion barrier layer 160. The material of antireflective layer 180 may include silicon nitride; the thickness range of which is, for example
Figure BDA0002152891030000124
In an alternative embodiment, the planar photodiode further includes: an N-type contact metal layer 192, the N-type contact metal layer 192 forming an ohmic contact with the N-type substrate 100. In one embodiment, the N-type contact metal layer 192 is located below the N-type substrate 100. The N-type contact metal layer 192 may be formed of Ti, for example
Figure BDA0002152891030000121
/Pt
Figure BDA0002152891030000122
/Au
Figure BDA0002152891030000123
And (4) forming. The reflectivity of the contact metal layer is 75% through testing, and the responsivity of the photodiode can be improved from 0.61A/W to 0.75A/W for an InGaAs light absorption layer with the thickness of 1.0 um.
In the embodiment of the invention, while the thickness of the I-type depletion layer (mainly the I-type InGaAs light absorption layer) is ensured, the lightly doped depletion region compensation layer is designed, the thickness of the depletion region is increased, and the dark current of the drift hole energy production of the light absorption layer is reduced. The doping concentration of the depletion region compensation layer is set to be 1e16cm-3To 5e16cm-3Mainly in view of: on one hand, in a 2.5Gbit/s GPON module, the capacitance of a photodiode must be less than 0.2pF to match with a super transimpedance amplifier, for the photodiode with the photosensitive surface diameter of 55 μm and the depletion layer thickness of 4 μm, the junction capacitance is generally 0.135pF, the parasitic capacitance is generally 0.05pF, and therefore the capacitance of the photodiode is about 0.185 pF; by calculation, this condition can be satisfied only if the thickness of the depletion layer is close to 4 μm or greater than 4 μm; on the other hand, it is also necessary to ensure that the responsivity of the photodiode is as large as possible above 1A/WWhen the In component of the InGaAs material is 0.43, the absorption coefficient of light with a wavelength of 1.55 μm is 7000cm-1When the thickness of the light absorption layer is 3.5 μm, the responsivity is close to 1A/W, and the thickness of the light absorption layer is generally selected to be increased in the field in order to improve the responsivity; however, since an increase in the thickness of the light-absorbing layer increases the dark current, the thickness of the light-absorbing layer can be only in the range of 3.5 to 4.0 μm in order to control the magnitude of the dark current. The embodiment of the invention sets the doping concentration to be 1e16cm-3To 5e16cm-3The depletion region compensation layer within the range of (1) increases the thickness of the depletion region under the condition of not changing the thickness of the light absorption layer, improves the responsivity, simultaneously avoids the problem of dark current increase caused by the drift holes of the capacity of the light absorption layer, and reduces the capacitance of the planar photodiode. In addition, the annular groove surrounding the P-type semiconductor region is arranged, so that the problem of parasitic capacitance caused by transverse diffusion is avoided; the annular groove is filled with the SOG material, so that the filling property is good, the high-temperature diffusion resistance is strong, the isolation property is good, the process is simple, and the cost is low; the annular groove is arranged to be in a shape of being wide at the top and narrow at the bottom, the preparation process is simple, and the controllability is good; the P-type contact layer is formed by MOCVD process, and the doping concentration can reach 1e19cm-3Above, the forward resistance is effectively reduced; the N-type contact metal layer adopts Ti
Figure BDA0002152891030000131
/Pt
Figure BDA0002152891030000132
/Au
Figure BDA0002152891030000133
Further providing the responsivity of the photodiode.
In summary, the planar photodiode provided in the embodiments of the present invention has the advantages of high responsivity, low dark current, low parasitic capacitance, and the like, thereby providing a possibility for replacing a mesa photodiode with a super transimpedance amplifier to meet the requirement of a receiving chip of a 2.5Gbit/s GPON module, the planar photodiode can be prepared by a process similar to a conventional planar PD, the characteristics of high reliability, simple process, low cost, and the like of the planar photodiode are retained, and a solution is provided for the cost problem of a 2.5Gbit/s APD chip and a 10Gbit/s mesa-type PD chip in current use.
On this basis, an embodiment of the present invention further provides a GPON module, including: a super transimpedance amplifier and a planar photodiode according to any of the embodiments of the present invention.
In addition, the embodiment of the invention also provides a preparation method of the planar photodiode; refer specifically to FIG. 3. As shown, the method comprises the steps of:
step 301, providing an N-type substrate;
step 302, sequentially forming a depletion region compensation layer, an I-type depletion layer and a P-type semiconductor region on the N-type substrate; wherein the depletion region compensation layer is an N-type doped layer with a doping concentration of 1e16cm-3To 5e16cm-3Within the range of (1).
The planar photodiode and the method for fabricating the planar photodiode according to the present invention will be further described in detail with reference to the schematic cross-sectional views of the device structures in the process of fabricating the planar photodiode in fig. 4a to 4 h.
First, please refer to fig. 4 a. Providing an N-type substrate 400; as an embodiment, the N-type substrate 400 comprises an N-type InP substrate with a doping concentration of, for example, 1e19cm-3That is, the N-type substrate 400 is specifically an N + + type InP substrate.
A depletion region compensation layer 410, an I-type depletion layer 420, and an I-type cap layer 430 are sequentially formed on the N-type substrate 400.
In an alternative embodiment, the depletion region compensation layer 410 comprises an N-type InP layer; the doping concentration of the depletion region compensation layer 410 is 1e16cm-3To 5e16cm-3In the range of (1), the N-type InP layer is specifically an N-type InP layer, so that not only a buffer action between the N-type substrate 400 and the I-type depletion layer 420 can be performed, but also the thickness of the depletion region can be increased. As shown, the depletion region compensation layer 410 is in direct contact with the I-type depletion layer 420, and no other structural layer is included therebetween. In one embodimentThe thickness of the depletion region compensation layer 410 ranges from 0.5 to 1.0 μm.
In an alternative embodiment, the I-type depletion layer 420 includes an I-type light absorbing layer having a thickness in the range of 3.5 to 4.0 μm. It should be understood that in the I-type depletion layer 420, the I-type light absorbing layer is the most dominant structural layer portion thereof, and is also the portion of the device that mainly provides the depletion region; in some embodiments, the type I depletion layer 420 may include not only the type I light absorbing layer, but also some other auxiliary layers, such as an energy band transition layer; in other embodiments, the I-type depletion layer 420 may also include only the I-type light absorbing layer.
When the thickness of the depletion region compensation layer 410 is in the range of 0.5 to 1.0 μm and the thickness of the I-type light absorption layer is in the range of 3.5 to 4.0 μm, the total thickness of the depletion region of the planar photodiode provided by the embodiment of the present invention can reach 4.0 to 5.0 μm (in the embodiment where the I-type depletion layer 420 further includes an energy band transition layer, the thickness of the energy band transition layer is generally negligible); thus, the thickness of the depletion region of the device can be increased without increasing the thickness of the light absorption layer by arranging the depletion region compensation layer.
In an alternative embodiment, the I-type depletion layer 420 may include a first I-type InGaAsP energy band transition layer 421, an I-type InGaAs light absorption layer 422, and a second I-type InGaAsP energy band transition layer 423, which are stacked in sequence; the doping concentration of the three layers is less than 5e15cm, for example, as an intrinsic semiconductor layer-3(ii) a The thickness of the first I-type InGaAsP band transition layer 421 and the second I-type InGaAsP band transition layer 423 is, for example, 0.03 to 0.045 μm; the thickness of the I-type InGaAs light absorption layer 422 ranges from 3.5 to 4.0 μm, for example.
In an alternative embodiment, the I-type cap layer 430 may include a type I InP layer; the doping concentration of the I-type cap layer 430 is, for example, less than 5e15cm as an intrinsic semiconductor layer-3(ii) a The thickness thereof is, for example, in the range of 0.5 to 1.0 μm.
In an optional embodiment, the method further comprises: forming a P-type contact layer 440 on the I-type cap layer 230, wherein the doping concentration of the P-type contact layer 440 is 1e19cm or more-3。
It is understood that the P-type contact layer 440 is embodied as a P + + type contact layer. The material of the P-type contact layer 440 includes, for example, P-type InGaAs; the thickness ranges from 0.1 to 0.15 μm. The P-type contact layer 440 is formed through an MOCVD process.
In an alternative embodiment, the depletion region compensation layer 410, the first I-type InGaAsP energy band transition layer 421, the I-type InGaAs light absorption layer 422, the second I-type InGaAsP energy band transition layer 423, the I-type cap layer 430, and the P-type contact layer 440 may be sequentially stacked on the N-type substrate 400 by using an MOCVD process.
As an implementation manner, the preparation of the planar photodiode provided by the embodiment of the present invention may be completed by using the epitaxial wafer provided by the foregoing embodiment of the present invention.
Next, please continue to refer to fig. 4 a. The P-type contact layer 440 is patterned by photolithography and etching processes to form an annular P-type contact layer required by design.
Next, please refer to fig. 4b to fig. 4 d. Etching the I-type cap layer 430 and the I-type depletion layer 420 to form an annular groove 450, wherein the annular groove 450 surrounds the preset forming position of the P-type semiconductor region; the annular trench 450 is filled with an SOG material.
In an alternative embodiment, as shown in fig. 4b, a first wet etching process is used to etch the I-type cap layer 430 and the I-type depletion layer 420 to form a first annular trench 451, and the first annular trench 451 is terminated in the I-type InGaAs light absorbing layer 422.
As an embodiment, the etching solution used in the first wet etching process includes hydrobromic acid: saturated bromine water: water is a mixed solution of 1:1: 1. It is to be understood that, before the first wet etching process, the method may further include a photolithography step of forming a patterned photoresist mask layer by exposure-development, the photoresist mask layer exposing a predetermined formation position of the first annular trench 451; and then, the etching solution is used for etching the I-type cap layer 430, the second I-type InGaAsP energy band transition layer 423 and the I-type InGaAs light absorption layer 422 to form the first annular groove 451.
Next, referring to fig. 4c, a second wet etching process is used to continuously etch the I-type depletion layer 420 along the first annular trench 451 to form a second annular trench 452, wherein the second annular trench 452 terminates on the compensation layer of the depletion region 410; the opening size of the first annular groove 451 is larger than the opening size of the second annular groove 452.
As an embodiment, the etching solution used in the second wet etching process includes concentrated sulfuric acid: hydrogen peroxide: water is a mixed solution of 1:1: 5. The etching solution has a large difference in etching rate between the I-type depletion layer 420 and the depletion region compensation layer 410, so that the second wet etching process is terminated on the depletion region compensation layer 410 based on the material difference.
It can be understood that the annular groove 450 is formed with a larger etching difficulty due to a larger aspect ratio of the required annular groove 450, and the control of the etching liquid in the groove can be facilitated by forming an annular groove structure with the opening size of the first annular groove 451 being larger than the opening size (i.e. wider at the top and narrower at the bottom) of the second annular groove 452; in addition, the first annular trench 451 terminates within the I-type InGaAs light absorption layer 422 to ensure isolation effect; since the thickness of the I-type InGaAs light absorbing layer 422 is relatively large, the etching depth control for the first annular groove 451 is easier; by utilizing the etching selection ratio difference caused by the different materials of the depletion region compensation layer 410 and the I-type depletion layer 420, the required etching of the annular trench 450 can be completed by using the depletion region compensation layer 410 as an etching barrier layer; in addition, when the I-type cap layer 430 and the depletion region compensation layer 410 both comprise I-type InP layers, the I-type cap layer 430 on the sidewall of the first annular groove 451 is not corroded by the etching liquid used for etching the second annular groove 452.
In an alternative embodiment, the distance between the annular trench 450 (specifically the first annular trench 451) and the P-type semiconductor region along the direction parallel to the N-type substrate 400 is in the range of 3-5 μm.
Next, please refer to fig. 4 d. The ring-shaped trench 450 is filled with an SOG material by using a spin coating method.
As can be understood, the SOG material has good filling property and can endure high-temperature diffusion at 500 ℃ compared with the traditional polyimide and other materials; on the other hand, the dielectric constant of the SOG material is larger, so that the diffusion isolation can be better realized, and the parasitic capacitance is reduced. Therefore, the SOG material is filled in the annular groove, and compared with other dielectric materials, the SOG material has the advantages of simple process, low cost, good isolation, strong high-temperature diffusion resistance and the like.
In an optional embodiment, the method further comprises: cleaning to remove the excessive SOG material on the surface; and passivating for 2 hours in a nitrogen atmosphere at the temperature of 600 ℃.
Next, please refer to fig. 4 e. A diffusion barrier layer 460 is formed on the I-type cap layer 430, and the diffusion barrier layer 460 has an opening exposing a predetermined formation location of the P-type semiconductor region. As an embodiment, the type I cap layer 430 may be formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process; the diffusion barrier layer 460 may have a thickness in the range of, for example
Figure BDA0002152891030000171
The material thereof includes, for example, silicon dioxide. The opening of the diffusion barrier 460 may be formed by a process of photolithography and etching.
Next, please continue to refer to fig. 4 e. A P-type semiconductor region 470 is formed. In one embodiment, the P-type semiconductor region 470 is formed in the I-type cap layer 430 and the second I-type InGaAsP energy band transition layer 423 by a diffusion process. It is understood that the cross-sectional shape of the P-type semiconductor region 470 is circular; the diameter of the circle may gradually decrease with the depth of doping, that is, the cross-sectional area of the P-type semiconductor region 470 gradually decreases in the direction close to the N-type substrate 400; the cross-sectional area of the P-type semiconductor region 470 at the upper surface of the I-type cap layer 430 may be greater than the open area of the diffusion barrier layer 460.
Next, please continue to refer to fig. 4 f. An anti-reflection layer 480 is formed. The anti-reflection layer 480 is at least located on the P-type semiconductor region 470 to perform the functions of anti-reflection and increasing light transmission(ii) a The anti-reflection layer 480 covers at least the central region of the P-type semiconductor region 470, and the anti-reflection layer 480 may also be located on the diffusion barrier layer 460. The material of antireflective layer 480 may comprise silicon nitride. The anti-reflection layer 480 may be formed by a PECVD process; the thickness range of which is, for example
Figure BDA0002152891030000172
Next, please continue to refer to fig. 4 f. The annular P-type contact layer 440 is exposed again by photolithography and etching processes.
Next, please continue to refer to fig. 4 g. A P-type contact metal layer 491 is formed, which is in ohmic contact with the P-type contact layer 440. As an embodiment, the P-type contact metal layer 491 is formed by an electron beam evaporation and lift-off process.
Next, please continue to refer to fig. 4 h. An N-type contact metal layer 492 is formed, the N-type contact metal layer 492 forming an ohmic contact with the N-type substrate 400. As an embodiment, before forming the N-type contact metal layer 492, the method further includes the step of thinning the N-type substrate 400; by thinning the N-type substrate 400, the epitaxial wafer forming the planar photodiode is, for example, thinned and polished to about 150 μm. The N-type contact metal layer 492 is formed by an electron beam evaporation process; the N-type contact metal layer 492 may be made of Ti, for example
Figure BDA0002152891030000181
/Pt
Figure BDA0002152891030000182
/Au
Figure BDA0002152891030000183
And (4) forming. The reflectivity of the contact metal layer is 75% through testing, and the responsivity of the photodiode can be improved from 0.61A/W to 0.75A/W for an InGaAs light absorption layer with the thickness of 1.0 um.
Finally, cleavage is carried out to form 300 x 300 μm2The planar photodiode chip.
It should be noted that the embodiments of the planar photodiode chip, the GPON module, the epitaxial wafer, and the method for manufacturing the planar photodiode chip provided by the present invention belong to the same concept; the technical features of the technical means described in the embodiments may be arbitrarily combined without conflict. It should be further described that, in the planar photodiode chip provided in the embodiments of the present invention, various technical feature combinations thereof can already solve the technical problems to be solved by the present invention; therefore, the planar photodiode chip provided in the embodiment of the present invention is not limited by the method for manufacturing the planar photodiode chip provided in the embodiment of the present invention, and any planar photodiode chip that can be manufactured by the method for manufacturing the planar photodiode chip structure provided in the embodiment of the present invention is within the scope of the present invention.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.

Claims (19)

1. An epitaxial wafer, comprising: the epitaxial layer is positioned on the substrate; wherein,
the substrate comprises an N-type substrate;
the epitaxial layer comprises a depletion region compensation layer and an I-type depletion layer which are sequentially positioned on the N-type substrate; the depletion region compensation layer is an N-type doped layer with the doping concentration of 1e16cm-3To 5e16cm-3Within the range of (1);
the depletion region compensation layer is in direct contact with the type I depletion layer.
2. The epitaxial wafer of claim 1, wherein the depletion region compensation layer has a thickness in the range of 0.5 to 1.0 μm.
3. The epitaxial wafer of claim 1 or 2, wherein the I-type depletion layer comprises an I-type light absorption layer having a thickness in the range of 3.5 to 4.0 μm.
4. The epitaxial wafer of claim 1, wherein the N-type substrate comprises an N-type InP substrate, the depletion region compensation layer comprises an N-type InP layer, and the I-type depletion layer comprises a first I-type InGaAsP energy band transition layer, an I-type InGaAs light absorption layer, and a second I-type InGaAsP energy band transition layer, which are sequentially stacked.
5. The epitaxial wafer of claim 1, wherein the epitaxial layer further comprises an I-type cap layer and a P-type contact layer sequentially located on the I-type depletion layer; the doping concentration of the P-type contact layer is more than or equal to 1e19cm-3。
6. A planar photodiode prepared based on the epitaxial wafer of any one of claims 1 to 5, so that the planar photodiode includes at least: the semiconductor device comprises an N-type substrate, an I-type depletion layer and a P-type semiconductor region, wherein the I-type depletion layer and the P-type semiconductor region are sequentially arranged on the N-type substrate; a depletion region compensation layer is further arranged between the N-type substrate and the I-type depletion layer, the depletion region compensation layer is an N-type doped layer, and the doping concentration of the depletion region compensation layer is 1e16cm-3To 5e16cm-3Within the range of (1);
the depletion region compensation layer is in direct contact with the type I depletion layer.
7. The planar photodiode of claim 6, further comprising an annular trench disposed in a direction perpendicular to the N-type substrate, the annular trench surrounding the P-type semiconductor region;
and spin-on liquid glass SOG materials are filled in the annular grooves.
8. The planar photodiode of claim 6, further comprising an annular trench disposed in a direction perpendicular to the N-type substrate, the annular trench surrounding the P-type semiconductor region;
the annular grooves comprise a first annular groove and a second annular groove which are distributed along the direction vertical to the N-type substrate, the lower surface of the first annular groove is lower than the lower surface of the P-type semiconductor region, the second annular groove is positioned on the depletion region compensation layer, and the upper surface of the second annular groove is connected with the lower surface of the first annular groove;
the opening size of the first annular groove is larger than that of the second annular groove.
9. A GPON module of a passive optical network having gigabit capability, comprising: a super transimpedance amplifier, and the planar photodiode of any one of claims 6 to 8.
10. A method of fabricating a planar photodiode, the method comprising:
providing an N-type substrate;
sequentially forming a depletion region compensation layer, an I-type depletion layer and a P-type semiconductor region on the N-type substrate; wherein the depletion region compensation layer is an N-type doped layer with a doping concentration of 1e16cm-3To 5e16cm-3Within the range of (1);
the depletion region compensation layer is in direct contact with the type I depletion layer.
11. The method of claim 10, wherein the depletion region compensation layer has a thickness in the range of 0.5 to 1.0 μm.
12. The method according to claim 10 or 11, wherein the I-type depletion layer comprises an I-type light absorption layer having a thickness in the range of 3.5 to 4.0 μm.
13. The method of claim 10, wherein the N-type substrate comprises an N-type InP substrate, the depletion region compensation layer comprises an N-type InP layer, and the I-type depletion layer comprises a first I-type InGaAsP energy band transition layer, an I-type InGaAs light absorption layer, and a second I-type InGaAsP energy band transition layer, which are sequentially stacked.
14. The method of claim 13, wherein forming the P-type semiconductor region comprises: and forming an I-shaped cap layer on the second I-shaped InGaAsP energy band transition layer of the I-shaped depletion layer, and forming the P-shaped semiconductor region in the I-shaped cap layer and the second I-shaped InGaAsP energy band transition layer by a diffusion process.
15. The method of claim 14, wherein prior to forming the P-type semiconductor region, the method further comprises:
etching the I-type cap layer and the I-type depletion layer to form an annular groove, wherein the annular groove surrounds the preset forming position of the P-type semiconductor region;
and filling spin-on liquid glass SOG materials in the annular groove.
16. The method of claim 14, wherein prior to forming the P-type semiconductor region, the method further comprises:
etching the I-type cap layer and the I-type depletion layer by adopting a first wet etching process to form a first annular groove, wherein the first annular groove is terminated in the I-type InGaAs light absorption layer;
continuously etching the I-type depletion layer along the first annular groove by adopting a second wet etching process to form a second annular groove, wherein the second annular groove is terminated on the depletion region compensation layer;
the opening size of the first annular groove is larger than that of the second annular groove.
17. The method of claim 16, wherein the etching solution used in the first wet etching process comprises hydrobromic acid: saturated bromine water: 1:1:1 mixed solution of water; the etching solution used in the second wet etching process comprises concentrated sulfuric acid: hydrogen peroxide: water is a mixed solution of 1:1: 5.
18. The method of claim 10, further comprising: forming a P-type contact layer with the doping concentration of 1e19cm or more-3(ii) a The P-type contact layer is located at a position conductively connected with the P-type semiconductor region.
19. The method of claim 18, wherein the P-type contact layer is formed by a Metal Organic Chemical Vapor Deposition (MOCVD) process.
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