CN117116815B - Chip mounting optimization method and system based on improved particle swarm optimization - Google Patents

Chip mounting optimization method and system based on improved particle swarm optimization Download PDF

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CN117116815B
CN117116815B CN202311371485.0A CN202311371485A CN117116815B CN 117116815 B CN117116815 B CN 117116815B CN 202311371485 A CN202311371485 A CN 202311371485A CN 117116815 B CN117116815 B CN 117116815B
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lead frame
pins
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swarm algorithm
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CN117116815A (en
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朱玲羽
杨佳琦
张贵阳
宗天煜
林子翔
徐天任
史曼芸
王云龙
刘畅
徐培涵
张夏玮
翟树峰
夏震然
赵雨辰
方绍伟
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Changshu Institute of Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06N3/00—Computing arrangements based on biological models
    • G06N3/004—Artificial life, i.e. computing arrangements simulating life
    • G06N3/006—Artificial life, i.e. computing arrangements simulating life based on simulated virtual individual or collective life forms, e.g. social simulations or particle swarm optimisation [PSO]

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Abstract

The invention discloses a chip mounting optimization method and a system based on an improved particle swarm algorithm, wherein the method comprises the following steps: acquiring pins of all chips and lead frames, and establishing a database; randomly selecting M chips from a wafer, wherein M is the number of lead frames, and constructing a matching degree function between the chip pins and the lead frame pins; and searching an optimal matching set of the chip and the lead frame, and mounting the chip on the corresponding lead frame according to the optimal solution. Aiming at the optimal matching of the chip and the lead frame in the chip mounting process, an optimization model based on a particle swarm algorithm is established, a better improved particle swarm algorithm is provided, the global optimal matching in the chip mounting is completed, and the purposes of improving the chip packaging quality and saving the material consumption are achieved.

Description

Chip mounting optimization method and system based on improved particle swarm optimization
Technical Field
The invention belongs to the technical field of chip packaging, and relates to a chip mounting optimization method and system based on an improved particle swarm algorithm.
Background
Chip mounting is one of key links in chip packaging links, and directly affects the quality and production efficiency of chip products. The chip mounting refers to fixing the bare chip on the lead frame through organic glue and metal solder, so that the subsequent process flows such as lead bonding and the like can be successfully completed. The lead frame is a carrier of the chip, and the lead-out terminals of the internal circuit of the chip are connected with the external leads through the internal leads by means of bonding materials. In chip production, a plurality of chips can be processed on one wafer. In order to improve the production efficiency, the lead frame is also generally arranged in a multi-block array mode, so that the chip mounting efficiency is improved. The conventional chip mounting method generally adopts a sequential method, that is, after chips are picked up from a wafer, positioning and mounting are sequentially performed according to the ordering sequence of the lead frames. However, certain errors occur in the processing process of various devices, although the method can finish the mounting work of the chip, the matching degree between the pins of the chip and the pins of the lead frame is not considered, so that lead material waste and bonding quality reduction occur in the subsequent process flows of lead bonding and the like, and meanwhile, potential adverse effects are brought to the yield, stability and the like of the chip.
Application number 2013104678103 discloses an array waveguide device alignment coupling method based on a particle swarm algorithm, which comprises the following steps: initial light seeking is performed on the array waveguide: searching a peak position based on particle swarm algorithm-mathematical optimization, adding an adaptive change inertial weight and performing simulation analysis; adopting limited measurement light power value and carrying out optimization iteration; the actual peak position is found by optimization iteration. The method does not address the optimum matching results of the chip and the lead frame in chip mounting.
Disclosure of Invention
The invention aims to provide a chip mounting optimization method and system based on an improved particle swarm algorithm, and aims to establish an optimization model based on the particle swarm algorithm aiming at the optimal matching of chips and lead frames in the chip mounting process, and provides a better improved particle swarm algorithm to complete global optimal matching in the chip mounting process so as to achieve the purposes of improving the packaging quality of the chips and saving the material consumption.
The technical solution for realizing the purpose of the invention is as follows:
a chip mounting optimization method comprises the following steps:
s01: acquiring pins of all chips and lead frames, and establishing a database;
s02: randomly select from the waferChip, 10>Constructing a matching degree function between the chip pins and the lead frame pins for the number of the lead frames;
s03: and searching an optimal matching set of the chip and the lead frame, and mounting the chip on the corresponding lead frame according to the optimal solution.
In a preferred embodiment, the matching degree function between the chip pins and the leadframe pins in step S02：
Wherein,、/>respectively refer to a chip and aLead frame (F)>For the number of edges of the chip, < > is>Index for chip and leadframe sides, +.>Is->Coordinate set of chip pins on strip edge, +.>Is->Coordinate set of lead frame pins on strip +.>Representing the covariance of both; />For the number of pins on each side +.>The weight coefficient is calculated as follows:
wherein,is natural logarithm.
In a preferred technical solution, the step S02 further includes constructing an optimization objective function of chip mounting:
wherein the method comprises the steps of，、/>Index of chip and leadframe, respectively, +.>For the number of leadframes in the leadframe array,is the number of chips on the wafer.
In the preferred technical scheme, in the step S03, an optimal matching set of the chip and the lead frame is found by an improved particle swarm algorithm, and the improved particle swarm algorithm improves the inertia weight and the learning rate in the standard particle swarm algorithm.
In a preferred technical scheme, the improved particle swarm algorithm is as follows:
wherein,represents the number of iterations, +.>For inertial weight function, +.>For particle index, ++>Index for a dimension in the particle, +.>Is particle velocity vector, +.>Indicate->The>Speed vector of dimension>Learning a factor function for an individual->For group learning factor function, ++>、/>Is section->Random number in the search for increasing the randomness of the search,/->Indicate->The>Maintaining the searched historical optimal position, +.>Representing the optimal position in the whole particle population, +.>Indicate->The>Maintain->The position at the time of the iteration;
the update method of (2) is as follows:
wherein,to be in interval->Random function on->、/>Representing maximum and minimum inertial weights, respectively;
、/>the update of (2) is shown in the following formula:
wherein,、/>the initial values of the two learning factors are respectively.
In a preferred technical solution, before searching the optimal matching set between the chip and the lead frame in step S03 further includes:
and establishing a database for the pin coordinate point information of the chip and the lead frame, and acquiring the coordinate information of each pin of the chip and the lead frame through machine vision.
The invention also discloses a chip mounting optimization system, which comprises:
the method comprises the steps of obtaining pins of all chips and lead frames by a chip and lead frame pin database construction module, and establishing a database;
matching degree function construction module, which randomly selects from waferChip, 10>Constructing a matching degree function between the chip pins and the lead frame pins for the number of the lead frames;
and the optimization solving module is used for searching an optimal matching set of the chip and the lead frame and attaching the chip to the corresponding lead frame according to the optimal solution.
In the preferred technical scheme, an optimal matching set of the chip and the lead frame is searched for by an improved particle swarm algorithm in the optimization solving module, and the improved particle swarm algorithm improves the inertia weight and the learning rate in the standard particle swarm algorithm.
In a preferred technical scheme, the improved particle swarm algorithm is as follows:
wherein,represents the number of iterations, +.>For inertial weight function, +.>For particle index, ++>Index for a dimension in the particle, +.>Is particle velocity vector, +.>Indicate->The>Speed vector of dimension>Learning a factor function for an individual->For group learning factor function, ++>、/>Is section->Random number in the search for increasing the randomness of the search,/->Indicate->The>Maintaining the searched historical optimal position, +.>Representing the optimal position in the whole particle population, +.>Indicate->The>Maintain->The position at the time of the iteration;
the update method of (2) is as follows:
wherein,to be in interval->Random function on->、/>Representing maximum and minimum inertial weights, respectively;
、/>the update of (2) is shown in the following formula:
wherein,、/>the initial values of the two learning factors are respectively.
The invention also discloses a computer storage medium, on which a computer program is stored, which when executed implements the above-mentioned chip mounting optimization method.
Compared with the prior art, the invention has the remarkable advantages that:
aiming at the optimization of chip mounting work, the invention starts from improving the matching degree of chip mounting, provides an optimization method based on a particle swarm algorithm, improves a standard particle swarm algorithm, provides a more optimal updating method of inertia weight and learning rate, and has the advantages that the improved particle swarm algorithm has higher convergence rate, and meanwhile, the algorithm can be effectively prevented from sinking into a local optimal solution, thereby improving the efficiency of the particle swarm algorithm, obtaining the optimal matching result of chips and lead frames in chip mounting, improving the quality of chip mounting, saving raw materials used in processes such as lead bonding and the like, and having wide application market space and economic value.
Drawings
FIG. 1 is a flow chart of a chip attach optimization method according to a preferred embodiment;
FIG. 2 is a schematic view of a leadframe structure;
FIG. 3 is a schematic diagram of an array arrangement of lead frames;
FIG. 4 is a schematic diagram of quality of chip pin and leadframe pin matching;
FIG. 5 is a flowchart of an improved particle swarm algorithm chip mounting optimization;
FIG. 6 is a graph showing the comparison of the effects of the modified particle swarm algorithm and the standard particle swarm algorithm.
Detailed Description
The principle of the invention is as follows: firstly, acquiring necessary data such as pins, appearance and the like of all chips and lead frames, and establishing a database; second randomly selecting from the waferChip, 10>For the number of lead frames, this is +.>The chip and the lead frame iterate through an improved particle swarm algorithm to find the optimal matching effect; and finally, according to the optimal solution, mounting the chip on the corresponding lead frame for subsequent work, so that the quality of chip mounting can be improved, and raw materials used in processes such as lead bonding and the like are saved.
Example 1:
as shown in fig. 1, a chip mounting optimization method includes the following steps:
s01: acquiring pins of all chips and lead frames, and establishing a database;
s02: randomly select from the waferChip, 10>Constructing a matching degree function between the chip pins and the lead frame pins for the number of the lead frames;
s03: and searching an optimal matching set of the chip and the lead frame, and mounting the chip on the corresponding lead frame according to the optimal solution.
In a preferred embodiment, the matching function between the chip pins and the leadframe pins in step S02：
Wherein,、/>respectively refer to a chipA lead frame->For the number of edges of the chip, < > is>Index for chip and leadframe sides, +.>Is->Coordinate set of chip pins on strip edge, +.>Is->Coordinate set of lead frame pins on strip +.>Representing the covariance of both; />For the number of pins on each side +.>The weight coefficient is calculated as follows:
wherein,is natural logarithm.
In a preferred embodiment, step S02 further includes constructing an optimized objective function for chip mounting:
wherein,、/>index of chip and leadframe, respectively, +.>For the number of leadframes in the leadframe array,is the number of chips on the wafer.
In a preferred embodiment, in step S03, the optimal matching set of the chip and the lead frame is found by an improved particle swarm algorithm, which improves the inertia weight and the learning rate in the standard particle swarm algorithm.
In a preferred technical scheme, the improved particle swarm algorithm is as follows:
wherein,represents the number of iterations, +.>For inertial weight function, +.>For particle index, ++>Index for a dimension in the particle, +.>Is particle velocity vector, +.>Indicate->The>Speed vector of dimension>Learning a factor function for an individual->For group learning factor function, ++>、/>Is section->Random number in the search for increasing the randomness of the search,/->Indicate->The>Maintaining the searched historical optimal position, +.>Representing the optimal position in the whole particle population, +.>Indicate->The>Maintain->The position at the time of the iteration;
the update method of (2) is as follows:
wherein,to be in interval->Random function on->、/>Representing maximum and minimum inertial weights, respectively;
、/>the update of (2) is shown in the following formula:
wherein,、/>the initial values of the two learning factors are respectively, and the invention is set according to the empirical data。
In a preferred embodiment, step S03 further includes, before searching the best matching set between the chip and the lead frame:
and establishing a database for the pin coordinate point information of the chip and the lead frame, and acquiring the coordinate information of each pin of the chip and the lead frame through machine vision.
In another embodiment, a computer storage medium has a computer program stored thereon, which when executed implements the chip attach optimization method described above.
In yet another embodiment, a chip mounting optimization system includes:
the method comprises the steps of obtaining pins of all chips and lead frames by a chip and lead frame pin database construction module, and establishing a database;
matching degree function construction module, which randomly selects from waferChip, 10>Constructing a matching degree function between the chip pins and the lead frame pins for the number of the lead frames;
and the optimization solving module is used for searching an optimal matching set of the chip and the lead frame and attaching the chip to the corresponding lead frame according to the optimal solution.
Specifically, the following describes the workflow of the chip mounting optimization system by taking a preferred embodiment as an example:
step one: and establishing a chip mounting optimization objective function.
The chip mounting refers to fixing the bare chip 10 on the lead frame 20 by using organic glue and metal solder, so that the subsequent process flows of wire bonding and the like can be successfully completed, and the method is one of key links of chip packaging. The lead frame 20 is a carrier of the chip while the chip internal circuit terminals are connected to the external leads 30 through the internal leads by means of bonding materials. In order to improve the production efficiency, the lead frame 20 is also generally arranged in a plurality of arrays, so as to improve the mounting efficiency of the chips, and the structure and array arrangement of the lead frame are shown in fig. 2 and 3. The conventional chip mounting method generally adopts a sequential method, i.e., after chips are picked up from a wafer, positioning and mounting are sequentially performed according to the order of the lead frames 20. However, certain errors occur in the processing process of various devices, although the method can finish the mounting work of the chip, the matching degree between the chip pins 11 and the lead frame pins 21 is not considered, so that lead material waste and bonding quality reduction occur in the subsequent process flows of lead bonding and the like, and meanwhile, potential adverse effects are brought to the yield, stability and the like of the chip, as shown in fig. 4. To solve these problems, the present invention constructs an optimization objective function from optimizing the degree of matching between chip pins and leadframe pins.
First, define the matching degree function between the chip pins and the lead frame pinsAs shown in formula (7), +.>The larger the instruction, the higher the matching degree.
（7）
Wherein,、/>respectively a chip and a lead frame, < >>The number of sides of the chip (lead frame is the same as the number of sides of the chip),/the number of sides of the chip is equal to the number of sides of the chip>Index for chip and leadframe sides, +.>Is->Coordinate set of chip pins on strip edge, +.>Is->Coordinate set of lead frame pins on strip +.>Representing the covariance of both; />For the number of pins on each side +.>The weight coefficient is calculated as follows:
（8）
wherein,is natural logarithm.
Is provided withFor the number of leadframes in the leadframe array, +.>For the number of chips on a wafer, an optimized objective function for chip mounting is defined as:
（9）
wherein,、/>index of the chip and the lead frame, respectively. According to the formula (9), the optimization problem of chip mounting is similar to the problems of traveling traders and the like, belongs to the NP-hard problem, and the problem does not have the optimal solution under the polynomial time complexity at present, and the relative optimal solution is usually solved through a heuristic algorithm and the like, namely the relative optimal solution can be solved through the heuristic algorithm and the like, and can also be solved through a standard particle swarm algorithm.
The invention uses improved particle swarm algorithm to complete the optimization solution of chip mounting.
Step two: the improved particle swarm algorithm finds the best matching set of the chip and the lead frame.
Step 21: and establishing a chip and lead frame pin information database.
In order to optimize chip mounting by using a particle swarm algorithm, a database is firstly required to be established for information such as pin coordinate points of a chip and a lead frame, accurate coordinate information of each pin of the chip and the lead frame is obtained in a machine vision mode and the like, and main fields and related information contained in the established database are shown in table 1.
TABLE 1 chip and lead frame Pin Primary information data
Step 22: the particle swarm algorithm is improved.
The particle swarm algorithm is a kind of algorithm designed by simulating the prey behavior of the bird swarm, searches in a solution space by arranging a plurality of particles, each particle is influenced by other particles in the searching process, the particles have the memory capacity of the optimal solution, and the particles are finally aggregated to an optimal point along with the evolution of calculation. The mathematical description of the standard particle swarm algorithm is shown in formula (10).
（10）
Wherein the method comprises the steps ofRepresents the number of iterations, +.>Is inertial weight, ++>For particle index, ++>Index for a dimension in the particle, +.>Is particle velocity vector, +.>Indicate->The>Speed vector of dimension>For individual learning factors->For group learning factors, ++>、/>Is section->Random number in the search for increasing the randomness of the search,/->Indicate->The>Maintaining the searched historical optimal position, +.>Representing the optimal position in the whole particle population, +.>Indicate->The>Maintain->The position at the time of the iteration. In each iteration, inertial weight +.>And the particle position is updated using the following formula:
（11）
wherein the method comprises the steps of、/>Representing maximum and minimum inertial weights, respectively, ">Representing the maximum number of iterations.
The standard particle swarm algorithm is widely applied to the fields of optimization, fuzzy control and the like, but has the defects of poor local searching capability, easy sinking into local extremum and the like, and aiming at the characteristics of chip mounting, the invention improves the particle swarm algorithm as follows:
1. inertial weights are improved using (12),
（12）
wherein the method comprises the steps ofTo be in interval->The random function above, we get +.>、/>。
2. Improved learning factor using periodic dynamic learning factor、/>The updating method of (1) comprises the following steps:
（13）
wherein,、/>the initial values of the two learning factors are respectively, and the invention is set according to the empirical data。
The improved particle swarm algorithm is as follows:
（14）
the invention uses improved particle swarm algorithm to carry on the chip mounting optimization flow, namely, firstly obtain the necessary data such as pins, appearance, etc. of all chips and lead frames, establish the database; second randomly selecting from the waferChip, 10>For the number of lead frames, this is +.>The chip and the lead frame iterate through an improved particle swarm algorithm to find the optimal matching effect; and finally, according to the optimal solution, mounting the chip on a corresponding lead frame for subsequent work, wherein the work flow chart is shown in fig. 5.
The improved particle swarm algorithm is tested and compared with the effect of the standard particle swarm algorithm, and the result is shown in fig. 6, from which it can be seen that the improved particle swarm algorithm of the invention has a higher convergence rate and can effectively prevent the algorithm from falling into a locally optimal solution. Meanwhile, according to calculation, the invention can finish better matching of the chip and the lead frame, so that expensive gold wires and other materials required by lead bonding can be effectively saved, the average saving rate can reach 5% through simulation, and meanwhile, the quality and the efficiency of the lead bonding can be effectively improved.
The foregoing examples are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the foregoing examples, and any other changes, modifications, substitutions, combinations, and simplifications that do not depart from the spirit and principles of the present invention should be made therein and are intended to be equivalent substitutes within the scope of the present invention.

Claims (9)

1. The chip mounting optimization method is characterized by comprising the following steps of:
s01: acquiring pins of all chips and lead frames, and establishing a database;
s02: randomly select from the waferChip, 10>For the number of lead frames, a matching degree function between the chip pins and the lead frame pins is constructed, the matching degree function +.>：
，
Wherein,、/>respectively a chip and a lead frame, < >>For the number of edges of the chip, < > is>Index for chip and leadframe sides, +.>Is->Coordinate set of chip pins on strip edge, +.>Is the first/>The coordinate set of the leadframe leads on the strip edge,representing the covariance of both; />For the number of pins on each side +.>The weight coefficient is calculated as follows:
，
wherein,is natural logarithm;
s03: and searching an optimal matching set of the chip and the lead frame, and mounting the chip on the corresponding lead frame according to the optimal solution.
2. The chip mounting optimization method according to claim 1, wherein the step S02 further comprises constructing an optimization objective function of chip mounting:
，
wherein,、/>index of chip and leadframe, respectively, +.>For the number of leadframes in the leadframe array, +.>Is the number of chips on the wafer.
3. The chip mounting optimization method according to claim 1, wherein in the step S03, the optimal matching set of the chip and the lead frame is found by an improved particle swarm algorithm, and the improved particle swarm algorithm improves the inertia weight and the learning rate in the standard particle swarm algorithm.
4. The chip mounting optimization method according to claim 3, wherein the modified particle swarm algorithm is:
，
wherein,represents the number of iterations, +.>For inertial weight function, +.>For particle index, ++>Index for a dimension in the particle, +.>Is particle velocity vector, +.>Indicate->The>Speed vector of dimension>Learning a factor function for an individual->For group learning factor function, ++>、/>Is section->Random number in the search for increasing the randomness of the search,/->Indicate->The>Maintaining the searched historical optimal position, +.>Representing the optimal position in the whole particle population, +.>Indicate->The>Maintain->The position at the time of the iteration;
the update method of (2) is as follows:
，
wherein,to be in interval->Random function on->、/>Representing maximum and minimum inertial weights, respectively;
、/>the update of (2) is shown in the following formula:
，
wherein,、/>the initial values of the two learning factors are respectively.
5. The method of optimizing chip mounting according to claim 1, wherein before searching for the optimum matching set of the chip and the lead frame in step S03 further comprises:
and establishing a database for the pin coordinate point information of the chip and the lead frame, and acquiring the coordinate information of each pin of the chip and the lead frame through machine vision.
6. A chip mounting optimization system, comprising:
the method comprises the steps of obtaining pins of all chips and lead frames by a chip and lead frame pin database construction module, and establishing a database;
matching degree function construction module, which randomly selects from waferChip, 10>For the number of lead frames, a matching degree function between the chip pins and the lead frame pins is constructed, the matching degree function +.>：
，
Wherein,、/>respectively a chip and a lead frame, < >>For the number of edges of the chip, < > is>Index for chip and leadframe sides, +.>Is->Coordinate set of chip pins on strip edge, +.>Is->The coordinate set of the leadframe leads on the strip edge,representing the covariance of both; />For the number of pins on each side +.>The weight coefficient is calculated as follows:
，
wherein,is natural logarithm;
and the optimization solving module is used for searching an optimal matching set of the chip and the lead frame and attaching the chip to the corresponding lead frame according to the optimal solution.
7. The chip mounting optimization system of claim 6, wherein the optimal matching set of chips and lead frames is found in the optimization solution module by an improved particle swarm algorithm that improves inertial weights and learning rates in a standard particle swarm algorithm.
8. The chip mounting optimization system of claim 7, wherein the modified particle swarm algorithm is:
，
wherein,represents the number of iterations, +.>For inertial weight function, +.>For particle index, ++>Index for a dimension in the particle, +.>Is particle velocity vector, +.>Indicate->The>Speed vector of dimension>For individualsLearning factor function->For group learning factor function, ++>、/>Is section->Random number in the search for increasing the randomness of the search,/->Indicate->The>Maintaining the searched historical optimal position, +.>Representing the optimal position in the whole particle population, +.>Indicate->The>Maintain->The position at the time of the iteration;
the update method of (2) is as follows:
，
wherein,to be in interval->Random function on->、/>Representing maximum and minimum inertial weights, respectively;
、/>the update of (2) is shown in the following formula:
，
wherein,、/>the initial values of the two learning factors are respectively.
9. A computer storage medium having a computer program stored thereon, wherein the computer program, when executed, implements the die attach optimization method of any one of claims 1-5.
CN202311371485.0A 2023-10-23 2023-10-23 Chip mounting optimization method and system based on improved particle swarm optimization Active CN117116815B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106599428A (en) * 2016-12-06 2017-04-26 东北大学 Chip hot layout method
CN112201585A (en) * 2020-06-29 2021-01-08 深圳卓橙科技有限公司 MCM integrated circuit packaging method fusing SMT
CN115954275A (en) * 2022-12-28 2023-04-11 无锡市宏湖微电子有限公司 Chip packaging method and device based on hot-pressing spherical bonding and chip packaging structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106599428A (en) * 2016-12-06 2017-04-26 东北大学 Chip hot layout method
CN112201585A (en) * 2020-06-29 2021-01-08 深圳卓橙科技有限公司 MCM integrated circuit packaging method fusing SMT
CN115954275A (en) * 2022-12-28 2023-04-11 无锡市宏湖微电子有限公司 Chip packaging method and device based on hot-pressing spherical bonding and chip packaging structure

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