CN106599428A - Chip hot layout method - Google Patents
Chip hot layout method Download PDFInfo
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- CN106599428A CN106599428A CN201611107317.0A CN201611107317A CN106599428A CN 106599428 A CN106599428 A CN 106599428A CN 201611107317 A CN201611107317 A CN 201611107317A CN 106599428 A CN106599428 A CN 106599428A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/08—Thermal analysis or thermal optimisation
Abstract
The present invention provides a particle swarm optimization and junction temperature combination-based chip hot layout method. The method comprises the steps of determining a number and sizes of chips to be distributed, and a size of a baseboard; using each chip as a particle, wherein all chips on the baseboard form a particle swarm, using a junction temperature of the chip as a fitness function, and seeking optimal chip coordinates by using a particle swarm optimization algorithm; and distributing each chip on the baseboard according to the determined optimal coordinates of each chip. In the method, the junction temperature of any chip can be designated as the fitness function by taking the advantage of the particle swarm optimization algorithm, the actual size of the chip is taken into account so as to prevent the chip to be out of the bound and overlap, so that all chips on the baseboard are distributed reasonably, further, temperature of a certain high-power chip, a chip not resisting high temperature, or a chip with special requirements reaches a minimum level as much as possible, therefore, hot-spot temperature on the whole baseboard is further reduced, a temperature difference of chips is reduced, and the performance and reliability of the device are improved.
Description
Technical field
The invention belongs to chip Thermal layout technical field, specifically a kind of chip Thermal layout method.
Background technology
Traditional Thermal layout has a heating power guidance method, various layout sides such as micro unit heat balance method of is combined with optimization method
Method.
《Thermal layout optimization based on electronic component on the pcb board of particle cluster algorithm》And《PCB based on ant group algorithm
The Thermal layout optimizing research of plate electronic component》In article, the two methods set up temperature point using micro unit heat balance method of
Cloth model, however, micro unit heat balance method of needs to derive various corresponding modal equations respectively, in complicated temperature field and convection current
In the case of, it is impossible to it is enough accurately to express the corresponding steady temperature value of each chip, also, the two methods be only suitable for some
The geometry of the simple rule carefully and neatly put on substrate, but in actual engineer applied, the electronic component on circuit board
The overwhelming majority is not that regular arrangement is placed, additionally, the two methods are not also limited to the geometrical condition of chip, is easily produced
Raw chip overlaps the problem with out-of-bounds.
《Thermal Placement Algorithm Based on Heat Conduction Analogy》Article
In, power leads algorithm calculating process complexity, and each iteration has all carried out accumulation calculating to the repulsion of every point-to-point transmission, i.e., each iteration
The part-time complexity reaches O (n2).If ignore side produce gravitation part calculate, and assume iteration to tend to balance when
Between complexity be O (n), then the time complexity of whole algorithm is O (n3), the calculating time is longer, the knot do not restrained easily occurs
Really, additionally, in the algorithm, each component is the thermal source for being reduced to particle, size this problem for ignoring component is relative
Than more serious, it is very important problem, it is because chip chamber may overlap and out-of-bounds problem, so, resulting
Layout result is not admissible, not with practical layout meaning.《Thermal Placement Algorithm Based
on Heat Conduction Analogy》In article, above-mentioned problem is equally existed.
《Multiobjective Optimal Placement of Convectively Cooled Electronic
Components on Printed Wiring Boards》In article, the power guiding method based on fuzzy model is introduced, is solved
The certainly Thermal layout problem on MCM, this method are compared genetic method and are calculated faster.But, in the method, the bigger core of power consumption
Piece is often placed on the border of substrate, result in and is more prone to produce focus in the overlap of chip, and four angles of substrate,
So that chip high temperature failure.
Conventional optimized algorithm has genetic algorithm, simulated annealing etc..《Thermal Placement Design
for MCM Applications》And《Integration of simulation and response surface
methods for thermal design of multichip modules》In article, genetic algorithm has been used on PCB
Electronic devices and components be optimized layout, but this method needs more memory spaces, because it must remember hundred million populations
In all of individual configurations, and there are problems that encode lack of standardization and coded representation it is inaccurate.Additionally, genetic algorithm is to algorithm
Precision, Feasible degree, the aspect such as computational complexity, also no effective quantitative analysis method.
《Object-Oriented Thermal Placement Using an Accurate Heat Model》Text
Zhang Zhong, has used simulated annealing, and the algorithm optimization process is long, needs to expend very many times, and to some
The solution of particular problem needs more difficult parameter adjustment, and the uncertain optimal solution that can find the overall situation.Additionally, as
Shown in article, the method does not impose a condition comprising border.
《Optimization of electronics component placement design on PCB
using self organizing genetic algorithm(SOGA)》In article, although the method has preferably convergence effect
Really, but it is also required to more process times.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of chip heat combined with junction temperature based on particle group optimizing
Layout method.
Technical scheme is as follows：
A kind of chip Thermal layout method combined with junction temperature based on particle group optimizing, including：
The number of chips of layout, the size of chip, the size of substrate are wanted in step 1, determination；
Step 2, using each chip as particle, all chip constituent particle groups on substrate, using the junction temperature of chip as
Fitness function, finds optimum chip coordinate using particle swarm optimization algorithm；
Step 3, according to determine optimum each chip coordinate by each chip layout to substrate.
The step 2, including：
Step 2.1, initialization：Population size is determined according to the number of chips of layout, it is random to generate primary group, with
Machine generates initial particle position and speed, sets maximum iteration time；Individual extreme value when will be each particle initial is set to
Global extremum is set to the particle current location of optimum by each particle current location；
Step 2.2, each corresponding fitness function value in particle current location is calculated i.e. according to current each chip coordinate meter
Calculate the junction temperature of each chip；
Step 2.3, using the minima of total junction temperature of all chips as current global extremum, total junction temperature of all chips
It is by a weighting function T for waiting weights linear combination to represent of one single chip junction temperaturei Tatal；
Step 2.4, will need reduce temperature specific certain chip junction temperature as current individual extreme value；
Step 2.5, according to speed renewal equation and location updating equation, constantly update each particle in the position at t+1 moment
Put and speed；
Step 2.6, judge whether the particle position for updating occurs chip out-of-bounds or chip chamber and overlap：It is, then return to step
2.5, otherwise execution step 2.7；
Step 2.7, using the Position And Velocity of current particle, calculate each corresponding fitness function in particle current location
Value；
Step 2.8, more new individual extreme value and global extremum；
Step 2.9, judge whether to reach maximum iteration time：It is that then current particle corresponding to global extremum is chip
Optimal location position, otherwise return to step 2.2.
The step 2.2, including：
Step 2.2.1, the multi-group data that each chip coordinate and junction temperature corresponding relation are obtained using hot simulation analysis software；
Step 2.2.2, Responds Surface Methodology is adopted, even experiment design is set up with SAS statistical analysis softwares, come
The functional relationship being fitted between the junction temperature of each chip and coordinate, and seek the optimized parameter of even experiment design；
Step 2.2.3, it is junction temperature of chip to weigh by fitness function to the good and bad degree of each particle.
In the step 2.5, the particle rapidity renewal equation is：
Vit+1=wVit+c1·rand1()·(PI, t-Xit)+c2·rand2()·(PG,t-Xit)
Wherein, VitFor the speed of t, Vit+1For the speed at t+1 moment；C1, c2 be Studying factors, rand1() and
rand2() is two [0,1] interval random number；Pi,tThe optimum state experienced by the particle of t, Pg,tFor t
The optimum state experienced by colony, XitFor the position of t；W is inertia weight, using improved inertia weight linear decrease
Strategy；
Improved inertia weight linear decrease strategy adopts following linear decrease formula：
Wherein, wmax、wminMaximum inertia weight, minimum inertia weight, iteration time of the iter for current particle are represented respectively
Number, itermaxFor maximum iteration time；
The particle position renewal equation is：
Xit+1=Xit+Vit+1
Wherein, Xit+1For the position at t+1 moment.
Judge in the step 2.6 whether the particle position for updating occurs chip out-of-bounds or chip chamber is overlapped, and is according to core
The geometrical constraint of piece coordinate determines；
The geometrical constraint of the chip coordinate, including：
(1) limit the geometrical constraint of chip out-of-bounds：
xL≤xi≤xU(i=1,2 ..., N)
yL≤yi≤yU(i=1,2 ..., N)
Wherein, xi、yiThe respectively abscissa of chip, vertical coordinate, xL、yLThe minimum of the abscissa of respectively i-th chip
Value, the minima of vertical coordinate, xU、yUFor the maximum of the abscissa of i-th chip, the maximum of vertical coordinate, N is to want layout
Chip number；
(2) limit the geometrical constraint that chip chamber is overlapped：
|xi-xj| ＞ L | | | yi-yj| ＞ W
Wherein, xj、yjThe abscissa of respectively j-th chip, vertical coordinate, L are half length of i-th chip and j-th chip
Sum, W are the half-breadth sums of i-th chip and j-th chip.
The step 2.8 more new individual extreme value and global extremum, including：
Step 2.8.1, each particle fitness function value and current individual extreme value for particle position will being updated and after speed
Fitness function value be compared, current individual extreme value is updated if the former is more excellent, otherwise individual extreme value is constant；
Step 2.8.2, the population fitness function value after particle position and speed will be updated enter with current global extremum
Row compares, and current global extremum is updated if the former is more excellent, and otherwise global extremum is constant.
Beneficial effect：
Advantage of the present invention using particle swarm optimization algorithm, it is possible to specify the arbitrarily junction temperature of chip as fitness function,
The actual size for considering chip prevents chip out-of-bounds or overlap so that all chips on substrate are on the basis of reasonable layout
On so that a certain high-power die, non-refractory chip, or the temperature for having the chip of particular/special requirement as far as possible reach it is minimum, so as to
More reduce the hot(test)-spot temperature on whole substrate, and reduce the temperature difference of chip chamber, improve the Performance And Reliability of device,
Meet the design requirement with hot environment industry to chip Thermal layout such as Aero-Space, oil drilling.
Description of the drawings
Fig. 1 is the chip Thermal layout method flow that combined with junction temperature based on particle group optimizing in the specific embodiment of the invention
Figure；
Fig. 2 is the particular flow sheet of step 2 in the specific embodiment of the invention.
Specific embodiment
Below in conjunction with the accompanying drawings the specific embodiment of the present invention is elaborated.
A kind of chip Thermal layout method combined with junction temperature based on particle group optimizing, as shown in figure 1, including：
The number of chips of layout, the size of chip, the size of substrate are wanted in step 1, determination；
Step 2, using each chip as particle, all chip constituent particle groups on substrate, using the junction temperature of chip as
Fitness function, finds optimum chip coordinate using particle swarm optimization algorithm；
Particle swarm optimization algorithm is more simpler than genetic algorithm rule, and it does not have intersection, variation and the reverse of genetic algorithm
Operation, but the direction of search and step-length are determined according to the speed of oneself, and there is memory ability, model simply easily realizes not having
There are many parameters to need adjustment, be a kind of general full search algorithm, with higher-dimension multiple-objection optimization ability.
Step 3, according to determine optimum each chip coordinate by each chip layout to substrate.
The step 2, as shown in Fig. 2 comprising the steps：
Step 2.1, initialization：Population size is determined according to the number of chips of layout, it is random to generate primary group,
Generate initial particle position and speed in the case of meeting the geometrical constraint of chip coordinate at random, set maximum iteration time；Will
Individual extreme value when each particle is initial is set to each particle current location, and the particle that global extremum is set to optimum is current
Position；
The geometrical constraint of the chip coordinate, including：
(1) limit the geometrical constraint of chip out-of-bounds：
xL≤xi≤xU(i=1,2 ..., N)
yL≤yi≤yU(i=1,2 ..., N)
Wherein, xi、yiThe respectively abscissa of chip, vertical coordinate, xL、yLThe minimum of the abscissa of respectively i-th chip
Value, the minima of vertical coordinate, xU、yUFor the maximum of the abscissa of i-th chip, the maximum of vertical coordinate, N is to want layout
Chip number；
(2) limit the geometrical constraint that chip chamber is overlapped：
|xi-xj| ＞ L | | | yi-yj| ＞ W
Wherein, xj、yjThe abscissa of respectively j-th chip, vertical coordinate, L are half length of i-th chip and j-th chip
Sum, W are the half-breadth sums of i-th chip and j-th chip.
Step 2.2, each corresponding fitness function value in particle current location is calculated i.e. according to current each chip coordinate meter
Calculate the junction temperature of each chip；
Step 2.2.1, each chip is obtained using hot simulation analysis software (such as Flotherm, ANSYS Icepak etc.) sit
The multi-group data of mark and junction temperature corresponding relation；
Step 2.2.2, Responds Surface Methodology is adopted, even experiment design is set up with SAS statistical analysis softwares, come
The functional relationship being fitted between the junction temperature of each chip and coordinate, and seek the optimized parameter of even experiment design；
Step 2.2.3, it is junction temperature of chip to weigh by following fitness function to the good and bad degree of each particle：
Wherein, TiIt is the junction temperature of i-th chip, N is the total number of base chip on board, Zi(i=1,2 ..., N) and Zj(j
=1,2 ..., N) be respectively i-th chip coordinate and j-th chip coordinate；B0、BjAnd Bij(i, j=1,2 ..., N)
It is the coefficient of even experiment design, is solved by SAS statistical analysis softwares and determined, E is random error；
Step 2.3, using the minima of total junction temperature of all chips as current global extremum, total junction temperature of all chips
It is by a weighting function T for waiting weights linear combination to represent of one single chip junction temperaturei Tatal；
Total junction temperature T of all chipsi TatalFormula is expressed as follows:
Wherein, (x, y) is the coordinate of chip, and N is the chip number on substrate；
Step 2.4, will need reduce temperature specific certain chip junction temperature as current individual extreme value, the chip can
Think the larger chip of power, the chip of non-refractory or have the chip of other particular/special requirements；
Step 2.5, according to speed renewal equation and location updating equation, constantly update each particle in the position at t+1 moment
Put and speed；
The particle rapidity renewal equation is：
Vit+1=wVit+c1·rand1()·(PI, t-Xit)+c2·rand2()·(PG, t-Xit)
Wherein, VitFor the speed of t, Vit+1For the speed at t+1 moment；C1, c2 be Studying factors, rand1() and
rand2() is two [0,1] interval random number, is typically set to identical value to give both same weights, c1=c2=2.05；
Pi,tThe optimum state experienced by the particle of t, Pg,tThe optimum state experienced by the colony of t, XitFor t
Position；W is inertia weight, adjusts hunting zone and search speed that its value can change particle, and the value adopts improved inertia
Weight linear decrease strategy.Make iteration initial stage algorithm that there is preferable ability of searching optimum, have iteration later stage algorithm more preferable
Local optimal searching ability, its convergence precision is substantially better than effect when w to be set to fixed value.
Improved inertia weight linear decrease strategy adopts following linear decrease formula：
Wherein, wmax、wminMaximum inertia weight, minimum inertia weight, iteration time of the iter for current particle are represented respectively
Number, itermaxFor maximum iteration time.By to inertia weight linear decrease, being that iteration arranges different inertia weights each time
Value.
The particle position renewal equation is：
Xit+1=Xit+Vit+1
Wherein, Xit+1For the position at t+1 moment；
The speed of the particle is defined as the distance of particle movement in each iteration, and each particle is designed with maximum restriction speed
Degree Vmax, if it exceeds Vmax, just it is defined as Vmax, VmaxFormula is expressed as follows：
Vmax=xmax-xmin
Wherein, xmaxAnd xminThe position coordinateses of expression particle are allowed respectively maximum changing range and minimum change model
Enclose, determined according to the geometrical constraint of chip coordinate；
Step 2.6, according to the geometrical constraint of chip coordinate judge update particle position whether there is chip out-of-bounds or core
Overlap between piece：It is, then return to step 2.5, otherwise execution step 2.7；
Step 2.7, using the Position And Velocity of current particle, calculate each corresponding fitness function in particle current location
Value；
Step 2.8, more new individual extreme value and global extremum；
Step 2.8.1, each particle fitness function value and current individual extreme value for particle position will being updated and after speed
Fitness function value be compared, current individual extreme value is updated if the former is more excellent, otherwise individual extreme value is constant；
Step 2.8.2, the population fitness function value after particle position and speed will be updated enter with current global extremum
Row compares, and current global extremum is updated if the former is more excellent, and otherwise global extremum is constant；
Seek the optimal location of chip position, by constantly updating global extremum so that all chips on substrate can
Rational deployment, meanwhile, during individual extreme value is constantly updated, cause the temperature of the objective chip of setting to reach individual pole again
Value, while integral layout optimum is met, the hot(test)-spot temperature of substrate is reduced, the layout temperature difference is reduced；
Step 2.9, judge whether to reach maximum iteration time：It is that then current particle corresponding to global extremum is chip
Optimal location position, otherwise return to step 2.2.
Claims (6)
1. a kind of chip Thermal layout method combined with junction temperature based on particle group optimizing, it is characterised in that include：
The number of chips of layout, the size of chip, the size of substrate are wanted in step 1, determination；
Step 2, using each chip as particle, all chip constituent particle groups on substrate, using the junction temperature of chip as adaptation
Degree function, finds optimum chip coordinate using particle swarm optimization algorithm；
Step 3, according to determine optimum each chip coordinate by each chip layout to substrate.
2. method according to claim 1, it is characterised in that the step 2, including：
Step 2.1, initialization：Population size is determined according to the number of chips of layout, it is random to generate primary group, random life
Into initial particle position and speed, maximum iteration time is set；Individual extreme value when will be each particle initial is set to each
Global extremum is set to the particle current location of optimum by particle current location；
Step 2.2, calculate each corresponding fitness function value in particle current location and calculate each according to current each chip coordinate
The junction temperature of chip；
Step 2.3, using the minima of total junction temperature of all chips as current global extremum, total junction temperature of all chips be by
A weighting function T for waiting weights linear combination to represent of one single chip junction temperaturei Tatal；
Step 2.4, will need reduce temperature specific certain chip junction temperature as current individual extreme value；
Step 2.5, according to speed renewal equation and location updating equation, constantly update each particle in the position at t+1 moment and
Speed；
Step 2.6, judge whether the particle position for updating occurs chip out-of-bounds or chip chamber and overlap：It is, then return to step 2.5,
Otherwise execution step 2.7；
Step 2.7, using the Position And Velocity of current particle, calculate each corresponding fitness function value in particle current location；
Step 2.8, more new individual extreme value and global extremum；
Step 2.9, judge whether to reach maximum iteration time：It is that then current particle corresponding to global extremum is that chip is optimum
Placement position, otherwise return to step 2.2.
3. method according to claim 2, it is characterised in that the step 2.2, including：
Step 2.2.1, the multi-group data that each chip coordinate and junction temperature corresponding relation are obtained using hot simulation analysis software；
Step 2.2.2, Responds Surface Methodology is adopted, even experiment design is set up with SAS statistical analysis softwares, be fitted
Functional relationship between the junction temperature and coordinate of each chip, and seek the optimized parameter of even experiment design；
Step 2.2.3, it is junction temperature of chip to weigh by fitness function to the good and bad degree of each particle.
4. method according to claim 2, it is characterised in that in the step 2.5,
The particle rapidity renewal equation is：
Vit+1=wVit+c1·rand1()·(PI, t-Xit)+c2·rand2()·(PG, t-Xit)
Wherein, VitFor the speed of t, Vit+1For the speed at t+1 moment；C1, c2 be Studying factors, rand1() and rand2
() is two [0,1] interval random number；Pi,tThe optimum state experienced by the particle of t, PG, tFor the colony of t
The optimum state for being experienced, XitFor the position of t；W is inertia weight, using improved inertia weight linear decrease strategy；
Improved inertia weight linear decrease strategy adopts following linear decrease formula：
Wherein, wmax、wminMaximum inertia weight, minimum inertia weight are represented respectively, and iter is the iterationses of current particle,
itermaxFor maximum iteration time；
The particle position renewal equation is：
Xit+1=Xit+Vit+1
Wherein, Xit+1For the position at t+1 moment.
5. method according to claim 2, it is characterised in that judge in the step 2.6 particle position that updates whether
The out-of-bounds of generation chip or chip chamber are overlapped, and are determined according to the geometrical constraint of chip coordinate；
The geometrical constraint of the chip coordinate, including：
(1) limit the geometrical constraint of chip out-of-bounds：
xL≤xi≤xU(i=1,2 ..., N)
yL≤yi≤yU(i=1,2 ..., N)
Wherein, xi、yiThe respectively abscissa of chip, vertical coordinate, xL、yLIt is the minima of the abscissa of respectively i-th chip, vertical
The minima of coordinate, xU、yUFor the maximum of the abscissa of i-th chip, the maximum of vertical coordinate, N is the chip for wanting layout
Number；
(2) limit the geometrical constraint that chip chamber is overlapped：
|xi-xj| ＞ L | | | yi-yj| ＞ w
Wherein, xj、yjThe abscissa of respectively j-th chip, vertical coordinate, L are half length of i-th chip and j-th chip
With W is the half-breadth sum of i-th chip and j-th chip.
6. method according to claim 2, it is characterised in that the step 2.8 more new individual extreme value and global extremum, bag
Include：
Step 2.8.1, fitting each particle fitness function value and current individual extreme value for updating particle position and after speed
Response functional value is compared, and current individual extreme value is updated if the former is more excellent, and otherwise individual extreme value is constant；
Step 2.8.2, the population fitness function value after particle position and speed will be updated compared with current global extremum
Compared with, current global extremum is updated if the former is more excellent, otherwise global extremum is constant.
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