CN117116746A - Molecular beam epitaxy process optimization method of InP-based semiconductor device - Google Patents
Molecular beam epitaxy process optimization method of InP-based semiconductor device Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 238000000034 method Methods 0.000 title claims abstract description 72
- 238000001451 molecular beam epitaxy Methods 0.000 title claims abstract description 41
- 238000005457 optimization Methods 0.000 title abstract description 15
- 230000007547 defect Effects 0.000 claims abstract description 277
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 238000012360 testing method Methods 0.000 claims abstract description 19
- 235000012431 wafers Nutrition 0.000 claims description 102
- 239000011159 matrix material Substances 0.000 claims description 20
- 238000012512 characterization method Methods 0.000 claims description 11
- 238000003795 desorption Methods 0.000 claims description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 6
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 6
- 238000012876 topography Methods 0.000 claims description 6
- 239000013081 microcrystal Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000002128 reflection high energy electron diffraction Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000010923 batch production Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- MFYSYFVPBJMHGN-UHFFFAOYSA-N Cortisone Natural products O=C1CCC2(C)C3C(=O)CC(C)(C(CC4)(O)C(=O)CO)C4C3CCC2=C1 MFYSYFVPBJMHGN-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02543—Phosphides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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Abstract
The application provides a molecular beam epitaxy process optimization method of an InP-based semiconductor device, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: under the preset As pressure, adopting a preset demolding temperature and a preset demolding time to perform demolding on the InP substrate; growing a device epitaxial layer on the substrate after the film removal to form an epitaxial wafer; performing surface morphology test on the epitaxial wafer to obtain defect data; and determining the demolding time when the epitaxial wafer grows next time according to the corresponding relation between the demolding time and the defect density, which is obtained in advance, based on the defect densities of the first type and the second type of defects. By acquiring the difference value of the two types of defect densities of the InP substrate under the preset demolding time, the optimized demolding time can be calculated according to the corresponding relation between the pre-established demolding time and the defect density, and in the batch production of the InP-based epitaxial wafer, the demolding time of the subsequent rounds can be optimized conveniently and rapidly according to the growth test result of each round, so that the quality of the epitaxial wafer is improved.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a molecular beam epitaxy process optimization method of an InP-based semiconductor device.
Background
Compared with the GaAs-based compound semiconductor material, the InP-based compound semiconductor material has higher electron saturation velocity, higher breakdown voltage of InP and unique performance, and is the first choice material for developing high-frequency and high-speed devices. InP-based semiconductor devices have higher conversion efficiency, higher operating frequency, greater output power, better noise characteristics, and radiation resistance than GaAs-based semiconductor devices. Accordingly, with the advancement of compound semiconductor technology, the demand for high-performance InP-based semiconductor devices has greatly increased.
The InP-based semiconductor device may be fabricated by a molecular beam epitaxy technique, in which an InP substrate is first subjected to a high-temperature stripping treatment in a molecular beam epitaxy apparatus to remove natural oxides on the surface of the InP substrate, and then a corresponding epitaxial layer is deposited and grown according to the device structure design. In the mass production of InP-based semiconductor devices, the advantages and disadvantages of the molecular beam epitaxy high-temperature stripping process directly affect the surface defect density of the prepared InP-based semiconductor device epitaxial wafer, thereby affecting the yield and reliability of the final device. Too long or too short a stripping time increases the defect density on the substrate surface. The more surface defects of the epitaxial wafer, the lower the yield of the device, and the poorer the reliability of the device.
Therefore, for mass production of InP-based semiconductor devices, an optimization technique of a molecular beam epitaxy stripping process is required to reduce the surface defect density of an InP-based semiconductor device epitaxial wafer and improve the quality of the InP-based semiconductor device epitaxial wafer.
Disclosure of Invention
The application aims to provide a molecular beam epitaxy process optimization method of an InP-based semiconductor device to solve the problem of improving the surface quality of an epitaxial wafer of the InP-based semiconductor device.
In order to achieve the above purpose, the technical scheme adopted by the application is as follows:
the application provides a molecular beam epitaxy process optimization method of an InP-based semiconductor device, which is used for optimizing the substrate demolding time when an InP-based semiconductor device epitaxial wafer is grown by molecular beam epitaxy, and comprises the following steps:
under the condition of preset As pressure, adopting preset stripping temperature T 0 And presetting a stripping time, and stripping the InP substrate;
growing a semiconductor device epitaxial layer with a first preset structure on the InP substrate subjected to film removal by utilizing molecular beam epitaxy so as to form a semiconductor device epitaxial wafer;
carrying out surface appearance characterization test on the epitaxial wafer of the semiconductor device to obtain surface defect data of the epitaxial wafer of the semiconductor device, wherein the surface defect data comprises defect types and defect densities corresponding to the defect types, the defect types comprise a first type of defect and a second type of defect, the first type of defect is a defect caused by incomplete desorption of surface natural oxide of the InP substrate during demolding, the first type of defect is an elliptic defect, point-shaped bulges exist in the inner area of the elliptic defect, the second type of defect is a defect caused by InAs microcrystals formed after phosphorus desorption of the surface of the InP substrate during demolding, the second type of defect is an elliptic defect, and the point-shaped bulges do not exist in the inner area of the elliptic defect;
and determining the demolding time of the InP substrate when the semiconductor device epitaxial wafer with the first preset structure grows next time according to the corresponding relation between the demolding time and the defect density, which is obtained in advance, based on the defect density of the first type defect and the defect density of the second type defect of the semiconductor device epitaxial wafer.
Alternatively, the correspondence between the release time and the defect density is obtained by:
under the condition of preset As pressure, adopting preset stripping temperature T 0 And employs a plurality of different stripping times t k Respectively stripping the InP substrates of the same specification by using k=1, 2,..m, and epitaxially growing an epitaxial layer with a second preset structure on the stripped InP substrates by using molecular beam to obtain a plurality of corresponding InP-based epitaxial wafers, wherein M is an integer greater than or equal to 5, and the thicknesses of natural oxides on the surfaces of the InP substrates of the same specification are the same；
Performing surface appearance characterization test on the plurality of InP-based epitaxial wafers to obtain surface defect data of the plurality of InP-based epitaxial wafers;
calculating defect density parameters of each InP-based epitaxial wafer in the plurality of InP-based epitaxial wafers, forming a relation matrix by the defect density parameters and corresponding demolding time, expressing the corresponding relation between the demolding time and the defect density by the relation matrix, wherein the defect density parameters comprise a first type parameter and a second type parameter, the first type parameter is a difference value between the defect density of the first type defect and the defect density of the second type defect, the second type parameter is the total defect density of the first type defect and the second type defect,
based on the defect density of the first type of defects and the defect density of the second type of defects of the semiconductor device epitaxial wafer, determining the demolding time of the InP substrate when the semiconductor device epitaxial wafer with the first preset structure grows next time according to the corresponding relation between the demolding time and the defect density, wherein the method comprises the following steps:
determining the corresponding demolding time when the second type parameter is minimum based on the corresponding relation between the second type parameter and the demolding time in the relation matrix, and taking the demolding time as the first demolding time;
calculating first type parameters of the semiconductor device epitaxial wafer based on the defect density of the first type defects and the defect density of the second type defects of the semiconductor device epitaxial wafer;
determining the demolding time corresponding to the first type parameter of the epitaxial wafer of the semiconductor device based on the corresponding relation between the first type parameter and the demolding time in the relation matrix, and taking the demolding time as a second demolding time;
the InP substrate film-off time t' at the next growth of the semiconductor device epitaxial wafer having the first preset structure is determined by:
t' =preset release time+ (first release time-second release time).
Optionally, the first preset structure and the second preset structure are the same structure.
Optionally, determining the demolding time corresponding to the first type parameter of the epitaxial wafer of the semiconductor device based on the corresponding relation between the first type parameter and the demolding time in the relation matrix specifically includes:
performing polynomial fitting on the first type parameters and the demolding time in the relation matrix, so as to obtain a polynomial corresponding relation between the first type parameters and the demolding time;
and calculating the demolding time corresponding to the first type parameter of the epitaxial wafer of the semiconductor device by using the polynomial corresponding relation.
Optionally, the plurality of different demolding times t k The following ranges are satisfied for each of the demolding times: greater than or equal to 3 minutes and less than or equal to 11 minutes.
Optionally, m=5, and the plurality of different release times t k The method comprises the following steps of: 3 minutes, 5 minutes, 7 minutes, 9 minutes, 11 minutes.
Optionally, the surface topography characterization test comprises: obtaining a surface morphology photo of a designated area on an epitaxial wafer to be tested under a preset multiple by utilizing a metallographic microscope, identifying defect types of defects on the surface morphology photo, and counting defect densities corresponding to each defect type, wherein the preset multiple is one of the following multiples: 200 times or 500 times or 1000 times.
Optionally, the designated area is represented by a radius r with the center of the epitaxial wafer to be tested as the center 0 Wherein r/50.ltoreq.r 0 And r/10, wherein r represents the radius of the epitaxial wafer to be tested.
Optionally, the preset As pressure ranges are: greater than or equal to 1X 10 -6 Torr, and is less than or equal to 6X 10 -6 Torr。
Optionally, the stripping temperature T is preset 0 In the range T c ≤T 0 ≤T c +20 ℃, wherein T c Is the reference temperature, the reference temperature T c Is determined by the following method: under the condition of preset As pressure, heating the InP substrate to raise the temperature until the RHEED pattern has x 4 reconstruction stripes, and determining the temperature at this time As a reference temperature T c 。
The beneficial effects of the application include:
InP-based semiconductor provided by the applicationThe molecular beam epitaxy process optimization method of the bulk device comprises the following steps: under the condition of preset As pressure, adopting preset stripping temperature T 0 And presetting a stripping time, and stripping the InP substrate; growing a semiconductor device epitaxial layer with a first preset structure on the InP substrate subjected to film removal by utilizing molecular beam epitaxy so as to form a semiconductor device epitaxial wafer; carrying out surface appearance characterization test on the epitaxial wafer of the semiconductor device to obtain surface defect data of the epitaxial wafer of the semiconductor device, wherein the surface defect data comprises defect types and defect densities corresponding to the defect types, the defect types comprise a first type of defect and a second type of defect, the first type of defect is a defect caused by incomplete desorption of surface natural oxide of the InP substrate during demolding, the first type of defect is an elliptic defect, point-shaped bulges exist in the inner area of the elliptic defect, the second type of defect is a defect caused by InAs microcrystals formed after phosphorus desorption of the surface of the InP substrate during demolding, the second type of defect is an elliptic defect, and the point-shaped bulges do not exist in the inner area of the elliptic defect; and determining the demolding time of the InP substrate when the semiconductor device epitaxial wafer with the first preset structure grows next time according to the corresponding relation between the demolding time and the defect density, which is obtained in advance, based on the defect density of the first type defect and the defect density of the second type defect of the semiconductor device epitaxial wafer. The optimized demolding time can be calculated and determined according to the corresponding relation between the demolding time and the defect density of the InP substrate with the same specification, which is established in advance, by acquiring the difference value of the two types of defect densities of the InP substrate under the condition of the preset demolding time, and in the batch production of the InP-based semiconductor device epitaxial wafer, the demolding time of the subsequent round can be optimized conveniently and rapidly according to the growth test result of each round, so that the quality of the InP-based semiconductor device epitaxial wafer is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a molecular beam epitaxy process optimization method of an InP-based semiconductor device according to an embodiment of the present application;
fig. 2 shows a schematic diagram of an InP-based semiconductor device epitaxial wafer surface defect morphology according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The InP-based semiconductor device may be fabricated by a molecular beam epitaxy technique, in which an InP substrate is first subjected to a high-temperature stripping treatment in a molecular beam epitaxy apparatus to remove natural oxides on the surface of the InP substrate, and then a corresponding epitaxial layer is deposited and grown according to the device structure design. In the mass production of InP-based semiconductor devices, the advantages and disadvantages of the molecular beam epitaxy high-temperature stripping process directly affect the surface defect density of the prepared InP-based semiconductor device epitaxial wafer, thereby affecting the yield and reliability of the final device. Too long or too short a stripping time increases the defect density on the substrate surface. The more surface defects of the epitaxial wafer, the lower the yield of the device, and the poorer the reliability of the device. Therefore, for mass production of InP-based semiconductor devices, an optimization technique of a molecular beam epitaxy stripping process is required to reduce the surface defect density of an InP-based semiconductor device epitaxial wafer and improve the quality of the InP-based semiconductor device epitaxial wafer.
Fig. 1 is a schematic flow chart of a molecular beam epitaxy process optimization method of an InP-based semiconductor device according to an embodiment of the present application.
As shown in fig. 1, an embodiment of the present application provides a method for optimizing a molecular beam epitaxy process of an InP-based semiconductor device, where the method is used for optimizing a substrate stripping time when an InP-based semiconductor device epitaxial wafer is grown by molecular beam epitaxy, and the method includes:
step 101, under the condition of preset As pressure, adopting preset stripping temperature T 0 And presetting a stripping time, and stripping the InP substrate.
In general, all the demolding processes involved in the embodiments of the present application are performed under the same preset As pressure conditions, corresponding to different optimal demolding conditions. Optionally, the preset As pressure ranges are: greater than or equal to 1X 10 -6 Torr, and is less than or equal to 6X 10 -6 Torr. For example, the preset As pressure may be 1×10 -6 Torr、2×10 -6 Torr, or 6X 10 -6 Torr, or other values within the above ranges. It should be understood that the above-described As pressure ranges are only preferred, and As pressures can take other values outside the above-described ranges As long As the preset As pressures remain the same As each other during the different rounds of the stripping process. Likewise, different demolding temperatures, corresponding to different optimal demolding times, refer to all demolding processes involved in the embodiment of the present application being at the same preset demolding temperature T 0 And is performed as follows. Optionally, the stripping temperature T is preset 0 In the range T c ≤T 0 ≤T c +20 ℃, wherein T c Is the reference temperature, the reference temperature T c Is determined by the following method: under the condition of preset As pressure, heating the InP substrate to raise the temperature until the RHEED pattern appears x 4 reconstruction stripe, and determining the temperature at this time As the reference temperature T c . It should be noted that the temperatures described in the present application refer to the thermocouple temperatures obtained by the thermocouples for sensing the temperatures of the corresponding components in the molecular beam epitaxy apparatus, and thus, the demolding temperature and the reference temperature refer to the thermocouple temperatures obtained by the thermocouples for sensing the temperatures of the substrates mounted on the sample holder. For example, in general, reference temperature T of InP substrates of the same specification for the same molecular beam epitaxy apparatus c Is stable and constant, and therefore, for InP substrates of any specificationReference temperature T c Can be obtained in advance. For example, the preset stripping temperature T 0 May be equal to T c ，T c +10℃orT c The stripping temperature T is preset only in the stripping process of different rounds at +20 DEG C 0 All that remains the same as each other.
Since the optimal demolding time is not determined before optimization, the demolding time can be selected as the preset demolding time within a reasonable range according to the past experience. For example, alternatively, any one of the demolding times may be selected as the preset demolding time within the following range: greater than or equal to 3 minutes and less than or equal to 11 minutes. For example, the preset demolding time may be 5 minutes.
And 102, growing a semiconductor device epitaxial layer with a first preset structure on the demolding InP substrate by utilizing molecular beam epitaxy so as to form a semiconductor device epitaxial wafer.
And after the demolding is finished, carrying out epitaxial growth on the InP substrate subjected to the demolding according to a material structure of an epitaxial layer of the semiconductor device required by the pre-design, thereby obtaining the epitaxial wafer of the semiconductor device. On the surface of the obtained semiconductor device epitaxial wafer, there are generally various types of surface defects, some of which are caused by the stripping process, some of which are caused by the quality problems of the substrate itself, and others of which cause the surface defects. The topography of surface defects caused by different causes is often different. The method provided by the application is only optimized for the stripping time in the stripping process, so that the surface defects of the epitaxial wafer caused by unsuitable stripping time are reduced.
And 103, carrying out surface appearance characterization test on the semiconductor device epitaxial wafer to obtain surface defect data of the semiconductor device epitaxial wafer.
The surface defect data includes defect types and defect densities corresponding to each defect type. The defect density mentioned in the present application means the number of defects per unit area. The defect types include a first type of defect and a second type of defect, the first type of defect is a defect caused by incomplete desorption of a natural oxide on the surface of the InP substrate at the time of film removal, the first type of defect has an oval shape, point-shaped protrusions exist in the inner area of the oval shape, the second type of defect is a defect caused by InAs microcrystals formed after desorption of phosphorus on the surface of the InP substrate at the time of film removal, specifically, the second type of defect is a defect caused by combination of indium points formed after desorption of phosphorus on the surface of the InP substrate with As and thus formed InAs microcrystals, the second type of defect has an oval shape, and point-shaped protrusions do not exist in the inner area of the oval shape. Fig. 2 shows a schematic diagram of an InP-based semiconductor device epitaxial wafer surface defect morphology according to an embodiment of the present application. As shown in fig. 2, the defects 201 and 204 are elliptical defects, and there are dot-like protrusions in the inner areas of the defects 201 and 204, the defects 201 and 204 are classified as a first type of defects, the defects 202, 203, and 205 are elliptical defects, and there are no dot-like protrusions in the inner areas of the defects 202, 203, and 205, thus classifying the defects 202, 203, and 205 as a second type of defects. It should be understood that the present application does not limit or consider the size of the defects themselves in classifying each defect. It should be understood that other types of defects besides the first type of defects and the second type of defects described above may also exist on the semiconductor device epitaxial wafer, and the present application does not account for the other types of defects.
Optionally, the surface topography characterization test comprises: obtaining a surface morphology photo of a designated area on an epitaxial wafer to be tested under a preset multiple by utilizing a metallographic microscope, identifying defect types of defects on the surface morphology photo, and counting defect densities corresponding to each defect type, wherein the preset multiple is one of the following multiples: 200 times or 500 times or 1000 times. In a specific operation, the defect type of the defect on the surface topography photograph is identified from the topography of the defect as described above with reference to fig. 2. Omission of small-size defects can be avoided by a larger microscope magnification, however, the magnification is too large, which reduces the efficiency of statistical recognition, preferably 500 times the preset magnification can be selected. Defects on the surface of an epitaxial wafer are typically distributed across the entire surface, typically substantiallyHomogeneous, but there are also the following cases: the number of defects is either abnormally small or abnormally large in a very small area. In order to more truly reflect the overall situation of defects on the surface of the epitaxial wafer, and simultaneously reduce the statistical workload as much as possible, an area with proper size on the surface of the epitaxial wafer can be selected as a surface morphology characterization test area. Optionally, the designated area is represented by a radius r with the center of the epitaxial wafer to be tested as the center 0 Wherein r/50.ltoreq.r 0 And r/10, wherein r represents the radius of the epitaxial wafer to be tested. For example, r can be chosen 0 Circular area =r/20.
Step 104, determining the demolding time of the InP substrate when the semiconductor device epitaxial wafer with the first preset structure grows next according to the corresponding relation between the demolding time and the defect density obtained in advance based on the defect density of the first type defect and the defect density of the second type defect of the semiconductor device epitaxial wafer.
The correspondence between the release time and the defect density is obtained by:
under the condition of preset As pressure, adopting preset stripping temperature T 0 And employs a plurality of different stripping times t k And (2) respectively stripping the InP substrates of the same specification by using k=1, 2,..m, and epitaxially growing an epitaxial layer with a second preset structure on the stripped InP substrates by using a molecular beam to obtain a plurality of corresponding InP-based epitaxial wafers, wherein M is an integer greater than or equal to 5, and the natural oxide thicknesses on the surfaces of the InP substrates of the same specification are the same. Optionally, the plurality of different demolding times t k The following ranges are satisfied for each of the demolding times: greater than or equal to 3 minutes and less than or equal to 11 minutes. Optionally, m=5, and the plurality of different release times t k The method comprises the following steps of: 3 minutes, 5 minutes, 7 minutes, 9 minutes, 11 minutes. Performing surface appearance characterization test on the plurality of InP-based epitaxial wafers to obtain surface defect data of the plurality of InP-based epitaxial wafers; calculating defect density parameters of each InP-based epitaxial wafer in the plurality of InP-based epitaxial wafers, forming a relation matrix by the defect density parameters and corresponding demolding time, and forming a relation matrix byThe relation matrix represents the corresponding relation between the demolding time and the defect density, wherein the defect density parameters comprise a first type parameter and a second type parameter, the first type parameter is the difference value between the defect density of the first type defect and the defect density of the second type defect, and the second type parameter is the total defect density of the first type defect and the second type defect, namely, the second type parameter is the sum of the defect density of the first type defect and the defect density of the second type defect. Different surface native oxide thicknesses correspond to different optimal stripping times. The optimal stripping time (at the same stripping temperature in the same equipment) for InP substrates of the same specification with the same surface native oxide thickness is the same. The InP substrates of the same specification described herein, in addition to meaning that the conventional specification parameters of the substrates are consistent, also mean that the thicknesses of the natural oxides on the surfaces of these substrates are consistent, and in general, the same batch of substrates of the same specification are selected and the pretreatment process (e.g., cleaning process, degassing process, etc.) before the stripping process is performed is the same, so that the thicknesses of the natural oxides on the surfaces of these InP substrates are ensured to be consistent. The first preset structure and the second preset structure may be the same or different, and preferably, the first preset structure and the second preset structure are the same structure.
Specifically, for InP substrates of the same specification (that is, the doping type, doping concentration, size, polishing type, and other conventional substrate parameters are the same), substrates produced in different batches may have differences in the thickness of the natural oxide on the InP substrate surface before undergoing the stripping due to substrate preparation process stability, environment, packaging factors, stability of the pretreatment process (e.g., cleaning process) of the substrate before entering the molecular beam epitaxy apparatus, etc., the stripping time may be too short, the natural oxide may not be removed cleanly, defects may be introduced (i.e., the first type defects described above), and the stripping time may be too long, although the natural oxide is removed, new defects may be introduced due to indium spots formed after the desorption of phosphorus (i.e., the second type defects described above). Thus, for natural oxides of different thickness, theoretically the optimal stripping time corresponds. In molecular beam epitaxy mass production, if the thickness of the surface native oxide of each InP substrate is precisely measured, time and test cost are greatly increased, and other contamination is introduced at the time of the test, so it is not practical to test the surface native oxide thickness of each InP substrate in mass production. The method of the application is to test the surface morphology of the epitaxial wafer after the growth (the epitaxial wafer is nondestructive by using a microscope, and the epitaxial wafer does not pollute the epitaxial layer after the growth), and then to feed back the rapid calculation to the subsequent growth.
Based on the defect density of the first type of defects and the defect density of the second type of defects of the semiconductor device epitaxial wafer, determining the demolding time of the InP substrate when the semiconductor device epitaxial wafer with the first preset structure grows next time according to the corresponding relation between the demolding time and the defect density, wherein the method comprises the following steps:
based on the corresponding relation between the second type of parameters and the demolding time in the relation matrix, determining the demolding time corresponding to the minimum second type of parameters, taking the demolding time as the first demolding time, and characterizing the total amount of surface defects on the surface of the epitaxial wafer caused by the demolding process per se by the total defect density (namely the second type of parameters) of the first type of defects and the second type of defects. The second type of parameter is specifically the sum of the defect density of the first type of defect and the defect density of the second type of defect. The smaller the second type parameter is, the fewer defects the demolding process itself causes on the surface of the epitaxial wafer are represented, and the larger the second type parameter is, the more defects the demolding process itself causes on the surface of the epitaxial wafer are represented, so the optimization of the demolding process aims at obtaining smaller second type parameters.
Calculating first type parameters of the semiconductor device epitaxial wafer based on the defect density of the first type defects and the defect density of the second type defects of the semiconductor device epitaxial wafer; and determining the demolding time corresponding to the first type parameter of the epitaxial wafer of the semiconductor device based on the corresponding relation between the first type parameter and the demolding time in the relation matrix, and taking the demolding time as the second demolding time. Optionally, determining the demolding time corresponding to the first type parameter of the epitaxial wafer of the semiconductor device based on the corresponding relation between the first type parameter and the demolding time in the relation matrix specifically includes: performing polynomial fitting on the first type parameters and the demolding time in the relation matrix, so as to obtain a polynomial corresponding relation between the first type parameters and the demolding time; and calculating the demolding time corresponding to the first type parameter of the epitaxial wafer of the semiconductor device by using the polynomial corresponding relation.
Since the first type of defects are defects caused by incomplete desorption of the natural oxide on the surface of the InP substrate during the film release, it is known that the defect density of the first type of defects gradually decreases with the increase of the film release time for the same piece of InP substrate; since the second type of defects are defects caused by InAs crystallites formed by the combination of As and indium sites formed by the desorption of phosphorus from the surface of an InP substrate during the film release, it is known that the defect density of the second type of defects gradually increases with the increase of the film release time for the same piece of InP substrate. To optimize the release time, the defect density of the first type of defect and the defect density of the second type of defect can be used to establish a reference index that directs the optimization of the release time.
If only one of the defect density of the first type of defect or the defect density of the second type of defect is used as a reference index, for example, the defect density of the first type of defect is used as a reference index, when the actual demolding time is too long, the defect density of the first type of defect is very small, and different demolding time periods may cause that the observed value of the defect density is not greatly different, so that a single defect density value cannot accurately guide the optimization process. Therefore, the application adopts the first type parameter (namely the difference value of the defect density of the first type defect minus the defect density of the second type defect) as the reference index, in this case, when the demolding time is too short, the defect density value of the first type defect is large, the defect density value of the second type defect is very small, and the change of the value of the first type parameter is mainly determined by the defect density value of the first type defect; when the demolding time is too long, the defect density value of the first type of defects is very small, the defect density value of the second type of defects is large, the change of the numerical value of the first type of parameters is mainly determined by the defect density value of the second type of defects, and the first type of parameters determined by the method can reflect the change condition of the defect density along with time when the demolding time is too short or too long. For the same InP substrate, the defect density of the first type of defect gradually decreases and the defect density of the second type of defect gradually increases as the stripping time increases, and thus the value of the first type of parameter gradually decreases. Thus, a correspondence between the first type of parameter and the release time can be established.
The InP substrate film-off time t' at the next growth of the semiconductor device epitaxial wafer having the first preset structure is determined by: t' =preset release time+ (first release time-second release time).
Preferably, the conventional parameters of the InP substrate (i.e., doping type, doping concentration, size, polishing type, etc. of the substrate) used in the growth of the first and second preset structures in the present application are the same, it being understood that the conventional parameters herein do not include native oxide thickness.
Specifically, in the experiments for establishing the correspondence, for InP substrates of the same specification and the same thickness of natural oxide, the correspondence between the first type of parameters and the stripping time is established, and at the same time, the stripping time (i.e., the first stripping time) corresponding to the minimum second type of parameters is obtained. For a new InP substrate, since the thickness of the native oxide of the substrate is unknown, the preset stripping time is usually not an optimal value, and for an epitaxial wafer grown after stripping with the preset stripping time, a first type of parameter of the epitaxial wafer may be obtained, and from this parameter, the corresponding stripping time (i.e., the second stripping time described above) may be obtained from the correspondence. If the first stripping time is longer than the second stripping time, that is, the current stripping time is shorter, the next stripping time needs to be increased. If the first stripping time is smaller than the second stripping time, that is, it is indicated that the current stripping time is longer, the next stripping time needs to be reduced, specifically, the next InP substrate stripping time=preset stripping time+ (first stripping time-second stripping time) when the semiconductor device epitaxial wafer having the first preset structure is grown.
It should be noted that, all the stripping processes and the epitaxy processes involved in the embodiments of the present application are directed to the same molecular beam epitaxy apparatus. In general, different molecular beam epitaxy apparatuses correspond to different optimal process parameters when in operation, so if the molecular beam epitaxy apparatus needs to be replaced, a relationship matrix needs to be reconstructed according to the method provided by the embodiment of the application for a new epitaxy apparatus.
In summary, by obtaining the difference between the two types of defect densities of the InP substrate under the preset demolding time conditions, the optimized demolding time can be calculated and determined according to the corresponding relationship between the demolding time and the defect density of the InP substrate with the same specification, and in the batch production of InP-based semiconductor device epitaxial wafers, the demolding time of the subsequent rounds can be optimized conveniently and rapidly according to the growth test result of each round, so that the quality of the InP-based semiconductor device epitaxial wafers is improved.
The above embodiments are only for illustrating the technical concept and features of the present application, and are intended to enable those skilled in the art to understand the content of the present application and implement the same, but not limit the scope of the present application, and all equivalent changes or modifications made according to the spirit of the present application should be included in the scope of the present application.
Claims (10)
1. A method for optimizing a molecular beam epitaxy process of an InP-based semiconductor device, wherein the method is used for optimizing a substrate stripping time when an InP-based semiconductor device epitaxial wafer is grown by molecular beam epitaxy, the method comprising:
under the condition of preset As pressure, adopting preset stripping temperature T 0 And presetting a stripping time, and stripping the InP substrate;
growing a semiconductor device epitaxial layer with a first preset structure on the InP substrate subjected to film removal by utilizing molecular beam epitaxy so as to form a semiconductor device epitaxial wafer;
carrying out surface appearance characterization test on the semiconductor device epitaxial wafer to obtain surface defect data of the semiconductor device epitaxial wafer, wherein the surface defect data comprises defect types and defect densities corresponding to the defect types, the defect types comprise a first type of defect and a second type of defect, the first type of defect is a defect caused by incomplete desorption of surface natural oxide of an InP substrate during demolding, the first type of defect is an elliptic defect, point-shaped bulges exist in the inner area of the elliptic defect, the second type of defect is a defect caused by InAs microcrystals formed after phosphorus on the surface of the InP substrate is desorbed during demolding, and the second type of defect is an elliptic defect and does not exist in the inner area of the elliptic defect;
and determining the demolding time of the InP substrate when the semiconductor device epitaxial wafer with the first preset structure grows next time according to the corresponding relation between the demolding time and the defect density obtained in advance based on the defect density of the first type defect and the defect density of the second type defect of the semiconductor device epitaxial wafer.
2. The method of optimizing a molecular beam epitaxy process of an InP-based semiconductor device according to claim 1, wherein the correspondence between the stripping time and defect density is obtained by:
under the condition of the preset As pressure, adopting the preset stripping temperature T 0 And employs a plurality of different stripping times t k Respectively performing film stripping on the InP substrates with the same specification, and performing epitaxial growth on the film-stripped InP substrates by using a molecular beam to obtain a plurality of corresponding InP-based epitaxial wafers, wherein k=1, 2, & M is an integer greater than or equal to 5, and the thicknesses of natural oxides on the surfaces of the InP substrates with the same specification are the same;
performing surface appearance characterization test on the plurality of InP-based epitaxial wafers to obtain surface defect data of the plurality of InP-based epitaxial wafers;
calculating defect density parameters of each InP-based epitaxial wafer in the plurality of InP-based epitaxial wafers, forming a relation matrix by the defect density parameters and corresponding demolding time, expressing the corresponding relation between the demolding time and the defect density by the relation matrix, wherein the defect density parameters comprise a first type parameter and a second type parameter, the first type parameter is a difference value of the defect density of the first type defect minus the defect density of the second type defect, the second type parameter is a total defect density of the first type defect and the second type defect,
the determining the InP substrate stripping time when the semiconductor device epitaxial wafer with the first preset structure is grown next according to the corresponding relationship between the pre-obtained stripping time and the defect density, wherein the defect density is based on the first type defect and the second type defect of the semiconductor device epitaxial wafer comprises:
determining the corresponding demolding time when the second type parameter is minimum based on the corresponding relation between the second type parameter and the demolding time in the relation matrix, and taking the demolding time as the first demolding time;
calculating first type parameters of the semiconductor device epitaxial wafer based on the defect density of the first type defects and the defect density of the second type defects of the semiconductor device epitaxial wafer;
determining the demolding time corresponding to the first type parameter of the epitaxial wafer of the semiconductor device based on the corresponding relation between the first type parameter and the demolding time in the relation matrix, and taking the demolding time as a second demolding time;
the InP substrate stripping time t' when the semiconductor device epitaxial wafer having the first preset structure is grown next time is determined by the following formula:
t' =preset release time+ (first release time-second release time).
3. The method of claim 2, wherein the first predetermined structure and the second predetermined structure are the same structure.
4. The method for optimizing molecular beam epitaxy process of InP-based semiconductor devices according to claim 2, wherein determining the demolding time corresponding to the first type parameter of the semiconductor device epitaxial wafer based on the correspondence between the first type parameter and the demolding time in the relation matrix specifically comprises:
performing polynomial fitting on the first type parameters and the demolding time in the relation matrix to obtain a polynomial corresponding relation between the first type parameters and the demolding time;
and calculating the demolding time corresponding to the first type parameter of the semiconductor device epitaxial wafer by utilizing the polynomial corresponding relation.
5. The method of optimizing molecular beam epitaxy process of InP-based semiconductor devices according to claim 2, wherein said plurality of different stripping times t k The following ranges are satisfied for each of the demolding times: greater than or equal to 3 minutes and less than or equal to 11 minutes.
6. The method of optimizing molecular beam epitaxy process of InP-based semiconductor devices according to claim 5, wherein m=5, and said plurality of different stripping times t k The method comprises the following steps of: 3 minutes, 5 minutes, 7 minutes, 9 minutes, 11 minutes.
7. The method of optimizing molecular beam epitaxy process of InP-based semiconductor devices according to claim 1, wherein the surface topography characterization test comprises: obtaining a surface morphology photo of a designated area on an epitaxial wafer to be tested under a preset multiple by utilizing a metallographic microscope, identifying defect types of defects on the surface morphology photo, and counting defect densities corresponding to each defect type, wherein the preset multiple is one of the following multiples: 200 times or 500 times or 1000 times.
8. The method for optimizing molecular beam epitaxy process of InP-based semiconductor device according to claim 7, wherein said designated region is represented by a radius r centered on the center of the epitaxial wafer to be tested 0 Wherein r/50.ltoreq.r 0 R/10, wherein r represents the substance to be testedRadius of the epitaxial wafer tested.
9. The method for optimizing molecular beam epitaxy process of InP-based semiconductor devices according to claim 1, wherein the pressure range of the preset As pressure is: greater than or equal to 1X 10 -6 Torr, and is less than or equal to 6X 10 -6 Torr。
10. The method of optimizing molecular beam epitaxy process of InP-based semiconductor devices according to claim 9, wherein said preset stripping temperature T 0 In the range T c ≤T 0 ≤T c +20 ℃, wherein T c Is the reference temperature, the reference temperature T c Is determined by the following method: under the condition of the preset As pressure, heating the InP substrate to raise the temperature until the RHEED pattern is in x 4 reconstruction stripes, and determining the temperature at the moment As a reference temperature T c 。
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| CN103820848A (en) * | 2014-02-27 | 2014-05-28 | 华南师范大学 | Method for epitaxial growth of II-type GaSb/InGaAs quantum point on InP substrate |
| CN112820630A (en) * | 2020-12-31 | 2021-05-18 | 中山大学 | Method for reducing dislocation defect density in silicon-based hetero-epitaxial growth III-V group semiconductor |
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| CN103820848A (en) * | 2014-02-27 | 2014-05-28 | 华南师范大学 | Method for epitaxial growth of II-type GaSb/InGaAs quantum point on InP substrate |
| CN112820630A (en) * | 2020-12-31 | 2021-05-18 | 中山大学 | Method for reducing dislocation defect density in silicon-based hetero-epitaxial growth III-V group semiconductor |
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