JP2001302395A - Method of producing highly flat epitaxial wafer - Google Patents

Method of producing highly flat epitaxial wafer

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Publication number
JP2001302395A
JP2001302395A JP2000118953A JP2000118953A JP2001302395A JP 2001302395 A JP2001302395 A JP 2001302395A JP 2000118953 A JP2000118953 A JP 2000118953A JP 2000118953 A JP2000118953 A JP 2000118953A JP 2001302395 A JP2001302395 A JP 2001302395A
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flatness
substrate
epitaxial growth
epitaxial
step
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Shinji Okawa
真司 大川
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Sumitomo Metal Ind Ltd
住友金属工業株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a method of producing a highly flat epitaxial wafer, by which the epitaxial wafer high in flatness can be obtained and the rate of inferior products can be reduced without adding a new process and causing lowering of flatness after epitaxially growing.
SOLUTION: After processing a substrate so as to make it flat, the flatness of an epitaxially grown wafer is estimated before epitaxially growing, and then epitaxial growth is carried out using only a substrate satisfying required standards.
COPYRIGHT: (C)2001,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】この発明は、シリコンやガリウム砒素などの半導体基板にエピタキシャル成長を行うウェーハの製造方法の改良に係り、基板の平坦化加工後、エピタキシャル成長前に同成長後の平坦度を予測して、所要基準を満たす基板にのみエピタキシャル成長を行い、高歩留りを得ることを特徴とする高平坦度エピタキシャルウェーハの製造方法に関する。 TECHNICAL FIELD The present invention relates to an improvement of a method for manufacturing a wafer for performing epitaxial growth on a semiconductor substrate such as silicon or gallium arsenide, after planarization of the substrate, predict the flatness after the growth before the epitaxial growth to perform the epitaxially grown only on the substrate to meet the required standards, the method for producing a high flatness epitaxial wafer, comprising obtaining a high yield.

【0002】 [0002]

【従来の技術】エピタキシャルシリコンウェーハは、デバイスを作成する表面のエピタキシャル層に酸素起因の欠陥や単結晶インゴット育成時に導入されるGrown‐in BACKGROUND ART epitaxial silicon wafer, Grown-in introduced during the epitaxial layer to the oxygen-induced defects and a single crystal ingot grown on the surface creating a device
欠陥(COPを含む)がない優れた特性を有している。 Defects (including COP) has no excellent characteristics.

【0003】近年、MPUやフラッシュメモリー等の高性能デバイスやMOS FET、IGBT等の高性能Powerデバイスにはエピタキシャルシリコンウェーハが使用されつつある。 [0003] In recent years, MPU and flash memory such as a high-performance device or MOS FET of, while epitaxial silicon wafer is used for the high-performance Power device such as an IGBT. 一方、デバイスの高集積化に伴って、半導体基板の高品質化とともに微細化パターンの作製のために、高平坦化が不可欠となっている。 On the other hand, with the integration of devices, for the production of fine patterns with a high quality of the semiconductor substrate, high planarization is indispensable.

【0004】高平坦度が要求されているウェーハのエピタキシャル成長は、枚葉処理によって膜厚均一性の向上が図られている。 [0004] High epitaxial growth of flatness is required wafer, improving the film thickness uniformity is achieved by single wafer processing. しかし、原料ガスの流れむらや温度分布が生じるため、エピ膜の膜厚に若干の不均一な分布が生じてしまう。 However, since the flow unevenness or temperature distribution of the feed gas occurs, some non-uniform distribution in the film thickness of the epitaxial layer occurs. この膜厚偏差がエピタキシャル成長後の平坦度劣化を引き起こすことになる。 The film thickness deviation will cause flatness degradation after the epitaxial growth.

【0005】 [0005]

【発明が解決しようとする課題】そこで、エピタキシャル成長条件の最適化を図り、膜厚みの不均一分布を低減する方法が多々提案されている。 [SUMMARY OF THE INVENTION Therefore, optimizes the epitaxial growth conditions, a method of reducing the uneven distribution of the membrane thickness have been proposed many. しかし、エピタキシャル成長の後に、平坦度不良が発生した場合、再び平坦化加工を行うことができないため、製品は不良品となり無駄になってしまう。 However, after the epitaxial growth, if the flatness defect occurs, it is not possible to carry out flattening again, the product is wasted become a defective product.

【0006】また、エピタキシャル成長後に基板の平坦度測定を行うことは、工程を増やすだけでなく、パーティクルなどの汚染を増加させる要因にもなる。 Further, by performing a flatness measurement of the substrate after the epitaxial growth, not only increasing the number of steps, also a cause of increasing contamination such as particles. この場合、パーティクルなどの除去のために洗浄工程が必要となり、 In this case, the cleaning step is required for removal of such particles,
さらに工程とコストの増大につながることになる。 Further comprising a lead to process and cost increase.

【0007】この発明は、上述の高平坦度エピタキシャルウェーハの製造に際しての問題を解消し、新たな工程を増やしたり、エピタキシャル成長後の平坦度の劣化を招来することなく、高平坦度を確保でき、製品不良を大きく減少させることが可能な高平坦度エピタキシャルウェーハの製造方法の提供を目的としている。 [0007] This invention is to solve the problem of the production of the high flatness epitaxial wafer described above, increased or a new step, without causing deterioration of flatness after the epitaxial growth, it is possible to ensure a high degree of flatness, It is intended to provide a high flatness epitaxial wafer manufacturing method of capable of reducing product defects increases.

【0008】 [0008]

【課題を解決するための手段】発明者は、通常、エピタキシャルウェーハの高平坦度を確保するために通常設定している、基板自体の高平坦化の加工条件とエピタキシャル成長時の均一に成膜する成膜条件に基づくように操業条件を、最大限に有効利用するため、平坦化の加工を完了した基板について、当該基板がエピタキシャル成長後に平坦度がどうなるか予測して、要求される基準に満たない場合は再度平坦化の加工を行うことにより、エピタキシャル成長後の歩留りの向上と高平坦化の確保が可能になることを知見し、この発明を完成した。 Means for Solving the Problems The inventors are usually normally set in order to ensure a high flatness of the epitaxial wafer is uniformly deposited upon the processing conditions and the epitaxial growth of high planarization of the substrate itself the operating conditions to be based on film forming conditions, in order to effectively use the most, the substrate after the processing of flattening, by predicting whether the substrate is what the flatness after the epitaxial growth, less than the required reference by performing processing of flattening again if, and it found that is possible to secure improved and high planarization of the yield after the epitaxial growth, thereby completing the present invention.

【0009】すなわち、この発明は、基板に平坦化加工を施す工程、その後エピタキシャル成長処理する工程を含むウェーハの製造方法において、平坦化加工後の平坦度の測定工程と、エピタキシャル成長後の基板平坦度の予測工程を経てからエピタキシャル成長を行うことを特徴とする高平坦度エピタキシャルウェーハの製造方法である。 [0009] Namely, the present invention includes the steps of applying a flattening on a substrate, then the method of manufacturing a wafer comprising a step of epitaxially growing process, the step of measuring the flatness after flattening, the substrate flatness after the epitaxial growth a high flatness epitaxial wafer manufacturing method which is characterized in that the epitaxial growth from the through prediction process.

【0010】また、この発明におけるエピタキシャル成長後基板平坦度の予測工程は、加工後の基板の平坦度測定による面内分布データに、予め測定したエピタキシャル成長後の基板の平坦度測定による面内分布データを加えて、平坦度の予測を行うことを特徴とする。 Further, the prediction process of the epitaxial growth after the substrate flatness in this invention, the in-plane distribution data by flatness measurement of the substrate after processing, the in-plane distribution data by the flatness measurement of the substrate after the epitaxial growth measured in advance in addition, and performs a prediction of flatness.

【0011】 [0011]

【発明の実施の形態】この発明による製造方法は、図1 Manufacturing method according to an embodiment of the Invention The present invention, FIG. 1
に示すごとく、まず、基板の平坦化加工を施した後、その平坦度を測定して所要の平坦度を満足するものを次工程に送り、基準を満足しないものは再度平坦化加工に戻す。 As shown in, first, after performing flattening of the substrate, feeding the one that satisfies the required flatness by measuring the flatness in the next step, which do not satisfy the criteria revert to planarization again.

【0012】ここで、平坦化加工方法は、目的の平坦度を得るために、公知の研削及び研磨方法のいずれの方法、組合せであっても適用できる。 [0012] Here, planarization methods, in order to obtain the flatness of the object, any method known in the grinding and polishing method can be applied even in combination. 例えば、高平面度に加工されたセラミックスプレートにウェーハを接着し、回転する高平面度の定盤の上に張られた研磨布の上に設置して、コロイダルシリカを主成分とする研磨スラリーを流しながら、セラミックスプレートに均等な荷重を加えかつ自転することにより研磨を行う方法がある。 For example, bonding the wafer to a ceramic plate which is processed with high flatness, and placed on a polishing cloth is stretched over the platen of a high flatness which rotates, the polishing slurry mainly composed of colloidal silica while flowing, there is a method of polishing by a uniform load is applied and rotation to the ceramic plate.

【0013】次に、所要の平坦度を満足した基板は、基板平坦度の予測工程にてエピタキシャル成長後の平坦度をシミュレートする。 [0013] Next, the substrate satisfying the requirements of flatness, to simulate the flatness after the epitaxial growth at a substrate flatness of the prediction process. シミュレート方法は基板情報にエピタキシャル情報を加えて、エピタキシャル成長後の情報を作成する。 Simulation method in addition to epitaxial information on board information, generates information after the epitaxial growth.

【0014】一例を示すと、先の平坦化加工後のある基板における面内平坦度データfs(x,y)が、図2Aに示すごとき状態であったとした場合、また、エピタキシャル成長後の膜厚みの平坦度を実測した面内平坦度データfe(x,y) [0014] As an example, in-plane flatness data fs (x, y) in the substrate with a post-planarization of previously, if a was in a state such shown in FIG. 2A, also, the film thickness after the epitaxial growth flatness of the measured in-plane flatness data fe (x, y)
が、図2Bに示すごとき状態であったとした場合、当該基板のエピタキシャル成長後の予測基板平坦度fE(x,y) But, when a which was in the state such 2B, the predicted substrate flatness fE after the epitaxial growth of the substrate (x, y)
は、先の両データの和(fs(x,y)+fe(x,y))として算出することができる。 It can be calculated as the sum of the previous two data (fs (x, y) + fe (x, y)).

【0015】エピタキシャル成長後の平坦度の予測工程で、 [0015] after the epitaxial growth in the flatness of the prediction process,
目的の成膜後の基板平坦度を満足すると判断された基板は、次工程のエピタキシャル成長へと送られ、基準を満足しなかった基板は再度平坦化加工工程へ戻される。 Purpose substrate is determined to satisfy the substrate flatness after the film formation of is sent to the epitaxial growth of the next step, the substrate did not satisfy the criteria is returned again to the flattening process.

【0016】目的の成膜後の基板平坦度を満足すると判断された基板は、エピタキシャル成長装置にて所要の成膜が施され、そのまま製品とすることができる。 [0016] substrate that is determined to satisfy the substrate flatness after the film formation of interest, the required film is subjected by epitaxial growth apparatus, it is possible to directly product. すなわち、 That is,
図1で想像線で示す、従来の工程である、エピタキシャル成長後の平坦度測定を行う必要もなく、また該測定で汚染される懸念もなくなる。 Shown in phantom in FIG. 1, a conventional process, it is not necessary to perform a flatness measurement after the epitaxial growth, also eliminates concern contaminated with the measurement.

【0017】この発明において、平坦化加工して所定の基準を満足した基板で、さらにエピタキシャル成長後の平坦度の予測工程でも目的の成膜後の基板平坦度を満足すると判断された基板は、エピタキシャル成長後にその平坦度の測定を行ったとしても基準を満足し、極めて高い歩留りを示す。 [0017] In the present invention, the substrate that satisfies a predetermined criterion by processing flattening, the substrate is determined that further satisfies the substrate flatness after the film formation of interest in the prediction step of flatness after the epitaxial growth, the epitaxial growth later also satisfy the criteria as were measured for the flatness, a very high yield. 従って、エピタキシャル成長後の平坦度測定を行う必要がない利点がある。 Therefore, there is an advantage not necessary to perform the flatness measurement after the epitaxial growth.

【0018】この発明において、エピタキシャル成長並びにその装置には公知のいずれ手段、構成も採用できる。 [0018] In the present invention, epitaxial growth and any known means to the device, can be adopted configurations. 例えば、エピタキシャル成長装置には、枚葉のシングルチャンバー型のランプ加熱炉が用いられる。 For example, in the epitaxial growth apparatus, single lamp heating furnace leaves the single-chamber is used.

【0019】 [0019]

【実施例】図1に示す工程を次の条件で実施してエピタキシャルシリコンウェーハを製造した。 EXAMPLES step shown in FIG. 1 under the following conditions to produce an epitaxial silicon wafer. エピタキシャル成長後そのまま製品とする場合と、成長後の平坦度測定を行う場合の2種の方法を実施した。 The case of the epitaxial growth after it products was carried out two methods for performing the flatness measurement after growth.

【0020】シリコンウェーハには、P(100)、0.01〜0.02Ω [0020] silicon wafer, P (100), 0.01~0.02Ω
・cm、裏面にCVD酸化膜を有するポリッシュドウェーハを用いた。 · Cm, using a polished wafer having a CVD oxide film on the back surface. 平坦度測定は、静電容量センサー方式による測定器を用いた。 Flatness measurements were used measuring apparatus according to the electrostatic capacitance sensor type. 判定は、FQA196mm、サイトサイズ25mm Determination, FQA196mm, site size 25mm
×25mm、SFQR0.18μmで実施、本規格に合格した96枚に対してエピタキシャル成長後の平坦度を予測した。 × 25 mm, carried out in SFQR0.18Myuemu, it predicted flatness after the epitaxial growth with respect to 96 sheets that pass this standard.

【0021】エピタキシャル成長後の平坦度予測は、基板平坦度測定データにエピタキシャル膜厚みデータを加えた後、FQA196mm、サイトサイズ25mm×25mm、SFQR0.18μm The flatness prediction after the epitaxial growth, after adding an epitaxial film thickness data to the substrate flatness measurement data, FQA196mm, site size 25mm × 25mm, SFQR0.18μm
で計算した。 In was calculated. 予測の結果96枚中、5枚が0.18μmより大きくなり、不合格と判定された。 Results 96 sheets of prediction, five sheets larger than 0.18 .mu.m, was determined to fail.

【0022】合格判定後の91枚に対して、SiHCl 3 /B 2 H 6を用いて、成長温度1135℃で膜厚み5μmエピタキシャル成長させた。 [0022] For 91 sheets after acceptance, with SiHCl 3 / B 2 H 6, was film thickness 5μm epitaxial growth at a growth temperature of 1135 ° C.. エピタキシャル成長後の平坦度測定を成長前の平坦度測定と同じ条件で実施したところ、91枚の中に不合格はなかった。 Was subjected to a flatness measurement after the epitaxial growth under the same conditions as flatness measurement before growth, there was no failure in the 91 sheets.

【0023】また比較のため、平坦度予測にて不合格と判定された5枚の基板についても、上記条件で、1)エピタキシャル成長、2)エピタキシャル成長後の平坦度測定の工程でエピタキシャルシリコンウェーハを製造した。 [0023] For comparison, five substrates it is determined that the failure in flatness prediction, under the above conditions, 1) epitaxial growth, 2) manufacturing an epitaxial silicon wafer in the step of flatness measurement after the epitaxial growth did. しかし、5枚のウェーハ全て、0.18μmより大きくなり、不合格となった。 However, all five of the wafer becomes larger than 0.18μm, was disqualified.

【0024】この発明の製造方法では、成長後の平坦度測定を行い不合格となった基板は、皆無であった。 [0024] In the production method of the present invention, a substrate that fail perform flatness measurements after growth, there was no. 一方、比較の従来法による場合は、最終の不良率は、96枚中5枚の5.2%であった。 On the other hand, if according to the conventional method of comparison, the final defect rate was 5.2% in five 96 sheets.

【0025】 [0025]

【発明の効果】この発明は、基板の平坦化加工後、エピタキシャル成長前に同成長後の平坦度を予測して、所要基準を満たす基板にのみエピタキシャル成長を行うことにより、目的の高平坦度を有するエピタキシャルシリコンウェーハを容易に製造でき、従来のごとく成長後の平坦度測定を行う工程が不要で、同測定工程で汚染される懸念もなくなる。 [Effect of the Invention] This invention has after planarization of the substrate, to predict the flatness after the growth before the epitaxial growth, by performing the epitaxially grown only on the substrate satisfies the required standards, the high flatness of the object the epitaxial silicon wafer can be easily manufactured, the step of performing flatness measurement of conventional as after the growth is not required, eliminating concern that are contaminated with the measurement process.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】この発明による製造工程を示すフローチャート図である。 1 is a flowchart showing a manufacturing process according to the present invention.

【図2】面内平坦度データを模式的に示す説明図であり、Aは平坦加工後の基板、Bは成膜された膜、Cはエピタキシャル成長後の基板の場合を示す。 [2] The plane flatness data is an explanatory view schematically showing, A is the substrate after flattening, B is deposited film, C is shown a case of the substrate after the epitaxial growth.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl. 7識別記号 FI テーマコート゛(参考) H01L 21/66 H01L 21/66 Z ────────────────────────────────────────────────── ─── of the front page continued (51) Int.Cl. 7 identification mark FI theme Court Bu (reference) H01L 21/66 H01L 21/66 Z

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 基板に平坦化加工を施す工程、その後エピタキシャル成長処理する工程を含むウェーハの製造方法において、平坦化加工後の平坦度の測定工程と、エピタキシャル成長後の基板平坦度の予測工程を経てからエピタキシャル成長を行う高平坦度エピタキシャルウェーハの製造方法。 1. A substrate step of performing flattening on, then in the method for producing a wafer comprising the step of epitaxially growing process, through a flatness after planarization measuring step, the substrate flatness after the epitaxial growth of prediction step high degree of flatness epitaxial wafer manufacturing method of conducting the epitaxial growth from.
  2. 【請求項2】 加工後基板平坦度の測定工程及び/又はエピタキシャル成長後基板平坦度の予測工程で、所要基準を満たさない基板を再度平坦化加工処理する請求項1に記載の高平坦度エピタキシャルウェーハの製造方法。 Wherein the measurement of the substrate flatness after the processing step and / or epitaxial growth substrate after the flatness of the prediction process, high flatness epitaxial wafer according to claim 1, re-flattening process the substrate that do not meet the required criteria the method of production.
  3. 【請求項3】 エピタキシャル成長後基板平坦度の予測工程は、加工後の基板の平坦度測定による面内分布データに、予め測定したエピタキシャル成長後の基板の平坦度測定による面内分布データを加えて、平坦度の予測を行う請求項1に記載の高平坦度エピタキシャルウェーハの製造方法。 3. A prediction step of epitaxial growth after the substrate flatness, the in-plane distribution data by flatness measurement of the substrate after processing, in addition to in-plane distribution data by flatness measurement of the substrate after the epitaxial growth measured in advance, high flatness epitaxial wafer manufacturing method according to claim 1 for predicting the flatness.
JP2000118953A 2000-04-20 2000-04-20 Method of producing highly flat epitaxial wafer Pending JP2001302395A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8021484B2 (en) 2006-03-30 2011-09-20 Sumco Techxiv Corporation Method of manufacturing epitaxial silicon wafer and apparatus therefor
JP2016505214A (en) * 2012-12-28 2016-02-18 サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited Prediction and control method of the epitaxial after the warp

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8021484B2 (en) 2006-03-30 2011-09-20 Sumco Techxiv Corporation Method of manufacturing epitaxial silicon wafer and apparatus therefor
US8888913B2 (en) 2006-03-30 2014-11-18 Sumco Techxiv Corporation Method of manufacturing epitaxial silicon wafer and apparatus therefor
JP2016505214A (en) * 2012-12-28 2016-02-18 サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited Prediction and control method of the epitaxial after the warp
US9601395B2 (en) 2012-12-28 2017-03-21 Sunedison Semiconductor Limited (Uen201334164H) Methods for post-epitaxial warp prediction and control

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