CN117097306A

CN117097306A - Oscillator, circuit control method and electronic equipment

Info

Publication number: CN117097306A
Application number: CN202310980802.2A
Authority: CN
Inventors: 杨林伟
Original assignee: Tuoer Microelectronics Co ltd
Current assignee: Tuoer Microelectronics Co ltd
Priority date: 2023-08-04
Filing date: 2023-08-04
Publication date: 2023-11-21

Abstract

The application provides an oscillator, a circuit control method and electronic equipment, wherein the oscillator comprises the following components: an odd number of inverters connected in series, a feedback loop comprising an oscillating resistor and an oscillating capacitor, a waveform generating module, a plurality of analog switch circuits, a plurality of control modules and an output circuit; one end of the oscillating resistor is connected with the input of the 1 st phase inverter, the other end of the oscillating resistor is connected with the output of the last phase inverter, the waveform generating module is connected with the output end of the last phase inverter and is used for applying a first electric signal and/or a second electric signal to the output of the last phase inverter, each control module is connected with one analog switch circuit, and each control module applies a control signal to the analog switch circuit connected respectively in a corresponding preset time period to adjust the equivalent resistance of the analog switch circuit connected respectively, so that the frequency of the output waveform of the oscillator is kept within a preset frequency interval. The application can increase the frequency point of the output waveform of the oscillator and reduce electromagnetic interference.

Description

Oscillator, circuit control method and electronic equipment

Technical Field

The present application relates to the field of electronic circuits, and more particularly, to an oscillator, a circuit control method, and an electronic apparatus in the field of electronic circuits.

Background

As shown in fig. 1, fig. 1 shows a schematic circuit configuration of an oscillator in the prior art. The existing frequency jittering technology changes the parameters of an oscillator through a clock technology to realize frequency change, when the frequency jittering of a digital circuit is realized, the frequency spectrum cannot be fully unfolded, as the digital circuit has only 0 and 1 states, the resistance value and the frequency point which can be generated by one-bit binary system have only two states, the existing frequency point is limited by the digital circuit, for example, the 4-bit binary system can only generate 16 frequency points, so that the frequency point of the output waveform of the oscillator is few, the obtained frequency spectrum is narrow, and the electromagnetic interference resistance is poor.

Disclosure of Invention

The application provides an oscillator, a circuit control method and electronic equipment.

In a first aspect, there is provided an oscillator comprising:

m inverters connected in series, wherein M is an odd number greater than or equal to 3;

the feedback loop comprises an oscillating resistor and an oscillating capacitor, wherein a first end of the oscillating resistor is connected with the input end of the 1 st phase inverter, a second end of the oscillating resistor is connected with the output end of the M phase inverter, and the oscillating capacitor is connected with the oscillating resistor in parallel;

The waveform generation module is connected with the output end of the Mth inverter and is used for applying a first electric signal and/or a second electric signal to the output end of the Mth inverter, and the magnitudes of signal parameters of the first electric signal and the second electric signal are different;

the N analog switch circuits are connected in parallel, and each analog switch circuit is connected with the first end of the oscillating resistor, wherein N is greater than or equal to 2;

each control module is connected with one analog switch circuit, and each control module is used for applying control signals to the corresponding analog switch circuit in a corresponding preset time period so as to adjust the equivalent resistance of the corresponding analog switch circuit, so that the frequency of the output waveform of the oscillator is kept within a preset frequency interval, wherein the waveform periods of the control signals output by the N control modules are different;

the input end of the output circuit is connected with the output end of the Mth inverter, the output end of the output circuit is the output end of the oscillator, and the output circuit is used for adjusting the output waveform of the oscillator.

With reference to the first aspect, in some possible implementations, the preset time periods corresponding to the N control modules are the same or different.

With reference to the first aspect and the foregoing implementation manner, in some possible implementation manners, the waveform generating module includes:

a first waveform generation circuit for generating a third electrical signal;

the second waveform generation circuit is provided with a first signal output end and a second signal output end, the second waveform generation circuit is connected with the first waveform generation circuit, and the first signal output end and/or the second signal output end are/is connected with the output end of the Mth inverter;

the second waveform generation circuit is used for generating the first electric signal and the second electric signal according to the third electric signal generated by the first waveform generation circuit, outputting the first electric signal by the first signal output end, and outputting the second electric signal by the second signal output end.

With reference to the first aspect and the foregoing implementation manners, in some possible implementation manners, the first waveform generating circuit includes a first current source, a second current source, a first capacitor, a first PMOS transistor and a first NMOS transistor; the positive electrode of the first current source is connected with a power supply, the negative electrode of the first current source is connected with the source electrode of the first PMOS tube, the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube, the grid electrode of the first NMOS tube is an input end of the first waveform generation circuit, and an input signal of the input end of the first waveform generation circuit is a preset switch control signal; the waveforms of the first electric signal, the second electric signal and the third electric signal are different from those of the preset switch control signal; the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are connected with the first end of the first capacitor, the first end of the first capacitor is connected with the second waveform generation circuit, the source electrode of the first NMOS tube is connected with the positive electrode of the second current source, and the negative electrode of the second current source and the second end of the first capacitor are grounded.

With reference to the first aspect and the foregoing implementation manner, in some possible implementation manners, the second waveform generating circuit includes a first operational amplifier, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first resistor; the positive input end of the first operational amplifier is connected with the first end of the first capacitor, the negative input end of the first operational amplifier is connected with the first end of the first resistor, and the second end of the first resistor is grounded; the source electrode of the second PMOS tube is connected with a power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube is connected with the output end of the first operational amplifier, and the source electrode of the second NMOS tube is connected with the first end of the first resistor; the grid electrode of the second PMOS tube and the drain electrode of the second PMOS tube are connected with the grid electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with a power supply, and the drain electrode of the third PMOS tube is the first signal output end; the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, the source electrode of the fourth PMOS tube is connected with a power supply, the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are all connected with the drain electrode of the fourth PMOS tube, the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are grounded, and the drain electrode of the fourth NMOS tube is the second signal output end.

With reference to the first aspect and the foregoing implementation manner, in some possible implementation manners, the second waveform generating circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a second resistor; the grid electrode and the drain electrode of the fifth NMOS tube are connected with the drain electrode of the fifth PMOS tube, and the source electrode of the fifth NMOS tube is grounded; the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube are connected with the grid electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is the second signal output end; the source electrode of the seventh NMOS tube is grounded, the drain electrode of the seventh NMOS tube is connected with the drain electrode of the sixth PMOS tube, the source electrode of the sixth PMOS tube is connected with a power supply, the grid electrode of the sixth PMOS tube and the drain electrode of the sixth PMOS tube are both connected with the grid electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with the power supply, and the drain electrode of the seventh PMOS tube is the first signal output end.

With reference to the first aspect and the foregoing implementation manners, in some possible implementation manners, the first waveform generating circuit includes a second operational amplifier, a third current source, a reference voltage source, a second capacitor, an eighth PMOS transistor and an eighth NMOS transistor; the positive electrode of the third current source is connected with a power supply, the negative electrode of the third current source is connected with the source electrode of the eighth PMOS tube, and the grid electrode of the eighth PMOS tube and the grid electrode of the eighth NMOS tube are both connected with the output end of the second operational amplifier; the drain electrode of the eighth PMOS tube and the drain electrode of the eighth NMOS tube are both connected with the first end of the second capacitor, the source electrode of the eighth NMOS tube is connected with the positive electrode of the reference voltage source, and the negative electrode of the reference voltage source and the second end of the second capacitor are both grounded; the first end of the second capacitor is connected with the positive input end of the second operational amplifier, the input signal of the reverse input end of the second operational amplifier is a preset reference voltage signal, and the positive input end of the second operational amplifier is connected with the second waveform generation circuit.

With reference to the first aspect and the foregoing implementation manner, in some possible implementation manners, the second waveform generating circuit includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a third resistor; the source electrode of the ninth PMOS tube is connected with a power supply, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube, the grid electrode of the ninth NMOS tube is connected with the positive input end of the second operational amplifier, the source electrode of the ninth NMOS tube is connected with the first end of the third resistor, and the second end of the third resistor is grounded; the grid electrode of the ninth PMOS tube and the drain electrode of the ninth PMOS tube are connected with the grid electrode of the tenth PMOS tube, the source electrode of the tenth PMOS tube is connected with a power supply, and the drain electrode of the tenth PMOS tube is the first signal output end; the grid electrode of the eleventh PMOS tube is connected with the grid electrode of the tenth PMOS tube, the source electrode of the eleventh PMOS tube is connected with a power supply, the drain electrode of the tenth NMOS tube, the grid electrode of the tenth NMOS tube and the grid electrode of the eleventh NMOS tube are all connected with the drain electrode of the eleventh PMOS tube, the source electrode of the tenth NMOS tube and the source electrode of the eleventh NMOS tube are both grounded, and the drain electrode of the eleventh NMOS tube is the second signal output end.

With reference to the first aspect and the foregoing implementation manner, in some possible implementation manners, for each analog switch circuit, the analog switch circuit includes a third capacitor and a MOS transistor; the first end of the third capacitor is connected with the first end of the oscillating resistor, the second end of the third capacitor is connected with the drain electrode of the MOS tube, the grid electrode of the MOS tube is connected with the control module corresponding to the analog switch circuit, and the source electrode of the MOS tube is grounded.

In a second aspect, a circuit control method is provided, which is applied to the above-mentioned oscillator, and the circuit control method includes:

acquiring preset time periods corresponding to N control modules respectively, wherein N is greater than or equal to 2;

controlling each control module to output control signals, wherein the waveform periods of the control signals respectively output by the N control modules are different;

for each control module, in the preset time period corresponding to each control module, applying a control signal output by each control module to an analog switch circuit connected with each control module; the method comprises the steps of,

and controlling the waveform generation module to apply a first electric signal and/or a second electric signal to the output end of the Mth inverter so as to regulate the current output by the output end of the Mth inverter.

With reference to the second aspect, in some possible implementations, the step of obtaining a preset time period corresponding to each of the N control modules includes: acquiring N different numbers; setting a time unit for each number to obtain N set time lengths; and uniformly dividing the N set time durations to N control circuits to obtain preset time periods corresponding to the N control circuits respectively.

In a third aspect, there is provided a circuit control device including:

the period acquisition module is used for acquiring N preset time periods corresponding to the control modules respectively, wherein N is greater than or equal to 2;

the signal generation module is used for controlling each control module to output a control signal, wherein the waveform periods of the control signals respectively output by the N control modules are different;

the first signal applying module is used for applying control signals output by each control module to the analog switch circuit connected with each control module in the preset time period corresponding to each control module;

and the second signal applying module is used for controlling the waveform generating module to apply the first electric signal and/or the second electric signal to the output end of the Mth inverter so as to regulate the current output by the output end of the Mth inverter.

With reference to the third aspect, in some possible implementations, the period acquisition module includes:

the digital acquisition unit is used for acquiring N different numbers;

the time length setting unit is used for setting a time unit for each number to obtain N set time lengths;

and the duration distribution unit is used for uniformly distributing the N set durations to the N control modules to obtain preset time periods corresponding to the N control modules respectively.

In a fourth aspect, an electronic device is provided, comprising an oscillator, a memory and a processor as described above. The memory is for storing executable program code and the processor is for calling and running the executable program code from the memory to cause the electronic device to perform the circuit control method of the second aspect or any one of the possible implementations of the second aspect.

In a sixth aspect, a computer readable storage medium is provided, the computer readable storage medium storing computer program code which, when run on a computer, causes the computer to perform the circuit control method of the second aspect or any one of the possible implementation manners of the second aspect.

The oscillator, the circuit control method and the electronic equipment provided by the embodiment of the application have the following technical effects:

the oscillator provided by the embodiment of the application comprises: an odd number of inverters connected in series, a feedback loop comprising an oscillating resistor and an oscillating capacitor, a waveform generating module, a plurality of analog switch circuits, a plurality of control modules and an output circuit; the first end of the oscillating resistor is connected with the input end of the 1 st phase inverter, the second end of the oscillating resistor is connected with the output end of the last phase inverter, the oscillating capacitor is connected in parallel with the oscillating resistor, the waveform generating module is connected with the output end of the last phase inverter and is used for applying a first electric signal and/or a second electric signal to the output end of the last phase inverter, the first electric signal and the second electric signal are electric signals with different signal parameters, the plurality of analog switch circuits are connected in parallel, each analog switch circuit is connected with the first end of the oscillating resistor, each control module is connected with one analog switch circuit, each control module is used for applying a control signal to each connected analog switch circuit in a corresponding preset time period so as to adjust the equivalent resistance of each connected analog switch circuit, so that the frequency of the output waveform of the oscillator is kept in a preset frequency range, the input end of the output circuit is connected with the output end of the last phase inverter, the output end of the output circuit is the output end of the oscillator, and the output circuit is used for adjusting the waveform of the oscillator. According to the preset time period corresponding to each control module and the time period of the waveform generation module for applying the first electric signal and/or the second electric signal to the output end of the last inverter, the cycle time of the output waveform of the oscillator is calculated, if the calculated cycle time of the output waveform of the oscillator is a larger value, the cycle of a single frequency point can be calculated through the average frequency of all frequencies in the preset frequency interval, so that the cycle of the output waveform of the oscillator and the cycle of the single frequency point can be obtained, a plurality of frequency points can be obtained, the frequency point of the output waveform of the oscillator is increased, the frequency spectrum of the output waveform is widened, and electromagnetic interference can be greatly reduced.

Drawings

Fig. 1 is a schematic diagram showing a circuit configuration of an oscillator in the related art;

FIG. 2 is a diagram showing an exemplary circuit configuration of an oscillator according to an embodiment of the present application;

FIG. 3 illustrates another exemplary circuit configuration of an oscillator provided by an embodiment of the present application;

FIG. 4 shows a schematic circuit connection of a waveform generation module;

FIG. 5 illustrates an exemplary circuit schematic of a waveform generation module;

FIG. 6 illustrates another exemplary circuit schematic of a waveform generation module;

FIG. 7 shows yet another exemplary circuit schematic of a waveform generation module;

FIG. 8 shows an exemplary circuit schematic of an analog switching circuit;

FIG. 9 shows a schematic diagram of control signals of different periods;

FIG. 10 shows a schematic flow chart of a circuit control method provided by an embodiment of the application;

fig. 11 is a schematic structural diagram of a control device according to an embodiment of the present application;

fig. 12 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical scheme of the application will be clearly and thoroughly described below with reference to the accompanying drawings. Wherein, in the description of the embodiments of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B: the text "and/or" is merely an association relation describing the associated object, and indicates that three relations may exist, for example, a and/or B may indicate: the three cases where a exists alone, a and B exist together, and B exists alone, and furthermore, in the description of the embodiments of the present application, "plural" means two or more than two.

The terms "first," "second," and the like, are used below for descriptive purposes only and are not to be construed as implying or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.

The following is an embodiment of an oscillator provided in the embodiments of the present application.

As shown in fig. 2, fig. 2 shows an exemplary circuit configuration diagram of an oscillator according to an embodiment of the present application, where the oscillator includes M series-connected inverters, a feedback loop, a waveform generation module A, N analog switch circuits, N control modules and an output circuit E, M is an odd number greater than or equal to 3, and N is greater than or equal to 2. Wherein:

the feedback loop comprises an oscillating resistor R and an oscillating capacitor C0-1, wherein the first end of the oscillating resistor R is connected with the input end of the 1 st phase inverter F1, the second end of the oscillating resistor R is connected with the output end of the M phase inverter FM, the oscillating capacitor C0-1 is connected with the oscillating resistor R in parallel, the first end of the oscillating capacitor C0-1 is connected with the first end of the oscillating resistor R, and the second end of the oscillating capacitor C0-1 is grounded. For example, when m=3, the 3 rd inverter is F3, and then the first end of the oscillating resistor R is connected to the input terminal of the 1 st inverter F1, and the second end of the oscillating resistor R is connected to the output terminal of the 3 rd inverter F3.

The waveform generation module a is connected to the output end of the mth inverter FM, and is configured to apply a first electrical signal I3 and/or a second electrical signal I4 to the output end of the mth inverter FM, where the magnitudes of the signal parameters of the first electrical signal I3 and the second electrical signal I4 are different, for example, the first electrical signal I3 and the second electrical signal I4 are currents, the signal parameters of the first electrical signal I3 and the second electrical signal I4 are current values, the current value of the first electrical signal I3 is different from the current value of the second electrical signal I4, and the first electrical signal I3 and the second electrical signal I4 are used to adjust the current output by the output end of the mth inverter, that is, adjust the current output by the output end of the last inverter. The time periods of the first electrical signal I3 and the second electrical signal I4 applied by the waveform generating module a to the output end of the mth inverter are preset, may be the same or different, and the time periods of the first electrical signal I3 and the second electrical signal I4 applied by the waveform generating module a to the output end of the mth inverter may be understood as the signal durations of the first electrical signal I3 and the second electrical signal I4 applied to the output end of the mth inverter, and the time of charging and discharging of the capacitor in the oscillator is controlled by the first electrical signal I3 and the second electrical signal I4.

N analog switch circuits are connected in parallel, and each analog switch circuit is connected with a first end of the oscillating resistor R. The N analog switch circuits are respectively in parallel connection with each other, and the X1, the X2, the X3, the X1, the X2, the X N are connected with the first end of the oscillating resistor R.

The N control modules are Y1, Y2, Y3, YN respectively, each control module is connected with an analog switch circuit, for example, Y1 is connected with X1, Y2 is connected with X2, Y3 is connected with X3, and so on, and YN is connected with XN.

Each control module is configured to apply a control signal to the analog switch circuit connected to each control module in a corresponding preset time period, so as to adjust an equivalent resistance of the analog switch circuit connected to each control module, so that a frequency of an output waveform of the oscillator is kept within a preset frequency interval, where waveforms of the control signals output by each of the N control modules are the same, for example, all square waves, but periods of the waveforms of the control signals output by each of the N control modules are different, for example, although waveforms of the control signals output by each of the N control modules are all square waves, but periods of the square waves of the control signals output by each of the control modules are different. Each control module is used for applying control signals to the analog switch circuits connected with the control modules in a corresponding preset time period, and then the analog switch circuits connected with the control modules are in a conducting state.

For example, Y1 applies a control signal S0 to X1 during a corresponding preset time period to adjust the equivalent resistance of X1; y2 applies a control signal S1 to X2 in a corresponding preset time period to adjust the equivalent resistance of X2; and so on, YN applies a control signal S (N-1) to XN in a corresponding preset time period to adjust the equivalent resistance of XN. Wherein S0,..and S (N-1) are all square waves, but the waveform periods are different.

The preset time periods corresponding to Y1, Y2, Y3, and YN may be the same or different, and in the same case, the preset time periods corresponding to the N control modules are the same, the control signals are simultaneously applied to the analog switch circuits connected to each other by Y1, Y2, Y3, and YN, and the duration of each control module applying the control signals to the analog switch circuits connected to each other is the same, but the preset time periods need to be sufficiently large. Under the condition of different conditions, the preset time periods corresponding to the N control modules are different, and control signals are simultaneously applied to the analog switch circuits connected with the N control modules by Y1, Y2, Y3 and YN, wherein the difference is that the duration of each control module for applying the control signals to the analog switch circuits connected with the N control modules is different, if the preset time period corresponding to Y1 is 20us, and the duration of each control module for applying the control signals to X1 is 20us; the preset time period corresponding to Y2 is 40us, and the duration of the control signal applied to X2 by Y2 is 40us; the preset time period corresponding to Y3 is 80us, and the duration of the control signal applied to X3 by Y3 is 80us; y4 corresponds to a preset time period of 160us and the duration of the control signal applied to X4 by Y4 is 160us.

Further, in the case of different situations, the preset time periods corresponding to the N control modules are different, and the same common divisor does not exist between the preset time periods corresponding to the N control modules, specifically, the preset time periods corresponding to the N control modules are different prime numbers, that is, the preset time periods corresponding to the Y1, Y2, Y3, Y2, and YN are not the same common divisor, specifically, the preset time periods corresponding to the Y1, Y2, Y3, Y2, and YN are different prime numbers, and the analog switch circuits connected to the respective control modules simultaneously apply the control signals, which is different in that the duration of each control module applying the control signals to the analog switch circuits connected to the respective control modules is different, for example, the preset time period corresponding to the Y1 is 7us, the duration of the control signal applied to the X1 is 7us, the preset time period corresponding to the Y2 is 13us, and the duration of the control signal applied to the X2 is 13us.

After the control signals are applied to the analog switch circuits connected respectively in the preset time periods corresponding to the Y1, Y2, Y3 and YN, the equivalent resistances of the analog switch circuits connected respectively by the Y1, Y2, Y3 and YN are adjusted, so that the equivalent resistances of the oscillator are adjusted, and the frequency of the output waveform of the oscillator is kept in the preset frequency interval.

The input end of the output circuit E is connected with the output end of the Mth inverter, the output end of the output circuit E is the output end of the oscillator, and the output circuit E is used for adjusting the output waveform of the oscillator, in particular adjusting the phase of the output waveform so as to improve the output waveform.

Wherein, Y1, Y2, Y3, &, YN apply the control signal to the analog switch circuit that connects respectively in the corresponding preset time period of each, and after waveform generation module A applied the first electric signal I3 of appointed time period and/or the second electric signal I4 of appointed time period to the output of the Mth phase inverter, the frequency point of the output waveform that output circuit E output is many, has widened the frequency spectrum of the waveform that the oscillator outputs in a cycle time. Wherein, if the waveform generating module a applies the first electric signal I3 with a specified time period to the output terminal of the mth inverter, the first electric signal I3 increases the current output by the output terminal of the mth inverter, and if the waveform generating module a applies the second electric signal I4 with a specified time period to the output terminal of the mth inverter, the second electric signal I4 decreases the current output by the output terminal of the mth inverter, thereby realizing the adjustment of the current output by the output terminal of the mth inverter, and the charge-discharge current of the oscillating capacitor C0-1 and the capacitor in each analog switch circuit is the current output by the output terminal of the mth inverter.

If the preset time periods of the control signals applied by all the control modules to the respectively connected analog switch circuits are the same, the preset time periods are large enough, and the designated time periods of the first electric signal I3 and the second electric signal I4 applied by the waveform generation module A to the output end of the Mth inverter are the same, and the preset time periods corresponding to the control modules are the same, one period time of the output waveform of the oscillator can be calculated according to the preset time periods corresponding to all the control modules, the designated time periods corresponding to the first electric signal I3 and the second electric signal I4, and the period time calculation process is as follows:

assuming that the preset time periods corresponding to Y1, Y2, Y3, and YN are t, and the specified time periods corresponding to the first electrical signal I3 and the second electrical signal I4 are t, one cycle time of the oscillator output waveform is: t, i.e., t is the least common multiple of the preset time period corresponding to each of Y1, Y2, Y3, and YN and the specified time period corresponding to the first electrical signal I3 and the second electrical signal I4.

Since Y1, Y2, Y3, and YN apply control signals to the analog switch circuits connected to each other in the respective preset time periods, and after the waveform generation module a applies the first electrical signal I3 of the specified time period and/or the second electrical signal I4 of the specified time period to the output terminal of the mth inverter, the frequency of the output waveform of the oscillator remains in the preset frequency interval, and the average frequency of all frequencies in the preset frequency interval can be obtained, assuming that the average frequency=p, then the period corresponding to the average frequency is 1/P, and the period corresponding to the average frequency represents one frequency point, that is, the period of a single frequency point, then the number of frequency points of the output waveform of the oscillator is: t/(1/P), if t is large enough, the frequency point of the output waveform of the oscillator is large, i.e. the frequency point of the output waveform of the oscillator is increased, the frequency spectrum of the output waveform is widened, and electromagnetic interference (ElectroMagnetic Interference, EMI) can be greatly reduced.

If all control modules apply control signals to the analog switch circuits which are connected respectively for different preset time periods and the specified time periods corresponding to the first electric signal I3 and the second electric signal I4, one period time of the output waveform of the oscillator is the least common multiple of all preset time periods and the specified time periods corresponding to the first electric signal I3 and the second electric signal I4, and the period time is calculated as follows:

assuming that preset time periods corresponding to Y1, Y2, Y3, and YN are t1, t2, t3, and tN, respectively, the specified time period corresponding to the first electrical signal I3 is Z3, the specified time period corresponding to the second electrical signal I4 is Z4, and t1, t2, t3, and tN, Z3, and Z4 are different, if tN is the least common multiple of t1, t2, t3, and tN, Z3, and Z4, one period time of the oscillator output waveform is: tN.

Since Y1, Y2, Y3, and YN apply control signals to the analog switch circuits connected to each other in the respective preset time periods, and after the waveform generation module a applies the first electrical signal I3 of the specified time period and the second electrical signal I4 of the specified time period to the output terminal of the mth inverter, the frequency of the output waveform of the oscillator remains in the preset frequency interval, and the average frequency of all frequencies in the preset frequency interval can be obtained, assuming that the average frequency=p, then the period corresponding to the average frequency is 1/P, the period corresponding to the average frequency represents one frequency point, that is, the period of a single frequency point, and then the number of frequency points of the output waveform of the oscillator is: tN/(1/P). If tN is large, the frequency points of the output waveform of the oscillator are large, namely, the frequency points of the output waveform of the oscillator are increased, the frequency spectrum of the output waveform is widened, and electromagnetic interference can be greatly reduced.

If the preset time periods of the control signals applied by all the control modules to the respectively connected analog switch circuits and the designated time periods of the first electric signal I3 and the second electric signal I4 applied by the waveform generation module A to the output end of the Mth inverter are different, and the preset time periods corresponding to all the control modules and the designated time periods corresponding to the first electric signal I3 and the second electric signal I4 are different prime numbers, the same common divisor does not exist, so that one cycle time of the output waveform of the oscillator can be calculated according to the product of the preset time periods corresponding to all the control modules and the designated time periods corresponding to the first electric signal I3 and the second electric signal I4, and the cycle time calculation process is as follows:

assuming that the preset time periods corresponding to Y1, Y2, Y3, and YN are t1, t2, t3, and tN, respectively, the specified time period corresponding to the first electrical signal I3 is Z3, the specified time period corresponding to the second electrical signal I4 is Z4, and the same common divisor does not exist between t1, t2, t3, and tN, Z3, and Z4, for example, t1, t2, t3, and tN, Z3, and Z4 are prime numbers, one cycle time of the oscillator output waveform is: t1×t2×t3×.×tnxz3×z4.

Since Y1, Y2, Y3, and YN apply control signals to the analog switch circuits connected to each other in the respective preset time periods, and after the waveform generation module a applies the first electrical signal I3 of the specified time period and the second electrical signal I4 of the specified time period to the output terminal of the mth inverter, the frequency of the output waveform of the oscillator remains in the preset frequency interval, and the average frequency of all frequencies in the preset frequency interval can be obtained, assuming that the average frequency=p, then the period corresponding to the average frequency is 1/P, the period corresponding to the average frequency represents one frequency point, that is, the period of a single frequency point, and then the number of frequency points of the output waveform of the oscillator is: (t1×t2×t3×.×tn×z3×z4)/(1/P). Therefore, the frequency points of the output waveform of the oscillator are many, namely, the frequency points of the output waveform of the oscillator are increased, the frequency spectrum of the output waveform is widened, and electromagnetic interference can be greatly reduced.

As shown in fig. 3, fig. 3 shows another exemplary circuit configuration of an oscillator according to an embodiment of the present application, where the oscillator includes 3 inverters connected in series, a feedback loop, a waveform generation module a, 4 analog switch circuits, 4 control modules, and an output circuit E. Wherein:

The 3 inverters connected in series are F1, F2 and F3 in sequence, namely the output end of F1 is connected with the input end of F2, the output end of F2 is connected with the input end of F3, and the output end of F3 is connected with the output circuit E; the feedback loop comprises an oscillating resistor R and an oscillating capacitor C0-1, wherein the first end of the oscillating resistor R is connected with the input end of the 1 st phase inverter F1, the second end of the oscillating resistor R is connected with the output end of the F3, the oscillating capacitor C0-1 is connected with the oscillating resistor R in parallel, namely the first end of the oscillating capacitor C0-1 is connected with the first end of the oscillating resistor R, and the other end of the first end of the oscillating capacitor C0-1 is connected with GND. The 1 st inverter F1 is a schmitt inverter.

4 analog switch circuits are connected in parallel, and each analog switch circuit is connected with a first end of the oscillating resistor R. The 4 analog switch circuits are respectively X1, X2, X3 and X4, the X1, X2, X3 and X4 are mutually connected in parallel, and the X1, the X2, the first end of the oscillating resistor R is connected with the X4.

The 4 control modules are Y1, Y2, Y3 and Y4 respectively, each control module is connected with an analog switch circuit, for example, Y1 is connected with X1, Y2 is connected with X2, Y3 is connected with X3, and Y4 is connected with X4.

The output circuit E comprises an inverter F0, the input end of the inverter F0 is connected with the output end of the F3, the input end of the inverter F0 is the input end of the output circuit E, the input end of the inverter F0 is connected with the output end of the 3 rd inverter F3, and the output end of the inverter F0 is the output end of the output circuit E, namely the output end of the oscillator.

In one possible implementation, as shown in fig. 4, fig. 4 shows a schematic circuit connection diagram of the waveform generation module. The waveform generation module A comprises a first waveform generation circuit A1 and a second waveform generation circuit A2; the first waveform generating circuit A1 is configured to generate a third electrical signal I0, the second waveform generating circuit A2 has a first signal output end a21in and a second signal output end a22in, the second waveform generating circuit A2 is connected to the first waveform generating circuit A1, the first signal output end a21in is connected to an output end of an mth inverter, the second signal output end a22in is connected to an output end of the mth inverter, and if m=3, the first signal output end a21in and the second signal output end a22in are both connected to an output end of the 3 rd inverter.

The second waveform generation circuit A2 is configured to generate a first electrical signal I3 and a second electrical signal I4 according to the third electrical signal I0 generated by the first waveform generation circuit A1, output the first electrical signal I3 through the first signal output terminal a21in, output the second electrical signal I4 through the second signal output terminal a22in, that is, input the third electrical signal I0 generated by the first waveform generation circuit A1 into the second waveform generation circuit A2, and output the first electrical signal I3 and the second electrical signal I4 through the second waveform generation circuit A2. The waveforms of the first electrical signal I3, the second electrical signal I4, and the third electrical signal I0 are the same, for example, the waveforms of the first electrical signal I3, the second electrical signal I4, and the third electrical signal I0 are triangular waves.

In one possible implementation, as shown in fig. 5, fig. 5 shows an exemplary circuit schematic of the waveform generation module. The first waveform generation circuit A1 comprises a first current source L1, a second current source L2, a first capacitor C0-2, a first PMOS tube and a first NMOS tube, wherein the first PMOS tube is denoted as PMOS1, and the first NMOS tube is denoted as NMOS1;

the positive electrode of the first current source L1 is connected to a power supply, the negative electrode of the first current source L1 is connected to a source electrode of a first PMOS tube, a gate electrode of the first PMOS tube is connected to a gate electrode of a first NMOS tube, the gate electrode of the first NMOS tube is an input end of the first waveform generation circuit A1, an input signal of the input end of the first waveform generation circuit A1 is a preset switch control signal Y, that is, the input end of the first waveform generation circuit A1 is connected to an external device (e.g., a controller) capable of generating the preset switch control signal Y, and waveforms of the first electrical signal I3, the second electrical signal I4, and the third electrical signal I0 are different from those of the preset switch control signal Y, for example, the waveform of the preset switch control signal Y is a square wave.

The drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are both connected with the first end of the first capacitor C0-2, the first end of the first capacitor C0-2 is connected with the second waveform generation circuit A2, the source electrode of the first NMOS tube is connected with the positive electrode of the second current source L2, and the negative electrode of the second current source L2 and the second end of the first capacitor C0-2 are both grounded. The current output by the first current source L1 and the second current source L2 are fixed and smaller than the corresponding preset value, which means that the current output by the first current source L1 and the second current source L2 are smaller, so that the charging time and the discharging time of the first capacitor C0-2 are longer, and the period of the triangular wave generated by the first waveform generating circuit A1 is longer.

In a possible implementation manner, as shown in fig. 5, the second waveform generating circuit A2 includes a first operational amplifier W1, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first resistor R1, where the second PMOS transistor is denoted as PMOS2, the third PMOS transistor is denoted as PMOS3, the fourth PMOS transistor is denoted as PMOS4, the second NMOS transistor is denoted as NMOS2, the third NMOS transistor is denoted as NMOS3, and the fourth NMOS transistor is denoted as NMOS4. Wherein:

the positive input end of the first operational amplifier W1 is connected with the first end of the first capacitor C0-2, the reverse input end of the first operational amplifier W1 is connected with the first end of the first resistor R1, and the second end of the first resistor R1 is grounded. The source electrode of the second PMOS tube is connected with a power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube is connected with the output end of the first operational amplifier W1, and the source electrode of the second NMOS tube is connected with the first end of the first resistor R1. The grid electrode of the second PMOS tube and the drain electrode of the second PMOS tube are both connected with the grid electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with a power supply, and the drain electrode of the third PMOS tube is a first signal output end A21in. The grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, the source electrode of the fourth PMOS tube is connected with a power supply, the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are all connected with the drain electrode of the fourth PMOS tube, the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are both grounded, and the drain electrode of the fourth NMOS tube is the second signal output end A22in.

In one possible implementation, as shown in fig. 6, fig. 6 shows another exemplary circuit schematic of the waveform generation module, where the first waveform generation circuit A1 in fig. 6 has the same circuit structure as the first waveform generation circuit A1 in fig. 5. The second waveform generation circuit A2 includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a second resistor R2, where the fifth PMOS transistor is denoted as PMOS5, the sixth PMOS transistor is denoted as PMOS6, the seventh PMOS transistor is denoted as PMOS7, the fifth NMOS transistor is denoted as NMOS5, the sixth NMOS transistor is denoted as NMOS6, and the seventh NMOS transistor is denoted as NMOS7. Wherein:

the grid electrode of the fifth PMOS tube is connected with the first end of the first capacitor C0-2, the source electrode of the fifth PMOS tube is connected with the first end of the second resistor R2, the second end of the second resistor R2 is connected with a power supply, the grid electrode and the drain electrode of the fifth NMOS tube are connected with the drain electrode of the fifth PMOS tube, and the source electrode of the fifth NMOS tube is grounded. The grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube are connected with the grid electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is a second signal output end A22in. The source electrode of the seventh NMOS tube is grounded, the drain electrode of the seventh NMOS tube is connected with the drain electrode of the sixth PMOS tube, the source electrode of the sixth PMOS tube is connected with a power supply, the grid electrode of the sixth PMOS tube and the drain electrode of the sixth PMOS tube are both connected with the grid electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with the power supply, and the drain electrode of the seventh PMOS tube is a first signal output end A21in.

In one possible implementation, as shown in fig. 7, fig. 7 shows a further exemplary circuit schematic of the waveform generation module. The first waveform generation circuit A1 comprises a second operational amplifier W2, a third current source L3, a reference voltage source U, a second capacitor C0-3, an eighth PMOS tube and an eighth NMOS tube, wherein the eighth PMOS tube is represented as PMOS8, and the eighth NMOS tube is represented as NMOS8. Wherein:

the positive pole of the third current source L3 is connected with a power supply, the negative pole of the third current source L3 is connected with the source electrode of the eighth PMOS tube, and the grid electrode of the eighth PMOS tube and the grid electrode of the eighth NMOS tube are connected with the output end of the second operational amplifier W2. The drain electrode of the eighth PMOS tube and the drain electrode of the eighth NMOS tube are both connected with the first end of the second capacitor C0-3, the source electrode of the eighth NMOS tube is connected with the positive electrode of the reference voltage source U, and the negative electrode of the reference voltage source U and the second end of the second capacitor C0-3 are both grounded. The first end of the second capacitor C0-3 is connected with the positive input end of the second operational amplifier W2, the input signal of the negative input end of the second operational amplifier W2 is a preset reference voltage signal, and the positive input end of the second operational amplifier W2 is connected with the second waveform generation circuit A2. The preset reference voltage signal is output by an external reference voltage circuit.

In a possible implementation manner, as shown in fig. 7, the second waveform generating circuit A2 includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a third resistor R3, where the ninth PMOS transistor is denoted as PMOS9, the tenth PMOS transistor is denoted as PMOS10, the eleventh PMOS transistor is denoted as PMOS11, the ninth NMOS transistor is denoted as NMOS9, the tenth NMOS transistor is denoted as NMOS10, and the eleventh NMOS transistor is denoted as NMOS11. Wherein:

the source electrode of the ninth PMOS tube is connected with a power supply, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube, the grid electrode of the ninth NMOS tube is connected with the positive input end of the second operational amplifier W2, the source electrode of the ninth NMOS tube is connected with the first end of the third resistor R3, and the second end of the third resistor R3 is grounded. The grid electrode of the ninth PMOS tube and the drain electrode of the ninth PMOS tube are connected with the grid electrode of the tenth PMOS tube, the source electrode of the tenth PMOS tube is connected with a power supply, and the drain electrode of the tenth PMOS tube is a first signal output end A21in. The grid electrode of the eleventh PMOS tube is connected with the grid electrode of the tenth PMOS tube, the source electrode of the eleventh PMOS tube is connected with a power supply, the drain electrode of the tenth NMOS tube, the grid electrode of the tenth NMOS tube and the grid electrode of the eleventh NMOS tube are all connected with the drain electrode of the eleventh PMOS tube, the source electrode of the tenth NMOS tube and the source electrode of the eleventh NMOS tube are both grounded, and the drain electrode of the eleventh NMOS tube is a second signal output end A22in.

In one possible implementation, as shown in fig. 8, fig. 8 shows an exemplary circuit schematic of an analog switching circuit. For each analog switch circuit, the analog switch circuit comprises a third capacitor C0-4 and an MOS tube T, wherein the first end of the third capacitor C0-4 is connected with the first end of an oscillating resistor R, the second end of the third capacitor C0-4 is connected with the drain electrode of the MOS tube T, the grid electrode of the MOS tube T is connected with a control module corresponding to the analog switch circuit, and the source electrode of the MOS tube T is grounded. The capacitance values of the third capacitors C0-4 in any two analog switch circuits have a multiple relationship, and the capacitance values of the third capacitors C0-4 in any two analog switch circuits are set to have the multiple relationship, so that the same frequency point in the output waveform of the oscillator can be avoided.

In a possible implementation manner, for each analog switch circuit, the analog switch circuit includes a third capacitor C0-4 and a digital switch, that is, the MOS transistor T may be replaced by a digital switch, that is, the digital switch is an electronically controlled single-pole-throw switch, a first end of the third capacitor C0-4 is connected to a first end of the oscillating resistor R, a second end of the third capacitor C0-4 is connected to a first end of the digital switch, and a second end of the digital switch is grounded. When the analog switch circuit comprises a digital switch, the digital switch is closed after a control signal is applied to the analog switch circuit.

The three different waveform generation modules a shown in fig. 5, 6 and 7 can be understood as three reference circuits for generating a triangular wave current source, that is, the waveforms of the generated first electrical signal I3 and the generated second electrical signal I4 are all triangular waves, and the first electrical signal I3 and the generated second electrical signal I4 are variable current sources generated by the waveform generation module a for use by an oscillator. According to actual requirements, waveforms of the first electrical signal I3 and the second electrical signal I4 may be any periodically-changed waveforms, or any non-periodically-changed waveforms, and current magnitudes of the first electrical signal I3 and the second electrical signal I4 are always continuously changed, and current magnitudes of the first electrical signal I3 and the second electrical signal I4 are different. The rising period and the falling period in the waveform periods of the first electric signal I3 and the second electric signal I4 in fig. 5 and fig. 6 are much larger than the period of the output waveform of the oscillator, and at this time, the on and off times of the MOS transistors in the nth analog switch circuit may be set to be different, which corresponds to the on and off times of the switches, for example, the on and off times of S3 in fig. 3 may be set to be different, so that the rising rate and the falling rate of the waveform of the charge and discharge current in the oscillator are also different. When all the analog switch circuits are in a conducting state, that is, the corresponding control signals are applied to the analog switch circuits by the control modules corresponding to the analog switch circuits, and the designated time period of the first electric signal I3 and the second electric signal I4 applied to the output end of the Mth inverter by the waveform generation module A, the charge and discharge time of the capacitor in each analog switch circuit is continuously changed, so that the frequency point of the output waveform of the oscillator is increased.

As shown in fig. 2 to 9, a first signal output end a21in and a second signal output end a22in of the second waveform generation circuit A2 are commonly connected between a connection point between a second end of the oscillating resistor R and the output circuit E and an output end of the mth inverter, and the working principle of the oscillator provided by the embodiment of the present application is as follows:

a device capable of generating a preset switch control signal Y connected to an input terminal of the first waveform generation circuit A1, the preset switch control signal Y having a square wave is input to the first waveform generation circuit A1, the first waveform generation circuit A1 generates a third electric signal I0 having a triangular wave according to the preset switch control signal Y, the first waveform generation circuit A1 inputs the third electric signal I0 to the second waveform generation circuit A2, the second waveform generation circuit A2 generates a first electric signal I3 and a first electric signal I4 having a triangular wave according to the third electric signal I0, the second waveform generation circuit A2 applies the first electric signal I3 and/or the second electric signal I4 to an output terminal of the 3 rd inverter F3, for example, at the same point in time, the second waveform generation circuit A2 applies the first electric signal I3 having a specified time period Z3 and the second electric signal I4 having a specified time period Z4 to an output terminal of the 3 rd inverter F3 to adjust a current output terminal of the 3 rd inverter F3; and under the same time point, each control module applies a control signal to the analog switch circuit connected with each control module in a corresponding preset time period, as shown in fig. 9, fig. 9 shows a schematic diagram of the control signals in different periods, the control module corresponding to X1 applies a control signal S0 to the gate of the MOS transistor in X1 in a preset time period t1, the control module corresponding to X2 applies a control signal S1 to the gate of the MOS transistor in X2 in a preset time period t2, the control module corresponding to X3 applies a control signal S2 to the gate of the MOS transistor in X3 in a preset time period t3, and the control module corresponding to X4 applies a control signal S3 to the gate of the MOS transistor in X4 in a preset time period t4, so that the equivalent resistance of each analog switch circuit is adjusted, and the frequency of the output waveform of the oscillator is kept in a preset frequency interval. Wherein the control signals S0-S3 are all square wave signals, but the waveform periods of the control signals S0-S3 are different.

Applying the first electric signal I3 of the specified time period Z3 and the second electric signal I4 of the specified time period Z4 to the output end of the 3 rd inverter F3, and under the condition that the control module corresponding to X1 applies the control signal S0 to the gate of the MOS transistor in X1 in the preset time period t1, the control module corresponding to X2 applies the control signal S1 to the gate of the MOS transistor in X2 in the preset time period t2, the control module corresponding to X3 applies the control signal S2 to the gate of the MOS transistor in X3 in the preset time period t3, and the control module corresponding to X4 applies the control signal S3 to the gate of the MOS transistor in X4 in the preset time period t4, the following is the case: assuming that t1 to t4 and Z3, Z4 are the same, if t1 to t4 and Z3, Z4 are sufficiently large, for example, t1 to t4 and Z3, Z4 are 10000us, if the preset frequency interval is [1M,2M ], the average frequency of all the frequencies in the preset frequency interval is 1.5M, the period corresponding to the average frequency is about 0.666us, and the period corresponding to the average frequency represents one frequency point, the number of frequency points of the output waveform of the oscillator is: 10000us/0.666us is approximately 15015, namely the output waveform of the oscillator has about 15015 frequency points, so that the frequency points of the output waveform of the oscillator are increased, the frequency spectrum of the output waveform is widened, and electromagnetic interference can be greatly reduced.

Another case is: assuming that t1 to t4 and Z3, Z4 are all different, for example, t1=20us, t2=40us, t3=80us, t4=160 us, z3=320 us, z4=640 us, from the application of the control signal to X1 to X4, and the application of the first electric signal I3 and the second electric signal I4 to the output terminal of the 3 rd inverter F3 for one period is 640us, which is also one period time of the oscillator output waveform, if the preset frequency interval is [1M,2M ], the average frequency of all frequencies in the preset frequency interval is 1.5M, the period corresponding to the average frequency is about 0.666us, the period corresponding to the average frequency represents one frequency point, the number of frequency points of the output waveform of the oscillator is: 640us/0.666us is approximately 960 frequency points of the output waveform of the oscillator, so that the frequency points of the output waveform of the oscillator are increased, the frequency spectrum of the output waveform is widened, and electromagnetic interference can be greatly reduced.

Still another case is: assuming that t1 to t4 and Z3, Z4 are all different, there is no common divisor between t1 to t4 and Z3, Z4, specifically that t1 to t4 and Z3, Z4 are all different prime numbers, for example, t1=7us, t2=13us, t3=29 us, t4=53 us, z3=23 us, Z4=31 us, then one cycle time of the oscillator output waveform is: 7×13×29×53×23×31= 56366401us. If the preset frequency interval is [1M,2M ], the average frequency of all the frequencies in the preset frequency interval is 1.5M, the period corresponding to the average frequency is about 0.666us, and the period corresponding to the average frequency represents one frequency point, the number of frequency points of the output waveform of the oscillator is as follows: 56366401us/0.666us approximately equal to 84634235, namely the output waveform of the oscillator has about 84634235 frequency points, so that the frequency points of the output waveform of the oscillator are increased, the frequency spectrum of the output waveform is widened, and electromagnetic interference can be greatly reduced.

For example, when the oscillator is applied to a charge pump, since the frequency spectrum of the output waveform of the oscillator is wide, after the frequency spectrum is spread, the energy generated by the charge pump is dispersed along with the frequency spread, so that the electromagnetic interference is reduced, that is, the more frequency points are, the smaller the electromagnetic interference is.

The following is an embodiment of a circuit control method provided in the embodiments of the present application.

Fig. 10 shows a schematic flow chart of a circuit control method according to an embodiment of the present application. As shown in fig. 10, an embodiment of the present application provides a circuit control method applied to the above-mentioned oscillator, where the circuit control method includes the following schemes:

s110: and acquiring the preset time periods corresponding to the N control modules respectively, wherein N is greater than or equal to 2.

In an exemplary embodiment, a preset time period corresponding to each of the N control modules is obtained. As shown in fig. 3, the N control modules are 4, and Y1, Y2, Y3, and Y4 respectively, obtain preset time periods corresponding to Y1, Y2, Y3, and Y4 respectively, and obtain specified time periods of the first electric signal I3 and the second electric signal I4 applied by the waveform generation module a to the output terminal of the 3 rd inverter F3. For example, the preset time period of Y1 corresponds to t1, the preset time period of Y2 corresponds to t2, the preset time period of Y3 corresponds to t3, the preset time period of Y3 corresponds to t4, the designated time period of the first electric signal I3 applied to the output terminal of the 3 rd inverter F3 is Z3, the designated time period of the second electric signal I4 applied to the output terminal of the 3 rd inverter F3 is Z4, t1 to t4 and Z3 and Z4 are the same, but t1 to t4 and Z3 and Z4 need to be sufficiently large, or t1 to t4 and Z3 and Z4 are not the same, and the same common divisor does not exist between t1 to t4 and Z3 and Z4.

In a possible implementation manner, S110 includes the following schemes:

acquiring N different numbers;

setting a time unit for each number to obtain N set time lengths;

and uniformly dividing the N set time durations to N control modules to obtain the preset time periods corresponding to the N control modules respectively.

For example, if the number of N control modules is 4, and Y1, Y2, Y3, and Y4 are respectively, 4 different numbers are obtained, and then a time unit, for example, a time unit of us, is set for each number, so as to obtain 4 set durations. And then, equally distributing the 4 set time periods to the 4 control modules to obtain the preset time periods corresponding to the 4 control modules respectively. For example, the 4 set durations are t1, t2, t3 and t4, t1 is assigned to Y1, t2 is assigned to Y2, t3 is assigned to Y3, and t4 is assigned to Y4, so as to obtain preset time periods corresponding to each of Y1, Y2, Y3 and Y4, that is, t1, t2, t3 and t4, for example, t1=20us, t2=40us, t3=80us, t4=160us, respectively. The designated time period of the first electrical signal and the second electrical signal applied by the waveform generating module to the output end of the mth inverter FM is the same as the above-mentioned obtaining manner of each preset time period, and will not be described herein again.

In a possible implementation manner, S110 includes the following schemes:

acquiring N different numbers; wherein the N different numbers do not have the same common divisor;

setting a time unit for each number to obtain N set time lengths;

For example, if the number of N control modules is 4, and Y1, Y2, Y3, and Y4 are respectively, 4 different numbers are obtained, the same common divisor does not exist between the 4 different numbers, for example, the 4 different numbers are prime numbers, and then a time unit, for example, a time unit is us, is set for each number, so as to obtain 4 set durations. And then, equally distributing the 4 set time periods to the 4 control modules to obtain the preset time periods corresponding to the 4 control modules respectively. For example, the 4 set durations are t1, t2, t3 and t4, t1 is assigned to Y1, t2 is assigned to Y2, t3 is assigned to Y3, and t4 is assigned to Y4, so as to obtain preset time periods corresponding to Y1, Y2, Y3 and Y4, that is, t1, t2, t3 and t4, respectively. The designated time period of the first electrical signal and the second electrical signal applied by the waveform generating module to the output end of the mth inverter FM is the same as the above-mentioned obtaining manner of each preset time period, and will not be described herein again.

In a possible implementation manner, S110 includes the following schemes:

acquiring an arrival target number greater than a preset number in the integer;

setting a time unit for each target number to obtain a set duration;

setting the set time length for the N control modules to obtain the preset time periods corresponding to the N control modules respectively.

For example, the N control modules are 4, and Y1, Y2, Y3, and Y4, respectively, and the target number is obtained by obtaining an integer greater than a preset number, for example, 1000, and the target number is obtained by obtaining an integer greater than 1000, for example, 10000, so that a preset time period corresponding to the sufficiently large control module can be set. After the target numbers are obtained, a time unit is set for each target number, for example, the time unit is us, and the obtained set duration is 10000us. And setting a set time length for the 4 control modules to obtain preset time periods corresponding to the 4 control modules respectively, namely 10000us for the preset time periods corresponding to the 4 control modules respectively. The designated time period of the first electrical signal and the second electrical signal applied by the waveform generating module to the output end of the mth inverter FM is the same as the above-mentioned obtaining manner of each preset time period, and will not be described herein again.

S120: and controlling each control module to output control signals, wherein the waveform periods of the control signals respectively output by the N control modules are different.

Under the same time point, each control module is adopted to output a control signal, and the waveform periods of the control signals respectively output by the N control modules are different, namely, the 1 st control module is adopted to output a control signal 1, the 2 nd control module is adopted to output a control signal 2, & gt, the N th control module is adopted to output a control signal N, the control signal 1, the control signal 2 and the waveform periods of the control signal N are different. For example, n=4, and the 4 circuits are Y1, Y2, Y3, and Y4, respectively, and as shown in fig. 9, the control signal output by Y1 is S0, the control signal output by Y2 is S1, the control signal output by Y3 is S2, and the control signal output by Y4 is S3.

S130: and aiming at each control module, applying a control signal output by each control module to an analog switch circuit connected with each control module in the preset time period corresponding to each control module.

For each control module, in a preset time period corresponding to each control module, applying a control signal output by each control module to an analog switch circuit connected with each control module so as to keep the frequency of an output waveform of the oscillator within a preset frequency interval, which can be understood as follows: the N analog switch circuits are respectively X1, X2, X3, & gt, XN, the N control modules are respectively Y1, Y2, Y3, & gt, YN, each control module is connected to an analog switch circuit, for example, Y1 is connected to X1, Y2 is connected to X2, Y3 is connected to X3, and so on, YN is connected to XN. Y1 applies a control signal S0 to X1 in a corresponding preset time period to adjust the equivalent resistance of X1; y2 applies a control signal S1 to X2 in a corresponding preset time period to adjust the equivalent resistance of X2; and so on, YN applies a control signal S (N-1) to XN in a corresponding preset time period to adjust the equivalent resistance of XN. After the respective equivalent resistances of X1, X2, X3, and XN are adjusted, the adjustment of the equivalent resistance of the oscillator is thereby achieved, so that the frequency of the output waveform of the oscillator is maintained within the preset frequency interval. The analog switch circuit is equivalent to a digital switch and has two states, namely an open state and a closed state, and after a control signal is applied to the analog switch circuit, the analog switch circuit is in the closed state, namely the closed state of the analog switch circuit is corresponding to the adjustment of the equivalent resistance of the oscillator.

S140: and controlling the waveform generation module to apply a first electric signal and/or a second electric signal to the output end of the Mth inverter so as to regulate the current output by the output end of the Mth inverter.

And in a preset time period corresponding to each control module, applying a control signal output by each control module to an analog switch circuit connected with each control module, and simultaneously, controlling the waveform generation module to apply a first electric signal of a specified time period and/or a second electric signal of a specified time period to the output end of the Mth inverter according to the specified time period corresponding to the first electric signal and/or the second electric signal, for example, applying the first electric signal and the second electric signal, so as to adjust the current output by the output end of the Mth inverter. Because the current sizes of the first electric signal and the second electric signal are always continuously changed, the current sizes of the first electric signal and the second electric signal are different, when the corresponding control modules of all the analog switch circuits respectively apply corresponding control signals to the first electric signal and the second electric signal, the charge and discharge time of the capacitor in each analog switch circuit is continuously changed, and therefore the frequency point of the output waveform of the oscillator can be increased.

In a possible implementation manner, the circuit control method further includes the following scheme:

switching MOS tubes in each of the N analog switch circuits to a conducting state, and determining a first equivalent resistor and a first capacitance parameter; the first equivalent resistor comprises an equivalent resistor of the oscillator in a conducting state, and the first capacitance parameter comprises capacitance values of all capacitors in the oscillator in the conducting state;

determining the minimum value of a preset frequency interval according to the first equivalent resistor and the first capacitance parameter;

switching MOS tubes in each of the N analog switch circuits to an off state, and determining a second equivalent resistor and a second capacitance parameter; the second equivalent resistor comprises an equivalent resistor of the oscillator in an off state, and the second capacitance parameter comprises capacitance values of all capacitors in the oscillator in the off state;

determining the maximum value of a preset frequency interval according to the second equivalent resistance and the second capacitance parameter;

and determining a preset frequency interval according to the maximum value and the minimum value.

As shown in fig. 2, the MOS transistors in each of the N analog switch circuits are controlled to be switched to the on state, where the MOS transistors can be understood as varistors, and when the MOS transistors are all switched to the on state, that is, the resistance value of the varistors is the smallest, that is, the equivalent resistance of the MOS transistor is the smallest, and the resistance value is negligible, and then the equivalent resistance of the oscillator is calculated according to the resistance values of the equivalent resistance and the oscillating resistance R of each of the N MOS transistors, so as to obtain a first equivalent resistance, and obtain capacitance values of capacitors in each of the N analog switch circuits, so as to obtain a first capacitance parameter, and thus calculate a minimum value of a preset frequency interval according to the first equivalent resistance and the first capacitance parameter. For example, as shown in fig. 3 and 8, the minimum value of the preset frequency interval is calculated according to the respective equivalent resistances of T0 to T3, the resistance value of the oscillating resistor R, and the capacitance values of C0 to 1 and C0 to C3. Wherein, C0 in X1, C1 in X2, C2 in X3, C3 in X4 can be represented by C0-4 in FIG. 8, and the difference is in capacitance value. As shown in fig. 2, the first electrical signal I3 is a current flowing into the output terminal of the mth inverter, the second electrical signal I4 is a current flowing out of the output terminal of the mth inverter, the direction in which the first electrical signal I3 flows into the output terminal of the mth inverter is a positive direction, the direction in which the second electrical signal I4 flows out of the output terminal of the mth inverter is a negative direction, the larger the frequency of the output waveform of the oscillator is, the smaller the frequency of the output waveform of the oscillator is, and the smaller the frequency of the output waveform of the oscillator is. When calculating the minimum value of the preset frequency interval, the sum of the first electric signal I3 and the second electric signal I4 needs to be kept to be minimum, that is, the first electric signal I3 and the second electric signal I4 are at the minimum value. When the first electric signal I3 and the second electric signal I4 are at the minimum value, the charge and discharge speeds of the capacitors in the oscillator are the slowest, and the N analog switch circuits are controlled to be in a conducting state, which is equivalent to the closing of the N switches.

After the minimum value of the preset frequency interval is obtained, controlling the MOS tubes in each of the N analog switch circuits to be switched to an off state, and when the MOS tubes are switched to the off state, namely, the resistance value of the rheostat is the maximum, namely, the equivalent resistance of the MOS tubes is the maximum, namely, the MOS tubes are in an open state. And further determining the resistance value of the oscillating resistor R as the equivalent resistance of the oscillator to obtain a second equivalent resistance, and obtaining the capacitance value of C0-1 to obtain a second capacitance parameter, so that the second equivalent resistance and the second capacitance parameter calculate the maximum value of the preset frequency interval. When calculating the maximum value of the preset frequency interval, the sum of the first electrical signal I3 and the second electrical signal I4 needs to be kept to be the maximum, that is, the first electrical signal I3 and the second electrical signal I4 are at the maximum value. When the first electric signal I3 and the second electric signal I4 are at the maximum value, the charge and discharge speeds of the capacitors in the oscillator are the fastest, and the N analog switch circuits are controlled to be in the off state, which is equivalent to the opening of the N switches.

And after calculating the maximum value and the minimum value of the preset frequency interval, obtaining the preset frequency interval. The frequency of the waveform output by the oscillator is always in a preset frequency interval, and the extremum of the preset frequency interval can be changed by adjusting the resistance value of the oscillating resistor R, the capacitance values of C0-1 and C0-C3, and the current values of the first electric signal I3 and the second electric signal I4.

The preset time period for applying the control signals to the respective connected analog switch circuits by all the control modules can be the same or different. If the preset time periods of the control signals applied by all the control modules to the respectively connected analog switch circuits are the same and are large enough, a period time of the output waveform of the oscillator can be obtained according to the preset time periods corresponding to all the control modules, and the period time is calculated as follows:

Since Y1, Y2, Y3, and YN apply control signals to the analog switch circuits connected to each other in the respective preset time periods, and after the waveform generation module a applies the first electrical signal I3 of the specified time period and the second electrical signal I4 of the specified time period to the output terminal of the mth inverter, the frequency of the output waveform of the oscillator remains in the preset frequency interval, and the average frequency of all frequencies in the preset frequency interval can be obtained, assuming that the average frequency=p, then the period corresponding to the average frequency is 1/P, the period corresponding to the average frequency represents one frequency point, that is, the period of a single frequency point, and then the number of frequency points of the output waveform of the oscillator is: t/(1/P), if t is large enough, the frequency point of the output waveform of the oscillator is large, namely, the frequency point of the output waveform of the oscillator is increased, the frequency spectrum of the output waveform is widened, and electromagnetic interference can be greatly reduced.

As shown in fig. 3, 8 and 9, the frequency points of the output waveform of the oscillator are calculated as follows:

when the first electrical signal I3 and the second electrical signal I4 are applied to the output end of the mth inverter, and the control module corresponding to X1 applies the control signal S0 to the gate of the MOS transistor in X1 in the preset time period t1, the control module corresponding to X2 applies the control signal S1 to the gate of the MOS transistor in X2 in the preset time period t2, the control module corresponding to X3 applies the control signal S2 to the gate of the MOS transistor in X3 in the preset time period t3, and the control module corresponding to X4 applies the control signal S3 to the gate of the MOS transistor in X4 in the preset time period t4, the following is the following: assuming that t1 to t4 and Z3, Z4 are the same, if t1 to t4 and Z3, Z4 are sufficiently large, for example, t1 to t4 and Z3, Z4 are 10000us, if the preset frequency interval is [1M,2M ], the average frequency of all the frequencies in the preset frequency interval is 1.5M, the period corresponding to the average frequency is about 0.666us, and the period corresponding to the average frequency represents one frequency point, the number of frequency points of the output waveform of the oscillator is: 10000us/0.666us is approximately 15015, namely the output waveform of the oscillator has about 15015 frequency points, so that the frequency points of the output waveform of the oscillator are increased, the frequency spectrum of the output waveform is widened, and electromagnetic interference can be greatly reduced.

According to the circuit control method provided by the embodiment of the application, the corresponding preset time period of the plurality of control modules is obtained, each control module is controlled to output a control signal, wherein the waveform periods of the control signals respectively output by the plurality of control modules are different, for each control module, the control signal output by each control module is applied to an analog switch circuit connected with each control module in the corresponding preset time period of each control module, and the control waveform generation module applies a first electric signal and/or a second electric signal to the output end of the last inverter so as to adjust the current output by the output end of the last inverter.

The following are examples of the apparatus of the present application that may be used to perform the method embodiments of the present application. For details not disclosed in the embodiments of the apparatus of the present application, please refer to the embodiments of the method of the present application.

Fig. 11 shows a schematic structural diagram of a circuit control device according to an embodiment of the present application. Illustratively, as shown in FIG. 11, the circuit control device 1100 includes:

the period obtaining module 1110 is configured to obtain a preset time period corresponding to each of the N control modules, where N is greater than or equal to 2;

the signal generating module 1120 is configured to control each of the control modules to output a control signal, where the waveform periods of the control signals output by the N control modules are different;

a first signal applying module 1130, configured to apply, for each control module, a control signal output by each control module to an analog switch circuit connected to each control module in the preset time period corresponding to each control module;

a second signal applying module 1140, configured to control the waveform generating module to apply the first electrical signal and/or the second electrical signal to the output terminal of the mth inverter, so as to adjust the current output by the output terminal of the mth inverter.

In a possible implementation manner, the period obtaining module 1110 includes:

the digital acquisition unit is used for acquiring N different numbers;

It should be noted that, when the circuit control method is executed, the circuit control device provided in the foregoing embodiment is only exemplified by the division of the foregoing functional modules, and in practical application, the foregoing functional allocation may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the circuit control device and the circuit control method provided in the foregoing embodiments belong to the same concept, so for details not disclosed in the embodiments of the device of the present application, please refer to the embodiments of the circuit control method of the present application, and the details are not repeated here.

The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

Illustratively, as shown in FIG. 12, the electronic device 1200 includes: a memory 1201, a processor 1202 and the above-mentioned oscillator 1203, wherein the memory 1201 stores therein an executable program code 12011, and the processor 1202 is configured to call and execute the executable program code 12011 to execute a circuit control method.

In this embodiment, the electronic device may be divided into functional modules according to the above method example, for example, each functional module may be corresponding to one processing module, or two or more functions may be integrated into one processing module, where the integrated modules may be implemented in a hardware form. It should be noted that, in this embodiment, the division of the modules is schematic, only one logic function is divided, and another division manner may be implemented in actual implementation.

In the case of dividing each function module with corresponding each function, the electronic device may include: the device comprises a period acquisition module, a signal generation module, a first signal output module, a second signal output module and the like. It should be noted that, all relevant contents of each step related to the above method embodiment may be cited to the functional description of the corresponding functional module, which is not described herein.

The electronic device provided in this embodiment is configured to execute the above-described circuit control method, so that the same effects as those of the above-described implementation method can be achieved.

In case an integrated unit is employed, the electronic device may comprise a processing module, a memory module. The processing module can be used for controlling and managing the actions of the electronic equipment. The memory module may be used to support the electronic device in executing, inter alia, program code and data.

Wherein a processing module may be a processor or controller that may implement or execute the various illustrative logical blocks, modules, and circuits described in connection with the present disclosure. A processor may also be a combination of computing functions, e.g., including one or more microprocessors, digital signal processing (digital signal processing, DSP) and microprocessor combinations, etc., and a memory module may be a memory.

The present embodiment also provides a computer-readable storage medium having stored therein computer program code which, when run on a computer, causes the computer to perform the above-described related method steps to implement a circuit control method in the above-described embodiments.

The present embodiment also provides a computer program product which, when run on a computer, causes the computer to perform the above-described related steps to implement a circuit control method in the above-described embodiments.

In addition, the electronic device provided by the embodiment of the application can be a chip, a component or a module, and the electronic device can comprise a processor and a memory which are connected; the memory is used for storing instructions, and when the electronic device runs, the processor can call and execute the instructions to enable the chip to execute one of the circuit control methods in the above embodiments.

The electronic device, the computer readable storage medium, the computer program product or the chip provided in this embodiment are used to execute the corresponding circuit control method provided above, so that the beneficial effects achieved by the electronic device, the computer readable storage medium, the computer program product or the chip can refer to the beneficial effects in the corresponding circuit control method provided above, and are not repeated herein.

It will be appreciated by those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to perform all or part of the functions described above.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules or units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another apparatus, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

1. An oscillator, the oscillator comprising:

2. The oscillator of claim 1, wherein the respective predetermined time periods of the N control modules are the same or different.

3. The oscillator of claim 1, wherein the waveform generation module comprises:

a first waveform generation circuit for generating a third electrical signal;

4. The oscillator of claim 3, wherein the first waveform generation circuit comprises a first current source, a second current source, a first capacitor, a first PMOS transistor, and a first NMOS transistor;

the positive electrode of the first current source is connected with a power supply, the negative electrode of the first current source is connected with the source electrode of the first PMOS tube, the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube, the grid electrode of the first NMOS tube is an input end of the first waveform generation circuit, and an input signal of the input end of the first waveform generation circuit is a preset switch control signal; the waveforms of the first electric signal, the second electric signal and the third electric signal are different from those of the preset switch control signal;

the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are connected with the first end of the first capacitor, the first end of the first capacitor is connected with the second waveform generation circuit, the source electrode of the first NMOS tube is connected with the positive electrode of the second current source, and the negative electrode of the second current source and the second end of the first capacitor are grounded.

5. The oscillator of claim 4, wherein the second waveform generation circuit comprises a first operational amplifier, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first resistor;

the positive input end of the first operational amplifier is connected with the first end of the first capacitor, the negative input end of the first operational amplifier is connected with the first end of the first resistor, and the second end of the first resistor is grounded;

the source electrode of the second PMOS tube is connected with a power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube is connected with the output end of the first operational amplifier, and the source electrode of the second NMOS tube is connected with the first end of the first resistor;

the grid electrode of the second PMOS tube and the drain electrode of the second PMOS tube are connected with the grid electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with a power supply, and the drain electrode of the third PMOS tube is the first signal output end;

the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, the source electrode of the fourth PMOS tube is connected with a power supply, the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are all connected with the drain electrode of the fourth PMOS tube, the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are grounded, and the drain electrode of the fourth NMOS tube is the second signal output end.

6. The oscillator of claim 4, wherein the second waveform generation circuit comprises a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a second resistor;

the grid electrode and the drain electrode of the fifth NMOS tube are connected with the drain electrode of the fifth PMOS tube, and the source electrode of the fifth NMOS tube is grounded;

the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube are connected with the grid electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is the second signal output end;

the source electrode of the seventh NMOS tube is grounded, the drain electrode of the seventh NMOS tube is connected with the drain electrode of the sixth PMOS tube, the source electrode of the sixth PMOS tube is connected with a power supply, the grid electrode of the sixth PMOS tube and the drain electrode of the sixth PMOS tube are both connected with the grid electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with the power supply, and the drain electrode of the seventh PMOS tube is the first signal output end.

7. The oscillator of claim 3, wherein the first waveform generation circuit comprises a second operational amplifier, a third current source, a reference voltage source, a second capacitor, an eighth PMOS transistor, and an eighth NMOS transistor;

the positive electrode of the third current source is connected with a power supply, the negative electrode of the third current source is connected with the source electrode of the eighth PMOS tube, and the grid electrode of the eighth PMOS tube and the grid electrode of the eighth NMOS tube are both connected with the output end of the second operational amplifier;

the drain electrode of the eighth PMOS tube and the drain electrode of the eighth NMOS tube are both connected with the first end of the second capacitor, the source electrode of the eighth NMOS tube is connected with the positive electrode of the reference voltage source, and the negative electrode of the reference voltage source and the second end of the second capacitor are both grounded;

the first end of the second capacitor is connected with the positive input end of the second operational amplifier, the input signal of the reverse input end of the second operational amplifier is a preset reference voltage signal, and the positive input end of the second operational amplifier is connected with the second waveform generation circuit.

8. The oscillator of claim 7, wherein the second waveform generation circuit comprises a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a third resistor;

The source electrode of the ninth PMOS tube is connected with a power supply, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube, the grid electrode of the ninth NMOS tube is connected with the positive input end of the second operational amplifier, the source electrode of the ninth NMOS tube is connected with the first end of the third resistor, and the second end of the third resistor is grounded;

the grid electrode of the ninth PMOS tube and the drain electrode of the ninth PMOS tube are connected with the grid electrode of the tenth PMOS tube, the source electrode of the tenth PMOS tube is connected with a power supply, and the drain electrode of the tenth PMOS tube is the first signal output end;

the grid electrode of the eleventh PMOS tube is connected with the grid electrode of the tenth PMOS tube, the source electrode of the eleventh PMOS tube is connected with a power supply, the drain electrode of the tenth NMOS tube, the grid electrode of the tenth NMOS tube and the grid electrode of the eleventh NMOS tube are all connected with the drain electrode of the eleventh PMOS tube, the source electrode of the tenth NMOS tube and the source electrode of the eleventh NMOS tube are both grounded, and the drain electrode of the eleventh NMOS tube is the second signal output end.

9. The oscillator according to any one of claims 1 to 8, characterized in that for each of the analog switching circuits, the analog switching circuit comprises a third capacitor and a MOS transistor;

The first end of the third capacitor is connected with the first end of the oscillating resistor, the second end of the third capacitor is connected with the drain electrode of the MOS tube, the grid electrode of the MOS tube is connected with the control module corresponding to the analog switch circuit, and the source electrode of the MOS tube is grounded.

10. A circuit control method applied to the oscillator according to any one of claims 1 to 9, comprising:

11. The circuit control method according to claim 10, wherein the step of obtaining the preset time periods corresponding to the N control modules respectively includes:

Acquiring N different numbers;

setting a time unit for each number to obtain N set time lengths;

and uniformly dividing the N set time durations to N control circuits to obtain preset time periods corresponding to the N control circuits respectively.

12. An electronic device, the electronic device comprising:

the oscillator of any one of claims 1 to 9;

a memory for storing executable program code;

a processor for calling and running the executable program code from the memory, causing the electronic device to perform the circuit control method as claimed in claim 10 or 11.